8P73S674NLGI8

1.8V LVPECL Clock Divider 8P73S674 DATA SHEET General Description Features The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer. The device has been designed for clock signal division and fanout in wireless base station (radio and base band), high-end computing and telecommunication equipment. The device is optimized to deliver excellent phase noise performance. The 8P73S674 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection. The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four low-skew 1.8V LVPECL outputs are available for and support clock output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL outputs are terminated 50 to GND. Outputs can be disabled to save power consumption if not used. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The device is a member of the high-performance clock family from IDT. • • • • • • • • • • • Block Diagram Pin Assignment Supports frequency division of ÷1, ÷2, ÷4 and ÷8 Maximum Output frequency: 1GHz Output skew: 100ps (maximum) LVPECL output rise/fall time (20% - 80%): 220ps (maximum) 1.8V core and output supply mode Supports 1.8V I/O LVCMOS logic levels for all control pins -40°C to +85°C ambient operating temperature Q1 nQ1 19 18   VCC 20 Q0 nQ0 Lead-free (RoHS 6) 20-lead VFQFN packaging Q0 nQ0 2x 50 VT Four low-skew LVPECL clock outputs nOEA ÷N SiGe technology for high-frequency and fast signal rise/fall times GND IN nIN Clock signal division and distribution 17 16 nIN 1 15 nQ1 NC 2 14 Q1 VT 3 13 nQ2 IN 4 12 Q2 N0 5 11 VCC N[1:0] 6 7 8 9 10 nQ3 Q3 Q3 nQ3 nOEB nOEB 8P73S674 N1 Q2 nQ2 GND nOEA 20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package 8P73S674 REVISION 1 12/17/14 1 ©2014 Integrated Device Technology, Inc. 8P73S674 DATA SHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 nIN Input — Clock signal inverting differential input. Internal termination 50 to VT. 2 NC Unused — Not connected. 3 VT — — Leave open if IN, nIN is used with LVDS signals. 4 IN Input — Clock signal non-inverting differential input. Internal termination 50 to VT. 5 N0 Input Pulldown 6 GND Power — 7 N1 Input Pulldown Frequency divider control. 1.8V LVCMOS/LVTTL interface levels. 8 nOEB Input Pulldown Output enable control for the Q1, Q2 and Q3 outputs.  1.8V LVCMOS/LVTTL interface levels. 9 nQ3 Output — 10 Q3 Output — 11 VCC Power — 12 Q2 Output — 13 nQ2 Output — 14 Q1 Output — 15 nQ1 Output — 16 VCC Power — 17 Q0 Output — 18 nQ0 Output — 19 nOEA Input Pulldown 20 GND Power — Power supply ground. EPAD GND_EP Power — Exposed package pad negative supply voltage (GND).  Return current path for the Q0, Q1, Q2 and Q3 outputs. Frequency divider control. 1.8V LVCMOS/LVTTL interface levels. Power supply ground. Differential clock output 3. 1.8V LVPECL output levels. Supply voltage for the clock outputs. Differential clock output 2. 1.8V LVPECL output levels. Differential clock output 1. 1.8V LVPECL output levels. Supply voltage for the clock outputs. Differential clock output 0. 1.8V LVPECL output levels. Output enable control for the Q0 output.  1.8V LVCMOS/LVTTL interface levels. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k 1.8V LVPECL CLOCK DIVIDER Test Conditions 2 Minimum Typical Maximum Units REVISION 1 12/17/14 8P73S674 DATA SHEET Truth Tables Table 3A. N Clock Divider Input N1 N0 Divider Value 0 (default) 0 (default) ÷1 0 1 ÷2 1 0 ÷4 1 1 ÷8 Table 3B. nOEA Output Enable Input Output nOEA Q0 0 (default) Output is enabled 1 Output is disabled in logic low state Table 3C. nOEB Output Enable Input Output nOEB Q1, Q2, Q3 0 (default) Outputs are enabled 1 Outputs are disabled in logic low state REVISION 1 12/17/14 3 1.8V LVPECL CLOCK DIVIDER 8P73S674 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs -0.5V to VCC + 0.5V Input Current, IN, nIN ±30mA VT Current, IVT ±60mA Outputs, IO (LVPECL) Continuous Current Surge Current  50mA 100mA Junction Temperature 125C Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C Symbol Parameter Test Conditions VCC Core Supply Voltage ICC Power Supply Current Minimum Typical Maximum Units 1.65 1.8 1.95 V 62 73 mA Typical Maximum Units Outputs Unloaded Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage 1.2 1.8 V VIL Input Low Voltage -0.3 0.3 V IIH Input High Current N0, N1, nOEA, nOEB VCC = 1.95V, VIN = 1.95V 150 µA IIL Input Low Current N0, N1, nOEA, nOEB VCC = 1.95V, VIN = 0V -10 µA Table 4C. Differential Input DC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C Symbol Parameter RIN Differential Input Resistance IN, nIN IIN Input Current IN, nIN 1.8V LVPECL CLOCK DIVIDER Test Conditions Minimum Typical Maximum Units Across IN and nIN with VT floated 70 100 130  25 mA 4 REVISION 1 12/17/14 8P73S674 DATA SHEET Table 4D. LVPECL DC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C Symbol Parameter Test Conditions 1 VOH Output High Voltage VOL 1 Output Low Voltage VSWING Peak-to-Peak Output  Voltage Swing1 Minimum Typical VCC – 1.1 0.6 Maximum Units VCC – 0.75 V VCC – 1.5 V 1.0 V NOTE 1: Outputs terminated with 50 to GND. AC Electrical Characteristics Table 5. AC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C1, 2 Symbol Parameter VPP Input Voltage Swing IN, nIN VDIFF_IN Differential Input Voltage Swing VCMR Common Mode Input Voltage3 fOUT fIN Test Conditions Maximum Units 0.2 1 V IN, nIN 0.4 2 V IN, nIN 0.9 VCC –VPP/2 V N = ÷1 1000 MHz N = ÷2 500 MHz N = ÷4 250 MHz N = ÷8 125 MHz 1000 MHz 100 ps Output Frequency, Q[3:0] Minimum Typical Input Frequency, IN, nIN Skew4, 5 tsk(o) Output tPD Propagation Delay 40 N = ÷1 200 600 ps N = ÷2, ÷4, ÷8 400 900 ps 500 ps Skew4, 6 tsk(pp) Part-to-Part tR / tF Output Rise/Fall Time tjit(Ø) Phase Jitter Noise Floor, >100kHz offset7 tjit(Ø) Additive Phase Noise, RMS odc Output Duty Cycle 10%-90% 270 410 ps 20%-80% 150 220 ps any Q, fOUT = 1000MHz -153 122.88 MHz; 1kHz-40MHz 100 180 fs 122.88 MHz; 12kHz-20MHz 60 120 fs 50 55 % 50% Input Duty Cycle 45 dBc/Hz NOTE 1: Outputs terminated with 50 to GND. NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 3: Common mode input voltage is defined as the signal crosspoint. NOTE 4: This parameter is defined in accordance with JEDEC standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crosspoints. NOTE 6: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the output differential crosspoints. NOTE 7: VCMR is set to 1.12V. REVISION 1 12/17/14 5 1.8V LVPECL CLOCK DIVIDER 8P73S674 DATA SHEET Parameter Measurement Information 1.8V±0.15V VCC VCC Qx SCOPE nIN IN nQx GND VEE 1.8V LVPECL Output Load Test Circuit Differential Input Level Par t 1 nQx nQx Qx Qx nQy nQy Qy Par t 2 Qy tsk(pp) Output Skew Part-to-Part Skew nQ[0:3] nQ[0:3] Q[0:3] Q[0:3] Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time 1.8V LVPECL CLOCK DIVIDER 6 REVISION 1 12/17/14 8P73S674 DATA SHEET Applications Information Recommendations for Unused Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 1. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) REVISION 1 12/17/14 7 1.8V LVPECL CLOCK DIVIDER 8P73S674 DATA SHEET 1.8V Differential Clock Input Interface interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN /nIN accepts LVDS and other differential signals. The differential input signal must meet both the VPP and VCMR input requirements. Figure 2A to Figure 2C show interface examples for the IN /nIN input driven by the most common driver types. The input 3.3V, 2.5V, 1.8V 2.5V, 1.8V 1.8V Zo = 50 1.8V Zo = 50 IN VT VT Zo = 50 nIN Zo = 50 Receiv er nIN Receiv er LVPECL LVDS Figure 2A. Differential Input Driven by an LVDS Driver 1.8V IN Figure 2C. Differential Input Driven by an LVPECL Driver 1.8V Zo = 50 IN VT Zo = 50 nIN Receiv er CML Figure 2B. Differential Input Driven by a CML Driver 1.8V LVPECL CLOCK DIVIDER 8 REVISION 1 12/17/14 8P73S674 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 8P73S674.  Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8P73S674 is the sum of the core power plus the power dissipated due to loading.  The following is the power dissipation for VCC = 1.8V + 0.15V = 1.95V, which gives worst case results. The following calculation is for 85°C. The maximum current at 85°C is 68.3mA. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. • Power (core)MAX = VCC_MAX * ICC_MAX = 1.95V * 68.3mA = 133.2mW • Power (outputs)MAX = 31.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 31.5mW = 126mW • Power Dissipation for internal termination RT Power (RT)MAX = 2 * [(IIN_MAX)2 * 50] = 2 * (25mA)2 * 50 = 62.5mW Total Power_MAX = Power (core)MAX + Power (outputs)MAX + Power (RT)MAX = 133.2+ 126mW + 62.5mW = 321.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 62.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.322W * 70.7°C/W = 108°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 20-Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION 1 12/17/14 0 1 2 70.7°C/W 67.0°C/W 65.3°C/W 9 1.8V LVPECL CLOCK DIVIDER 8P73S674 DATA SHEET 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 3. VCC Q1 VOUT RL Figure 3. LVPECL Driver Circuit and Termination To calculate power dissipation due to loading, use the following equations which assume a 50 load. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.75V (VCC_MAX – VOH_MAX) = 0.75V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V (VCC_MAX – VOL_MAX) = 1.5V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX)/RL] * (VCC_MAX – VOH_MAX)  = [(VCC_MAX – 0.75)/RL] * (VCC_MAX – VOH_MAX)  = [(1.95V – 0.75V)/50] * 0.75V = 18mW Pd_L = [(VOL_MAX)/RL] * (VCC_MAX – VOL_MAX)  = [(VCC_MAX – 1.5v)/RL] * (VCC_MAX – VOL_MAX)  = [(1.95V – 1.5V)/50] * 1.5V = 13.5mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.5mW 1.8V LVPECL CLOCK DIVIDER 10 REVISION 1 12/17/14 8P73S674 DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 20-Lead VFQFN JA at 0 Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 70.7°C/W 67.0°C/W 65.3°C/W Transistor Count The transistor count for the 8P73S674 is: 1,238 REVISION 1 12/17/14 11 1.8V LVPECL CLOCK DIVIDER 8P73S674 DATA SHEET Package Information 1.8V LVPECL CLOCK DIVIDER 12 REVISION 1 12/17/14 8P73S674 DATA SHEET Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8P73S674NLGI 8P73S674NLGI 20-Lead VFQFN, Lead-Free Tray -40°C to +85°C 8P73S674NLGI8 8P73S674NLGI 20-Lead VFQFN, Lead-Free Tape & Reel -40°C to +85°C REVISION 1 12/17/14 13 1.8V LVPECL CLOCK DIVIDER Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. 8P73S674 DATA SHEET REVISION 1 12/17/14 15 1.8V LVPECL CLOCK DIVIDER