8T49N285A-999NLGI8

FemtoClock® NG Octal Universal Frequency Translator 8T49N285 Datasheet Description Features The 8T49N285 has a fractional-feedback PLL that can be used as a jitter attenuator or frequency translator. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 different output frequencies, ranging from 8kHz to 1GHz. Three of these frequencies are completely independent of each other and the inputs. The other five are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. • Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions • • • • 95nF, otherwise set to 1. 0 = 1 ppm accuracy 1 = 16 ppm accuracy DBITM R/W 0b Digital Lock Manual Override Setting for Analog PLL: 0 = Automatic Mode 1 = Manual Mode VCOMAN R/W 1b Manual Lock Mode VCO Selection Setting for Analog PLL: 0 = VCO2 1 = VCO1 DBIT1[4:0] R/W 01011b Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL. DBIT2[4:0] R/W 00000b Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL. SYN_MODE R/W 0b Rsvd R/W - ©2021 Renesas Electronics Corporation. Frequency Synthesizer Mode Control for PLL: 0 = PLL jitter attenuates and translates one or more input references 1 = PLL synthesizes output frequencies using only the crystal as a reference Note that the STATE0[1:0] field in the Digital PLL Control Register must be set to Force Freerun state Reserved. Always write 0 to this bit location. Read values are not defined. 29 March 8, 2021 8T49N285 Datasheet Table 6M. Power Down Control Register Bit Field Locations and Descriptions Power Down Control Register Block Field Locations Address (Hex) D7 D6 D5 00B4 D3 D2 D1 Rsvd 00B5 1 Rsvd Q7_DIS 1 1 Q6_DIS 00B8 Q5_DIS Q4_DIS D0 DBL_DIS Rsvd 00B6 00B7 D4 CLK1_DIS CLK0_DIS Rsvd Q3_DIS Q2_DIS Q1_DIS Q0_DIS 1 DPLL_DIS 1 CALRST Rsvd Power Down Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description DBL_DIS R/W 0b Controls whether Crystal Input Frequency is doubled before being used in PLL: 0 = 2x Actual Crystal Frequency Used 1 = Actual Crystal Frequency Used CLKm_DIS R/W 0b Disable Control for Input Reference m: 0 = Input Reference m is Enabled 1 = Input Reference m is Disabled Qm_DIS R/W 0b Disable Control for Output Qm, nQm: 0 = Output Qm, nQm functions normally 1 = All logic associated with Output Qm/nQm is Disabled & Driver in High-Impedance state DPLL_DIS R/W 0b Disable Control for Digital PLL: 0 = Digital PLL Enabled 1 = Digital PLL Disabled CALRST R/W 0b Reset Calibration Logic for APLL: 0 = Calibration Logic for APLL Enabled 1 = Calibration Logic for APLL Disabled Rsvd R/W - ©2021 Renesas Electronics Corporation. Reserved. Always write 0 to this bit location. Read values are not defined. 30 March 8, 2021 8T49N285 Datasheet Table 6N. Input Monitor Control Register Bit Field Locations and Descriptions Input Monitor Control Register Block Field Locations Address (Hex) D7 D6 D5 00B9 D4 D3 D2 D1 Rsvd LOS_0[16] 00BA LOS_0[15:8] 00BB LOS_0[7:0] 00BC Rsvd LOS_1[16] 00BD LOS_1[15:8] 00BE LOS_1[7:0] 00BF D0 Rsvd 00C0 Rsvd Rsvd 00C1 Rsvd 00C2 Rsvd Rsvd 00C3 Rsvd 00C4 Rsvd 00C5 Rsvd 00C6 Rsvd Input Monitor Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description LOS_m[16:0] R/W 1FFFFh Rsvd R/W - Number of Input Monitoring clock periods before Input Reference m is considered to be missed (soft alarm). Minimum setting is 3. Reserved. Always write 0 to this bit location. Read values are not defined. Table 6O. Interrupt Enable Control Register Bit Field Locations and Descriptions Interrupt Enable Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00C7 Rsvd LOL_EN Rsvd HOLD_EN Rsvd Rsvd LOS1_EN LOS0_EN Interrupt Enable Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description LOL_EN R/W 0b Interrupt Enable Control for Loss-of-Lock Interrupt Status Bit for PLL: 0 = LOL_INT register bit will not affect status of nINT output signal 1 = LOL_INT register bit will affect status of nINT output signal HOLD_EN R/W 0b Interrupt Enable Control for Holdover Interrupt Status Bit for PLL: 0 = HOLD_INT register bit will not affect status of nINT output signal 1 = HOLD_INT register bit will affect status of nINT output signal LOSm_EN R/W 0b Interrupt Enable Control for Loss-of-Signal Interrupt Status Bit for Input Reference m: 0 = LOSm_INT register bit will not affect status of nINT output signal 1 = LOSm_INT register bit will affect status of nINT output signal ©2021 Renesas Electronics Corporation. 31 March 8, 2021 8T49N285 Datasheet Table 6P. Digital Phase Detector Control Register Bit Field Locations and Descriptions Digital Phase Detector Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 00C8 D3 D2 D1 D0 Rsvd 1 Rsvd Rsvd Rsvd 1 Rsvd Rsvd 27h 00C9 1 Rsvd 00CA 27h 00CB 1 Rsvd Digital Phase Detector Control Register Block Field Descriptions Bit Field Name Field Type Rsvd R/W Default Value Description ©2021 Renesas Electronics Corporation. - Reserved. Always write 0 to this bit location. Read values are not defined. 32 March 8, 2021 8T49N285 Datasheet Table 6Q. Interrupt Status Register Bit Field Locations and Descriptions This register contain sticky’ bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C). Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0200 Rsvd LOL_INT Rsvd HOLD_INT Rsvd Rsvd LOS1_INT LOS0_INT 0201 Rsvd 0202 Rsvd 0203 Rsvd Interrupt Status Register Block Field Descriptions Bit Field Name LOL_INT HOLD_INT Field Type Default Value Description R/W1C R/W1C 0b Interrupt Status Bit for Loss-of-Lock on PLL: 0 = No Loss-of-Lock alarm flag on PLL has occurred since the last time this register bit was cleared 1 = At least one Loss-of-Lock alarm flag on PLL has occurred since the last time this register bit was cleared 0b Interrupt Status Bit for Holdover on PLL: 0 = No Holdover alarm flag on PLL has occurred since the last time this register bit was cleared 1 = At least one Holdover alarm flag on PLL has occurred since the last time this register bit was cleared Interrupt Status Bit for Loss-of-Signal on Input Reference m: 0 = No Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared 1 = At least one Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared LOSm_INT R/W1C 0b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Table 6R. Output Phase Adjustment Status Register Bit Field Locations and Descriptions Output Phase Adjustment Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0204 PA_BUSY7 PA_BUSY6 PA_BUSY5 PA_BUSY4 PA_BUSY3 PA_BUSY2 PA_BUSY1 PA_BUSY0 Output Phase Adjustment Status Register Block Field Descriptions Bit Field Name PA_BUSYm Field Type Default Value Description R/O ©2021 Renesas Electronics Corporation. - Phase Adjustment Event Status for output Qm, nQm: 0 = No phase adjustment is currently in progress on output Qm, nQm 1 = Phase adjustment still in progress on output Qm, nQm. Do not initiate any new phase adjustment at this time 33 March 8, 2021 8T49N285 Datasheet The following register is included for debug purposes only. It shows the actual digital PLL state directly. This means that the bits may change rapidly as the DPLL operates. The fields in this register do not represent a “snapshot” in time, so they may be inconsistent with one another if the DPLL is rapidly changing at the time of reading. Fast changes in the status of the PLL cannot be captured by polling these bits, in which case, Renesas recommends using the Sticky Bits interrupts and GPIOs. Table 6S. Digital PLL Status Register Bit Field Locations and Descriptions Digital PLL Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 0205 Rsvd EXTLOS NO_REF0 0206 Rsvd PLL0LCK Rsvd 0207 D2 D1 D0 CURR_REF0[2:0] Rsvd SM_STS0[1:0] Rsvd Rsvd 0208 Rsvd 0209 Rsvd 020A Rsvd Rsvd 020B Rsvd 020C Rsvd 020D Rsvd 020E Rsvd Digital PLL Status Register Block Field Descriptions Default Value Description Bit Field Name Field Type EXTLOS R/O - External Loopback signal lost for PLL: 0 = PLL has a valid feedback reference signal 1 = PLL has lost the external feedback reference signal and is no longer locked NO_REF0 R/O - Valid Reference Status for Digital PLL0: 0 = At least one valid Input Reference is present 1 = No valid Input References present CURR_REF0[2:0] R/O - Currently Selected Reference Status for Digital PLL: 000 - 011 = No reference currently selected 100 = Input Reference 0 (CLK0, nCLK0) selected 101 = Input Reference 1 (CLK1, nCLK1) selected 110 = Reserved 111 = Reserved PLL0LCK R/O - Digital PLL0 phase error value is less than the LOCK window setting. Not asserted if PLL0 is in Synthesizer Mode. SM_STS0[1:0] R/O - Current State of Digital PLL0: 00 = Reserved 01 = Freerun 10 = Normal 11 = Holdover Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. ©2021 Renesas Electronics Corporation. 34 March 8, 2021 8T49N285 Datasheet Table 6T. General Purpose Input Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 0219 D4 Rsvd D3 D2 D1 D0 GPI[3] GPI[2] GPI[1] GPI[0] General Purpose Input Status Register Block Field Descriptions Bit Field Name Field Type GPI[3:0] R/O Default Value Description - Shows current values on GPIO[3:0] pins that are configured as General-Purpose Inputs. Table 6U. Global Interrupt Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 021A D4 D3 D2 Rsvd D0 Rsvd 021B INT Rsvd 021C Rsvd Rsvd 021D Rsvd Rsvd 021E 021F D1 Rsvd Rsvd Rsvd Rsvd Rsvd nEEP_CRC Rsvd Rsvd BOOTFAIL Rsvd Rsvd EEPDONE Global Interrupt Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description INT R/O - Device Interrupt Status: 0 = No Interrupt Status bits that are enabled are asserted (nINT pin released) 1 = At least one Interrupt Status bit that is enabled is asserted (nINT pin asserted low) BOOTFAIL R/O - Reading of Serial EEPROM failed. Once set this bit is only cleared by reset. nEEP_CRC R/O - EEPROM CRC Error (Active Low): 0 = EEPROM was detected and read, but CRC check failed - please reset the device via the nRST pin to retry (serial port is locked) 1 = No EEPROM CRC Error EEPDONE R/O - Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. ©2021 Renesas Electronics Corporation. 35 March 8, 2021 8T49N285 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI OSCI Other Input 0V to 2V -0.5V to VCC + 0.5V Outputs, VO, (Q[0:7], nQ[0:7]) -0.5V to VCCOX + 0.5V Outputs, VO, (GPIO[3:0], SDATA, SCLK, nINT) -0.5V to VCC + 0.5V Outputs, IO (Q[7:0], nQ[7:0]) Continuous Current Surge Current 40mA 65mA Outputs, IO (GPIO[3:0], SDATA, SCLK, nINT) Continuous Current Surge Current 8mA 13mA Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. Supply Voltage Characteristics Table 7A. Power Supply Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.09 3.3 VCC V ICC Power Supply Current1 64 90 mA Current1 122 187 mA 468 630 mA Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC – 0.09 ICCA Analog Supply IEE Power Supply Current2 Q[0:7] Configured for LVPECL Logic Levels; Outputs Unloaded NOTE 1: ICC and ICCA are included in IEE when Q[0:7] is configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. Table 7B. Power Supply Characteristics, VCC = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Power Supply Test Conditions 2.5 VCC V Current1 63 85 mA Current1 119 182 mA 441 595 mA ICCA Analog Supply IEE Power Supply Current2 Q[0:7] Configured for LVPECL Logic Levels; Outputs Unloaded NOTE 1: ICC and ICCA are included in IEE when Q[0:7] is configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. ©2021 Renesas Electronics Corporation. 36 March 8, 2021 8T49N285 Datasheet Table 7C. Maximum Output Supply Current, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C1 Test Conditions VCCOx2 = 3.3V ±5% VCCOx2 = 1.8V ±5% VCCOx2 = 2.5V ±5% LVPECL LVDS HCSL LVCMOS LVPECL LVDS HCSL LVCMOS LVCMOS Outputs Unloaded 50 60 50 55 40 50 40 45 35 mA Q1, nQ1 Output Supply Current Outputs Unloaded 50 60 50 55 40 50 40 45 35 mA ICCO2 Q2, nQ2 Output Supply Current Outputs Unloaded 80 90 80 80 70 80 70 70 60 mA ICCO3 Q3, nQ3 Output Supply Current Outputs Unloaded 80 90 80 80 70 80 70 70 60 mA ICCO4 Q4, nQ4 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO5 Q5, nQ5 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO6 Q6, nQ6 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO7 Q7, nQ7 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA Symbol Parameter ICCO0 Q0, nQ0 Output Supply Current ICCO1 Units NOTE 1: Internal dynamic switching current at maximum fOUT is included. NOTE 2: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. ©2021 Renesas Electronics Corporation. 37 March 8, 2021 8T49N285 Datasheet DC Electrical Characteristics Table 8A. LVCMOS/LVTTL DC Characteristics, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH VOL Input High Current Input Low Current Output High Voltage Output Low Voltage Test Conditions Minimum VCC = 3.3V Typical Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V PLL_BYP, S_A0 VCC = VIN = 3.465V or 2.625V 150 µA nRST, SDATA, SCLK VCC = VIN = 3.465V or 2.625V 5 µA GPIO[3:0] VCC = VIN = 3.465V or 2.625V 1 mA PLL_BYP, S_A0 VCC = 3.465V or 2.625V, VIN = 0V -5 µA nRST, SDATA, SCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA GPIO[3:0] VCC = 3.465V or 2.625V, VIN = 0V -1 mA nINT, SDATA, SCLK1 VCC = 3.3V+5%, IOH = -5µA 2.6 V GPIO[3:0] VCC = 3.3V+5%, IOH = -50µA 2.6 V nINT, SDATA, SCLK1 VCC = 2.5V+5%, IOH = -5µA 1.8 V GPIO[3:0] VCC = 2.5V+5%, IOH = -50µA 1.8 V nINT, SDATA, SCLK1 VCC = 3.3V+5% or 2.5V+5%, IOL = 5mA 0.5 V GPIO[3:0] VCC = 3.3V+5% or 2.5V+5%, IOL = 50µA 0.5 V NOTE 1: Use of external pull-up resistors is recommend. Table 8B. Differential Input DC Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C1 2 Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLKx, nCLKx Minimum VCC = VIN = 3.465V or 2.625V Typical Maximum Units 150 µA CLKx VCC = 3.465V or 2.625V, VIN = 0V -5 µA nCLKx VCC = 3.465V or 2.625V, VIN = 0V -150 µA Voltage3 VPP Peak-to-Peak VCMR Common Mode Input Voltage3, 4 0.15 1.3 V VEE VCC – 1.2 V NOTE 1: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1. NOTE 2: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 3: VIL should not be less than -0.3V. VIH should not be higher than VCC. NOTE 4: Common mode voltage is defined as the cross-point. ©2021 Renesas Electronics Corporation. 38 March 8, 2021 8T49N285 Datasheet Table 8C. LVPECL DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VCCOX = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C1, 2 VCCOx = 3.3V±5% Symbol Parameter Test Conditions VOH Output High Voltage3 Qx, nQx VOL Output Low Voltage3 Qx, nQx Minimum Typical VCCOx = 2.5V±5% Maximum Minimum VCCOx - 1.3 VCCOx - 0.8 VCCOx - 1.95 VCCOx - 1.75 Typical Maximum Units VCCOx - 1.4 VCCOx - 0.9 V VCCOx - 1.95 VCCOx - 1.75 V NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE 3: Outputs terminated with 50 to VCCOx – 2V. Table 8D. LVDS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOX = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C1, 2, 3 Symbol Parameter Test Conditions VOD Differential Output Voltage Qx, nQx VOD VOD Magnitude Change Qx, nQx VOS Offset Voltage Qx, nQx VOS VOS Magnitude Change Qx, nQx Minimum Typical Maximum 195 1.1 Units 454 mV 50 mV 1.375 V 50 mV NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE 3: Terminated 100 across Qx and nQx. Table 8E. LVCMOS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C1, 2 VCCOx = 3.3V±5% Test Conditions Minimum Qx, nQx IOH = -8mA 2.6 Qx, nQx IOL = 8mA Symbol Parameter VOH Output High Voltage VOL Output Low Voltage Typical VCCOx = 2.5V±5% Maximum Minimum Typical VCCOx = 1.8V ±5% Maximum 1.8 0.5 Minimum Typical Maximum 1.1 0.5 Units V 0.5 V NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. ©2021 Renesas Electronics Corporation. 39 March 8, 2021 8T49N285 Datasheet Table 9. Input Frequency Characteristics, VCC = 3.3V ± 5% or 2.5V±5%, TA = -40°C to 85°C1 Symbol fIN Parameter Input Frequency2 OSCI, OSCO Test Conditions Minimum Using a Crystal (See Table 10, Crystal Characteristics) Maximum Units 10 40 MHz Overdriving Crystal Input, Doubler Logic Enabled3 10 62.5 MHz Overdriving Crystal Input, Doubler Logic Disabled3 16 125 MHz 0.008 875 MHz 100 400 kHz CLKx, nCLKx fSCLK Serial Port Clock SCLK Slave Mode Typical NOTE 1: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1. NOTE 2: For the input reference frequency, the divider values must be set for the VCO to operate within its supported range. NOTE 3: For optimal noise performance, the use of a quartz crystal is recommended. Refer to Applications Information,Overdriving the XTAL Interface. Table 10. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 40 MHz Fundamental Frequency 10 Equivalent Series Resistance (ESR) 15  Load Capacitance (CL) 12 pF Frequency Stability (total) ©2021 Renesas Electronics Corporation. -100 40 100 ppm March 8, 2021 8T49N285 Datasheet AC Electrical Characteristics Table 11A. AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C1, 2 Symbol Parameter fVCO VCO Operating Frequency fOUT Test Conditions LVPECL, LVDS, HCSL Output Frequency Maximum Units 3000 4000 MHz Q0, Q1, Q4, Q5, Q6, Q7 Outputs 0.008 1000 MHz Q2, Q3 Outputs Integer Divide Ratio & No Added Phase Delay 0.008 666.67 MHz Q2, Q3 Outputs Non-integer Divide and/or Added Phase Delay 0.008 400 MHz 0.008 250 MHz LVCMOS LVPECL tR / tF SR Minimum Typical 20% to 80% 145 360 600 ps 20% to 80% 100 230 400 ps 20% to 80% 150 300 600 ps 20% to 80%, VCCOx = 3.3V 180 350 600 ps 20% to 80%, VCCOx = 2.5V 200 350 550 ps 20% to 80%, VCCOx = 1.8V 200 410 650 ps LVPECL Measured on Differential Waveform, ±150mV from Center 1 5 V/ns LVDS Measured on Differential Waveform, ±150mV from Center 0.5 4 V/ns VCCOx = 2.5V, fOUT 125MHz, Measured on Differential Waveform, ±150mV from Center 1.5 4 V/ns VCCOx = 3.3V, fOUT 125MHz, Measured on Differential Waveform, ±150mV from Center 2.5 5.5 V/ns LVDS Output HCSL Rise and Fall Times LVCMOS3, 4 Output Slew Rate5 HCSL ©2021 Renesas Electronics Corporation. 41 March 8, 2021 8T49N285 Datasheet Table 11A. AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditions LVPECL LVDS tsk(b) Bank Skew HCSL LVCMOS odc Output Duty Cycle11 Minimum Typical Maximum Units Q0, nQ0, Q1, nQ1 NOTE6, 7, 8, 9 75 ps Q4, nQ4, Q5, nQ5 NOTE6, 7, 8, 9 75 ps Q6, nQ6, Q7, nQ7 NOTE6, 7, 8, 9 75 ps Q0, nQ0, Q1, nQ1 NOTE6, 7, 8, 9 75 ps Q4, nQ4, Q5, nQ5 NOTE6, 7, 8, 9 75 ps Q6, nQ6, Q7,nQ7 NOTE6, 7, 8, 9 75 ps Q0, nQ0, Q1, nQ1 NOTE6, 7, 8, 9 75 ps Q4, nQ4, Q5, nQ5 NOTE6, 7, 8, 9 75 ps Q6, nQ6, Q7, nQ7 NOTE6, 7, 8, 9 75 ps Q0, nQ0, Q1, nQ1 NOTE3, 6, 7, 9, 10 80 ps Q4, nQ4, Q5, nQ5 NOTE3, 6, 7, 9, 10 115 ps Q6, nQ6, Q7, nQ7 NOTE3, 6, 7, 9, 10 115 ps LVPECL, LVDS, HCSL fOUT  666.667MHz 45 50 55 % fOUT > 666.667MHz 40 50 60 % 40 50 60 % 50 ppb LVCMOS Initial Frequency Offset12, 13, 14 Switchover or Entering / Leaving Holdover State Output Phase Change in Fully Hitless Switching13, 14, 15 Switchover or Entering / Leaving Holdover State 5 ns -50 SSB(1k) 1kHz 122.88MHz Output -123 dBc/Hz SSB(10k) 10kHz 122.88MHz Output -131 dBc/Hz SSB(100k Single Sideband ) Phase Noise16 SSB(1M) 100kHz 122.88MHz Output -134 dBc/Hz 1MHz 122.88MHz Output -147 dBc/Hz SSB(10M) 10MHz 122.88MHz Output -153 dBc/Hz SSB(30M) >30MHz 122.88MHz Output -154 dBc/Hz >800kHz 122.88MHz Output -83 dBc Spurious Limit at Offset17 ©2021 Renesas Electronics Corporation. 42 March 8, 2021 8T49N285 Datasheet Table 11A. AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditions Internal OTP Startup13 tstartup SPO Startup Time 13, 18 External EEPROM Startup Typical Maximum Units from VCC >80% to First Output Clock Edge 110 150 ms from VCC >80% to First Output Clock Edge (0 retries). I2C Frequency = 100kHz 150 200 ms from VCC >80% to First Output Clock Edge (0 retries). I2C Frequency = 400kHz 130 150 ms from VCC >80% to First Output Clock Edge (31 retries). I2C Frequency = 100kHz 925 1200 ms from VCC >80% to First Output Clock Edge(31 retries). I2C Frequency = 400kHz 360 500 ms 175 ps Static Phase Offset Variation19 fIN = fOUT = 156.25 MHz Minimum -175 NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 3: Appropriate SE_MODE bit must be configured to select phase-aligned or phase-inverted operation. NOTE 4: All Q and nQ outputs in phase-inverted operation. NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 6: This parameter is guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. NOTE 8: Measured at the output differential cross point. NOTE 9: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 10: Measured at VCCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned. NOTE 11: Characterized in synthesizer mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device. NOTE 12: Tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable. NOTE 13: This parameter is guaranteed by design. NOTE 14: Using internal feedback mode configuration. NOTE 15: Device programmed with SWMODEn = 0 (absorbs phase differences). NOTE 16: Characterized with 8T49N285-901 units (synthesizer mode). NOTE 17: Tested with all outputs operating at 122.88MHz. NOTE 18: Assuming a clear I2C bus. NOTE 19: This parameter was measured using CLK0 as the reference input and CLK1 as the external feedback input. Characterized with 8T49N285-908. ©2021 Renesas Electronics Corporation. 43 March 8, 2021 8T49N285 Datasheet Table 11B. HCSL AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C1 Symbol Parameter Test Conditions 2, 3 VRB Ring-back Voltage Margin tSTABLE Time before VRB is allowed2, 3 Minimum -100 Absolute Max. Output Voltage VMIN Absolute Min. Output Voltage4, 6 Absolute Crossing Voltage VCROSS Total Variation of VCROSS Over all Edges7, 9 Units 100 mV ps 1150 mV -300 7, 8 VCROSS Maximum 500 4, 5 VMAX Typical 230 mV 550 mV 140 mV NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 2: Measurement taken from differential waveform. NOTE 3: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 4: Measurement taken from single ended waveform. NOTE 5: Defined as the maximum instantaneous voltage including overshoot. NOTE 6: Defined as the minimum instantaneous voltage including overshoot NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Qn equals the falling edge of nQn. NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 9: Defined as the total variation of all crossing voltages of rising Qn and falling nQn. This is the maximum allowed variance in VCROSS for any particular system. ©2021 Renesas Electronics Corporation. 44 March 8, 2021 8T49N285 Datasheet Table 12A. Typical RMS Phase Jitter (Synthesizer Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C1, 2, 3 Symbol Test Conditions LVPECL LVDS HCSL LVCMOS4 Units fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz5 279 285 277 286 fs fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz6 270 262 263 270 fs fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz7 291 264 263 N/A8 fs Q2, Q3 Integer5 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 309 310 303 317 fs Q2, Q3 Fractional9 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 266 266 257 263 fs Q4, Q5, Q6, Q75 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 298 301 292 300 fs Parameter Q0, Q1 tjit() RMS Phase Jitter (Random) NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE 3: All outputs configured for the specific output type, as shown in the table. NOTE 4: Qx and nQx are 180° out of phase. NOTE 5: Characterized with 8T49N285-901. NOTE 6: Characterized with 8T49N285-902. NOTE 7: Characterized with 8T49N285-903. NOTE 8: This frequency is not supported for LVCMOS operation. NOTE 9: Characterized with 8T49N285-900. Table 12B. Typical RMS Phase Jitter (Jitter Attenuator Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C1, 2, 3, 4 Symbol Test Conditions LVPECL LVDS HCSL LVCMOS5 Units fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz6 279 285 276 276 fs fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz7 259 262 254 266 fs fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz8 216 195 194 N/A9 fs Q2, Q3 Integer6 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 311 310 303 306 fs Q2, Q3 Fractional10 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 269 269 261 266 fs Q4, Q5, Q6, Q76 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 298 302 291 288 fs Parameter Q0, Q1 tjit() RMS Phase Jitter (Random) NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Measured using a Rohde & Schwarz SMA100A as the input source. NOTE 3: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE 4: All outputs configured for the specific output type, as shown in the table. NOTE 5: Qx and nQx are 180° out of phase. NOTE 6: Characterized with 8T49N285-905. NOTE 7: Characterized with 8T49N285-906. NOTE 8: Characterized with 8T49N285-907. NOTE 9: This frequency is not supported for LVCMOS operation. NOTE 10: Characterized with 8T49N285-904. ©2021 Renesas Electronics Corporation. 45 March 8, 2021 8T49N285 Datasheet Table 13. PCI Express Jitter Specifications, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C1, 2 Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 8 16 86 ps tREFCLK_HF_RMS Phase Jitter (PCIe Gen 2) RMS4, 5, 6 ƒ = 100MHz, 40MHz Crystal Input, High Band: 1.5MHz - Nyquist (clock frequency/2) 0.8 1.8 3.1 ps tREFCLK_LF_RMS Phase Jitter (PCIe Gen 2) RMS 4, 5, 6 ƒ = 100MHz, 40MHz Crystal Input, Low Band: 10kHz - 1.5MHz 0.03 0.5 3.0 ps ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.2 0.5 0.8 ps Symbol tj (PCIe Gen 1) tREFCLK_RMS (PCIe Gen 3) Parameter Phase Jitter Peak-to-Peak 3, 4, 5 Phase Jitter RMS4, 5, 7 Test Conditions Minimum NOTE 1: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1. NOTE 4: This parameter is guaranteed by characterization. Not tested in production NOTE 5: Outputs configured for HCSL mode. Fox 277LF-40-18 crystal used with doubler logic enabled. NOTE 6: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 7: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. ©2021 Renesas Electronics Corporation. 46 March 8, 2021 8T49N285 Datasheet Noise Power (dBc/Hz) Typical Phase Noise at 156.25MHz Offset Frequency (Hz) ©2021 Renesas Electronics Corporation. 47 March 8, 2021 8T49N285 Datasheet Applications Information Overdriving the XTAL Interface The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 5A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 5B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the OSCI input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. Input signal duty cycle worse than 50% will result in phase noise degradation. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. 26&2 9&& 5  5R =R Ω 56 & 26&, M) =R 5R5V 5  /9&026B'ULYHU Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface OSCO C2 Zo = 50Ω OSCI 0.1μF Zo = 50Ω LVPECL_Driver R1 50 R2 50 R3 50 Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface ©2021 Renesas Electronics Corporation. 48 March 8, 2021 8T49N285 Datasheet Wiring the Differential Input to Accept Single-Ended Levels Figure 6 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 6. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2021 Renesas Electronics Corporation. 49 March 8, 2021 8T49N285 Datasheet 3.3V Differential Clock Input Interface CLKx/nCLKx accepts LVDS, LVHSTL, LVPECL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 7A to Figure 7E show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 7A, the input termination applies for Renesas open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 7A. CLKx/nCLKx Input Driven by an Renesas Open Emitter LVHSTL Driver Figure 7D. CLKx/nCLKx Input Driven by a 3.3V LVPECL Driver Figure 7B. CLKx/nCLKx Input Driven by a 3.3V LVPECL Driver Figure 7E. CLKx/nCLKx Input Driven by a 3.3V LVDS Driver 3.3V 3.3V *R3 CLK nCLK HCSL *R4 Differential Input Figure 7C. CLKx/nCLKx Input Driven by a 3.3V HCSL Driver ©2021 Renesas Electronics Corporation. 50 March 8, 2021 8T49N285 Datasheet 2.5V Differential Clock Input Interface CLKx/nCLKx accepts LVDS, LVHSTL, LVPECL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 8A to Figure 8D show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 8A, the input termination applies for Renesas open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 2.5V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK LVHSTL IDT Open Emitter LVHSTL Driver R1 50Ω R2 50Ω Differential Input Figure 8A. CLKx/nCLKx Input Driven by a Renesas Open Emitter LVHSTL Driver Figure 8C. CLKx/nCLKx Input Driven by a 2.5V LVPECL Driver Figure 8B. CLKx/nCLKx Input Driven by a 2.5V LVPECL Driver Figure 8D. CLKx/nCLKx Input Driven by a 2.5V LVDS Driver ©2021 Renesas Electronics Corporation. 51 March 8, 2021 8T49N285 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLKx/nCLKx Input LVPECL Outputs For applications not requiring the use one or more reference clock inputs, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLKx to ground. It is recommended that CLKx, nCLKx not be driven with active signals when not enabled for use. Any unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs Any unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace attached. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS Outputs Any LVCMOS output can be left floating if unused. There should be no trace attached. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. Renesas offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. LVDS Driver The standard termination schematic as shown in Figure 9A can be used with either type of output structure. Figure 9B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact Renesas and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT ZT LVDS Receiver Figure 9A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 9B. Optional Termination ©2021 Renesas Electronics Corporation. 52 March 8, 2021 8T49N285 Datasheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 10A and Figure 10B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are R3 125Ω 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω + _ Input Zo = 50Ω R1 84Ω Figure 10A. 3.3V LVPECL Output Termination ©2021 Renesas Electronics Corporation. R2 84Ω Figure 10B. 3.3V LVPECL Output Termination 53 March 8, 2021 8T49N285 Datasheet Termination for 2.5V LVPECL Outputs level. The R3 in Figure 11B can be eliminated and the termination is shown in Figure 11C. Figure 11A and Figure 11B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground 2.5V VCCO = 2.5V 2.5V 2.5V VCCO = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 11A. 2.5V LVPECL Driver Termination Example Figure 11C. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 11B. 2.5V LVPECL Driver Termination Example ©2021 Renesas Electronics Corporation. 54 March 8, 2021 8T49N285 Datasheet 2.5V and 3.3V HCSL Output Termination Figure 12A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output 0.5" Max L1 Rs types. All traces should be 50 impedance single-ended or 100 differential. L1 0.5 - 3.5" 1-14" 0-0.2" 22 to 33 +/-5% L2 L4 L2 L4 L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 12A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 12B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max L1 L1 Rs 0 to 33 0 to 33 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential. 0-18" 0-0.2" L2 L3 L2 L3 PCI Expres s Driver 49.9 +/- 5% Rt Figure 12B. Recommended Termination (where a point-to-point connection can be used) ©2021 Renesas Electronics Corporation. 55 March 8, 2021 8T49N285 Datasheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 13. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 13. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) Schematic and Layout Information Schematics for 8T49N285 can be found on Renesas.com. Please search for the 8T49N285 device and click on the link for evaluation board schematics. Crystal Recommendation This device was validated using FOX 277LF series through-hole crystals including part #277LF-40-18 (40MHz) and 277LF-38.88-2 (38.88MHz). If a surface mount crystal is desired, we recommend FOX Part #603-40-48 (40MHz) or 603-38.88-7 (38.88MHz). I2C Serial EEPROM Recommendation The 8T49N285 was designed to operate with most standard I2C serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used during device characterization and is recommended for use. Please contact Renesas for review of any other I2C EEPROM’s compatibility with the 8T49N285. ©2021 Renesas Electronics Corporation. 56 March 8, 2021 8T49N285 Datasheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) SerDes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   PCIe Gen 2A Magnitude of Transfer Function In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function PCIe Gen 3 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ©2021 Renesas Electronics Corporation. For a more thorough overview of PCI Express jitter analysis methodology, please refer to Renesas Application Note PCI Express Reference Clock Requirements. 57 March 8, 2021 8T49N285 Datasheet Power Dissipation and Thermal Considerations The 8T49N285 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. The 8T49N285 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the power consumption will be much lower. Please contact Renesas technical support for any concerns on calculating the power dissipation for your own specific configuration. Power Domains The 8T49N285 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). Figure 14 below indicates the individual domains and the associated power pins.                   CLK Input &  Divider Block  (Core Vcc)  Analog & Digital PLL0  (Core Vcc)  Output Divider / Buffer Q0 (Vcco0)  Output Divider / Buffer Q1 (Vcco1)  Output Divider / Buffer Q2 (Vcco2)  Output Divider / Buffer Q3 (Vcco3)  Output Divider / Buffer Q4 (Vcco4)  Output Divider / Buffer Q5 (Vcco5)  Output Divider / Buffer Q6 (Vcco6)  Output Divider / Buffer Q7 (Vcco7)  Figure 14. 8T49N285 Power Domains For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use a second structure and Q[4:7] use a 3rd structure. Power consumption data will vary slightly depending on the structure used as shown in the appropriate tables below. Power Consumption Calculation Determining total power consumption involves several steps: 1. Determine the power consumption using maximum current values for core and analog voltage supplies from Table 7A and Table 7B. 2. Determine the nominal power consumption of each enabled output path. 3. a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 15A through Table 15I (depending on the chosen output protocol). b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output frequency by the FQ_Factor shown in Table 15A through Table 15I. All of the above totals are then summed. ©2021 Renesas Electronics Corporation. 58 March 8, 2021 8T49N285 Datasheet Thermal Considerations Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 14 below. Please contact Renesas for assistance in calculating results under other scenarios. Table 14. Thermal Resistance JA for 56-Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.0°C/W 12.14°C/W 11.02°C/W Current Consumption Data and Equations Table 15A. 3.3V LVPECL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base_Current (mA) 0.00593 40.1 0.01363 63.8 0.00591 42.9 Table 15D. 2.5V LVPECL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15B. 3.3V HCSL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base_Current (mA) 0.00582 40.1 0.01358 63.8 0.00553 43.1 FQ_Factor (mA/MHz) Base_Current (mA) 0.00627 48.6 0.01404 72.5 0.00630 51.3 ©2021 Renesas Electronics Corporation. Base_Current (mA) 0.00373 32.8 0.01134 56.5 0.00369 35.7 Table 15E. 2.5V HCSL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15C. 3.3V LVDS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) FQ_Factor (mA/MHz) Base_Current (mA) 0.00354 32.9 0.01125 56.5 0.00353 35.7 Table 15F. 2.5V LVDS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 59 FQ_Factor (mA/MHz) Base_Current (mA) 0.00366 40.8 0.01148 64.5 0.00367 43.7 March 8, 2021 8T49N285 Datasheet Table 15G. 3.3V LVCMOS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15I. 1.8V LVCMOS Output Calculation Table Base_Current (mA) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 37.4 61.6 40.6 Base_Current (mA) 27.4 51.4 30.3 Table 15H. 2.5V LVCMOS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Base_Current (mA) 30.8 54.8 33.7 Applying the values to the following equation will yield output current by frequency: Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current where: Qx Current is the specific output current according to output type and frequency FQ_Factor is used for calculating current increase due to output frequency Base_Current is the base current for each output path independent of output frequency The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: TJ = TA + (JA * Pdtotal) where: TJ is the junction temperature (°C) TA is the ambient temperature (°C) JA is the thermal resistance value from Table 14, dependent on ambient airflow (°C/W) Pdtotal is the total power dissipation of the 8T49N285 under usage conditions, including power dissipated due to loading (W) Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs. When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 2) and output frequency: PdOUT = CPD * FOUT * VCCO2 where: PdOUT is the power dissipation of the output (W) CPD is the power dissipation capacitance (pF) FOUT is the output frequency of the selected output (MHz) VCCO is the voltage supplied to the appropriate output (V) ©2021 Renesas Electronics Corporation. 60 March 8, 2021 8T49N285 Datasheet Example Calculations Example 1. Common Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Output Type LVPECL LVPECL HCSL HCSL LVDS LVDS LVCMOS LVCMOS VCCO Frequency (MHz) 625 625 212.5 212.5 25 25 125 125 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 • Core Supply Current, ICC = 90mA (max) • Analog Supply Current, ICCA = 187mA (max) Q0 Current = 0.00593x625 + 40.1 = 43.8mA Q1 Current = 0.00593x625 + 40.1 = 43.8mA Q2 Current = 0.01358x212.5 + 63.8 = 66.69mA Q3 Current = 0.01358x212.5 + 63.8 = 66.69mA Q4 Current = 0.00630x25 + 51.3 = 51.46mA Q5 Current = 0.00630x25 + 51.3 = 51.46mA Q6 Current = 40.6mA Q7 Current = 40.6mA • Total Output Current = 405.1mA (max) Total Device Current = 90mA + 187mA + 405.1mA = 682.1mA Total Device Power = 3.465V * 682.1mA = 2363.5mW • Power dissipated through output loading: LVPECL = 27.95mW * 2 = 55.9mW HCSL = 44.5mW * 2 = 89mW LVDS = already accounted for in device power LVCMOS = 14.5pF * 125MHz * 3.465V2 * 2 output pairs = 43.5mW • Total Power = 2363.5mW + 55.9mW + 89mW + 43.5mW = 2551.9mW or 2.55W With an ambient temperature of 85°C and no airflow, the junction temperature is: TJ = 85°C + 16.0°C/W * 2.55W = 125.8°C This junction temperature is above the maximum allowable. In instances where maximum junction temperature is exceeded adjustments need to be made to either airflow or ambient temperature. In this case, adjusting airflow to 1m/s (JA = 12.14°C/W) will reduce junction temperature to 116°C. If no airflow adjustments can be made, the maximum ambient operating temperature must be reduced by a minimum of 0.8°C. ©2021 Renesas Electronics Corporation. 61 March 8, 2021 8T49N285 Datasheet Example 2. High-Frequency Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Output Type LVDS LVDS LVDS LVCMOS LVCMOS LVCMOS LVCMOS LVDS Frequency (MHz) 156.25 156.25 161.133 33.333 25 25 25 156.25 VCCO 2.5 2.5 2.5 1.8 1.8 1.8 1.8 2.5 • Core Supply Current, ICC = 85mA (max) • Analog Supply Current, ICCA = 182mA (max) Q0 Current = 0.00366x156.25 + 40.8 = 41.37mA Q1 Current = 0.00366x156.25 + 40.8 = 41.37mA Q2 Current = 0.01148x161.133 + 64.5 = 66.35mA Q3 Current = 51.4mA Q4 Current = 30.3mA Q5 Current = 30.3mA Q6 Current = 30.3mA Q7 Current = 0.00367x156.25 + 43.7 = 44.27mA • Total Output Current = 193.36mA (VCCO = 2.5V), 142.3mA (VCCO = 1.8V) Total Device Power = 2.625V *(85mA + 182mA + 193.36mA) + 1.89V * 142.3mA = 1477.4mW • Power dissipated through output loading: LVPECL = n/a LVDS = already accounted for in device power LVCMOS_33.3MHz = 17pF * 33.3MHz * 1.89V2 * 1 output pair = 2.02mW LVCMOS_25MHz = 12.5pF * 25MHz * 1.89V2 * 3 output pairs = 3.35mW Total Power = 1477.4mW + 2.02mW + 3.35mW = 1482.77mW or 1.48W With an ambient temperature of 85°C, the junction temperature is: TJ = 85°C + 16.0°C/W *1.48W = 108.7°C This junction temperature is below the maximum allowable. ©2021 Renesas Electronics Corporation. 62 March 8, 2021 8T49N285 Datasheet Reliability Information Table 16. JA vs. Air Flow Table for a 56-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.0°C/W 12.14°C/W 11.02°C/W NOTE: Theta JA (JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70m) copper plating on all 4 layers. Transistor Count The transistor count for 8T49N285 is: 998,958 Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. Marking Diagram 1. Line 1 (excluding “IDT”) and Line 2 indicate the part number. “001” will vary due to configuration. 2. Line 3 indicates the following: ▪ “#” denotes the stepping mark. ▪ “YYWW” is the last two digits of the year and week that the part was assembled. ▪ “$” denotes the mark code. ©2021 Renesas Electronics Corporation. 63 March 8, 2021 8T49N285 Datasheet Ordering Information Table 17. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T49N285A-dddNLGI IDT8T49N285A-dddNLGI 56-Lead VFQFN, Lead-Free Tray -40C to +85C 8T49N285A-dddNLGI8 IDT8T49N285A-dddNLGI 56-Lead VFQFN, Lead-Free Tape & Reel, Pin 1 Orientation: EIA-481-C -40C to +85C 8T49N285A-dddNLGI# IDT8T49N285A-dddNLGI 56-Lead VFQFN, Lead-Free Tape & Reel, Pin 1 Orientation: EIA-481-D -40C to +85C NOTE: For the specific, publicly available -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document. For custom -ddd order codes, please contact Renesas for more information. Table 18. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION NLGI8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION NLGI# CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED ©2021 Renesas Electronics Corporation. 64 March 8, 2021 8T49N285 Datasheet Revision History Revision Date Description of Change March 8, 2021 • Updated Figure 5A • Completed other minor changes July 15, 2020 • Corrected the Marking Diagram description • Changed IDT references to Renesas January 21, 2019 • Corrected the I2C read sequence diagrams in Figure 3 and Figure 4 to match I2C specification and device actual performance. Note: Only the drawings were incorrect – the part’s behavior did not change and continues to meet the I2C specification. • Added a Marking Diagram January 31, 2018 September 8, 2017 • Updated I2C Mode Operation to indicate support for v2.1 of the I2C specification • Added a note preceding Digital PLL Status Register Bit Field Locations and Descriptions. • Added the following fields to Digital PLL Status Register Bit Field Locations and Descriptions: NO_REF, SM_STS, and PLLLCK. • Updated the package outline drawings; however, no mechanical changes. October 26, 2016 Page 56, Crystal Recommendation - deleted IDT crystal reference. January 29, 2016 T17-page 64, Per PCN# W1512-01, Effective Date 03/18/2016 - changed Part/Order Number from 8T49N285-dddNLGI to 8T49N285A-dddNLGI, and Marking from IDT8T49N285-dddNLGI to IDT8T49N285A-dddNLGI. Updated Datasheet header/footer. June 29, 2015 T11A, pages 11, 41, 53, and 56 Device Start-up & Reset Behavior - added additional information (second paragraph). AC Characteristics Table - added missing minimum Output Frequency spec for Q2, Q3 (LVPECL, LVDS) and LVCMOS. “Termination for 3.3V LVPECL Outputs” - updated Figure 10A. “Crystal Recommendation” - included additional crystal recommendation. Deleted IDT prefix/suffix throughout the datasheet. ©2021 Renesas Electronics Corporation. 65 March 8, 2021 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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