8V97003NLGI8

171.875MHz to 18GHz RF / mmWave Wideband Synthesizer with Integrated VCO 8V97003 Datasheet Description Features The 8V97003 is a high-performance mmWave wideband Synthesizer / Phase Lock Loop (PLL) that generates output frequencies up to 18GHz from an integrated Voltage Controlled Oscillator (VCO) offering an octave of frequency tuning range. The device also offers a high-performance 32-bit fractional feedback divider and an output divider to allow users to fully benefit from the wideband characteristics of the VCO. ▪ Output frequency range: 171.875MHz to 18GHz ▪ Ultra-low phase noise VCO • -60.6dBc integrated phase jitter (35fs rms jitter) from 20kHz to 100MHz at 6GHz ▪ Figure of Merit: -236dBc/Hz ▪ Input reference frequency: • 10MHz to 1.6GHz (LVPECL, LVDS) • 10MHz to 250MHz (LVCMOS) The device's figure of merit (FOM) of -236dBc/Hz and the excellent VCO performance allow for very low phase noise and RMS phase jitter. ▪ Fractional-N synthesizer and integer-N synthesizer ▪ 32-bit of fractional and modulus resolution ▪ Phase frequency detector (PFD) operation up to 500MHz The 8V97003 offers a very low output-to-output phase skew drift of < 10° across all operating conditions and frequencies, reducing radio path recalibration occurrences in beamforming applications, such as 5G radio card massive MIMO systems. (Integer mode) or 250MHz (Fractional mode) ▪ Programmable RF output power levels ▪ RF output power < -80dBm when in MUTE ▪ Programmable input multiplier (MULT) to increase PFD The output drivers have programmable output power settings and can deliver high single-ended output power up of +12dBm at 8GHz, and +4dBm at 18GHz, when using inductively loaded output terminations (double termination). When the outputs are resistively loaded, the output drivers can deliver a single-ended output power of +9.5dBm at 8GHz, and up to -2.5dBm at 18GHz. The output power can be further increased when using differential outputs and measuring the output power differentially. frequency when using a low input frequency ▪ -40°C to +95°C ambient temperature range; and up to +105°C board temperature The 8V97003 relies on a single 3.3V power supply and offers low noise integrated LDOs for excellent power supply noise immunity. ▪ ▪ ▪ ▪ Typical Applications Simplified Block Diagram ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ 3.3V single power supply operation 7 7 mm 48-VFQFPN package SPI interface is compatible with 1.8V logic and tolerant to 3.3V Supported in the Timing CommanderTM design tool Loop Filter 5G millimeter wave wireless infrastructure Massive MIMO Phase Array Antennas and beam forming x2 Clock Input Wireless backhaul Point-to-point and point-to-multipoint microwave links SPI Satellites / VSATs Test equipment/instrumentation x2 Registers ÷R 2x RF Out PLL 16-Bit Integer + 32-Bit Fractional ÷M0 0.171-18GHz Clock generation High-speed RF converters sampling clocks Radar ©2021 Renesas Electronics Corporation 1 April 8, 2021 8V97003 Datasheet Block Diagram 8V97003 Lock Detect MULT REF_IN nREF_IN ÷R LD Charge Pump PFD x2 CPOUT External Loop Filter VTUNE 16-bit Int / 32-bit Frac Divider SDO SDIO SCLK CSB nRESET SPI RF_OUTA nRF_OUTA /M0 CE Logic and Registers x2 RF_OUTB nRF_OUTB SYNC MUTE ©2021 Renesas Electronics Corporation 2 April 8, 2021 8V97003 Datasheet Contents Description ........................................................................................................................................................................................................... 1 Typical Applications.............................................................................................................................................................................................. 1 Features ............................................................................................................................................................................................................... 1 Simplified Block Diagram ..................................................................................................................................................................................... 1 Block Diagram ...................................................................................................................................................................................................... 2 Contents ................................................................................................................................................................................................................ 3 Pin Assignments................................................................................................................................................................................................... 8 Pin Descriptions ................................................................................................................................................................................................... 8 Absolute Maximum Ratings................................................................................................................................................................................ 11 Recommended Operating Conditions ................................................................................................................................................................ 11 Thermal Characteristics and Reliability Information ........................................................................................................................................... 12 DC Electrical Characteristics ............................................................................................................................................................................. 12 AC Electrical Characteristics .............................................................................................................................................................................. 15 Typical Performance Characteristics.................................................................................................................................................................. 18 Theory of Operation ........................................................................................................................................................................................... 21 Synthesizer Programming........................................................................................................................................................................... 22 Reference Input Stage ................................................................................................................................................................................ 22 Input Reference Divider (R) ........................................................................................................................................................................ 23 Reference Doubler...................................................................................................................................................................................... 23 Reference Multiplier (MULT)....................................................................................................................................................................... 23 Feedback Divider ........................................................................................................................................................................................ 23 Phase and Frequency Detector (PFD) and Charge Pump.......................................................................................................................... 25 PFD Frequency........................................................................................................................................................................................... 25 External Loop Filter..................................................................................................................................................................................... 25 Charge Pump High-Impedance................................................................................................................................................................... 25 Integrated Low Noise VCO ......................................................................................................................................................................... 26 Output Clock Distribution and Optional Output Doubler.............................................................................................................................. 26 Output Matching.......................................................................................................................................................................................... 27 Band Selection Disable............................................................................................................................................................................... 27 Phase Adjust............................................................................................................................................................................................... 28 RF Output Power ........................................................................................................................................................................................ 28 Output Phase Synchronization.................................................................................................................................................................... 28 Input-to-Output .................................................................................................................................................................................. 28 Output Phases of Multiple 8V97003 Devices .................................................................................................................................... 28 Power-Down Mode...................................................................................................................................................................................... 29 Default Power-Up Conditions...................................................................................................................................................................... 29 VCO Calibration .......................................................................................................................................................................................... 29 3- or 4-Wire SPI Interface Description................................................................................................................................................................ 29 3/4-Wire Mode............................................................................................................................................................................................. 29 Active Clock Edge....................................................................................................................................................................................... 29 Reset........................................................................................................................................................................................................... 29 Least Significant Bit Position....................................................................................................................................................................... 30 Addressing .................................................................................................................................................................................................. 30 Read Operation........................................................................................................................................................................................... 30 Mirrored Register Bits ................................................................................................................................................................................. 30 Double-Buffered Registers.......................................................................................................................................................................... 30 Operation Protocols .................................................................................................................................................................................... 31 ©2021 Renesas Electronics Corporation 3 April 8, 2021 8V97003 Datasheet Register Map ...................................................................................................................................................................................................... 35 Register Block Descriptions ........................................................................................................................................................................ 38 Preface Registers........................................................................................................................................................................................ 39 Feedback Divider Control Registers ........................................................................................................................................................... 41 Phase Adjustments Control Registers ........................................................................................................................................................ 43 DSM Control Registers ............................................................................................................................................................................... 44 Calibration Control Registers ...................................................................................................................................................................... 45 Band Select Clock Divider Control Registers.............................................................................................................................................. 46 Lock Detect Control Registers .................................................................................................................................................................... 47 Power Down Control Registers................................................................................................................................................................... 48 Input Control Registers ............................................................................................................................................................................... 49 Charge Pump Control Registers ................................................................................................................................................................. 51 Re-Sync Control Registers.......................................................................................................................................................................... 52 Output Control Registers............................................................................................................................................................................. 53 Status Registers.......................................................................................................................................................................................... 55 Applications Information ..................................................................................................................................................................................... 56 Loop Filter Calculations............................................................................................................................................................................... 56 2nd Order Loop Filter ........................................................................................................................................................................ 56 3rd Order Loop Filter ......................................................................................................................................................................... 58 Recommendations for Unused Input and Output Pins................................................................................................................................ 59 Inputs................................................................................................................................................................................................. 59 Outputs.............................................................................................................................................................................................. 59 Schematic Example .................................................................................................................................................................................... 59 Power Considerations ........................................................................................................................................................................................ 60 Package Outline Drawings ................................................................................................................................................................................. 61 Marking Diagram ............................................................................................................................................................................................... 61 Ordering Information .......................................................................................................................................................................................... 62 Revision History ................................................................................................................................................................................................. 63 ©2021 Renesas Electronics Corporation 4 April 8, 2021 8V97003 Datasheet List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View ................................................................................................... 8 Phase Noise at 6GHz (Fractional Mode).......................................................................................................................................... 18 Phase Noise at 6GHz (Integer Mode) .............................................................................................................................................. 18 Phase Noise at 8GHz (Integer Mode) .............................................................................................................................................. 19 Phase Noise at 11GHz (Integer Mode) ............................................................................................................................................ 19 Phase Noise at 18GHz (Integer Mode) ............................................................................................................................................ 20 Phase Noise at 8GHz (Open Loop).................................................................................................................................................. 20 Typical Output Power vs. RF Output Frequency (Over Different Loads).......................................................................................... 21 Test Setup for RF Output Power Measurement ............................................................................................................................... 21 Input Reference Path........................................................................................................................................................................ 22 RF Feedback N Divider .................................................................................................................................................................... 23 Simplified PFD Circuit using D-type Flip-Flop................................................................................................................................... 25 Output Clock Distribution ................................................................................................................................................................. 26 Output Stage .................................................................................................................................................................................... 26 Resistive Matching Termination ...................................................................................................................................................... 27 Inductively Loaded Termination ....................................................................................................................................................... 27 4-Wire MSB First, Single Byte Write and Read ................................................................................................................................ 31 4-Wire LSB First, Single Byte Write and Read ................................................................................................................................. 32 4-Wire MSB First, Multiple Bytes Write (2 Bytes Shown as Example) ............................................................................................. 32 4-Wire LSB First, Multiple Bytes Read (2 Bytes Shown as Example) .............................................................................................. 33 3-Wire MSB First, Single Byte Read and Write ................................................................................................................................ 33 SPI Timing Diagram ......................................................................................................................................................................... 34 Typical 2nd Order Loop Filter............................................................................................................................................................ 56 Typical 3rd Order Loop Filter ........................................................................................................................................................... 58 Loop Filter Example.......................................................................................................................................................................... 58 Schematic Example.......................................................................................................................................................................... 60 ©2021 Renesas Electronics Corporation 5 April 8, 2021 8V97003 Datasheet List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Pin Descriptions .................................................................................................................................................................................. 8 Pin Characteristics ............................................................................................................................................................................ 10 Supply Pins and Associated Current Return Paths........................................................................................................................... 10 Absolute Maximum Ratings .............................................................................................................................................................. 11 Recommended Operating Conditions............................................................................................................................................... 11 Thermal Characteristics .................................................................................................................................................................... 12 Thermal Resistance θJA for 48-VFQFPN, Forced Convection......................................................................................................... 12 Power Supply DC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.) ...... 12 Typical Current by Power Domain .................................................................................................................................................... 13 LVCMOS DC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.) ............. 14 AC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Maximum Board or Junction Temp.)...................... 15 RF_OUT[A:B] Phase Noise Char., VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.) ...... 16 Fractional Spurs Due to the Quantization Noise............................................................................................................................... 24 Timing Requirements........................................................................................................................................................................ 28 SPI Read / Write Cycle Timing Parameters...................................................................................................................................... 34 Preface Registers ............................................................................................................................................................................. 35 Control Registers .............................................................................................................................................................................. 35 Status Registers................................................................................................................................................................................ 37 Register Block Descriptions .............................................................................................................................................................. 38 Preface Register Block ..................................................................................................................................................................... 39 Preface Register Bits ........................................................................................................................................................................ 39 Preface Register Description ............................................................................................................................................................ 40 Feedback Divider Control Block........................................................................................................................................................ 41 Feedback Divider Control Register Bits ............................................................................................................................................ 41 Feedback Divider Control Register Description ................................................................................................................................ 42 Phase Adjustments Control Register Block ...................................................................................................................................... 43 Phase Adjustments Control Register Bits ......................................................................................................................................... 43 Phase Adjustments Control Register Descriptions ........................................................................................................................... 43 DSM Control Register Block ............................................................................................................................................................. 44 DSM Control Register Bits ................................................................................................................................................................ 44 DSM Control Register Descriptions .................................................................................................................................................. 44 Calibration Control Register Block .................................................................................................................................................... 45 Calibration Control Register Bits....................................................................................................................................................... 45 Calibration Control Register Descriptions ......................................................................................................................................... 45 Band Select Clock Divider Control Register Block............................................................................................................................ 46 Band Select Clock Divider Control Register Bits............................................................................................................................... 46 Band Select Clock Divider Control Register Descriptions................................................................................................................. 46 Lock Detect Control Register Block .................................................................................................................................................. 47 Lock Detect Control Register Bits ..................................................................................................................................................... 47 Lock Detect Control Register Descriptions ....................................................................................................................................... 47 Power Down Control Register Block................................................................................................................................................. 48 Power Down Control Register Bits.................................................................................................................................................... 48 Power Down Control Register Descriptions...................................................................................................................................... 48 Input Control Register Block ............................................................................................................................................................. 49 Input Control Register Bits ................................................................................................................................................................ 49 Input Control Register Descriptions .................................................................................................................................................. 49 Charge Pump Control Register Block ............................................................................................................................................... 51 Charge Pump Control Register Bits.................................................................................................................................................. 51 ©2021 Renesas Electronics Corporation 6 April 8, 2021 8V97003 Datasheet Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Charge Pump Control Register Descriptions .................................................................................................................................... 51 Re-Sync Control Register Block........................................................................................................................................................ 52 Re-sync Control Register Bits........................................................................................................................................................... 52 Re-sync Control Register Descriptions ............................................................................................................................................. 52 Output Control Register Block........................................................................................................................................................... 53 Output Control Register Bits ............................................................................................................................................................. 53 Output Control Register Descriptions................................................................................................................................................ 53 Status Register Block........................................................................................................................................................................ 55 Status Register Bits .......................................................................................................................................................................... 55 Status Register Descriptions............................................................................................................................................................. 55 Ordering Information ......................................................................................................................................................................... 62 Pin 1 Orientation in Tape and Reel Packaging ................................................................................................................................. 62 ©2021 Renesas Electronics Corporation 7 April 8, 2021 8V97003 Datasheet Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View VREFVCO2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 VREFVCO1 NC NC 2 35 VDDVCO2 3 34 NC VREGVCO2 4 33 VDDVCO1 VTUNE 5 32 VREGVCO1 NC 6 31 nRESET MUTE 7 30 SYNC LD 8 29 CE NC 9 28 SDIO CPOUT 10 27 SDO CPBIAS 11 26 SCLK VDDPDCP 8V97003 25 12 13 14 15 16 17 18 19 20 21 22 23 24 CSB Pin Descriptions Table 1. Pin Descriptions Pull-up/ Pull-Down Pin Number Name Type 1 VREFVCO2 Analog Reference node for VCO regulator. Connect 22µF capacitor from this pin to GND. 2 NC Unused Do not connect. 3 VDDVCO2 Power VDD power supply for VCO. 4 VREGVCO2 Analog Regulator for VCO. Connect 22µF capacitor from this pin to GND. 5 VTUNE Analog VCO Tuning Voltage. 6 NC Unused Do not connect. 7 MUTE Input 8 LD Output Lock Detector (CMOS). 9 NC Unused Do not connect. 10 CPOUT Analog Charge Pump Output. ©2021 Renesas Electronics Corporation PD Description Outputs disable / High-Impedance. 1.8V LVCMOS logic levels (3.3V tolerant). 8 April 8, 2021 8V97003 Datasheet Table 1. Pin Descriptions (Cont.) Pull-up/ Pull-Down Pin Number Name Type Description 11 CPBIAS Analog Bias node for charge pump. Connect 22µF capacitor from this pin to GND. 12 VDDPDCP Power VDD power supply for phase detector and charge pump. 13 NC Unused Do not connect. 14 VSSPDCP Ground VSS power supply ground for phase detector and charge pump. 15 VDDFB Power VDD power supply for feedback divider. 16 NC Unused Do not connect. 17 VSSFB Ground VSS power supply ground for feedback divider. 18 VDDDIG Power VDD power supply for Digital, SPI and SDM. 19 VSSDIG Ground VSS power supply ground for Digital, SPI and SDM. 20 VSSIN Ground VSS power supply ground for reference input path. 21 NC Unused Do not connect. 22 REF_IN Input PD 23 nREF_IN Input PD/PU 24 VDDIN Power 25 CSB Input 26 SCLK Input 27 SDO Output 28 SDIO Input/Output PU SPI Data Input/ Output. 1.8V LVCMOS logic levels (3.3V tolerant). 29 CE Input PU Chip Enable. 1.8V LVCMOS logic levels (3.3V tolerant). CE = 0: Power-down mode CE = 1: Normal operation Differential reference clock input+ (LVDS, LVPECL, CMOS). Differential reference clock input– (LVDS, LVPECL). VDD power supply for reference input path. PD SPI Chip Select Bar. 1.8V LVCMOS logic levels (3.3V tolerant). SPI Clock Input. 1.8V LVCMOS logic levels (3.3V tolerant). SPI Data Output. 30 SYNC Input PD SYNC pin can be used to implement a deterministic delay between the reference input rising edge and the output signal rising edge. If not used, this pin can either be tied to ground, or left floating since it has an internal pulldown. 3.3V LVCMOS input. 31 nRESET Input PU Chip Reset. 1.8V LVCMOS logic levels (3.3V tolerant). 32 VREGVCO1 Analog Regulator for VCO. Connect 22µF capacitor from this pin to GND. 33 VDDVCO1 Power VDD power supply for VCO. 34 NC Unused Do not connect. 35 VREFVCO1 Analog Reference node for VCO regulator. Connect 22µF capacitor from this pin to GND. 36 NC Unused Do not connect. 37 VDDOUTA Power VDD output power supply for output pair A. 38 VSSOUTA Ground VSS power supply ground for output pair A. 39 nRF_OUTA Output Negative side of output pair A (CML – Open Collector). The output power level is programmable. ©2021 Renesas Electronics Corporation 9 April 8, 2021 8V97003 Datasheet Table 1. Pin Descriptions (Cont.) Pull-up/ Pull-Down Pin Number Name Type Description 40 RF_OUTA Output Positive side of output pair A (CML – Open Collector). The output power level is programmable. 41 VSSOUTA Ground VSS power supply ground for output pair A. 42 NC Analog Do not connect. 43 NC Analog Do not connect. 44 VSSOUTB Ground VSS power supply ground for output pair B. 45 RF_OUTB Output Positive side of output pair B (CML – open collector). The output power level is programmable. 46 nRF_OUTB Output Negative side of output pair B (CML – open collector). The output power level is programmable. 47 VSSOUTB Ground VSS power supply ground for output pair B. 48 VDDOUTB Power VDD output power supply output pair B. EP EPAD Ground Must be connected to ground. Table 2. Pin Characteristics Symbol Parameter Test Condition Minimum Typical Maximum Units CIN Input Capacitance REF_IN, nREF_IN 1 pF ROUT LVCMOS Output Impedance LD 15 Ω RPULLUP Input Pullup Resistor 50 kΩ RPULLDOWN Input Pulldown Resistor 50 kΩ Table 3. Supply Pins and Associated Current Return Paths Power Supply Associated Ground Pin Number Pin Name Pin Number Pin Name 3 VDDVCO2 EP EPAD 12 VDDPDCP 14 VSSPDCP 15 VDDFB 17 VSSFB 18 VDDDIG 19 VSSDIG 24 VDDIN 20 VSSIN 33 VDDVCO1 EP EPAD 37 VDDOUTA 38; 41 VSSOUTA 48 VDDOUTB 44; 47 VSSOUTB ©2021 Renesas Electronics Corporation 10 April 8, 2021 8V97003 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 8V97003 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 4. Absolute Maximum Ratings[a] Symbol VDDx[b] Parameter Supply Voltage Rating Units 3.63 V VI Input Voltage (REF_IN, nREF_IN, MUTE, SDIO, VTUNE, SCLK, CSB, CE, nRESET, and SYNC) -0.5 to VDDx[a] +0.5 V Vo Output Voltage (RF_OUTA, nRF_OUTA, RF_OUTB, nRF_OUTB, LD, CPOUT, SDIO, SDO) -0.5 to VDDx[a] +0.5 V I0 Output Current Continuous Current 60 mA Surge Current 90 mA I0 Output Current (SDO, SDIO, LD) Continuous Current 40 mA Surge Current 65 mA TJ Maximum Junction Temperature 150 °C TS Storage Temperature -65 to 150 °C — ESD – Human Body Model 2000 V — ESD – Charged Device Model 750 V [a] Over operating ambient temperature range (unless otherwise indicated). [b] VDDx denotes, VDDVCO2, VDDPDCP, VDDFB, VDDDIG, VDDIN, VDDVCO1, VDDOUTA, VDDOUTB. Recommended Operating Conditions Table 5. Recommended Operating Conditions[a][b] Symbol TA Parameter Minimum Ambient Air Temperature Typical -40 Maximum Units +95 °C TB Board Temperature [c] +105 °C TJ Junction Temperature +125 °C [a] It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed. [b] All conditions in this table must be met to guarantee device functionality. [c] Measured at solder connection to printed circuit board on exposed pad. ©2021 Renesas Electronics Corporation 11 April 8, 2021 8V97003 Datasheet Thermal Characteristics and Reliability Information Table 6. Thermal Characteristics Symbol Parameter Value Units θJB Theta JB. Junction to board 0.76 °C/W θJC Theta JC. Junction to case 10.33 °C/W Table 7. Thermal Resistance θJA for 48-VFQFPN, Forced Convection θJA by Velocity Air Flow Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 m/s 22.3 18.84 17.3 °C/W DC Electrical Characteristics Table 8. Power Supply DC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.)[a][b][c] Symbol VDDx [d] IDDx[e] IVCO — Parameter Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V RF_OUTA, nRF_OUTA – Active RF_OUTB, nRF_OUTB – Muted 516 590 mA RF_OUTA, nRF_OUTA – Active RF_OUTB, nRF_OUTB – Active 566 650 mA RF_OUTA, nRF_OUTA – Muted RF_OUTB, nRF_OUTB – Muted 464 538 mA VCO Frequency = 6GHz 225 271 mA VCO Frequency = 6GHz, CE = Low, VCO_EN = 1 250 302 mA CE = Low, VCO_EN = 0[h] 71 90 mA Power Supply Voltage Power Supply Current[f] VCO Supply Current Power Down Current[g] [a] RF outputs terminated to 50Ω to VDDOUT[A:B]. [b] Output power set to 0101 (see RF_OUTx_pwr[3:0] in Table 55). [c] Over Recommended Operating Conditions (unless otherwise indicated). [d] VDDx denotes, VDDVCO2, VDDPDCP, VDDFB, VDDDIG, VDDIN, VDDVCO1, VDDOUTA, VDDOUTB. [e] IDDx denotes IDDVCO2, IDDPDCP, IDDFB, IDDDIG, IDDIN, IDDVCO1, IDDOUTA, IDDOUTB. [f] Input Frequency = 122.88MHz, Input Doubler Enabled, Output Frequency = 6GHz; PLL is in Fractional mode. [g] VCO_EN is located in register 0x28, bit position 0. CE: Chip Enable, pin 29. [h] Power Down Current with VCO_EN = 0 and CE = Low is independent of the VCO frequency. ©2021 Renesas Electronics Corporation 12 April 8, 2021 8V97003 Datasheet Table 9. Typical Current by Power Domain[a][b] Pin Name Pin Number VDDVCO2, VDDVCO1[c] 3, 33 VDDPDCP 12 VDDFB 15 VDDDIG VDDIN VDDOUTA VDDOUTB 18 24 37 48 Condition Typical Unit 270 mA 65 mA 49 mA PFD frequency: 245.76MHz DSM setting: 3rd Order (Fractional mode) 34 mA PFD frequency: 245.76MHz DSM OFF (Integer Mode) 23 mA Input doubler OFF, MULT OFF, Input divider OFF 36 mA RF_OUT Disabled 10 mA RF_OUTA Enabled; RF Output Power Setting: 0001 (Minimum setting) 43 mA RF_OUTA Enabled; RF Output Power Setting: 1100 (Maximum setting) 82 mA RF_OUTB Disabled 54 mA RF_OUTB Enabled; RF Output Power Setting: 0001 (Minimum setting) 88 mA RF_OUTB Enabled; RF Output Power Setting: 1100 (Maximum setting) 126 mA RF_OUTB Enabled; RF Output Power Setting: 1100; Output doubler ON 137 mA RF_OUTB Enabled; RF Output Power Setting: 0010; Output Divider: Divide by 2 89 mA 8GHz VCO frequency ICP = 8mA [a] Operating conditions are: REF_IN = 122.88MHz; RF_OUTA = RF_OUTB = 8GHz. [b] Over Recommended Operating Conditions (unless otherwise indicated). [c] Total current from VDDVCO1 and VDDVCO2 (externally connected). ©2021 Renesas Electronics Corporation 13 April 8, 2021 8V97003 Datasheet Table 10. LVCMOS DC Characteristics, VDDx[a] = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.)[b] Symbol VIH Parameter Input High Voltage Test Conditions Maximum Units 1.2 VDDx[a] V 2 VDDx[a] V nRESET, CE, MUTE, CSB, SCLK, SDIO 0.65 V SYNC 0.8 nRESET, CE, MUTE, CSB, SCLK, SDIO SYNC VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage VOL Output Low Voltage Minimum Typical nRESET, CE, SDIO VDDx = VIN = 3.465V 5 µA CSB, MUTE, SYNC VDDx = VIN = 3.465V 150 µA nRESET, CE, SDIO VDDx = 3.465V, VIN = 0V -150 µA CSB, MUTE, SYNC VDDx = 3.465V, VIN = 0V -5 µA VDDx = 3.465V, IOH = -2mA 2.4 V SDO, SDIO[c], LD SDO, SDIO[c], LD VDDx = 3.465V, IOL = 2mA 0.4 V [a] VDDx denotes, VDDVCO2, VDDPDCP, VDDFB, VDDDIG, VDDIN, VDDVCO1, VDDOUTA, VDDOUTB. [b] Over Recommended Operating Conditions (unless otherwise indicated). [c] SDIO as output. ©2021 Renesas Electronics Corporation 14 April 8, 2021 8V97003 Datasheet AC Electrical Characteristics Table 11. AC Characteristics, VDDx[a] = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Maximum Board or Junction Temp.)[b] Symbol Parameter REF_IN Input Reference Frequency Test Conditions Minimum Typical Maximum Units Reference doubler disabled 10 1600 MHz Reference doubler enabled 10 250 MHz 0.4 VDDx[a] V VDDx/2[c] VPP REF_IN Input Sensitivity Biased at fVCO VCO Frequency Fundamental VCO mode 5,500 11,000 MHz Output doubler disabled 171.875 11,000 MHz Output doubler enabled 11,000 18,000 MHz Fractional mode 250 MHz Integer mode 500 MHz fRF_OUT fPFD KVCO Output Frequency PFD Frequency VCO Sensitivity[d] VCO Frequency = 5.625GHz 100 VCO Frequency = 6.23GHz 120 VCO Frequency = 6.975GHz 140 VCO Frequency = 7.8GHz 160 VCO Frequency = 8.65GHz 210 VCO Frequency = 9.575GHz 165 VCO Frequency = 10.3GHz 155 VCO Frequency = 10.9GHz 170 PLL Lock Time[e] Time from Low to High of CSB until Low to High of LD 1 ms Frequency Lock Time One frequency to another frequency locking time when VCO calibration is bypassed. 70 µs < -80 dBm RF_OUT = 8GHz 9.5 dBm RF_OUT = 18GHz -2.5 dBm RF_OUT = 8GHz 5 dBm RF_OUT = 18GHz -6.5 dBm RF_OUTn_pwr = 1100 (max) 1nH Inductive Loading RF_OUT = 8GHz 12 dBm RF_OUTn_pwr = 1100 (max) 0.6nH Inductive Loading RF_OUT = 18GHz 4 dBm RF_OUT at 11GHz ±2 dBm RF_OUT from 11GHz to 18GHz ±4 dBm 0.3/2.2 V tLOCK Muted RF_OUTn_pwr = 1100 (max) 50-ohm Resistive Loading - MHz/V Single-Ended RF Output Power[f] - RF Output Power Variation Across Temperature[g] - Min/Max VCO Tuning Voltage ©2021 Renesas Electronics Corporation RF_OUTn_pwr = 0110 50-ohm Resistive Loading 15 April 8, 2021 8V97003 Datasheet Table 11. AC Characteristics, VDDx[a] = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Maximum Board or Junction Temp.)[b] (Cont.) Symbol Parameter Test Conditions Minimum Typical - Output-to-Output Skew - Output-to-Output Skew Drift Any value of fRF_OUT. Measurement taken from -40°C to +95°C. 2 - Input-to-Output Skew Drift Any value of fRF_OUT. Measurement taken from -40°C to +95°C. 9 Maximum Units 5 ps 10 ° ps [a] VDDx denotes VDDVCO2, VDDPDCP, VDDFB, VDDDIG, VDDIN, VDDVCO1, VDDOUTA, VDDOUTB. [b] Over Recommended Operating Conditions (unless otherwise indicated). [c] AC-coupling the reference signal ensures VDDx / 2 biasing. [d] The value depends on VCO frequency. [e] Band Select/Calibration Resolution = 4x (BandSelAcc[1:0]=10), fPFD/BndSelDiv ~100kHz. [f] Single-Ended RF Output Power values are based on after de-embedding the trace and cable losses while other output is connected with same length of cable and terminated to 50ohm resistor. For test setup, see Figure 9. For output terminations, see Figure 26. [g] Output Power setting = 0110b. Table 12. RF_OUT[A:B] Phase Noise Char., VDDx[a] = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.)[b] Symbol tjit(Ø) Parameter Integrated Phase Noise/Jitter ΦN(10k) ΦN(100k) ΦN(1M) ΦN(10M) RF Output Phase Noise Performance at 6GHz (Open Loop) ΦN(60M) ©2021 Renesas Electronics Corporation Test Conditions Typical Maximum Units fRF_OUT = 6GHz Integration Range: 20kHz – 100MHz PFD = 245.76MHz (Fractional Mode) -55 -48.8 dBc fRF_OUT = 6GHz Integration Range: 20kHz – 100MHz PFD = 500MHz (Integer Mode) -60.6 -57.4 dBc 35 50 fs RMS fRF_OUT = 8GHz Integration Range: 20kHz – 100MHz PFD = 500MHz (Integer Mode) -57.6 -55 dBc 36.8 50 fs RMS fRF_OUT = 11GHz Integration Range: 20 kHz – 100MHz PFD = 500MHz (Integer Mode) -53.3 -47 dBc 44 82 fs RMS fRF_OUT = 18GHz Integration Range: 20 kHz – 100MHz PFD = 250kHz (Integer Mode) -50.2 -46.4 dBc 38.5 58 fs RMS 10kHz offset from carrier -74.9 -72.8 dBc/Hz 100kHz offset from carrier -104.8 -102.7 dBc/Hz 1MHz offset from carrier -133.2 -130.9 dBc/Hz 10MHz offset from carrier -153.8 -152.6 dBc/Hz 60MHz offset from carrier -157.8 -156.8 dBc/Hz 16 Minimum 66 fs RMS April 8, 2021 8V97003 Datasheet Table 12. RF_OUT[A:B] Phase Noise Char., VDDx[a] = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Board or Junction Temp.)[b] (Cont.) Symbol Parameter Typical Maximum Units 10kHz offset from carrier -71.5 -69.3 dBc/Hz 100kHz offset from carrier -101.9 -100.6 dBc/Hz 1MHz offset from carrier -130.6 -128.4 dBc/Hz 10MHz offset from carrier -152.1 -149.5 dBc/Hz ΦN(60M) 60MHz offset from carrier -157.7 -155.7 dBc/Hz ΦN(10k) 10kHz offset from carrier -67.1 -65.2 dBc/Hz 100kHz offset from carrier -98 -93.3 dBc/Hz 1MHz offset from carrier -125.1 -114.2 dBc/Hz 10MHz offset from carrier -144.7 -133.2 dBc/Hz ΦN(60M) 60MHz offset from carrier -150.8 -142.2 dBc/Hz ΦN(10k) 10kHz offset from carrier -64.6 -62.7 dBc/Hz 100kHz offset from carrier -95.5 -93.2 dBc/Hz 1MHz offset from carrier -123.4 -119.9 dBc/Hz 10MHz offset from carrier -144.1 -140.0 dBc/Hz 60MHz offset from carrier -148.6 -142.1 dBc/Hz fPFD = 245.76MHz; RF_OUT = 7.86432GHz; Integer Mode -83.2 -77.5 dB fPFD = 245.76MHz; RF_OUT = 8GHz; Fractional Mode -74.1 -69.9 dB ΦN(10k) ΦN(100k) ΦN(1M) ΦN(10M) ΦN(100k) ΦN(1M) ΦN(10M) ΦN(100k) ΦN(1M) ΦN(10M) RF Output Phase Noise Performance at 8GHz (Open Loop) RF Output Phase Noise Performance at 11GHz (Open Loop) RF Output Phase Noise Performance at 18GHz (Open Loop) ΦN(60M) — ΦN(SYNTH) Spurious Signals due to PFD Frequency Test Conditions Minimum Normalized Phase Noise Floor -236 dBc/Hz dBc/Hz ΦN(1/f) Normalized 1/f Noise[c] 10kHz Offset; fRF_OUT = 8GHz -132 H2 VCO second harmonic fVCO = 8GHz -36 H3 VCO third harmonic fVCO = 8GHz -33 dB [a] VDDx denotes VDDVCO2, VDDPDCP, VDDFB, VDDDIG, VDDIN, VDDVCO1, VDDOUTA, VDDOUTB. [b] Over recommended operating conditions (unless otherwise indicated). [c] N(1/f) = ΦN(RF_OUT) – 10 Log(10kHz ÷ f) – 20 Log (fRF_OUT ÷ 1GHz) where ΦN(1/f) is the 1/f noise contribution at a RF_OUT frequency (fRF_OUT) and at a frequency offset f. ©2021 Renesas Electronics Corporation 17 April 8, 2021 8V97003 Datasheet Typical Performance Characteristics Figure 2. Phase Noise at 6GHz (Fractional Mode) Figure 3. Phase Noise at 6GHz (Integer Mode) ©2021 Renesas Electronics Corporation 18 April 8, 2021 8V97003 Datasheet Figure 4. Phase Noise at 8GHz (Integer Mode) Figure 5. Phase Noise at 11GHz (Integer Mode) ©2021 Renesas Electronics Corporation 19 April 8, 2021 8V97003 Datasheet Figure 6. Phase Noise at 18GHz (Integer Mode) Figure 7. Phase Noise at 8GHz (Open Loop) ©2021 Renesas Electronics Corporation 20 April 8, 2021 8V97003 Datasheet Figure 8. Typical Output Power vs. RF Output Frequency (Over Different Loads) RF_OUTn_pwr Setting = 1100 (Maximum) Single-Ended Output Power, dBm vs Output Frequency, GHz 16 14 RF Output Power, dBm 12 10 8 6 4 2 0 ‐2 Load_50ohm ‐4 Load_1nH Load_0.6nH ‐6 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RF Output Frequency, GHz Figure 9. Test Setup for RF Output Power Measurement Vdd Spectrum Analyzer 50Ω 8V97003 50Ω 50Ω 50Ω Vdd Theory of Operation The 8V97003 is a high-performance frequency synthesizer with an integrated wideband VCO for wide frequency coverage. The VCO provides an octave frequency from 5.5GHz to 11GHz. An optional VCO-doubler is used to generate frequencies larger than the maximum VCO frequency (11GHz) up to 18GHz and an optional output divider can be used to divide the VCO frequency to an output frequency as low as 171.875 MHz. The input reference can support frequencies from 10MHz to 1600MHz. The phase detector (PFD) can support frequencies from 10MHz to 250MHz in fractional mode, and up to 500MHz in Integer mode. A Delta Sigma Modulator (DSM) controls the feedback divider of the PLL in order to create fractional N-divider values. The fractional numerator and the modulus are programmable to 32-bit long, allowing a very fine frequency resolution. The device provides two outputs with individually programmable RF output power (for more information, see Table 55). The digital logic is a 3- or 4-wire SPI interface that is 1.8V compatible and 3.3V tolerant. ©2021 Renesas Electronics Corporation 21 April 8, 2021 8V97003 Datasheet Synthesizer Programming The Fractional-N divider architecture is implemented via a cascaded programmable dual modulus prescaler, controlled by a DSM. The N divider offers a division ratio in the feedback path of the Phase Lock Loop (PLL), and is given by programming the value of INT, FRAC, and MOD in the following equation: N = INT + FRAC/MOD where: ▪ INT is the divide ratio of the binary 16-bit counter (see Table 25). ▪ FRAC is the numerator value of the fractional divide ratio. It is programmable from 0 to (MOD – 1) (see Table 25). ▪ MOD is the 32-bit modulus. It is programmable from 2 to 4,294,967,295 (see Table 25). The VCO frequency (fVCO) at RF_OUTA or RF_OUTB is given by the following equation: fVCO = fPFD  (INT + FRAC/MOD) (1) fPFD is the frequency at the input of the Phase and Frequency Detector (PFD). The 8V97003 supports an Integer mode. It is enabled by programming the FRAC value to 0. The device’s VCO is separated into several frequency bands in order to cover the entire range with sufficient margin for process, voltage, and temperature variations. These are automatically selected by invoking the Autocal feature. The charge pump current is also programmable via the ICP SETTING register for maximum flexibility. The Output Control Registers can be used to enable RF_OUTA, or RF_OUTB, or both outputs. Reference Input Stage The 8V97003 features one differential reference clock input, REF_IN. This differential input can also be configured as one single-ended input, and it can be driven by an AC-coupled sine wave or square wave. The input type (Differential or Single-ended) can be programmed via the bit Input_Type in the Input Control Registers. In Power-down mode (set pin CE = 0), this input is set to High-Impedance to prevent loading of the reference source. The reference input signal path also includes a reference divider (R) and an optional doubler (D), as well as an optional multiplier (MULT) that allows accommodating a higher PFD frequency when the input reference frequency is low (see Figure 10). Having a high enough PFD frequency is typically better for phase noise performance. However, note that the MULT multiplier also adds its own additive noise. In both cases (doubler and / or multiplier enabled), the maximum PFD frequency is limited to 500MHz in Integer mode and to 250MHz in Fractional mode. Figure 10. Input Reference Path MULT REF_IN nREF_IN ÷R To PFD x2 1+D f PFD = REFIN  -------------  MULT R ▪ REFIN is the input reference (REF_IN) frequency ▪ D is the input reference doubler (0 if not active, or 1 if active) ▪ MULT is the multiplication factor of the input Multiplier “MULT”. It is equal to 1 if it is bypassed. ©2021 Renesas Electronics Corporation 22 April 8, 2021 8V97003 Datasheet Input Reference Divider (R) A 10-bit input reference divider (R Divider) is available to scale the input reference frequency to a frequency suitable for the PFD. Reference Doubler In order to improve the phase noise performance of the device, the reference doubler can be used. By using the doubler, the PFD frequency is also doubled to allow a more frequent update of the VCO, which may optimize the phase noise performance. When operating the device in Fractional mode, the speed of the Sigma Delta modulator of the N counter is limited to 250MHz, which is also the maximum PFD frequency that can be used in fractional mode. When the part operates in integer-N mode, the PFD frequency is limited to 500MHz. Reference Multiplier (MULT) The 8V97003 input path offers an optional frequency multiplier that can multiply the input reference frequency (or the frequency after the optional reference doubler D) to a frequency that must be between 160MHz and 250MHz. That multiplied frequency is used as the PFD frequency. When possible, enabling the doubler is recommended in order to provide a higher input frequency to the MULT multiplier, and thus, optimize its phase noise performance. When it is used, the optional MULT multiplier may degrade the in-band phase noise within the loop bandwidth of the 8V97003. Note: The input reference multiplier can only output 160MHz to 250MHz before reaching the input reference divider on the input path. Using the input reference multiplier to output a frequency out of that range will not guarantee a lock. Feedback Divider The feedback divider N supports fractional division capability in the PLL feedback path. It consists in an integer N divider of 16 bits, and a Fractional divider of 32 bits (FRAC) over 32-bits (MOD). Figure 11. RF Feedback N Divider From VCO Output To PFD N Counter 3rd Order Σ Modulator 32-bit FRAC 16-bit INT + 32-bit MOD The 16 INT bits (NInt[15:0] in the Feedback Divider Control Registers set the integer part of the feedback division ratio. The 32 FRAC bits (Bit NFrac[31:0] in the registers set the numerator of the fraction that goes into the Sigma Delta modulator. The 32 MOD bits (NMod[31:0] in the registers set the denominator of the fraction that goes into the Sigma Delta modulator. From the relation (1), the VCO minimum step frequency is determined by (1/MOD)  fPFD. ©2021 Renesas Electronics Corporation 23 April 8, 2021 8V97003 Datasheet FRAC values from 0 to (MOD –1) cover channels over a frequency range equal to the PFD reference frequency. The PFD frequency is calculated as follows: 1+D f PFD = REFIN  ------------R ▪ REFIN is the input reference (REF_IN) frequency ▪ D is the input reference doubler (0 if not active, or 1 if active) ▪ R is the 10-bit programmable input reference pre-divider This formula assumes that the MULT input multiplier is bypassed. The programmable modulus (MOD) is determined based on the input reference (REF_IN) frequency and the desired channelization (or output frequency resolution). The high resolution provided on the R counter and the Modulus allows the user to choose from several configuration of the PLL to optimize the performance. The high resolution Modulus also allows the use of the same input reference frequency to achieve different channelization requirements. Using a unique PFD frequency for several needed channelization requirements allows the user to design a loop filter for the different needed setups and ensure the stability of the loop. f MOD PFD The channelization is given by ------------- In low noise mode (dither disabled), the Sigma Delta modulator can generate some fractional spurs that are due to the quantization noise. The spurs are located at regular intervals equal to fPFD/L where L is the repeat length of the code sequence in the Sigma Delta modulator. That repeat length depends on the MOD value, as described in Table 13. Table 13. Fractional Spurs Due to the Quantization Noise Condition (Dither Disabled) L Spur intervals MOD can be divided by 2, but not by 3 2  MOD fPFD/(2  MOD) MOD can be divided by 3, but not by 2 3  MOD fPFD/(3  MOD) MOD can be divided by 6 6  MOD fPFD/(6  MOD) MOD fPFD/MOD (channel step) Other conditions In order to reduce the spurs, the user can enable the dither function to increase the repeat length of the code sequence in the Sigma Delta Modulator. The increased repeat length is 232 − 1 cycles so that the resulting quantization error is spread to appear like broadband noise. As a result, the in-band phase noise may be degraded when using the dither function. When the application requires the lowest possible phase noise and when the loop bandwidth is low enough to filter most of the undesirable spurs, or if the spurs will not affect the system performance, it is recommended to use the low noise mode with dither disabled. ©2021 Renesas Electronics Corporation 24 April 8, 2021 8V97003 Datasheet Phase and Frequency Detector (PFD) and Charge Pump The phase detector compares the outputs from the R counter and N counter, and generates an output corresponding to the phase and frequency difference between the two inputs at the PFD. The charge pump current is programmable through the serial port (SPI) to several different levels (see Table 49). Figure 12. Simplified PFD Circuit using D-type Flip-Flop ICP VDD D1 Q1 REFIN  [(1+D)/R]  MULT CPOUT DELAY VDD D1 Q1 ICP FB PFD Frequency The operating frequency for the PFD is up to 500MHz when the device operates in integer mode, and up to 250MHz when the device operates in fractional mode. External Loop Filter The 8V97003 requires an external loop filter. The design of that filter is application specific. For more information, see Applications Information. Charge Pump High-Impedance In order to put the charge pump into three-state mode, the user must set the bits CP_HiZ (Bit D5) to 1 in Register 47 in the Charge Pump Control Registers. This bit should be set to 0 for normal operation. ©2021 Renesas Electronics Corporation 25 April 8, 2021 8V97003 Datasheet Integrated Low Noise VCO The VCO used in the 8V97003 is divided into several frequency bands. This allows for a lower VCO sensitivity (Kvco), which results in the best possible VCO phase noise and spurious performance. The user does not have to select the different VCO bands. The VCO band select logic of the 8V97003 will automatically select the most suitable band of operation at power up or after programming. In addition, the Force_Relock bit (register 33, bit D7) can be used to automatically select the best frequency band. Output Clock Distribution and Optional Output Doubler The 8V97003 device provides two differential outputs. Either of the two outputs generates a frequency equal to fVCO when bypassing the optional output doubler and the optional output divider M0, or to 2  fVCO (up to 18GHz) when using the optional output doubler, or an integer division of the VCO frequency fVCO. The division ratios of the output divider are provided in the Output Control Registers. Figure 13. Output Clock Distribution From VCO /M0 x2 RF_OUTA nRF_OUTA Mute Switches RF_OUTB nRF_OUTB RF_OUT and nRF_OUT are derived from the collector of an NPN differential pair driven by the VCO output (or the output doubler), as displayed in Figure 14. Figure 14. Output Stage RF_OUT nRF_OUT VCO or Optional Output Doubler Or Optional Output Divider The 8V97003 offers 4 bits of programmability for the RF output power of each output. The user can configure the RF output power to multiple available settings (see RF Output Power). If the auxiliary output (RF_OUTB) is not used, it can be powered down by using the QB_ena bit in the Output Control Registers. The outputs can be disabled until the part achieves lock. To enable this mode, the user will set the Mute_until_LD bit in the Outputs Control Registers (see Output Control Registers). The MUTE pin can be used to mute all outputs and be used as a similar function. ©2021 Renesas Electronics Corporation 26 April 8, 2021 8V97003 Datasheet Output Matching The outputs of the 8V97003 are “open collector outputs” and can be matched in different ways. A simple resistive matching is used to terminate the open collector RF_OUT output with a 50Ω to VDD, and with an AC coupling capacitor in series. Two termination scheme examples are shown in Figure 15 and Figure 16. When considering the frequencies involved from the 8V97003, an inductively loaded configuration is recommended for better performance and optimal power transmission, and to minimize the distortion of the output signal. The resistive matching termination is not ideal to achieve maximum output power transmission, especially for high frequencies. Figure 15. Resistive Matching Termination VDD 3.3V 50 3.3V 50 100pF RF_OUT Z0 = 50 100 nRF_OUT 100pF Z0 = 50 8V97003 Input Receiver This termination scheme provides one of the selected output powers on the differential pair when connected to a 50Ω load. For additional information about the output power selection, see RF Output Power. The 50Ω resistor connected to VDD can also be replaced by a choke to provide better performance and optimal power transmission. The pull-up inductor value is frequency dependent. For impedance matching of 50Ω, the inductance value can be calculated as L = 50 ÷ (2f), where “f” is the operating frequency. In this example, L = 1nH is for an operating frequency of approximately 6GHz. Figure 16. Inductively Loaded Termination VVCO 3.3V 1nH RF_OUT 3.3V 1nH 100pF Z0 = 50 100 nRF_OUT 100pF Z0 = 50 Input Receiver 8V97003 For more recommendations on the termination scheme, see Applications Information. Band Selection Disable For a given frequency, the output phase can be adjusted when using the BandSelDisable bit (Bit D5 in Register 33; see Calibration Control Registers). When this bit is enabled (Bit D5 set to 1), the device does not complete a VCO band selection after changing the settings. When the Band_Sel_Disable bit is set to 0, and when the settings are updated, the device proceeds to a VCO band selection. The Band_Sel_Disable bit is useful when the user wants to make small changes in the output frequency (< 1MHz from the nominal frequency) without recalibrating the VCO and minimizing the settling time. ©2021 Renesas Electronics Corporation 27 April 8, 2021 8V97003 Datasheet Phase Adjust The 8V97003 supports adjusting the phase delay between the outputs (RF_OUT/ nRF_OUT) and the input (REF_IN) of the device by shifting the output phase by a fraction of the size of the fractional denominator, when the device is used in fractional mode. Writing to the Phase Adjustments Control Registers triggers a phase shift (see Table 28). The phase adjustment value set by the bits, Phase[31:0], should be less than the fractional-N denominator register, MOD. The actual phase shift can be obtained with the following equation: T T OUT VCO ---------------  ------------Phase adjustment (degrees) = 360  Phase - MOD or Phase MOD Phase adjustment (ns) = T VCO   --------------- 360° represents one cycle of output clock, TVCO is the period of VCO (in ns), TOUT is the period at the output of the 8V97003, and Phase is a programmable value, the same bit length as MOD. RF Output Power Each output buffer RF_OUTA and RF_OUTB offers a configurable RF output power. The RF output power can be programmed via the bits RF_OUTA_pwr[3:0] and RF_OUTB_pwr[3:0] in the Output Control Registers. Output Phase Synchronization Input-to-Output The device input-to-output phase relations is deterministic with a fixed phase offset when the PLL feedback divider is integer and the output divider is not used. The phase offset remains the same across power cycles. Output Phases of Multiple 8V97003 Devices The output phases of multiple devices can be aligned on the rising signal edge. This is supported for devices with identical configurations and the same input phase and frequency. The devices can use any setting of the input divider, input multiplier, integer and fractional feedback divider, the output frequency doubler, and the 1x frequency output path, but not the output divider. Phase alignment across devices is established automatically when the PLL feedback divider is integer and the input frequency divider is not used. In other configurations, an external pulse to the SYNC input establishes an output phase alignment. The SYNC pulse can be applied to the device at any time after the configuration is loaded with the AutoReSync register bit is set to 1 and the PLL is locked. Internal to the device, this synchronization procedure first resets the input divider and then resets the DSM. For applicable input SYNC and REF_IN timing requirements, see the following table. Table 14. Timing Requirements Symbol Parameter tS Setup Time Rising edge of SYNC pulse to Rising Edge of REF_IN 0.5 ns tH Hold Time Rising Edge of REF_IN to Falling Edge of SYNC Pulse 0.5 ns ©2021 Renesas Electronics Corporation Test Conditions 28 Minimum Maximum Unit April 8, 2021 8V97003 Datasheet Power-Down Mode When power-down is activated, the following events occur: 1. VCO is not powered-down 2. RF_OUT buffers are disabled 3. The input stage is powered down and set to High-Impedance 4. Input registers remain active and capable of loading and latching data 5. The CE pin is set to low level (logic zero) for activating power-down mode. More power-down control bits are available in register 0x0028. Default Power-Up Conditions All the RF outputs are muted at power-up. For default values in registers, see Register Map. VCO Calibration For proper VCO calibration, the 8V97003 must be programmed with the following recommended settings: ▪ The band select clock divider (Bits BndSelDiv[12:0] in the Band Select Clock Divider Control Registers) must be set to divide down the PFD frequency in between 50kHz to 100kHz (PFD Frequency/BandSelDiv[12:0] ≤ 100kHz and > 50kHz). ▪ BandSelAcc[1:0] bits must be set to 10 or 11. 3- or 4-Wire SPI Interface Description The 8V97003 has a selectable 3/4-wire serial control port that can respond as a slave in an SPI configuration to allow read and write access to any of the internal registers for device programming or read back. The SPI interface consists of SCLK (clock), SDIO (serial data input and output in 3-wire mode, input in 4-wire mode), SDO (output in 4-wire mode), and CSB (chip select). A data transfer contains 16-bit instructions (direction +15 bit address) and any integer multiple of 8 bits data. Internal register data is organized in 8-bit byte. 3/4-Wire Mode The 3- or 4-wire mode is defined by the SDO Active bit in the device configuration register 0x00 bit3 and bit4. If both bits are set to 0, the device is in a 3-wire mode and the SDIO pin is a bi-directional data input/ output, and the SDO pin is in high-impedance. Otherwise, the device is in a 4-wire mode, the SDIO pin is the data input, and the SDO pin is the data output. Active Clock Edge SDIO is always clocked-in on the rising edge of SCLK. SDIO (or SDO if in 4-wire mode) is always clocked-out on the falling edge of SCLK. Reset After power-up or reset by the nRESET pin, the SPI engine is reset and all internal registers reset to their default values. The SPI interface is in 3-wire mode with SDO in high-impedance, MSB-first mode, and address is in auto-decrement mode. The function of SoftReset bit in register 0x00 bit7 and bit0 is similar to the nRESET pin. It resets all the registers to their default values, except registers 0x00 and 0x01. ©2021 Renesas Electronics Corporation 29 April 8, 2021 8V97003 Datasheet Least Significant Bit Position The 8V97003 supports both the least significant bit first and most significant bit first transfers. ▪ If LSBFirst in register 0x00 bit6 and bit1 is set to 0, data is transferred in this order: transfer direction bit, the address bits A14 to A0, then first data byte D7 to D0, 2nd data byte D7 to D0, and so on until CSB is set to 1. ▪ If LSBFirst is set to 1, the order is: address bits A0 to A14, then the transfer direction bit, then the first data byte D0 to D7, 2nd data byte D0 to D7, and so on until CSB is set to 1. By default, LSBFirst is set to 0. Addressing The 8V97003 implements registers at the addresses from 0x00 to 0x49. The addressing mode is 15-bit. During transferring operation, address increments automatically if AddressAcend in register 0x00 bit5 and bit2 is set to 1; otherwise it decrements. In incrementing mode, if address reaches 0x49, it wrap-around to 0x00. In decrementing mode, if address reaches 0x00, it wrap-around to 0x49. By default, decrementing mode is set. Read Operation A SPI operation starts when there is a high to low transition on CSB, and stops when there is a low to high transition on CSB. If the transfer direction bit R/nW is 1, it is a read operation; otherwise it is a write operation. This device supports multi-byte read or write operations. Bits A14 to A0 refer to the register address. The device reads or writes data to this address and continues as long as CSB is held at low. The device automatically increments or decrements the address depending on AddressAcend bit. Figure 17 to Figure 22 show the operation protocols. Mirrored Register Bits In register 0x00, bits D7–D4 are mirrored with the bits D3–D0. The mirrored bits pair must set to the same value. Double-Buffered Registers Configuration registers that are wider than 8 bits are double-buffered for synchronous access. For these registers, it is required to write the multiple-byte setting into the buffered registers first. The new configurations will not take effect until writing 1 to the TransferOn bit in register 0x0F bit0 to transfer them from the buffered registers to the active registers. TransferOn bit is self-clearing. Multiple-byte configuration data can be read-back either from buffered registers or active registers as specified by the BufferReadMode bit in register 0x01 bit5. Register 0x10 to 0x1D, 0x22 to 0x25, and 0x29 to 0x2C are double buffered. ©2021 Renesas Electronics Corporation 30 April 8, 2021 8V97003 Datasheet Operation Protocols Figure 17. 4-Wire MSB First, Single Byte Write and Read CSB nCS Single-byte data write SCLK SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D1 D0 Register Reg( n) Data Register Address Instruction CSB nCS D3 D2 Single-byte data readback SCLK SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Instruction Register Address D7 D6 D5 D4 SDO D3 D2 D1 D0 Register Reg( n) Data ©2021 Renesas Electronics Corporation 31 April 8, 2021 8V97003 Datasheet Figure 18. 4-Wire LSB First, Single Byte Write and Read CSB nCS Single-byte data write SCLK SDIO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D6 D7 Register Reg( n) Data Register Address Instruction CSB nCS D4 D5 Single-byte data readback SCLK SDIO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W Instruction Register Address D0 D1 D2 D3 SDO D4 D5 D6 D7 Register Reg( n) Data Figure 19. 4-Wire MSB First, Multiple Bytes Write (2 Bytes Shown as Example) CSB nCS Address decrementing SCLK SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 Register Reg( n) Data Register Address Instruction CSB nCS D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register Reg( n-1) Data Address incrementing SCLK SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 Register Reg( Register Address Instruction ©2021 Renesas Electronics Corporation 32 D3 D2 n) Data D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register Reg( n+1) Data April 8, 2021 8V97003 Datasheet Figure 20. 4-Wire LSB First, Multiple Bytes Read (2 Bytes Shown as Example) CSB nCS Address decrementing SCLK SDO SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO Register Address Instruction  CSB nCS Register Reg（n）Data Register Reg（n‐1）Data Address incrementing SCLK SDO SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO Register Reg（n）Data Register Address Instruction  Register Reg（n+1）Data Figure 21. 3-Wire MSB First, Single Byte Read and Write CSB nCS SCLK SDIO R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 Instruction A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Reg( n) Data Register Address ©2021 Renesas Electronics Corporation A2 33 April 8, 2021 8V97003 Datasheet Figure 22. SPI Timing Diagram ts1 nCS CSB tpwh th1 tpwl th2 ts2 SCLK SDIO R/W A1 A0 td2 td1 SDO Hi‐z D0 Hi‐z D1 Table 15. SPI Read / Write Cycle Timing Parameters Parameter Minimum Maximum Units 20 MHz fSCLK SCLK Frequency tpwh SCLK High Pulse Width 25 ns tpwl SCLK Low Pulse Width 25 ns tS1 Setup Ttime, CSB falling to SCLK rising 10 ns th1 Hold Time, SCLK falling to CSB rising 30 ns tS2 Setup Time, SDIO input edge to SCLK rising 8 ns th2 Hold Time, SCLK rising to SDIO input edge 8 ns td1 SCLK Falling Edge to valid readback data on SDIO if in 3-wire mode, or SDO if in 4-wire mode 10 ns td2 CSB Rising Edge to High-Impedance on SDIO if in 3-wire mode, or SDO if in 4-wire mode 10 ns ©2021 Renesas Electronics Corporation 34 April 8, 2021 8V97003 Datasheet Register Map Table 16. Preface Registers Register Addr Type Default Value D7 D6 D5 D4 D3 D2 D1 D0 0 0000 R/W 0000_0000 SoftReset LSBFirst AddressAs cend SDOActive SDOActive AddressAs cend LSBFirst SoftReset 1 0001 R/W 0000_0000 Unused Unused BufferRead Mode Unused Unused Unused Unused Unused 2 0002 R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 3 0003 R 0000_0110 ChipType ChipType ChipType ChipType ChipType ChipType ChipType ChipType 4 0004 R 0000_0000 ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID 5 0005 R 0000_0000 ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID 6 0006 R 0000_0000 ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion 7 0007 R 0001_0001 ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption 8 0008 R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 9 0009 R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 10 000A R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 11 000B R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 12 000C R 0010_0110 VendorID VendorID VendorID VendorID VendorID VendorID VendorID VendorID 13 000D R 0000_0100 VendorID VendorID VendorID VendorID VendorID VendorID VendorID VendorID 14 000E R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 15 000F R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused TransferOn Table 17. Control Registers[a] Register Addr Type Default Value D7 D6 D5 D4 D3 D2 D1 D0 16 0010 R/W 0001_1111 NInt NInt NInt NInt NInt NInt NInt NInt 17 0011 R/W 0000_0000 NInt NInt NInt NInt NInt NInt NInt NInt 18 0012 R/W 1000_0110 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 19 0013 R/W 1111_1110 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 20 0014 R/W 1111_1111 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 21 0015 R/W 1011_1100 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 22 0016 R/W 0000_0000 NMod NMod NMod NMod NMod NMod NMod NMod 23 0017 R/W 1111_1110 NMod NMod NMod NMod NMod NMod NMod NMod 24 0018 R/W 1111_1111 NMod NMod NMod NMod NMod NMod NMod NMod 25 0019 R/W 1111_1111 NMod NMod NMod NMod NMod NMod NMod NMod 26 001A R/W 0000_0001 Phase Phase Phase Phase Phase Phase Phase Phase 27 001B R/W 0000_0000 Phase Phase Phase Phase Phase Phase Phase Phase ©2021 Renesas Electronics Corporation 35 April 8, 2021 8V97003 Datasheet Table 17. Control Registers[a] (Cont.) Register Addr Type Default Value D7 D6 D5 D4 D3 D2 D1 D0 28 001C R/W 0000_0000 Phase Phase Phase Phase Phase Phase Phase Phase 29 001D R/W 0000_0000 Phase Phase Phase Phase Phase Phase Phase Phase 30 001E R/W 0111_0010 0 DSMOrder DSMOrder DSMOrder DitherG DitherG ShapeDithe rEn DitherEn 31 001F R/W 0000_1000 ManualBa ndEn 0 0 0 VCOManu VCOManu VCOManu VCOManu 32 0020 R/W 0100_0000 Unused BandManu BandManu BandManu BandManu BandManu BandManu BandManu 33 0021 R/W 0000_0011 ForceRelo ck PhAdj BandSelDi sable ManualRe Sync 0 0 BandSelAc c BandSelAc c 34 0022 R/W 0000_0000 BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv 35 0023 R/W 0000_1010 Unused Unused Unused BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv 36 0024 R/W 0000_0000 1 0 0 0 0 0 0 0 37 0025 R/W 0000_0000 0 0 0 0 0 0 0 0 38 0026 R/W 0000_0000 Unused Unused Unused LD_Enable AutoRecal En 0 0 0 39 0027 R/W 0000_0000 Unused Unused LDPinMode LDPinMode Unused LDP LDP LDP 40 0028 R/W 0000_0001 Reserved ref_vreg_p wrdwn pdcp_vreg _pwrdwn fb_vreg_p wrdwn outA_vreg _pwrdwn outBbuf_vr eg_pwrdwn PDNAnaR egu VCO_En 41 0029 R/W 0000_0001 R R R R R R R R 42 002A R/W 0000_1100 Unused Unused Unused RefDouble r_Delay Input_Type RefDouble r_En R R 43 002B R/W 0000_0000 Mult_En Mult_reset Mult Mult Mult Mult Mult Mult 44 002C R/W 0000_0000 nMultpwrd wn nMultpwrd wn nMultpwrd wn Mult_force _vchi Mult_force _vclow 1 0 0 45 002D R/W 0001_1101 Unused Unused Icp_pmos< 5> Icp_pmos< 4> Icp_pmos< 3> Icp_pmos< 2> Icp_pmos< 1> Icp_pmos< 0> 46 002E R/W 0001_1101 Unused Unused Icp_nmos< 5> Icp_nmos< 4> Icp_nmos< 3> Icp_nmos< 2> Icp_nmos< 1> Icp_nmos< 0> 47 002F R/W 0000_0000 CP_HiZ Icp_bleede r Icp_bleede r Icp_bleede r Icp_bleede r Icp_bleede r Icp_bleede r Icp_bleede r 48 0030 R/W 0110_0010 Unused Unused Unused Unused pfd_pw pfd_pw 1 Unused 49 0031 R/W 0000_0000 1 0 0 0 1 0 0 0 50 0032 R/W 0000_0000 AutoReSy nc 0 0 1 0 0 1 1 51 0033 R/W 0000_0000 Unused Unused Unused Unused RF_OUTA _pwr RF_OUTA _pwr RF_OUTA _pwr RF_OUTA _pwr 52 0034 R/W 0000_1000 1 Unused Mute_until _LD RF_OUTA _ena 1 1 1 0 53 0035 R/W 0000_0000 Unused Unused Unused Unused RF_OUTB _pwr RF_OUTB _pwr RF_OUTB _pwr RF_OUTB _pwr ©2021 Renesas Electronics Corporation 36 April 8, 2021 8V97003 Datasheet Table 17. Control Registers[a] (Cont.) Register Addr Type Default Value D7 D6 D5 D4 D3 D2 D1 D0 54 0036 R/W 0000_1000 1 Unused Unused RF_OUTB _ena 1 1 1 0 55 0037 R/W 0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 56 0038 R/W 0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 57 0039 R/W 0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 58 003A R/W 0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 59 003B R/W 0000_0000 OutDoubler _Ena OutDivider_ Ena OutDoubler _Freq Unused Unused OutDiv OutDiv OutDiv 60 003C R/W 0000_0000 Unused Unused Unused Unused 0 0 1 0 61 003D R/W 0000_0000 Unused Unused Unused Reserved Reserved 0 0 0 62 003E R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 63 003F R/W 0000_0000 Unused Unused Unused Unused Unused Unused Unused Reserved 64 0040 R/W 0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 65 0041 R/W 0110_0010 0 1 1 0 Unused Unused 1 0 66 0042 R/W 0010_0010 Unused Unused 1 0 Unused Unused 1 0 67 0043 R/W 0010_0010 Unused Unused 1 0 Unused Unused 1 0 [a] It is recommended to write 0 for Unused and Reserved bits when writing. Table 18. Status Registers Register Addr Type Default Value D7 D6 D5 D4 D3 D2 D1 D0 68 0044 R 0000_0000 DigLock BandSelD one Unused Unused VcoSts VcoSts VcoSts VcoSts 69 0045 R 0000_0000 Unused BandSts BandSts BandSts BandSts BandSts BandSts BandSts 70 0046 R 0000_0000 0 0 0 0 0 0 0 0 71 0047 R 0000_0000 Unused Unused 0 0 0 0 0 0 72 0048 R 0000_0000 Unused Unused Unused Unused Unused Unused Unused Unused 73 0049 R/W 0000_0000 Unused Unused Unused Unused Unused LossLock Unused Unused ©2021 Renesas Electronics Corporation 37 April 8, 2021 8V97003 Datasheet Register Block Descriptions Table 19. Register Block Descriptions Register Blocks (Hex) Preface Registers 0000–0001 0002 Reserved Device Type, ID Version, and Option Registers 0008–000B Unused 000C–000D Vendor ID Control Registers 000E–000F Unused 0010–0019 Feedback Divider Control Registers 001A–001D Phase Adjustments Control Registers 001F–0020 0021 Control Registers Startup Control Registers 0003–0007 001E DSM Control Registers Manual VCO and Digital Band Selection Calibration Control Registers 0022–0023 Band Select Clock Divider Control Registers 0024–0025 Reserved 0026–0027 Lock Detect Control Registers 0028 Power Down Control Registers 0029–002C Input Control Registers 002D–002F Charge Pump Current Control Registers 0030 Status Registers Register Block Descriptions PFD Pulse Width Control Registers 0031–0032 Re-Sync Control Registers 0033–003B Output Control Registers 003C Reserved 003D Reserved 003E–0040 Unused or Reserved 0041–0043 Reserved 0044 Digital Lock and Calibration and VCO Status Registers 0045 Digital Band Status Registers 0046–0048 0049 ©2021 Renesas Electronics Corporation Reserved or Unused Loss of Lock Status Registers 38 April 8, 2021 8V97003 Datasheet Preface Registers Table 20. Preface Register Block Register Blocks (Hex) Register Block Descriptions 0000–0001 Startup Control Registers 0002 Reserved 0003–0006 Device Type, ID and Version Registers 0007 Reserved 0008–000B Unused 000C 000D Vendor ID Control Registers 000E–000F Unused Table 21. Preface Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0000 SoftReset LSBFirst AddressAscend SDOActive 0001 Unused Unused BufferReadMode Unused Unused Unused Unused Unused 0002 Unused Unused Unused Unused Unused Unused Unused Unused 0003 ChipType ChipType ChipType ChipType ChipType ChipType ChipType ChipType 0004 ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID 0005 ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID 0006 ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion ChipVersion 0007 ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption ChipOption 0008 Unused Unused Unused Unused Unused Unused Unused Unused 0009 Unused Unused Unused Unused Unused Unused Unused Unused 000A Unused Unused Unused Unused Unused Unused Unused Unused 000B Unused Unused Unused Unused Unused Unused Unused Unused 000C VendorID VendorID VendorID VendorID VendorID VendorID VendorID VendorID 000D VendorID VendorID VendorID VendorID VendorID VendorID VendorID VendorID 000E Unused Unused Unused Unused Unused Unused Unused Unused 000F Unused Unused Unused Unused Unused Unused Unused TransferOn ©2021 Renesas Electronics Corporation 39 April 8, 2021 8V97003 Datasheet Table 22. Preface Register Description Bit Field Name SoftReset LSBFirst AddressAscend Field Type R/W Auto-Clear R/W R/W Default (Binary) Description 0 Soft Reset Function: 0 = Normal operation 1 = Register reset. The device loads the default values into the registers, 0002 - 0049. The content of the register addresses 0000 an 0001 and the SPI engine are not reset. SoftReset bit D7 is mirrored with in bit position D0. Register reset requires setting both SoftReset and bits. 0 Least Significant Bit Position: Defines the bit transmitted first in SPI transfers between slave and master. 0 = The most significant bit (D7) first 1 = The least significant bit (D0) first The LSBFirst bit D6 is mirrored with the in bit position D1. Changing LSBFirst to most significant bit requires setting both LSBFirst and bits. 0 Address Ascend On: 0 = Address Ascend is off (addresses auto-decrement in streaming SPI mode) 1 = Address Ascend is on (addresses auto-increment in streaming SPI mode) The AddressAscend bit specifies whether addresses are incremented or decremented in streaming SPI transfers. The AddressAscend bit D5 is mirrored with the in bit position D2. Changing AddressAscend to “ON” requires setting both the AddressAscend and bits. SPI 3/4-Wire Mode: Selects the unidirectional or bidirectional data transfer mode for the SDIO pin. 0 = SPI 3-wire mode: SDOActive R/W 0 BufferReadMode R/W 0 ChipType[7:0] R only 0000 0110 ©2021 Renesas Electronics Corporation – SDIO is the SPI bidirectional data I/O pin – SDO pin is not used and is in high-impedance 1 = SPI 4-wire mode – SDIO is the SPI data input pin – SDO is the SPI data output pin The SDOActive bit D4 is mirrored with in bit position D3. Changing SDOActive to SPI 4-wire mode requires setting both the SDOActive and bits. Read Back Mode of the Buffer Registers: 0 = Read from active registers 1 = Read from the Buffer Register (case of Doubled Buffer Registers); If the register being read is not doubled buffered, a 1 value will read from the active register. Device (Chip) Type: Reads 00000110 (RF Synthesizer / PLL) after power-up and reset. 40 April 8, 2021 8V97003 Datasheet Table 22. Preface Register Description (Cont.) Bit Field Name Field Type Default (Binary) ChipID[15:0] R only 0000000000000001 ChipVersion[7:0] R only 0000 0010 Device (Chip) Version ChipOption[7:0] R only 0001 0001 Device (Chip) Option VendorID[15:0] R only 0000 0100 0010 0110 Vendor ID: 0x0426 (IDT/Renesas). Reads 0x0426 (IDT/Renesas) after power-up and reset. 0 Transfer On Function transfers the buffer registers values into the active registers: 1 = Transfer ON 0 = Transfer OFF This bit must be set 1 to transfer the contents of the buffers into the active registers. This bit is self-clearing; that is, it does not have to be set back to 0. When this bit is set to 1 (self-clearing), the device updates the active registers to the contents of the buffer registers simultaneously. This is done in order to avoid taking effect asynchronously during programming a multi-bit value (more than 8 bits) into several registers. R/W Auto-Clear TransferOn Description Device (Chip) ID Feedback Divider Control Registers Table 23. Feedback Divider Control Block Register Blocks (Hex) Register Block Descriptions 0010–0019 Feedback Divider Control Registers Table 24. Feedback Divider Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0010 NInt NInt NInt NInt NInt NInt NInt NInt 0011 NInt NInt NInt NInt NInt NInt NInt NInt 0012 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 0013 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 0014 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 0015 NFrac NFrac NFrac NFrac NFrac NFrac NFrac NFrac 0016 NMod NMod NMod NMod NMod NMod NMod NMod 0017 NMod NMod NMod NMod NMod NMod NMod NMod 0018 NMod NMod NMod NMod NMod NMod NMod NMod 0019 NMod NMod NMod NMod NMod NMod NMod NMod ©2021 Renesas Electronics Corporation 41 April 8, 2021 8V97003 Datasheet Table 25. Feedback Divider Control Register Description Register Description Bit Field Name Field Type Default (Binary) Description Nint[15:0] R/W 0000 0000 0001 1111 = d'31 Nfrac[31:0] R/W 1011 1100 1111 1111 1111 1110 1000 0110 = d'3,170,893,446 PLL Feedback Divider N Fractional Portion FRAC [a]: 0000 0000 0000 0000 0000 0000 0000 0000 = d'0 … 1011 1100 1111 1111 1111 1110 1000 0110 = d'3,170,893,446 (default) … 1111 1111 1111 1111 1111 1111 1111 1111 = d'4,294,967,295 Nmod[31:0] R/W 1111 1111 1111 1111 1111 1110 0000 0000 = d'4,294,966,784 PLL Feedback Divider N Modulus Portion MOD: 0000 0000 0000 0000 0000 0000 0000 0000 = Not allowed 0000 0000 0000 0000 0000 0000 0000 0001 = Not allowed 0000 0000 0000 0000 0000 0000 0000 0010 = d'2 … 1111 1111 1111 1111 1111 1110 0000 0000 = d'4,294,966,784 (default) … 1111 1111 1111 1111 1111 1111 1111 1111 = d'4,294,967,295 PLL Feedback Divider N Integer Portion INT: Minimum divide ratio is 12 0000 0000 0000 0000 = Not allowed … 0000 0000 0000 1011 = Not allowed 0000 0000 0000 0111 = 12 … 0000 0000 0001 1111 = 31 (default) … 1111 1111 1111 1111 = 65,535 [a] Nfrac is the numerator value of the fractional divide ratio. It is programmable from 0 to (MOD −1). ©2021 Renesas Electronics Corporation 42 April 8, 2021 8V97003 Datasheet Phase Adjustments Control Registers Table 26. Phase Adjustments Control Register Block Register Blocks (Hex) Register Block Descriptions 001A–001D Phase Adjustments Control Registers Table 27. Phase Adjustments Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 001A Phase Phase Phase Phase Phase Phase Phase Phase 001B Phase Phase Phase Phase Phase Phase Phase Phase 001C Phase Phase Phase Phase Phase Phase Phase Phase 001D Phase Phase Phase Phase Phase Phase Phase Phase Table 28. Phase Adjustments Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Phase[31:0] R/W 0000 0000 0000 0000 0000 0000 0000 0001 = d'1 Description Phase Adjustments[a] 0000 0000 0000 0000 0000 0000 0000 0000 = d'0 0000 0000 0000 0000 0000 0000 0000 0001 = d'1 (default) … 1111 1111 1111 1111 1111 1111 1111 1111 = d'4,294,967,295 [a] Phase adjustment (Phase value) must be less than the Modulus (Nmod value). ©2021 Renesas Electronics Corporation 43 April 8, 2021 8V97003 Datasheet DSM Control Registers Table 29. DSM Control Register Block Register Blocks (Hex) Register Block Descriptions 001E DSM Control Registers Table 30. DSM Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 001E 0 DSMOrder DSMOrder DSMOrder DitherG DitherG ShapeDitherEn DitherEn Table 31. DSM Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) DSMOrder[2:0] R/W 111 DSM Order 000 = OFF. The device operates in integer mode and the fractional part is ignored 001 = 1st order 010 = 2nd order 011 = 3rd order 100 = Reserved 101 = Reserved 110 = Reserved 111 = 3rd order (default) DitherG[1:0] R/W 00 Dither Gain 00 = LSB Dither (Recommended) (default) 01 = LSB x2 Dither 10 = LSB x4 Dither 11 = LSB x8 Dither ShapeDitherEn R/W 1 Shape Dither Enable 0 = Shaped dither disabled 1 = Shaped dither enabled DitherEn R/W 0 Dither Enable 0 = Dither off 1 = Dither on ©2021 Renesas Electronics Corporation Description 44 April 8, 2021 8V97003 Datasheet Calibration Control Registers Table 32. Calibration Control Register Block Register Blocks (Hex) Register Block Descriptions 001F–0021 Calibration Control Registers Table 33. Calibration Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 001F ManuBandEn 0 0 0 VCOManu VCOManu VCOManu VCOManu 0020 0 BandManu BandManu BandManu BandManu BandManu BandManu BandManu 0021 ForceRelock PhAdj BandSelDisable ManualReSync 0 0 BandSelAcc BandSelAcc Table 34. Calibration Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) ManuBandEn R/W 0 Calibration Mode Enable 0 = Automatic VCO and Digital Band Selection 1 = Manual VCO and Digital Band Selection VCOManu[3:0] R/W 1000 Manual VCO Selection (when ManuBandEn=1) 0000 = VCO0 0001= VCO1 ... 0111 = VCO7 1000 – 1111 = Unused Bandmanu[6:0] R/W 10000000 ForceRelock R/W 0 ForceRelock 0 = Normal operation (default) 1 = VCO forced to recalibrate. This bit is self-clearing. Note: When the PLL is used in integer mode, this bit must be set to 1 after programming the feedback divider value. PhAdj R/W 0 Phase Adjust Triggers 0 = Normal operation 1 = Trigger phase adjustment once. This bit is self-clearing. ©2021 Renesas Electronics Corporation Description Manual Digital Band Selection (when ManuBandEn=1) 0000000 = Band 0000001 = Band1 ... 1111111 = Band127 45 April 8, 2021 8V97003 Datasheet Table 34. Calibration Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Description BandSelDisable R/W 0 Band Select Disable This bit will prevent a VCO recalibration when registers 0x0010 0x0019 are written. 0 = VCO recalibrates when registers 0x0010 - 0x0019 are written 1 = VCO does not recalibrate when registers 0x0010 - 0x0019 are written ManualReSync R/W 0 0 = Normal operation 1 = Reset the DSM immediately BandSelAcc[1:0] R/W 11 Band select/Calibration resolution 00 = Reserved 01 = Reserved 10 = 4x resolution 11 = 8x resolution (default) Band Select Clock Divider Control Registers Table 35. Band Select Clock Divider Control Register Block Register Blocks (Hex) Register Block Descriptions 0022–0023 Band Select Clock Divider Control Registers Table 36. Band Select Clock Divider Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0022 BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv 0023 Unused Unused Unused BndSelDiv BndSelDiv BndSelDiv BndSelDiv BndSelDiv Table 37. Band Select Clock Divider Control Register Descriptions Register Description Bit Field Name BndSelDiv[12:0] Field Type Default (Binary) R/W 0 1010 0000 0000 = d'2,560 Description Band Select Clock Divider[a] 0 0000 0000 0000 = Not allowed 0 0000 0000 0001 = d'1 … 0 1010 0000 0000 = d'2,560 (default) … 1 1111 1111 1111 = d'8,192 [a] This value should be set so that FPFD / BndSelDiv is < 100kHz and > 50kHz. ©2021 Renesas Electronics Corporation 46 April 8, 2021 8V97003 Datasheet Lock Detect Control Registers Table 38. Lock Detect Control Register Block Register Blocks (Hex) Register Block Descriptions 0026–0027 Lock Detect Control Registers Table 39. Lock Detect Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0026 Unused Unused Unused LD_Disable AutoRecalEn 0 0 0 0027 Unused Unused LDPinMode LDPinMode Unused LDP LDP LDP Table 40. Lock Detect Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) LD_Disable R/W 0 Lock Detect Disable 0 = Disable lock detect circuitry (default) 1 = Enable lock detect circuitry AutoRecalEn R/W 0 Automatic Recalibration Enable 0 = Disable (default) 1 = Enable (an automatic recalibration occurs if an unlock on LD is detected) LDPinMode[1:0] R/W 00 LD Pin Mode 00 = Digital Lock Detect (default); Normal lock detector function 01 = Calibration done 10 = Low 11 = High LDP[2:0] R/W 000 Lock Detector Precision setting (ns) 000 = 0.375 (default) 001 = 0.75 010 = 1.5 011 = 2.4 100 = 5.2 101 = 5.2 110 = 8.5 111 = 8.5 ©2021 Renesas Electronics Corporation Description 47 April 8, 2021 8V97003 Datasheet Power Down Control Registers Table 41. Power Down Control Register Block Register Blocks (Hex) Register Block Descriptions 0028 Power Down Control Registers Table 42. Power Down Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0028 Reserved ref_vreg_ pwrdwn pdcp_vreg_ pwrdwn fb_vreg_ pwrdwn outA_vreg_ pwrdwn outBbuf_vreg_ pwrdwn PDNAnaRegu VCO_En Table 43. Power Down Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Description ref_vreg_pwrdwn R/W 0 Reference Input Path Regulator Power Down Control 0 = Regulator enabled (default) 1 = Regulator powered down pdcp_vreg_pwrdwn R/W 0 Phase Detector and Charge Pump Regulator Power Down Control 0 = Regulator enabled (default) 1 = Regulator powered down fb_vreg_pwrdwn R/W 0 Feedback Divider Regulator Power Down Control 0 = Regulator enabled (default) 1 = Regulator powered down outA_vreg_pwrdwn R/W 0 OutputA Regulator Power Down Control 0 = Regulator enabled (default) 1 = Regulator powered down outBbuf_vreg_pwrdwn R/W 0 Power Down Control for output path regulator and outputB regulator 0 = Regulator enabled (default) 1 = Regulator powered down PDNAnaRegu R/W 0 Analog Regulators Power Down Control[a] 0 = Normal working mode (default) 1 = Power down all analog regulators VCO_En R/W 1 VCO Enable 0 = Disable all VCOs (reduces VCO supply current IVCO to 46mA (typ.)) 1 = Normal mode [a] A value of 1 in PDNAnaRegu will supersede the values set for ref_vreg_pwrdwn, pdcp_vreg_pwrdwn, fb_vreg_pwrdwn, and out_vreg_pwrdwn. ©2021 Renesas Electronics Corporation 48 April 8, 2021 8V97003 Datasheet Input Control Registers Table 44. Input Control Register Block Register Blocks (Hex) Register Block Descriptions 0029–002C Input Control Registers Table 45. Input Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0029 R R R R R R R R 002A Unused Unused Unused RefDoubler_ Delay Input_Type RefDoubler_ En R R 002B Mult_En nMult_Reset Mult Mult Mult Mult Mult Mult 002C Mult_mux_ena Mult_d2s_ena Mult_cp_ena Mult_force_v chi Mult_force_v clow 1 0 0 Table 46. Input Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) R[9:0] R/W 00 0000 0001 = d'1 RefDoubler_Delay R/W 0 Selects the standard or extended pulse width delay for the input doubler. 0 = Standard pulse width (default). Use if the input reference frequency is > 50MHz. 1 = Extended pulse width for use with low frequencies (< 50MHz) Input_Type R/W 1 Input type: Selects either differential or single-ended input 0 = Single-ended input 1 = Differential input (default) RefDoubler_En R/W 1 Reference Doubler Enable Enables the Input Reference Doubler 0 = Input reference doubler disabled 1 = Input reference doubler enabled (default) Mult_En R/W 0 MULT Enable 0 = MULT not enabled 1 = MULT enabled ©2021 Renesas Electronics Corporation Description Input reference divide value 00 0000 0000 = d'1 00 0000 0001 = d'1 (default) ... 11 1111 1111 = d'1023 49 April 8, 2021 8V97003 Datasheet Table 46. Input Control Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) Description Mult_reset R/W 0 Mult R/W 000000 Mult_mux_ena R/W 0 Mux enable for the multiplier 0 = Multiplier mux is disabled (default) 1 = Multiplier mux is enabled Mult_d2s_ena R/W 0 Differential to single-ended block enable for the Multiplier 0 = Multiplier differential to single-ended block disabled (default) 1 = Multiplier differential to single-ended block enabled Mult_cp_ena R/W 0 Charge Pump enable for the multiplier 0 = Multiplier charge pump disabled (default) 1 = Multiplier charge pump enabled Mult_force_vchi R/W 0 Force Multiplier Control Voltage High 0 = Normal operation (default) 1 = Multiplier control voltage is charged to VDD Mult_force_vclow R/W 0 Force Multiplier Control Voltage Low[b] 0 = Normal operation (default) 1 = Multiplier control voltage is discharged to GND Resets the Reference Multiplier Block (MULT) 0 = Multiplier is active (default) 1 = Multiplier is reset[a] Frequency multiplication factor for the input clock. When enabled, the multiplier block (Mult) multiplies the input frequency to a higher frequency for the phase detector. 000000 = Unused 000001 = Unused 000010 = Unused 000011 = Multiplication by 3 000100 = Multiplication by 4 … 111111 = Multiplication by 63 [a] When Input Multiplier (MULT) is being used, it is recommended to program the device with proper MULT settings keeping Mult_reset = 1 and toggle it to low (active), then transfer the data using TransferOn Bit (Register 15, Bit 0) for Doubled-buffered registers and re-lock the PLL (ForceRelock). [b] If Input Multiplier is not used, it is recommended to program the Mult_force_vclow bit to 1 (High). ©2021 Renesas Electronics Corporation 50 April 8, 2021 8V97003 Datasheet Charge Pump Control Registers Table 47. Charge Pump Control Register Block Register Blocks (Hex) Register Block Descriptions 002D–0030 Charge Pump Control Registers Table 48. Charge Pump Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 002D Unused Unused Icp_pmos Icp_pmos Icp_pmos Icp_pmos Icp_pmos Icp_pmos 002E Unused Unused Icp_nmos Icp_nmos Icp_nmos Icp_nmos Icp_nmos Icp_nmos 002F CP_HiZ Icp_blee der Icp_bleeder Icp_bleeder Icp_bleeder Icp_bleeder Icp_bleeder Icp_bleeder 0030 Unused Unused Unused Unused pfd_pw pfd_pw 1 Unused Table 49. Charge Pump Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Icp_pmos[5:0][a] R/W 01 1101 Charge Pump Pmos Current Setting 00 0000 = 166uA 00 0001 = 333uA ... 01 1101 = 5mA (default) ... 11 1111 = 10.66mA Icp_nmos[5:0][b] R/W 01 1101 Charge Pump Nmos Current Setting 00 0000 = 166uA 00 0001 = 333uA ... 01 1101 = 5mA (default) ... 11 1111 = 10.66mA ©2021 Renesas Electronics Corporation Description 51 April 8, 2021 8V97003 Datasheet Table 49. Charge Pump Control Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) Description CP_HiZ R/W 0 Charge Pump High-Impedance Control 0 = Charge pump active 1 = Charge pump high-impedance Icp_bleeder[6:0][c] R/W 000 0000 Charge Pump Bleeder Current Setting 000 0000 = Off (0uA) (Default) 000 0001 = 20 uA 000 0010 = 40 uA ... 111 1111 = 2540 uA pfd_pw R/W 00 PFD Pulse Width Setting 00 = 260ps (default) 01 = 348ps 10 = 487ps 11 = 583ps [a] ICP_pmos = 166.66e - 6  (binary value + 1) [b] ICP_pmos = 166.66e - 6  (binary value + 1) [c] ICP_bleeder = 20e - 6 (binary value) Re-Sync Control Registers Table 50. Re-Sync Control Register Block Register Blocks (Hex) Register Block Descriptions 0031-0032 Re-Sync Control Registers Table 51. Re-sync Control Register Bits Addr 0031 0032 D7 1 AutoReSync D6 0 0 D5 0 0 D4 0 1 D3 1 0 D2 0 0 D1 0 1 D0 0 1 Table 52. Re-sync Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) AutoReSync R/W 0 ©2021 Renesas Electronics Corporation Description 0 = Normal operation and single-device operation 1 = Required setting for synchronizing the output phase of multiple devices. Waits for a pulse at the SYNC input and then resets the DSM. 52 April 8, 2021 8V97003 Datasheet Output Control Registers Table 53. Output Control Register Block Register Blocks (Hex) Register Block Descriptions 0033–003B Outputs Control Registers Table 54. Output Control Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0033 Unused Unused Unused Unused RF_OUTA_p wr RF_OUTA_p wr RF_OUTA_p wr RF_OUTA_p wr 0034 1 Unused Mute_until_LD RF_OUTA_ena 1 1 1 0 0035 Unused Unused Unused Unused RF_OUTB_p wr RF_OUTB_p wr RF_OUTB_p wr RF_OUTB_p wr 0036 1 Unused Unused RF_OUTB_e na 1 1 1 0 0037 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0038 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0039 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 003A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 003B OutDoubler_ Ena OutDivider_E na OutDoubler_ Freq Unused Unused OutDiv OutDiv OutDiv Table 55. Output Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Description RF_OUTA_pwr[3:0] R/W 0000 RF_OUTA Power Setting Set the output power for RF_OUTA. Higher setting number provides more output power up to a maximum value, depending on the output loading used. 0000 = OFF (default) 0001 = Minimum output power setting 1100–1111: Maximum output power setting Mute_until_LD R/W 0 Mute until Lock Detect selection 0 = Outputs are enabled independent of Lock Detect (default) 1 = Outputs are enabled only when Lock Detect is high RF_OUTA_ena R/W 0 RF_OUTA Enable 0 = RF_OUTA is disabled (MUTED) 1 = RF_OUTA is enabled ©2021 Renesas Electronics Corporation 53 April 8, 2021 8V97003 Datasheet Table 55. Output Control Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) Description RF_OUTB_pwr[3:0] R/W 0000 RF_OUTB Power Setting Set the output power for RF_OUTB. Higher setting number provides more output power up to a maximum value, depending on the output loading used. 0000 = OFF (Default) 0001 = Minimum output power setting 1100–1111: Maximum output power setting RF_OUTB_ena R/W 0 RF_OUTB Enable 0 = RF_OUTB is disabled (MUTED) 1 = RF_OUTB is enabled OutDoubler_Ena R/W 0 RF Output Doubler Enable[a] 0 = 1x path (Divide by 1) path Enabled (default)[b] 1 = 2x path Enabled (RF Output Doubler Enabled) OutDivider_Ena R/W 0 RF Output Divider Enable 0 = 1x or 2x path Enabled (default) 1 = RF Output Divider Enabled Note: The output divider M0 can only be used (OutDivider_Ena=1) if the output doubler is disabled (OutDoubler_Ena=0).[c] OutDoubler_Freq R/W 1 RF Output Doubler Frequency Setting 0 = Use this setting for VCO frequency = 7.0-9.0GHz (default) 1 = Use this setting for VCO frequency = 5.5-7.0GHz OutDiv[2:0] R/W 000 RF Output Divider (M0) Settings 000 = Unused 001 = Div By 2 010 = Div By 4 011 = Div By 8 100 = Div By 16 101 = Div By 32 110 = Unused 111 = Unused [a] OutDoubler_Ena can only be set to 1 if the VCO frequency is not greater than 9GHz. [b] For Divide by 1 (Output Divider and Doubler bypassed), both OutDoubler_Ena Bit and Out_Divider_Ena bit must be set 0 (Low). [c] Both the OutDoubler_Ena and Out_Divider_Ena bits must not be set 1 (High) at the same time. ©2021 Renesas Electronics Corporation 54 April 8, 2021 8V97003 Datasheet Status Registers Table 56. Status Register Block Register Blocks (Hex) Register Block Descriptions 0044 Digital Lock and Calibration and VCO Status Registers 0045 Digital Band Status Registers 0046–0047 Reserved 0048 Unused 0049 Loss of Lock Status Registers Table 57. Status Register Bits Addr D7 D6 D5 D4 D3 D2 D1 D0 0044 DigLock BandSelDone Unused Unused VcoSts VcoSts VcoSts VcoSts 0045 Unused BandSts BandSts BandSts BandSts BandSts BandSts BandSts 0046 0 0 0 0 0 0 0 0 0047 Unused Unused 0 0 0 0 0 0 0048 Unused Unused Unused Unused Unused Unused Unused Unused 0049 Unused Unused Unused Unused Unused LossLock Unused Unused Table 58. Status Register Descriptions Register Description Bit Field Name Field Type Default (Binary) DigLock R 0 Digital Lock 0 = PLL not locked 1 = PLL locked (according to LDP settings in Register 39) BandSelDone R 0 Band Select Done (calibration completed) 0 = Band selection not completed 1 = Band selection completed VcoSts[3:0] R 0000 BandSts[6:0] R 000 0000 ©2021 Renesas Electronics Corporation Description Status bits reporting the current VCO 0000 = VCO0 0001 = VCO1 … 0111 = VCO7 1000–1111 = Unused Status bits reporting the current digital band 000 0000 = Band0 000 0001 = Band1 ... 111 1111 = Band127 55 April 8, 2021 8V97003 Datasheet Table 58. Status Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) LossLock R/W1C 0 Description Status bit stating device loss of lock Sticky bit. Write 1 to this bit to clear 0 = Locked since last time register was cleared 1 = Loss of Lock since last time register was cleared Applications Information Loop Filter Calculations 2nd Order Loop Filter This section provides design information for a 2nd order loop filter for the 8V97003. A general 2nd order loop filter is shown in Figure 23. Step-by-step calculations to determine Rz, Cz, and Cp values for a desired loop bandwidth are described below. Required parameters are provided. A spreadsheet for calculating the loop filter values is also available. Figure 23. Typical 2nd Order Loop Filter CZ Cp RZ 1. Determine desired loop bandwidth fc. 2. Calculate Rz: 2    fc  NR Z = --------------------------------I CP  K VCO Where, ▪ ICP is charge pump current. ICP is programmable from 166µA to 10.66mA. ▪ N is effective feedback divider. N must be programmed into the following value. f VCO N = ---------------fP F D ▪ fVCO is VCO frequency. VCO frequency range: 5500 to 11000MHz ©2021 Renesas Electronics Corporation 56 April 8, 2021 8V97003 Datasheet ▪ fPFD is phase detector input frequency. f REF f PFD = -----------PV ▪ fREF is reference clock (REF_IN) input frequency. ▪ PV is overall pre-divider or input doubler setting. ▪ KVCO is VCO gain depends on VCO Frequency (see VCO gain in KVCO in Table 11). 3. Calculate Cz:  C Z = -------------------------------------2    fc  R Z Where, ▪  = fc/ fz, user can determine an  number. ▪  > 6 is recommended. fz is frequency at zero. 4. Calculate Cp: CZ C P = ----------- Where, ▪  = fp/fc, user can determine  number. ▪  > 4 is recommended. fp is frequency at pole. 5. Verify Phase Margin (PM). b–1 PM = ar tan  ----------------  2  b Where, b  1 Cz Cp The phase margin (PM) should be greater than 50°. A spreadsheet for calculating the loop filter component values is available at www.IDT.com. To use the spreadsheet, simply enter the following parameters: fc, F_ref, PV, Icp, FVCO,  and . The spreadsheet will provide the component values, Rz, Cz, and Cp as the result. The spreadsheet also calculates the maximum phase margin for verification. ©2021 Renesas Electronics Corporation 57 April 8, 2021 8V97003 Datasheet 3rd Order Loop Filter This section provides design information for a 3rd order loop filter for the 8V97003. A general 3rd order loop filter is shown in Figure 24. Figure 24. Typical 3rd Order Loop Filter RP2 Rp2 Rz RZ CCp P CCp2 P2 CCz Z The Rz, Cz, and Cp can be calculated as 2nd order loop filter. The following equation helps determine the 3rd order loop filter Rp2 and Cp2. Pick an Rp2 value. Rp2 ~ 1.5xRz is suggested. Where, ▪  is ratio between the 1st pole frequency and the 2nd pole frequency. ▪ > 4 is recommended. Figure 25 shows an example of a loop filter that can be used on the 8V97003. Figure 25. Loop Filter Example ©2021 Renesas Electronics Corporation 58 April 8, 2021 8V97003 Datasheet Recommendations for Unused Input and Output Pins Inputs LVCMOS Control Pins All control pins have internal pullup and pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs Output Pins For any unused output, it can be left floating and disabled. Schematic Example Figure 26 shows a general application schematic example for the 8V97003. For power rails, bypass capacitors must be provided to all power supply pins. At least one bypass capacitor per power pin is suggested. Value can range from 0.01µF or 0.1µF. Mix values of bypass capacitors can help filtering wider range of power supply noise. The 8V97003 input is high impedance. The input termination depends on the termination requirement from the driver. There are two input termination examples in the schematic shown in Figure 26; both are designed for transmission line with characteristic impedance Zo = 50Ω. The first example, labeled “Input Reference” at the lower right corner of the schematic, shows an input termination scheme for accepting a reference clock from bench signal generators. 50Ω resistors, R82 and R83 to GND, present matched loads to signal generator’s source impedance; the reference clock signal is then AC-coupled with capacitors C156 and C157 to ensure proper DC-biased to level of VDDx/2 by voltage divider networks of R90, R91, R92, and R93. The second example shows an input termination scheme for accepting a reference clock from a TCXO. The values of R96, R96, R85, and R88 in this example are designed for a TCXO with a single-ended CMOS output on pin 5. They can be changed for different TCXO output signal types. The 8V97003 output pull-up loading can be resistors or inductors. For inductor pull-up loading, the inductor value is frequency dependent. One inductor value cannot cover all the output frequency range. For example, an inductance of L = 1.3nH that is suitable for approximately 6GHz operating frequency. The output can also drive single ended LO input. Figure 26 also shows an example of the 8V97003 output driving single-ended LO input of the mixer through an LC balun. The LC balun component values are frequency dependent. These values can be adjusted to optimize the performance. A single-ended LO receiver input also can tap to one side of the differential driver using resistor loading or inductor loading. For single-ended LO input, both sides of the differential driver still need to be loaded with a pull up. The output power level can also be adjusted further through programming. The loop filter values can be calculated to meet the loop bandwidth requirement (for detailed calculations, see Loop Filter Calculations). ©2021 Renesas Electronics Corporation 59 April 8, 2021 8V97003 Datasheet Figure 26. Schematic Example 5 4 3 2 1 Board Layer Stack-up (62mil) TOP LAYER 1oz COPPER GROUND PLANE 4 4 POWER PLANE Place output traces on top layer. Make them as short as possible VDDOUTA 18nH L2 2 1 2 J1 GND_D 1 J2 C5 L3 GND_D 2 GND_D R4 50 1 C92 1 0.01u 3 J3 2 1 R3 50 37 48 32 35 1 4 11 C15 C17 C22 C24 C26 22u 22u 22u 22u 22u 2 6 9 13 16 21 34 36 42 43 GND_D 22 23 VDD_INPDFB nRESET J5 2 TP RF_OUTA nRF_OUTA VDDPDCP VDDFB VDDIN VDDDIG RF_OUTB nRF_OUTB VDDOUTA VDDOUTB VREGVCO1 VREFVCO1 VREFVCO2 VREGVCO2 CPBIAS NC NC NC NC NC NC NC NC NC NC REF_IN nREF_IN RESET 0.1u RF_OUTB CPOUT SYNC VTUNE CSB SCLK SDO SDIO LD MUTE CE VSSPDCP VSSFB VSSDIG VSSIN VSSOUTA1 VSSOUTA2 VSSOUTB1 VSSOUTB2 EPAD GND_D S1 J4 45 46 C14 GND_D 0.1u nRF_OUTB S1 10 30 5 GND_D S1 SPI_CSN SPI_CLK 25 26 27 28 SPI_CSN SPI_CLK SPI_SDO SPI_DIO SPI_DIO LD1 8 7 29 R5 3 3 1K J16 3 R6 R7 1K 360 C19 C20 2.7nF 680pF VDD_DIG 14 17 19 20 38 41 44 47 49 R8 R9 2.2K 2.2K C21 47nF 2 8V9700 nRESET R50 31 VDDVCO1 VDDVCO2 C13 40 39 G2 12 15 24 18 GND_D 2 U1 33 3 G5 GND_D 1 GND_D 3 GND_D S1 VDDOUTB 18nH 0.01u 2 GND_D 0.1u nRF_OUTA C12 0.01u G4 C11 G3 0.1u G5 C10 0.1u G4 C9 0.1u G3 C8 0.1u G2 C7 0.1u G5 C6 0.1u G4 C4 0.1u GND_D S1 G3 C3 0.1u 0.1u RF_OUTA G2 C2 C1 VDDVCO G5 VDD_INPDFB G4 VDD_DIG G3 VDDOUTA G2 VDDOUTB 1 0.01u G5 C91 G4 2 50 Placed decoupling capacitors close to power pins R2 50 G3 1 2 R1 G2 BOTTOM LAYER 1oz COPPER GND_D GND_D 1K G2 G3 G5 G4 GND_D GND_D C32 S1 0.1u REFIN VDD_DIG J6 R10 VDD_INPDFB REFIN R51 1K R12 R13 2.2K 2.2K GND_D G2 G3 G5 GND_D G4 R52 1K C33 S1 A2 SW1 A1 B2 B1 GND_D 2 TCXO Layout Notes: 0.1u 3 nREFIN J8 R15 nREFIN R53 R16 100 1K 50 GND_D GND_D GND_D 1. Overlapping U5 and U7 footprint 2. U7 uses 4 pads; U5 can use 6 pads (skipping 4 and 8) NC1 E_D GND 7 VDD DNI 0 DNI nREFIN REFIN VDDTCXO VDDTCXO R44 U7 1 0 R46 5 RHF7050 3. Keeping branching traces short 4. R46/47 are DNIs unless U5 or U7 is used R47 6 nOUT OUT 5. R44/45 and R48/49 are used only when U7 is used NC VCC GND OUT 4 R48 100 DNI 1K DNI 2 6. Place R46/R47 close to the branching point merging with SMA traces of the same net names. 1 VDDTCXO U5 1 50 3 R45 RPT5032N R49 100 DNI 1K 1 DNI GND_D GND_D GND_D Title Size C Date: 5 4 3 2 Document Number Rev Sheet Thursday, March 26, 2020 1 of 3 1 Power Considerations This section provides information on power dissipation and junction temperature for the 8V97003. Equations and example calculations are also provided. 1. Power Dissipation. The power dissipation for the 8V97003 is the total power minus the power dissipated into the loads. The following is the power dissipation for VDDx = 3.3V + 5% = 3.465V at ambient temperature of 95°C. Maximum current at 95°C, IDDx_MAX = 650mA (see Table 8) ▪ Total Power Dissipation: Power_MAX = VDDx_MAX * IDDx_MAX = 3.465V * 650mA = 2252mW ▪ Power dissipation in external loads for both outputs: Power (output)MAX = 2 * ILOAD2 * 50Ω = 22.5mW (Load Current with Out_Pwr = 0101, ILOAD = 15mA) Power Dissipation, PD = Power_MAX – Power (output)MAX = 2252mA - 22.5mW = 2229.5mW ©2021 Renesas Electronics Corporation 60 April 8, 2021 8V97003 Datasheet 2. Junction Temperature. Junction temperature, Tj, signifies the hottest point on the device and exceeding the specified limit could cause device reliability issues. The maximum recommended junction temperature is 125°C. For devices like this and in systems where most heat escapes from the bottom exposed pad of the package, θJB is the primary thermal resistance of interest. The equation to calculate Tj using θJB is: Tj = θJB * PD + TB: Tj = Junction Temperature θJB = Junction-to-Board Thermal Resistance PD = Device Power Dissipation (example calculation is in section 1 above) TB = Board Temperature In order to calculate junction temperature, the appropriate junction-to-board thermal resistance θJB must be used. Assuming a 2-ground plane board, the appropriate value of θJB is 0.76°C/W (see Table 6). Therefore, Tj for a PCB maintained at 105°C with the outputs switching is: 105°C + 2.2295W * 0.76°C/W = 106.5°C which is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, heat transfer method, the type of board (multi-layer) and the actual maintained board temperature. Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-70-x70-x-085-mm-body-05mm-pitch-epad-530-x-530-mm-nlg48p3 Marking Diagram ▪ Lines 1–3 indicate the part number. ▪ Line 4 indicates the following: • “#” denotes stepping. • “YY” is the last two digits of the year; “WW” is the work week number when the part • was assembled. “$” denotes the mark code. ©2021 Renesas Electronics Corporation 61 April 8, 2021 8V97003 Datasheet Ordering Information Table 59. Ordering Information Orderable Part Number Package Shipping Packaging Temperature Tray -40°C to +95°C 8V97003NLGI 7  7 mm 48-VFQFPN, Lead-free 8V97003NLGI8 7  7 mm 48-VFQFPN, Lead-free Pin 1 Orientation: Quadrant 1 (EIA-481-C) Tape and Reel -40°C to +95°C 8V97003NLGI/W 7  7 mm 48-VFQFPN, Lead-free Pin 1 Orientation: Quadrant 2 (EIA-481-D) Tape and Reel -40°C to +95°C Table 60. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation NLGI8 Quadrant 1 (EIA-481-C) NLGI/W Quadrant 2 (EIA-481-D) ©2021 Renesas Electronics Corporation Illustration 62 April 8, 2021 8V97003 Datasheet Revision History Revision Date April 8, 2021 Description of Change ▪ Added Figure 9 November 17, 2020 ▪ Changed the pull-up/pull-down status of pin 31 (nRESET) to PU in Pin Descriptions ▪ Updated Figure 25 ▪ Added a note to Reference Multiplier (MULT) September 15, 2020 ▪ ▪ ▪ ▪ ▪ April 7, 2020 January 20, 2020 Updated the phase adjustment formulas and the last sentence in Phase Adjust Updated the description of Output Phase Synchronization Updated the first line of each field description in Table 25 Updated the description of ManualReSync in Table 34 Updated the description of AutoReSync in Table 52 ▪ ▪ ▪ ▪ Updated the description of CE in Table 1 Updated the Power-Down Current parameter in Table 8 Updated Reference Input Stage Changed D7 in register 0x0028 to reserved. Also updated the description of VCO_En in the same register (see Power Down Control Registers) ▪ Updated the schematic example in Figure 26 ▪ Updated loop filter values and typo corrections ▪ Corrected a typo for the maximum power setting in the typical current in Table 9 ▪ Added a description for register 7 (Chip option) (see Table 16 and Table 22) ▪ Corrected the product description on page 1 to indicate output frequency support of “171.875MHz to 18GHz” January 8, 2020 December 20, 2019 ▪ Updated the fRF_OUT = 8GHz test condition for tjit(Ø) in Table 12 ▪ Updated Figure 4 ▪ Rebranded the document as Renesas Initial release. ©2021 Renesas Electronics Corporation 63 April 8, 2021 48-VFQFPN, Package Outline Drawing 7.0 x7.0 x 0.85 mm Body, 0.5mm Pitch, Epad 5.30 x 5.30 mm NLG48P3, PSC-4203-04, Rev 02, Page 1 © Integrated Device Technology, Inc. 48-VFQFPN, Package Outline Drawing 7.0 x7.0 x 0.85 mm Body, 0.5mm Pitch, Epad 5.30 x 5.30 mm NLG48P3, PSC-4203-04, Rev 02, Page 2 Package Revision History © Integrated Device Technology, Inc. Description Date Created Rev No. July 9, 2018 Rev 01 New Format, Change QFN to VFQFPN July 24, 2018 Rev 02 Change P4 to P3 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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