9112AM-17LF

ICS9112-17 Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description Features The ICS9112-17 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz. • • • ICS9112-17 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. Zero input - output delay Frequency range 25 - 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps cycle to cycle Jitter Skew controlled outputs Skew less than 250 ps between outputs Available in 16 pin, 150 mil SSOP & SOIC package • • • • Pin Configuration The ICS9112-17 has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). The ICS9112-17 comes in a sixteen pin 150 mil SOIC or 16 pin SSOP package. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. 16 pin SSOP & SOIC Block Diagram Functionality FS2 FS1 0051K—11/02/04 CLKA (1, 4) CLKB (1, 4) CLKOUT Output Source PLL Shutdown 0 0 Tristate Tristate Driven PLL N 0 1 Driven Tristate Driven PLL N 1 0 PLL PLL Bypass Bypass Mode Mode PLL Bypass Mode REF Y 1 1 Driven Driven PLL N Driven ICS9112-17 Pin Descriptions PIN NUMBER 1 2 3 PIN NAME 2 REF IN 4, 13 VDD 5, 12 GND DESCRIPTION Input reference frequency. 3 OUT Buffered clock output, Bank A 3 OUT Buffered clock output, Bank A PWR Power Supply (3.3V) CLKA1 CLKA2 TYPE PWR Ground CLKB1 3 OUT Buffered clock output. Bank B 7 CLKB2 3 OUT Buffered clock output. Bank B 8 FS24 IN Select input, bit 2 9 FS14 IN Select input, bit 1 10 CLKB33 OUT Buffered clock output. Bank B 11 CLKB4 3 OUT Buffered clock output. Bank B CLKA3 3 OUT Buffered clock output, Bank A CLKA4 3 OUT Buffered clock output, Bank A OUT Buffered clock output, internal feedback on this pin 6 14 15 16 CLKOUT 3 Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 4. Weak pull-ups on these inputs 0051K—11/02/04 2 ICS9112-17 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input & Supply TA = 0 - 70C; Supply Voltage VDD = 5.0 V +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating current Input frequency Input Capacitance 1 SYMBOL CONDITIONS V IH V IL VIN = VDD IIH VIN = 0 V; IIL CL = 0 pF; FIN @ 66M IDD1 Fi1 CIN1 MIN 2.0 GND -0.5 TYP MAX UNITS 2.5 VDD +0.5 V 0.8 V 0.1 100 uA 19 50 uA 45 65 mA 25 133 MHz 5 pF VDD = 3.3 V; All Outputs Loaded Logic Inputs Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input & Supply TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating current Input frequency Input Capacitance SYMBOL CONDITIONS VIH VIL VIN = V DD IIH IIL VIN = 0 V; CL = 0 pF; FIN @ 66M IDD1 Fi 1 CIN1 VDD = 3.3 V; All Outputs Loaded Logic Inputs 1 Guarenteed by design, not 100% tested in production. 0051K—11/02/04 3 MIN 2.0 GND-0.3 TYP 2.0 0.1 19 30 25 MAX UNITS V DD+0.3 V 0.8 V 100 uA 50 uA 45 mA 133 MHz 5.0 pF ICS9112-17 Electrical Characteristics - OUTPUT TA = 0 - 70°C; VDD = VDDL = 5.0 V +/-10%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Rise Time1 1 Fall Time Tr CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) I OH = -8 mA I OL = 8 mA MIN 10 10 2.4 1 Duty Cycle Cycle to Cycle jitter1 Absolute Jitter1 Jitter; 1-Sigma1 Skew1 Device to Device Skew1 Delay Input-Output 1 TYP 2.9 0.25 MAX UNITS 24 Ω 24 Ω 5.0 V 0.4 V VOL = 0.8 V, V OH = 2.0 V 0.8 1.5 ns VOH = 2.0 V, VOL = 0.8 V Stable power supply, valid clock tLOCK presented on REF pin Dt VT = 1.4V;Cl=30pF Tcyc-cyc at 66MHz , Loaded Outputs Tcyc-cyc >66MHz , Loaded Outputs Tjabs 10000 cycles; Cl=30pF Tj1s 10000 cycles; Cl=30pF Tsk VT = 1.4 V (Window) Output to Output Measured at VDD/2 on the CLKOUT Tdsk-Tdsk pins of devices DR1 VT = 1.4 V 1.0 1.5 ns 1.0 ms 60 250 200 100 30 250 % ps ps ps ps ps 0 700 ps 0 700 ps Tf PLL Lock Time1 1 SYMBOL RDSP RDSN VOH V OL 40 50 -100 60 14 Guaranteed by design, not 100% tested in production. Electrical Characteristics - OUTPUT TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Rise Time1 SYMBOL RDSP RDSN VOH VOL Fall Time1 Tf Tr CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 8 mA VOL = 0.8 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.8 V Stable power supply, valid clock PLL Lock Time1 tLOCK presented on REF pin D VT = 1.4V;Cl=30pF t Duty Cycle1 Dt VT = Vdd/2; Fout 66MHz , Loaded Outputs Tjabs 10000 cycles; Cl=30pF Absolute Jitter1 1 Tj1s 10000 cycles; Cl=30pF Jitter; 1-Sigma Skew1 Tsk VT = 1.4 V (Window) Output to Output Measured at VDD/2 on the CLKOUT Device to Device Skew1 Tdsk-Tdsk pins of devices Delay Input-Output1 DR1 VT = 1.4 V 1 MIN 10 10 2.4 Guaranteed by design, not 100% tested in production. 0051K—11/02/04 4 TYP 2.9 0.25 MAX UNITS 24 Ω 24 Ω 3.3 V 0.4 V 1.2 2.0 ns 1.2 2.0 ns 1.0 ms 60 55 250 200 100 30 250 % % ps ps ps ps ps 0 700 ps 0 700 ps 40 45 50 50 -100 70 14 ICS9112-17 Output to Output Skew The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded than CLKOUT, CLKA/B will lag the CLKOUT. Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLKA/B outputs loaded equally, with CLKOUT loaded More. 0051K—11/02/04 REF input and CLKA/B outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations 5 ICS9112-17 Application Suggestion: ICS9112-17 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess jitter to the outputs of ICS9112-17. Below is a recommended lay out to alleviate any addition noise. For additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line stability. 33Ω 33Ω 0.1µF 33Ω 33Ω 10KΩ 1 REF CLKOUT 16 2 CLKA1 CLKA4 15 3 CLKA2 CLKA3 14 4 VDD VDD 13 5 GND GND 12 6 CLKB1 CLKB4 11 7 CLKB2 CLKB3 10 8 FS2 FS1 9 33Ω 33Ω 33Ω 0.1µF 33Ω 33Ω 10KΩ GND GND VDD VDD 0051K—11/02/04 6 ICS9112-17 SYMBOL A A1 A2 b c D E E1 e L N α ZD 150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° SEE VARIATIONS SEE VARIATIONS VARIATIONS N 16 D mm. MIN 4.80 MAX 5.00 ZD (Ref) 0.23 D (inch) MIN .189 MAX .197 Reference Doc.: JEDEC Publication 95, MO-137 10-0032 Ordering Information 9112yF-17LF-T Example: XXXX y F PPP Lx- T 0051K—11/02/04 Designation for tape and reel packaging Lead Option (Optional) LF = Lead Free LN = Lead Free Annealed Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type P 7 ZD (Ref) .009 ICS9112-17 150 mil (Narrow Body) SOIC In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D SEE VARIATIONS SEE VARIATIONS E 3.80 4.00 .1497 .1574 0.050 BASIC e 1.27 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° α C N L INDEX AREA H E h x 45° 1 2 D α A A1 e B SEATING PLANE VARIATIONS N .10 (.004) 16 D mm. MIN 9.80 MAX 10.00 D (inch) MIN MAX .3859 .3937 Reference Do c.: JEDEC P ublicatio n 95, M S-012 10-0030 Ordering Information 9112yM-17LF-T Example: XXXX y M PPP Lx- T Designation for tape and reel packaging Lead Option (Optional) LF = Lead Free LN = Lead Free Annealed Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M = SOIC 0051K—11/02/04 Revision Designator (will not correlate with datasheet revision) Device Type P 8