932S401EGLFT

ICS932S401 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for Intel-based Servers Recommended Application: CK410B clock for Intel-based servers Output Features: • 4 - 0.7V current-mode differential CPU pairs • 5 - 0.7V current-mode differential SRC pair • 4 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - 48MHz • 2 - REF, 14.318MHz Key Specifications: • CPU cycle-cycle jitter: < 50ps • SRC cycle-cycle jitter: < 125ps • PCI cycle-cycle jitter: < 500ps • CPU output skew: < 50ps • SRC output skew: < 250ps • ± 300ppm frequency accuracy on all outputs except 48MHz • ± 100ppm frequency accuracy on 48MHz Features/Benefits: • Supports spread spectrum modulation, 0 to -0.5% down spread 1 FS_C 0 0 0 0 1 1 1 1 1 2 FS_B FS_A 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error • • CPU clocks independent of SRC/PCI clocks D2/D3 SMBus address Pin Configuration SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI REF MHz MHz 33.33 14.318 33.33 14.318 33.33 14.318 33.33 14.318 33.33 14.318 33.33 14.318 33.33 14.318 Reserved USB MHz 48.000 48.000 48.000 48.000 48.000 48.000 48.000 1. FS_B and FS_C are three-level inputs. Please see VIL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_A is a low-threshold input. Please see the V IL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. VDDPCI GNDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI VDDPCI PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 48MHz GND48 VDDSRC SRCCLKT0 SRCCLKC0 SRCCLKC1 SRCCLKT1 GNDSRC SRCCLKT2 SRCCLKC2 SRCCLKC3 SRCCLKT3 VDDSRC SRCCLKT4 SRCCLKC4 VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS932S401 932S401 Functionality • 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_C/TEST_SEL REF0 REF1 VDDREF X1 X2 GNDREF FS_B/TEST_MODE FS_A VDDCPU CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GNDCPU CPUCLKT2 CPUCLKC2 VDDCPU CPUCLKT3 CPUCLKC3 VDDA GNDA IREF NC Vtt_PwrGd#/PD SDATA SCLK 56-pin SSOP & TSSOP 0921G—08/24/09 Integrated Circuit Systems, Inc. ICS932S401 Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VDDPCI GNDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI VDDPCI PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 48MHz GND48 VDDSRC SRCCLKT0 SRCCLKC0 SRCCLKC1 SRCCLKT1 GNDSRC SRCCLKT2 SRCCLKC2 SRCCLKC3 SRCCLKT3 VDDSRC SRCCLKT4 SRCCLKC4 VDDSRC PIN TYPE PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT PWR OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT OUT OUT PWR OUT OUT PWR DESCRIPTION Power supply for PCI clocks, nominal 3.3V Ground pin for the PCI outputs PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power pin for the 48MHz output.3.3V 48MHz clock output. Ground pin for the 48MHz outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal 0921G—08/24/09 2 Integrated Circuit Systems, Inc. ICS932S401 Pin Description (Continued) Pin # 29 30 PIN NAME SCLK SDATA Type IN I/O 31 Vtt_PwrGd#/PD 32 NC N/A 33 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 34 35 GNDA VDDA PWR PWR Ground pin for the PLL core. 3.3V power for the PLL core. 36 CPUCLKC3 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 37 CPUCLKT3 OUT 38 VDDCPU PWR 39 CPUCLKC2 OUT 40 CPUCLKT2 OUT 41 GNDCPU PWR 42 CPUCLKC1 OUT 43 CPUCLKT1 OUT 44 VDDCPU PWR 45 CPUCLKC0 OUT 46 CPUCLKT0 OUT 47 VDDCPU PWR 48 FS_A IN 49 FS_B/TEST_MODE IN 50 51 52 53 54 55 GNDREF X2 X1 VDDREF REF1 REF0 56 FS_C/TEST_SEL IN Pin Description Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. No Connection. PWR OUT IN PWR OUT OUT IN True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin for the CPU outputs Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for the REF outputs. Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock. 14.318 MHz reference clock. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 0921G—08/24/09 3 Integrated Circuit Systems, Inc. ICS932S401 General Description ICS932S401 is a main clock synthesizer for CK410-generation Intel server platforms. ICS932S401 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz USB clock is an exact 48.000 MHz clock. The ICS932S401 generates all clocks with less the +/- 300 ppm error. Block Diagram REF(1:0) X1 X2 48MHz XTAL OSC. FIXED PLL DIVIDER CPU PLL DIVIDERS SRC/PCI PLL DIVIDERS CPUCLK(2:0) SRCCLK(4:0) PCICLK(3:0), PCICLK_F(2:0) FS(C:A) TEST_SEL CONTROL LOGIC VTT_PWRGD#/PD SDATA SCLK IREF Power Groups Pin Number VDD GND 53 50 1,8 2,7 15,25,28 20 35 34 12 14 47,44,38 41 Description Xtal, Ref PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL_48 CPUCLK clocks 0921G—08/24/09 4 Integrated Circuit Systems, Inc. ICS932S401 Absolute Max Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 2000 Units V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors VSS - 0.3 -5 0.8 5 V uA I IL1 Input Low Current I IL2 MIN TYP MAX UNITS NOTES -5 uA -200 uA Low Threshold Input High Voltage VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V Low Threshold Input Low Voltage VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V Operating Supply Current IDD3.3OP 3.3 V +/-5%, Full Load 270 350 mA Powerdown Current I DD3.3PD Fi Lpin CIN COUT CINX 60 9 14.31818 90 15 Input Frequency 3 Pin Inductance1 all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 7 5 6 5 mA mA MHz nH pF pF pF 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 300 us 1 5 5 5.5 0.4 ns ns V V mA 1 2 1 1 1 (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 Input Capacitance1 Clk Stabilization1,2 TSTAB Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage VIMAX Low-level Output Voltage VOLSMBUS Current sinking at VOL = 0.4 V IPULLUP SCLK/SDATA TRI2C Clock/Data Rise Time SCLK/SDATA TFI2C Clock/Data Fall Time Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of Max. Voltage on SCLK/SDAT @ I PULLUP 30 4 1 Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 2 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs. 0921G—08/24/09 5 Integrated Circuit Systems, Inc. ICS932S401 Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Variation of crossing over all edges Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP 775 MAX UNITS NOTES Ω 1 850 1 mV -150 70 150 1150 -300 250 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.4128 9.8720 175 175 1 355 550 mV 1 1 1 90 140 mV 1 0 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 240 359 49 59 700 700 125 125 ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 mV Measurement from differential 45 49 55 % wavefrom tsk3 CPU (3:0) VT = 50% Skew 33 50 ps Measurement from differential tjcyc-cyc 38 50 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz Duty Cycle dt3 0921G—08/24/09 6 1 1 1 Integrated Circuit Systems, Inc. ICS932S401 Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage SYMBOL CONDITIONS MIN Zo VO = Vx 3000 VHigh VLow Vovs Vuds Statistical measurement on single ended signal using oscilloscope Measurement on single ended signal using absolute value. 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf MAX UNITS NOTES Ω 780 10 850 150 1150 -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP mV mV 1 1 1 1 1 369 550 mV 1 57 140 mV 1 ppm ns ns ns ps ps ps ps 1,2 2 2 1,2 1 1 1 1 -300 0 300 9.9970 10.0030 9.9970 10.0533 9.8720 175 283 700 175 291 700 27 125 30 125 Measurement from differential 45 51 55 % 1 wavefrom SRC(4:0), VT = 50% tsk3 15 250 ps 1 Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 38 125 ps 1 wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz Duty Cycle dt3 0921G—08/24/09 7 Integrated Circuit Systems, Inc. ICS932S401 Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 33.33MHz output nominal Tperiod Clock period 33.33MHz output spread Absolute Min/Max Clock 33.33MHz output nominal Tabs period 33.33MHz output spread th1 Clk High Time tl1 Clock Low Time IOH = -1 mA VOH Output High Voltage IOL = 1 mA VOL Output Low Voltage V OH @MIN = 1.0 V IOH Output High Current VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V IOL Output Low Current VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V tr1 Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 Fall Time dt1 VT = 1.5 V Duty Cycle VT = 1.5 V tsk1 Skew VT = 1.5 V tjcyc-cyc Jitter 1 2 MIN TYP MAX UNITS -300 0.00 300 ppm 29.99100 30.00900 ns 29.99100 30.15980 ns 29.49100 30.50900 ns 29.49100 30.65980 ns 12 N/A ns 12 N/A ns 2.4 V 0.55 V -33 mA -33 mA 30 mA 38 mA 0.5 0.74 2 ns 0.5 0.73 2 ns 45 50.4 55 % 43 500 ps 98 500 ps Notes 1,2 2 2 2 2 1 1 1 1 1 1 1 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz Electrical Characteristics - 48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Long Accuracy Clock period Absolute Min/Max Clock period Clk High Time Clock Low Time ppm Tperiod see Tperiod min-max values 48.0000MHz output nominal -100 20.83125 0 100 20.83542 ppm ns 1,2 2 Tabs Nominal 20.48125 21.18542 ns 2 1 1 Output High Current IOH ns ns mA mA mA mA ns ns % ps th1 tl1 Output Low Current IOL Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle tr1 tf1 dt1 tjcyc-cyc V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 1 8.094 7.694 -33 -33 30 1 1 45 1.1 1.3 52.3 243 38 2 2 55 350 UNITS Notes 1 1 1 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz 0921G—08/24/09 8 Integrated Circuit Systems, Inc. ICS932S401 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX Long Accuracy Clock period Absolute Min/Max Clock period Output High Voltage Output Low Voltage ppm Tperiod see Tperiod min-max values 14.318MHz output nominal -300 69.82033 0 300 69.86224 ppm ns 1 1 Tabs Nominal 68.82033 70.86224 ns 2 VOH VOL 2.4 0.4 V V 1 1 Output High Current IOH -29 -23 mA 1 Output Low Current IOL 29 27 mA 1 Rise Time Fall Time Skew Duty Cycle Jitter tr1 tf1 tsk1 dt1 IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 2 2 500 55 1000 ns ns ps % ps 1 1 1 1 1 tjcyc-cyc Guaranteed by design, not 100% tested in production. 0921G—08/24/09 9 0.5 0.5 45 0.6 0.85 26 52.7 917 UNITS NOTES Integrated Circuit Systems, Inc. ICS932S401 Single-ended Output Terminations ICS932S401 Zo Rs CL=5pF Test Load SEPP Output Buffer (Single Ended Push Pull) Zo Rs CL=5pF Zo Rs CL=5pF SEPP Output Buffer (Single Ended Push Pull) The singled-ended outputs of the ICS 932S401E default to a drive strength of 2 loads. The REF clocks can be turned down to 1-load strength via the SMBus. Suggested termination resistors are as follows for transmission lines with Zo = 50 ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Driving 1 load, Rs = 33 ohms Driving 2 loads, Rs = 7.5 ohms Single-ended outputs at 1-load strength (REF clock only) Driving 1 load, Rs = 22 ohms 0921G—08/24/09 10 Integrated Circuit Systems, Inc. ICS932S401 General SMBus serial interface information for the ICS932S401 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) T ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0921G—08/24/09 11 Not acknowledge stoP bit Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: SRC Output Enable Register Byte 0 Bit 7 Pin # NA Name SRCCLK7 Enable Control Function Output Enable Type RW 0 Disable-Hi-Z 1 Enable PWD 1 Bit 6 NA SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 NA SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 26,27 SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 23,24 SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 21,22 SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 18,19 SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 16,17 SRCCLK0 Enable Output Enable RW Disable-Hi-Z Enable 1 Type RW 0 Disable-Low 1 Enable PWD 1 SMBus Table: CPU, REF and 48 MHz Output Enable Register Byte 1 Bit 7 Pin # Name REF1 Enable Control Function Output Enable Bit 6 54 55 REF0 Enable Output Enable RW Disable-Low Enable 1 Bit 5 36,37 CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1 Bit 4 39,40 CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 Bit 2 Bit 1 Bit 0 0 RESERVED 42,43 45,46 CPU, SRC, PCI CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1 CPUCLK0 Output Enable RW Disable-Hi-Z Enable 1 Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0 SMBus Table: PCI and PCICLK_F Output Enable Register Byte 2 Bit 7 Pin # 6 Name PCICLK3 Control Function Output Enable Type RW 0 Disable-Low 1 Enable PWD 1 Bit 6 5 PCICLK2 Output Enable RW Disable-Low Enable 1 Bit 5 4 PCICLK1 Output Enable RW Disable-Low Enable 1 Bit 4 3 PCICLK0 Output Enable RW Disable-Low Enable 1 Bit 3 11 PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 10 PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 9 PCICLK_F0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 13 48MHz Enable Output Enable RW Disable-Low Enable 1 1 Stoppable PWD 1 1 SMBus Table: PCICLK_F and SRC Stop Control Register Byte 3 Bit 7 Pin # 11 Name PCICLK_F2 Stop En Control Function Bit 6 10 PCICLK_F1 Stop En RW Free-Running Stoppable Bit 5 9 PCICLK_F0 Stop En RW Free-Running Stoppable 1 Bit 4 26,27 SRCCLK4 Stop En RW Free-Running Stoppable 1 Bit 3 23,24 SRCCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 21,22 SRCCLK2 Stop En RW Free-Running Stoppable 1 Bit 1 18,19 SRCCLK1 Stop En RW Free-Running Stoppable 1 Bit 0 16,17 SRCCLK0 Stop En RW Free-Running Stoppable 1 Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 6, bit 3) 0921G—08/24/09 12 Type 0 RW Free-Running Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: CPU and SRC Stop and Power Down Mode Drive Control Register Byte 4 Bit 7 36,37 Name CPUCLK3 PD Drive Control Function Drive Mode in PD Type RW 0 Driven 1 Hi-Z PWD 0 Bit 6 39,40 CPUCLK2 PD Drive Drive Mode in PD RW Driven Hi-Z 0 Drive mode in PD RW Driven Hi-Z 0 Bit 4 42,43 45,46 CPUCLK1 PD Drive CPUCLK0 PD Drive Drive mode in PD RW Driven Hi-Z 0 Bit 3 36,37 CPUCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 39,40 CPUCLK2 Stop En RW Free-Running Stoppable 1 42,43 45,46 CPUCLK1 Stop En RW Free-Running Stoppable 1 RW Free-Running Stoppable 1 Type 0 1 PWD 0 Bit 5 Bit 1 Bit 0 Pin # Free-Running Control, Default: not affected by CPU_STOP CPUCLK0 Stop En SMBus Table: Output and Spread Spectrum Control Register Byte 5 Pin # Name Bit 7 Control Function RESERVED Bit 6 SRC SRC Stop Drive Mode Driven in STOP RW Driven Hi-Z 0 Bit 5 SRC SRC PD Drive Mode Driven in PD RW Driven Hi-Z 0 RESERVED Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 36,37 CPUCLK3 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 39,40 CPUCLK2 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 42,43 45,46 CPUCLK1 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 CPUCLK0 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 PWD 0 SMBus Table: Device ID Register Byte 6 Bit 7 - Name Test Mode Selection Control Function Test Mode Selection Type RW 0 Hi-Z 1 REF/N Bit 6 - Test Clock Mode Entry Test Mode RW Disable Enable Bit 5 - Bit 4 54,55 REF Drive Strength Bit 3 PCI, SRC PCI_STOP Control Bit 2 - Bit 1 Bit 0 Pin # RESERVED 0 0 RW 1X 2X 1 RW Stop Run 1 FS_C 1X or 2X Stop non-free running PC and SRC clocks. FS_C readback FS_B FS_B readback R FS_A FS_A readback R Control Function R See 932S401 Functionality Table Latch Latch Latch SMBus Table: Vendor & Revision ID Register Byte 7 Type 0 1 PWD Bit 7 - Pin # Name RID3 R - - X Bit 6 - RID2 R - - X Bit 5 - RID1 R - - X Bit 4 - RID0 R - - X Bit 3 - VID3 R - - 0 Bit 2 - VID2 R - - 0 Bit 1 - VID1 R - - 0 Bit 0 - VID0 R - - 1 REVISION ID VENDOR ID 0921G—08/24/09 13 Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: Byte Count Register Byte 8 Bit 7 - Pin # Name BC7 Control Function Bit 6 - BC6 RW Bit 5 - BC5 RW Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 RW Bit 1 - BC1 RW 1 Bit 0 - BC0 RW 1 Byte Count Programming b(7:0) Type RW RW RW 0 1 PWD 0 0 Writing to this register will configure how many bytes will be read back, default is 8 bytes. (0 to 7) 0 0 0 1 SMBus Table: Device ID Register Byte 9 Bit 7 Pin # Name DID7 Bit 6 Bit 5 Bit 4 DID4 Bit 3 DID3 Control Function Type R 0 - 1 - PWD 0 DID6 R - - 0 DID5 R - - 0 R - - 0 R - - 1 Bit 2 DID2 R - - 0 Bit 1 DID1 R - - 1 Bit 0 DID0 R - - 1 Type 0 1 PWD RW Disable Enable 0 RW Stop Run 1 Device ID (0B hex) SMBus Table: M/N Programming & Control Register Byte 10 Pin # Name Bit 7 - M/N_EN Bit 6 CPU CPU_STOP Control Bit 5 - Bit 4 - Bit 3 SRC, PCI Control Function CPU and SRC M/N Programming Enable Stop non-free running PC and SRC clocks. RESERVED 0 RESERVED Set SRC = 96 MHz and PCI = 32 MHz SRC Alternate Frequency Only active if (96% of Nominal) Byte 10, bit 2 = 1 Bit 2 CPU Bit 1 55 CPU Alternate Frequency (96% of Nominal) Only active if latched frequency is 166 MHz or 333 MHz. REF0 Drive Strength Bit 0 54 REF1 Drive Strength 0 RW Normal Alternate Frequency 0 Set alternate CPU frequency: 166 MHz to 160 MHz 333 MHz to 320 MHz RW Normal Alternate Frequency 0 1X or 2X RW 1X or 2X RW See REF Drive Strength Functionality Table 0921G—08/24/09 14 1 1 Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: CPU Frequency Control Register Byte 11 Bit 7 - Pin # Name CPU N Div8 Control Function N Divider Prog bit 8 Type RW Bit 6 - CPU N Div9 N Divider Prog bit 9 RW Bit 5 - CPU M Div5 Bit 4 - CPU M Div4 Bit 3 - CPU M Div3 Bit 2 - CPU M Div2 Bit 1 - CPU M Div1 RW Bit 0 - CPU M Div0 RW RW RW M Divider Programming bit (5:0) RW RW 0 1 The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X SMBus Table: CPU Frequency Control Register Byte 12 Bit 7 - Pin # Name CPU N Div7 Control Function Bit 6 - CPU N Div6 RW Bit 5 - CPU N Div5 RW Bit 4 - CPU N Div4 Bit 3 - CPU N Div3 Bit 2 - CPU N Div2 RW Bit 1 - CPU N Div1 RW Bit 0 - CPU N Div0 RW N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) Type RW RW RW 0 1 The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X SMBus Table: CPU Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 0 1 PWD Bit 7 - CPU SSP7 RW X Bit 6 - CPU SSP6 RW X Bit 5 - CPU SSP5 RW X Bit 4 - CPU SSP4 Bit 3 - CPU SSP3 Bit 2 - CPU SSP2 These Spread Spectrum bits in Byte 13 and 14 will program RW the spread pecentage of CPU RW Bit 1 - CPU SSP1 RW X Bit 0 - CPU SSP0 RW X Spread Spectrum Programming bit(7:0) RW X X X SMBus Table: CPU Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Type 0 1 PWD 0 Bit 7 - Bit 6 - CPU SSP14 RW X Bit 5 - CPU SSP13 RW X Bit 4 - CPU SSP12 X Bit 3 - CPU SSP11 Bit 2 - CPU SSP10 RW These Spread Spectrum bits in RW Byte 13 and 14 will program the spread pecentage of CPU RW Bit 1 - CPU SSP9 RW X Bit 0 - CPU SSP8 RW X Spread Spectrum Programming bit(14:8) 0921G—08/24/09 15 X X Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: SRC Frequency Control Register Byte 15 Bit 7 - Pin # Name SRC N Div8 Control Function N Divider Prog bit 8 Type RW Bit 6 - SRC N Div9 N Divider Prog bit 9 RW Bit 5 - SRC M Div5 RW Bit 4 - SRC M Div4 RW Bit 3 - SRC M Div3 RW Bit 2 - SRC M Div2 Bit 1 - SRC M Div1 RW Bit 0 - SRC M Div0 RW M Divider Programming bits RW 0 1 The decimal representation of M and N Divider in Byte 15 and 16 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X SMBus Table: SRC Frequency Control Register Byte 16 Bit 7 - Pin # Name SRC N Div7 Control Function Bit 6 - SRC N Div6 RW Bit 5 - SRC N Div5 RW Bit 4 - SRC N Div4 RW Bit 3 - SRC N Div3 Bit 2 - SRC N Div2 RW Bit 1 - SRC N Div1 RW Bit 0 - SRC N Div0 RW N Divider Programming b(7:0) Type RW RW 0 1 The decimal representation of M and N Divider in Byte 15 and 16 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X SMBus Table: SRC Spread Spectrum Control Register Byte 17 Bit 7 - Pin # Name SRC SSP7 Control Function Bit 6 - SRC SSP6 RW X Bit 5 - SRC SSP5 RW X Bit 4 - SRC SSP4 RW Bit 3 - SRC SSP3 Bit 2 - SRC SSP2 These Spread Spectrum bits in Byte 17 and 18 will program RW the spread pecentage of SRC RW Bit 1 - SRC SSP1 RW X Bit 0 - SRC SSP0 RW X Spread Spectrum Programming b(7:0) Type RW 0 1 PWD X X X X SMBus Table: SRC Spread Spectrum Control Register Byte 18 Bit 7 - Pin # Name Reserved Control Function Reserved Bit 6 - SRC SSP14 RW X Bit 5 - SRC SSP13 RW X Bit 4 - SRC SSP12 X Bit 3 - SRC SSP11 Bit 2 - SRC SSP10 RW These Spread Spectrum bits in RW Byte 17 and 18 will program RW the spread pecentage of SRC Bit 1 - SRC SSP9 RW X Bit 0 - SRC SSP8 RW X Spread Spectrum Programming b(14:8) 0921G—08/24/09 16 Type R 0 - 1 - PWD 0 X X Integrated Circuit Systems, Inc. ICS932S401 SMBus Table: CPU Programmable Output Divider Register Byte 19 Pin # Name Bit 7 - CPUDiv3 Bit 6 - CPUDiv2 Bit 5 - CPUDiv1 Bit 4 - CPUDiv0 Control Function Type 0 1 RW CPU Divider Ratio Programming Bits RW RW PWD X See CPU, SRC and PCI Divider Ratios Table RW X X X Bit 3 RESERVED X Bit 2 RESERVED X Bit 1 RESERVED X Bit 0 RESERVED X SMBus Table: SRC and PCI Programmable Output Divider Register Byte 20 Bit 7 - Pin # Name PCIDiv3 Control Function Bit 6 - PCIDiv2 Bit 5 - PCIDiv1 Bit 4 - PCIDiv0 RW Bit 3 - SRC_Div3 RW Bit 2 - SRC_Div2 RW Bit 1 - SRC_Div1 Bit 0 - SRC_Div0 PCI Divider Ratio Programming Bits SRC_ Divider Ratio Programming Bits Type RW RW RW RW 0 1 See CPU, SRC and PCI Divider Ratios Table PWD X X X X X See CPU, SRC and PCI Divider Ratios Table RW X X X SMBusTable: Test Byte Register Type RW Test Result ICS ONLY TEST Reserved PWD 0 Bit 6 ICS ONLY TEST RW Reserved 0 Bit 5 ICS ONLY TEST RW Reserved 0 Bit 4 ICS ONLY TEST RW Reserved 0 Bit 3 ICS ONLY TEST RW Reserved 0 Bit 2 ICS ONLY TEST RW Reserved 0 Bit 1 ICS ONLY TEST RW Reserved 0 Bit 0 ICS ONLY TEST RW Reserved 0 Byte 21 Bit 7 Test ` Test Function Note: Do NOT write to Bit 21. Erratic device operation will result! 0921G—08/24/09 17 Integrated Circuit Systems, Inc. REF Drive Strength Functionality Byte6, Byte 10, Byte 10, bit 4 bit 1 bit 0 REF1 0 X X 1x 1 0 0 1x 1 0 1 1x 1 1 0 2x 1 1 1 2x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ICS932S401 REF0 1x 1x 2x 1x 2x CPU, SRC and PCI Divider Ratios Div(3:0) Divider 0000 2 0001 3 0010 5 0011 15 0100 4 0101 6 0110 10 0111 30 1000 8 1001 12 1010 20 1011 60 1100 16 1101 24 1110 40 1111 120 0921G—08/24/09 18 Integrated Circuit Systems, Inc. ICS932S401 PD, Power Down PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down. When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is de-asserted. PD CPU CPU # SRC SRC# PCIF/PCI USB REF Note 1 Normal Normal Normal Normal 33MHz 48MHz 14.318MHz 1 0 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low 1 Notes: 1. Refer to SMBus Byte 4 for additional information. PD Assertion PD# should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. See SMBus Byte 4 for additional information. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz PCI, 33MHz REF, 14.31818 0921G—08/24/09 19 Integrated Circuit Systems, Inc. ICS932S401 PD De-assertion The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. Tstable 3-level latched input If power-up w/ V>2.0V (-0.3V) then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B6b6. If test mode is invoked by B6b6, only B6b7 is used to select HI-Z or REF/N FS_B/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) 0921G—08/24/09 20 REF/N or HI-Z B6b7 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N Integrated Circuit Systems, Inc. ICS932S401 c N SYMBOL A A1 b c D E E1 e h L N a L E1 INDEX AREA E 1 2 α h x 45° D In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N A 56 -Cb D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 A1 e D mm. MIN 18.31 10-0034 SEATING PLANE .10 (.004) C 0921G—08/24/09 21 MIN .720 MAX .730 Integrated Circuit Systems, Inc. ICS932S401 c N L E1 INDEX AREA E 1 2 a D A A2 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N A1 56 -C- D mm. MIN 13.90 D (inch) MAX 14.10 Reference Doc.: JEDEC Publication 95, MO-153 e SEATING PLANE b 10-0039 aaa C Ordering Information Part / Order Number 932S401EFLF 932S401EFLFT 932S401EGLF 932S401EGLFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 56-pin SSOP 56-pin SSOP 56-pin TSSOP 56-pin TSSOP Temperature 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C “LF” suffix to the part number denotes Pb-Free configuration, RoHS compliant. 0921G—08/24/09 22 MIN .547 MAX .555 Integrated Circuit Systems, Inc. ICS932S401 Revision History Rev. A B C D E F G Issue Date Description 1. Updated Electrical Characterisitcs tables with typical data 5/2/2005 2. Added Notes on Termination of Single-ended outputs 5/18/2006 1. Changed Max CPU Skew from 100ps to 50ps. 5/30/2006 Updated Key Specifications: CPU output skew. 8/22/2006 Updated Single-ended Output Terminations. 9/11/2006 Updated SMBus. Bytes 0-7 to match CK410B. 6/13/2007 Updated operating supply and power down current values 1. Updated Byte 3 table. 8/24/2009 2. Added new ordering information table. 0921G—08/24/09 23 Page # 5-10 6 1 10 12-13 5 13 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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