953008
Datasheet
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
VIA PT890/894 style chipset
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
10 - PCI, 33MHz
•
2 - REF, 14.318MHz
•
3 - 3V66, 66.66MHz
•
1 - 48MHz
•
1 - 24/48MHz selectable output
•
3 - PCI ExpressTM 0.7V current mode differential pairs
•
1 CPU/PCI Express 0.7 current mode selectable
differential pair
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
PCI outputs cycle-cycle jitter < 500ps
•
PCI Express outputs cycle-cycle jitter < 125ps
Functionality
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit3 Bit2 Bit1 Bit0
CPU
FS3 FSL2 FSL1 FSL0 MHz
266.66
0
0
0
0
133.33
0
0
0
1
200.00
0
0
1
0
N/A
0
0
1
1
0
1
0
0
N/A
100.00
0
1
0
1
400.00
0
1
1
0
200.00
0
1
1
1
266.66
1
0
0
0
133.33
1
0
0
1
200.00
1
0
1
0
N/A
1
0
1
1
N/A
1
1
0
0
100.00
1
1
0
1
400.00
1
1
1
0
200.00
1
1
1
1
0
0
0
0
269.33
134.66
0
0
0
1
202.00
0
0
1
0
N/A
0
0
1
1
274.66
0
1
0
0
137.33
0
1
0
1
206.00
0
1
1
0
0
1
1
1
N/A
279.99
1
0
0
0
140.00
1
0
0
1
210.00
1
0
1
0
N/A
1
0
1
1
287.99
1
1
0
0
144.00
1
1
0
1
216.00
1
1
1
0
1
1
1
1
N/A
1076—08/06/09
Pin Configuration
PCIEX
MHz
100.00
100.00
100.00
N/A
N/A
100.00
100.00
100.00
133.33
133.33
133.33
N/A
N/A
133.33
133.33
133.33
101.00
101.00
101.00
N/A
103.00
103.00
103.00
N/A
105.00
105.00
105.00
N/A
108.00
108.00
108.00
N/A
3v66
MHz
66.67
66.67
66.67
N/A
N/A
66.67
66.67
66.67
66.67
66.67
66.67
N/A
N/A
66.67
66.67
66.67
67.33
67.33
67.33
N/A
68.66
68.66
68.67
N/A
70.00
70.00
70.00
N/A
72.00
72.00
72.00
N/A
PCI
MHz
33.33
33.33
33.33
N/A
N/A
33.33
33.33
33.33
33.33
33.33
33.33
N/A
N/A
33.33
33.33
33.33
33.67
33.67
33.67
N/A
34.33
34.33
34.33
N/A
35.00
35.00
35.00
N/A
36.00
36.00
36.00
N/A
VDDA
GND
VDDREF
**FSL0/REF0
FSL1/REF1
1
2
3
4
5
56
55
54
53
52
GND
IREF
CPUCLKT0
CPUCLKC0
GNDCPU
X1 6
X2 7
GNDREF 8
VttPWR_GD/PD# 9
**FSL2/PCICLK0 10
51
50
49
48
47
CPUCLKT1
CPUCLKC1
VDDCPU
SDATA
CPUCLKT2/PCIEXT0
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CPUCLKC2/PCIEXC0
VDDPCIEX
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
GNDPCIEX
VDDPCIEX
PCIEXT3
PCIEXC3
GNDPCIEX
SCLK
GND3V66
3V66_0
3V66_1/FS4**
3V66_2/Mode0**
VDD3V66
GND48
**FS3/~PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK4
PCICLK5
PCICLK6
VDDPCI
GNDPCI
PCICLK7
PCICLK8
PCICLK9
*Turbo#
Reset#
VDD48
48MHz
*Sel24_48#/24_48MHz
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS953008
Bit4
FS4
0
0
0
0
0
56-Pin SSOP
*These inputs have 120K internal pull-up resistors to VDD.
**These inputs have 120K internal pull-down resistors to GND.
~This output is default 2X drive strength.
953008
Datasheet
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
PWR
PWR
3.3V power for the PLL core.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
clock.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the REF outputs.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.
Frequency select latch input pin / 3.3V PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
PCI clock output.
Real time input pin to change frequency to a pre-programmed under or over
clock entries located in the Rom table.
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
Power pin for the 48MHz output.3.3V
48MHz clock output.
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
1
2
3
VDDA
GND
VDDREF
4
**FSL0/REF0
I/O
5
FSL1/REF1
I/O
6
7
8
X1
X2
GNDREF
9
VttPWR_GD/PD#
IN
10
**FSL2/PCICLK0
I/O
11
12
13
14
15
16
17
18
19
20
21
22
23
**FS3/PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK4
PCICLK5
PCICLK6
VDDPCI
GNDPCI
PCICLK7
PCICLK8
PCICLK9
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
24
*Turbo#
IN
25
Reset#
OUT
26
27
VDD48
48MHz
PWR
OUT
28
*Sel24_48#/24_48MHz
IN
OUT
PWR
I/O
1076—08/06/09
2
953008
Datasheet
Pin Description
PIN #
PIN NAME
TYPE
PWR
PWR
DESCRIPTION
29
30
GND48
VDD3V66
31
3V66_2/Mode0**
32
33
34
35
36
37
38
39
40
41
42
43
44
45
3V66_1/FS4**
3V66_0
GND3V66
SCLK
GNDPCIEX
PCIEXC3
PCIEXT3
VDDPCIEX
GNDPCIEX
PCIEXC2
PCIEXT2
PCIEXC1
PCIEXT1
VDDPCIEX
I/O
OUT
PWR
IN
PWR
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
46
CPUCLKC2/PCIEXC0
OUT
47
CPUCLKT2/PCIEXT0
OUT
48
49
SDATA
VDDCPU
I/O
PWR
50
CPUCLKC1
OUT
51
CPUCLKT1
OUT
52
GNDCPU
PWR
53
CPUCLKC0
OUT
54
CPUCLKT0
OUT
55
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
56
GND
PWR
Ground pin.
I/O
Ground pin for the 48MHz outputs
Power pin for the 3.3V 66MHz clocks.
3.3V 66.66MHz clock output / Function select latch input pin for
CPUCLK/PCIEX selectable pin. 0 = PCIEXT/C ; 1 = CPUCLKT/C.
3.3V 66.66MHz clock output. / Frequency select latch input pin
3.3V 66.66MHz clock output
Ground pin for the 3.3V 66MHz clocks
Clock pin of SMBus circuitry, 5V tolerant.
Ground pin for the PCI-EX outputs
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin for the PCI-EX outputs
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias./
Complement clock of differential PCIEX pair
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
Data pin for SMBus circuitry, 5V tolerant.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
1076—08/06/09
3
953008
Datasheet
General Description
ICS953008 is a 56-pin clock chip for P4 type processors with PCI Express.
Block Diagram
Frequency
Dividers
PLL2
48MHz
24_48MHz
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
FSL (2:0)
3V66 (2:0)
FS (4:3)
SCLK
Sel24_48#
SDATA
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
PCICLK (9:0)
PCI-EXT (3:1)
PCI-EXC (3:1)
VTTPWRGD
CPUCLK2/PCIEXT0
PD#
Turbo#
CPUCLK2/PCIEXC0
Mode0
RESET#
I REF
1076—08/06/09
4
953008
Datasheet
Table1: Frequency Selection Table
Bit4
FS4
0
Bit3 Bit2 Bit1 Bit0
CPU
FS3 FSL2 FSL1 FSL0 MHz
0
0
0
0
266.66
PCIEX
MHz
100.00
3V66
MHz
66.67
PCI
MHz
33.33
0
0
0
0
1
133.33
100.00
66.67
33.33
0
0
0
1
0
200.00
100.00
66.67
33.33
0
0
0
1
1
N/A
N/A
N/A
N/A
0
0
1
0
0
N/A
N/A
N/A
N/A
0
0
1
0
1
100.00
100.00
66.67
33.33
0
0
1
1
0
400.00
100.00
66.67
33.33
0
0
1
1
1
200.00
100.00
66.67
33.33
0
1
0
0
0
266.66
133.33
66.67
33.33
0
1
0
0
1
133.33
133.33
66.67
33.33
0
1
0
1
0
200.00
133.33
66.67
33.33
0
1
0
1
1
N/A
N/A
N/A
N/A
0
1
1
0
0
N/A
N/A
N/A
N/A
0
1
1
0
1
100.00
133.33
66.67
33.33
0
1
1
1
0
400.00
133.33
66.67
33.33
0
1
1
1
1
200.00
133.33
66.67
33.33
1
0
0
0
0
269.33
101.00
67.33
33.67
1
0
0
0
1
134.66
101.00
67.33
33.67
1
0
0
1
0
202.00
101.00
67.33
33.67
1
0
0
1
1
N/A
N/A
N/A
N/A
1
0
1
0
0
274.66
103.00
68.66
34.33
1
0
1
0
1
137.33
103.00
68.66
34.33
1
0
1
1
0
206.00
103.00
68.67
34.33
1
0
1
1
1
N/A
N/A
N/A
NA/
1
1
0
0
0
279.99
105.00
70.00
35.00
1
1
0
0
1
140.00
105.00
70.00
35.00
1
1
0
1
0
210.00
105.00
70.00
35.00
1
1
0
1
1
N/A
N/A
N/A
N/A
1
1
1
0
0
287.99
108.00
72.00
36.00
1
1
1
0
1
144.00
108.00
72.00
36.00
1
1
1
1
1
1
1
1
0
1
216.00
108.00
72.00
36.00
N/A
N/A
N/A
N/A
1076—08/06/09
5
Spread
%
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
N/A
N/A
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
N/A
N/A
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
N/A
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
N/A
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
N/A
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
N/A
953008
Datasheet
General SMBus serial interface information for the ICS953008
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
1076—08/06/09
6
Not acknowledge
stoP bit
953008
Datasheet
2
I C Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Frequency H/W IIC
Select
RW
Latch Inputs
IIC
0
Bit 7
-
FS Source
Bit 6
-
SS_EN1
PLL1 Spread Enable RW
OFF
ON
0
Bit
Bit
Bit
Bit
Bit
Bit
-
SS_EN2
FS4
FS3
FSL2
FSL1
FSL0
PLL2 Spread Enable
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
OFF
ON
1
Latch
Latch
Latch
Latch
Latch
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
See Table1:PLL1 Frequency Selection
Table
2
I C Table: General Device Behaviour Register
Byte 1
Pin #
Name
Type
0
1
PWD
RW
6 x Iref
7 x Iref
0
RW
RW
RW
48MHz
PCIEXCLKT/C0
Sync
24MHz
CPUCLKT/C2
Async
Latch
Latch
0
RW
Sync
Async (PLL2)
0
Reserved
RW
RW
RW
00 = PLL2
01 = 66.0/33.0
-
10 = 75.4/37.7
11 = 88.0/44.0
-
0
0
0
Name
Control Function
Type
0
1
PWD
REF0
REF1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Name
Control Function
Type
0
1
PWD
48MHz
24_48MHz
3V66_2
3V66_1
3V66_0
PCICLK6
PCICLK7
PCICLK8
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 7
-
IREF Bit0
Bit 6
Bit 5
Bit 4
-
SEL24_48MHz
Mode 0
PCIEX PLL Cntrl
Bit 3
-
3V66/PCI PLL Cntrl
Bit 2
Bit 1
Bit 0
-
ASYNC1
ASYNC0
Reserved
Control Function
IREF Mulitiplier
Programming Bits
Output Select
Output Select
PCIEX PLL Source
3V66/PCI PLL
Source
3V66/PCI Async
Freq Prog bits
2
I C Table: Output Control Register
Byte 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
2
I C Table: Output Control Register
Pin #
Byte 3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
-
1076—08/06/09
7
953008
Datasheet
2
I C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
PCIEXCLKT/C3
Output Control
RW
Disable
Enable
1
Bit 6
-
PCIEXCLKT/C2
Output Control
RW
Disable
Enable
1
Bit
Bit
Bit
Bit
Bit
Bit
-
PCIEXCLKT/C1
CPUCLK2/PCIEX0
CPUCLKT/C1
CPUCLKT/C0
PCICLK9
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
Type
0
1
PWD
5
4
3
2
1
0
2
I C Table: Programmable Skew Control Register
Pin #
Byte 5
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
-
Name
PCISkw3
PCISkw2
PCISkw1
PCISkw0
3V66Skw3
3V66Skw2
3V66Skw1
3V66Skw0
Control Function
CPU-PCI 7 Steps
Skew Control (ps)
CPU-3V66 7 Steps
Skew Control (ps)
RW
RW
RW
RW
RW
RW
RW
RW
0000:0
0001:N/A
0010:N/A
0011:N/A
0000:0
0001:N/A
0010:N/A
0011:N/A
0100:150
0101:N/A
0110:N/A
0111:N/A
0100:150
0101:N/A
0110:N/A
0111:N/A
1000:300
1001:N/A
1010:N/A
1011:N/A
1000:300
1001:N/A
1010:N/A
1011:N/A
1100:450
1101:600
1110:750
1111:900
1100:450
1101:600
1110:750
1111:900
1
1
0
0
1
0
0
0
2
I C Table: Reserved Register
Byte 6
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Control Function
Reserved
Reserved
Reserved
Type
0
1
PWD
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
1
1
1
1
0
1
1
1
Name
Control Function
Type
0
1
PWD
REVID3
REVID2
Revision ID
Revision ID
R
R
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
R
R
R
R
R
-
0
0
REVID1
REVID0
VID3
VID2
VID1
-
VID0
Vendor ID
R
001 = ICS
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
I C Table: Vendor ID Register
Pin #
Byte 7
Bit 7
Bit 6
Bit 5
-
Bit
Bit
Bit
Bit
Bit
-
4
3
2
1
0
1076—08/06/09
8
0
0
0
0
0
1
953008
Datasheet
2
I C Table: Byte Count Register
Byte 8
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
BC7
RW
0
Bit 6
-
BC6
RW
0
Bit 5
-
BC5
RW
Bit 4
-
BC4
RW
Bit 3
-
BC3
Bit 2
-
BC2
RW
1
Bit 1
-
BC1
RW
1
Bit 0
-
BC0
RW
1
Byte Count
Programming b(7:0)
RW
0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
0
1
2
I C Table: WD Time Control Register
Byte 9
Pin #
Name
Bit 7
-
WDEN
Bit 6
-
WDSEN
Bit 5
-
WD Hard Status
Bit 4
-
WD Soft Status
Bit 3
-
WDTCtrl
Bit 2
Bit 1
Bit 0
-
WD2
WD1
WD0
Control Function
Watchdog Alarm
Enable (Hard alarm
only)
Watchdog Soft
Alarm Enable (Hard
and Soft alarm)
WD Hard Alarm
Status
WD Soft Alarm
Status
Watch Dog Time
base Control
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Type
0
1
PWD
RW
Disable
Enable
0
RW
Disable
Enable
0
R
Normal
Alarm
x
R
Normal
Alarm
x
RW
290ms Base
1160ms Base
0
RW
RW
RW
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
1
1
1
2
I C Table: M/N Programming & WD Safe Frequency Control Register
Byte 10
Pin #
Name
Bit 7
-
M/NEN
Bit 6
-
Bit 5
-
Bit 4
-
Reserved
WD Safe Freq
Source
WD SF4
Bit 3
-
WD SF3
Bit 2
-
WD SF2
Bit 1
-
WD SF1
Bit 0
-
WD SF0
Control Function
PLL1 M/N
Programming
Enable
Reserved
WD Safe Freq
Source
Type
0
1
PWD
RW
Disable
Enable
0
RW
-
-
0
RW
B10b(4:0)
Latch Inputs
0
RW
Watch Dog Safe
Freq Programming
bits
RW
RW
RW
RW
1076—08/06/09
9
0
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
0
0
0
0
953008
Datasheet
2
I C Table: PLL1 Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
N Div8
N Divider Prog bit 8
RW
Bit 6
-
N Div9
N Divider Prog bit 9
RW
-
M Div5
RW
X
Bit 4
-
M Div4
Bit 3
-
M Div3
Bit 2
-
M Div2
Bit 1
-
M Div1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
RW PLL1 VCO frequency. Default at power
up = latch-in or Byte 0 Rom table.
RW
VCO
Frequency = 14.318 x [NDiv(9:0)+8]
RW
/ [MDiv(5:0)+2]
RW
X
Bit 5
Bit 0
-
M Div0
RW
M Divider
Programming bits
X
X
X
X
X
X
2
I C Table: PLL1 Frequency Control Register
Byte 12
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Bit 6
-
N Div7
N Div6
RW
RW
Bit 5
-
N Div5
RW
X
Bit 4
-
N Div4
Bit 3
-
N Div3
Bit 2
-
N Div2
Bit 1
-
N Div1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
RW PLL1 VCO frequency. Default at power
up = latch-in or Byte 0 Rom table.
RW
RW VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
RW
X
X
Bit 0
-
N Div0
RW
N Divider
Programming b(7:0)
X
X
X
X
X
2
I C Table: PLL1 Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
SSP7
RW
X
Bit 6
-
SSP6
RW
X
Bit 5
-
SSP5
RW
X
Bit 4
-
SSP4
Bit 3
-
SSP3
Bit 2
-
SSP2
These Spread Spectrum bits in Byte 13
and 14 will program the spread pecentage
RW
of PLL1
RW
Bit 1
-
SSP1
RW
X
Bit 0
-
SSP0
RW
X
Spread Spectrum
Programming b(7:0)
RW
X
X
X
2
I C Table: PLL1 Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Reserved
Bit 7
-
Reserved
Bit 6
-
SSP14
Bit
Bit
Bit
Bit
Bit
Bit
-
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
5
4
3
2
1
0
Spread Spectrum
Programming
b(14:8)
1076—08/06/09
10
Type
0
1
PWD
R
-
-
0
RW
X
RW
These Spread Spectrum bits in Byte 13
RW
RW and 14 will program the spread pecentage
of PLL1
RW
RW
RW
X
X
X
X
X
X
953008
Datasheet
2
I C Table: VCO Frequency Control Register
Byte 15
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Control Function
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
N Divider Prog bit 9
M Divider
Programming bits
Type
0
1
RW
RW
The decimal representation of M and N
RW Divier in Byte 15 and 16 will configure the
RW PLL2 VCO frequency. Default at power
up = latch-in or Byte 0 Rom table.
RW
RW VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
RW
RW
PWD
X
X
X
X
X
X
X
X
2
I C Table: VCO Frequency Control Register
Byte 16
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control Function
N Divider
Programming b(7:0)
Type
0
1
RW
RW
The decimal representation of M and N
RW Divier in Byte 15 and 16 will configure the
RW PLL2 VCO frequency. Default at power
up = latch-in or Byte 0 Rom table.
RW
RW VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
RW
RW
PWD
X
X
X
X
X
X
X
X
2
I C Table: Spread Spectrum Control Register
Byte 17
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
-
Control Function
Spread Spectrum
Programming b(7:0)
Type
0
1
RW
RW
RW
These Spread Spectrum bits in Byte 17
RW
and 18 will program the spread pecentage
RW
of PLL2
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
2
I C Table: Spread Spectrum Control Register
Byte 18
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Control Function
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Reserved
Spread Spectrum
Programming
b(14:8)
1076—08/06/09
11
Type
0
1
R
RW
RW
RW
These Spread Spectrum bits in Byte 17
RW and 18 will program the spread pecentage
of PLL2
RW
RW
RW
PWD
0
X
X
X
X
X
X
X
953008
Datasheet
2
I C Table: Programmable Output Divider Register
Byte 19
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
PCIEXDiv3
PCIEXDiv2
PCIEXDiv1
PCIEXDiv0
Control Function
CPU Divider Ratio
Programming Bits
PCIEX Divider Ratio
Programming Bits
for Sync mode
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0000:/2
0001:/3
0010:/5
0011:/15
0000:/2
0001:/3
0010:/5
0011:/7
PWD
1
0100:/4
0101:/6
0110:/10
0111:/30
0100:/4
0101:/6
0110:/10
0111:/14
1000:/8
1001:/12
1010:/20
1011:/60
1000:/8
1001:/12
1010:/20
1011:/28
1100:/16
1101:/24
1110:/40
1111:/120
1100:/16
1101:/24
1110:/40
1111:/56
X
X
X
X
X
X
X
X
2
I C Table: Programmable Output Divider Register
Byte 20
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
3V66/PCIDiv3
3V66/PCIDiv2
3V66/PCIDiv1
3V66/PCIDiv0
PCIEXDiv3
PCIEXDiv2
PCIEXDiv1
PCIEXDiv0
Control Function
3V66/PCI Divider
Ratio Programming
Bits
PCIEX Divider Ratio
Programming Bits
for Async PLL2
mode
1076—08/06/09
12
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0000:/2
0001:/3
0010:/5
0011:/15
0000:/2
0001:/3
0010:/5
0011:/15
1
0100:/4
0101:/6
0110:/10
0111:/30
0100:/4
0101:/6
0110:/10
0111:/30
1000:/8
1001:/12
1010:/20
1011:/60
1000:/8
1001:/12
1010:/20
1011:/60
PWD
1100:/16
1101:/24
1110:/40
1111:/120
1100:/16
1101:/24
1110:/40
1111:/120
X
X
X
X
X
X
X
X
953008
Datasheet
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
1076—08/06/09
13
953008
Datasheet
Absolute Maximum Rating
1
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
3.3V Logic Input Supply
Voltage
Storage Temperature
VDD_A
-
VDD + 0.5V
V
1
VDD_In
-
V
1
Ts
-
-65
150
Ambient Operating Temp
Tambient
-
0
70
°C
1
Case Temperature
Tcase
-
115
°C
1
Input ESD protection HBM
ESD prot
-
V
1
MAX
UNITS
Notes
1
VDD + 0.5V
GND - 0.5
2000
°
C
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
-5
uA
1
-200
uA
1
IIL1
Input Low Current
IIL2
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Operating Supply Current
Operating Current
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
3.3 V +/-5%
0.7
VDD + 0.3
V
1
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
IDD3.3OP
Full Active, CL = Full load;
350
mA
1
IDD3.3OP
all outputs driven
400
mA
1
all diff pairs driven
70
mA
1
IDD3.3PD
Input Frequency
Fi
Pin Inductance
Lpin
CIN
Input Capacitance
COUT
CINX
X1 & X2 pins
all differential pairs tri-stated
mA
1
MHz
2
7
nH
1
Logic Inputs
5
pF
1
Output pin capacitance
6
pF
1
5
pF
1
1.8
ms
1
33
kHz
1
300
us
1
14.31818
Tfall_Pd#
Trise_Pd#
PD# rise time of
TSTAB
Modulation Frequency
Tdrive_PD#
12
VDD = 3.3 V
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
SMBus Voltage
TYP
VIH_FS
Powerdown Current
Clk Stabilization
MIN
30
2.7
VDD
Low-level Output Voltage
VOL
@ IPULLUP
Current sinking at
IPULLUP
VOL = 0.4 V
SCLK/SDATA
(Max VIL - 0.15) to
T RI2C
Clock/Data Rise Time
(Min VIH + 0.15)
(Min VIH + 0.15) to
SCLK/SDATA
T FI2C
(Max VIL - 0.15)
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
5
ns
1
5
ns
1
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
4
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
1076—08/06/09
14
953008
Datasheet
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
Current Source Output Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
850
mV
1,3
VLow
Statistical measurement on single
ended signal
660
Voltage Low
-150
150
mV
1,3
Measurement on single ended
signal using absolute value.
-300
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vx
Long Accuracy
ppm
Average period
Absolute min period
Tperiod
Tabsmin
MAX
1150
250
UNITS
NOTES
1
mV
1
mV
1
550
mV
1
140
mV
1
Variation of crossing over all
edges
see Tperiod min-max values
-300
300
ppm
1,2
400MHz nominal
2.4993
2.5008
ns
2
400MHz spread
2.4993
2.5133
ns
2
333.33MHz nominal
2.9991
3.0009
ns
2
333.33MHz spread
2.9991
3.016
ns
2
266.66MHz nominal
3.7489
3.7511
ns
2
266.66MHz spread
3.7489
3.77
ns
2
200MHz nominal
4.9985
5.0015
ns
2
200MHz spread
4.9985
5.0266
ns
2
166.66MHz nominal
5.9982
6.0018
ns
2
166.66MHz spread
5.9982
6.0320
ns
2
133.33MHz nominal
7.4978
7.5023
ns
2
133.33MHz spread
7.4978
7.5400
ns
2
100.00MHz nominal
9.9970
10.0030
ns
2
10.0533
100.00MHz spread
9.9970
ns
2
400MHz nominal/spread
2.4143
ns
1,2
333.33MHz nominal/spread
2.9141
ns
1,2
266.66MHz nominal/spread
3.6639
ns
1,2
200MHz nominal/spread
4.8735
ns
1,2
166.66MHz nominal/spread
5.8732
ns
1,2
133.33MHz nominal/spread
7.3728
ns
1,2
100.00MHz nominal/spread
9.8720
ns
1,2
1
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
55
%
1
Skew
tsk3
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
CPU(1:0), VT = 50%
100
ps
1
150
ps
1
125
ps
1
85
ps
1
45
CPU(1:0) to CPU2_ITP,
tsk4
Skew
VT = 50%
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
wavefrom (CPU2_ITP)
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
wavefrom, (CPU(1:0))
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF
1
TYP
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and V OH = 0.7V @ ZO=50.
1076—08/06/09
15
953008
Datasheet
Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
Current Source Output Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
850
mV
1,3
VLow
Statistical measurement on single
ended signal
660
Voltage Low
-150
150
mV
1,3
Measurement on single ended
signal using absolute value.
-300
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vx
Long Accuracy
ppm
MAX
1150
250
UNITS
Notes
1
mV
1
mV
1
550
mV
1
140
mV
1
Variation of crossing over all
edges
see Tperiod min-max values
-300
300
ppm
1,2
9.9970
10.0030
ns
2
10.0533
ns
2
ns
1,2
1
Average period
Tperiod
100.00MHz nominal
100.00MHz spread
9.9970
Absolute min period
Tabsmin
100.00MHz nominal/spread
9.8720
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
125
ps
1
125
ps
1
VOH = 0.525V VOL = 0.175V
Measurement from differential
Duty Cycle
wavefrom
VT = 50%
tsk3
Skew
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
wavefrom
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF
Fall Time Variation
d-tf
dt3
1
TYP
45
55
%
1
250
ps
1
125
ps
1
MAX
UNITS
NOTES
55
1
V
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and V OH = 0.7V @ ZO=50.
Electrical Characteristics - PCICLK/PCICLK_F
SYMBOL
RDSP
CONDITIONS*
VO = VDD*(0.5)
MIN
Output Impedance
PARAMETER
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
Output High Current
IOH
TYP
12
IOL = 1 mA
0.55
V OH @MIN = 1.0 V
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
1
1
mA
1
mA
1
Output Low Current
IOL
38
mA
1
Edge Rate
tslewr/f
Rising/Falling edge rate
1
4
V/ns
1
Rise Time
tr
VOL = 0.4 V, V OH = 2.4 V
0.5
2
ns
1
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Group Skew
tskew
VT = 1.5 V
500
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
VOL @ MAX = 0.4 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (unless otherwise specified)
1
V
mA
Guaranteed by design and characterization, not 100% tested in production.
1076—08/06/09
16
953008
Datasheet
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS*
see Tperiod min-max values
MIN
-100
Clock period
Tperiod
48.00MHz output nominal
UNITS
ppm
20.8313
20.8354
ns
55
1
V
1
Output Impedance
RDSP
VO = VDD*(0.5)
12
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
Output High Current
IOH
IOL = 1 mA
0.55
V OH @MIN = 1.0 V
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
Output Low Current
IOL
Edge Rate
tslewr/f
Rising/Falling edge rate
Edge Rate
tslewr/f_USB
Rise Time
tr
NOTES
MAX
100
Output High Voltage
TYP
-33
30
VOL @ MAX = 0.4 V
1
V
1
mA
1
mA
1
mA
1
38
mA
1
1
4
V/ns
1
USB48 Rising/Falling edge rate
1
2
V/ns
1
VOL = 0.4 V, V OH = 2.4 V
0.5
2
ns
1
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Rise Time
tr_USB
VOL = 0.4 V, V OH = 2.4 V
1
2
ns
1
Fall Time
tf_USB
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Group Skew
tskew
VT = 1.5 V
250
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
MAX
UNITS
NOTES
55
1
V
1
0.55
V
1
mA
1
mA
1
mA
1
38
mA
1
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only)
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - AGPCLK/3V66
SYMBOL
RDSP
CONDITIONS*
VO = VDD*(0.5)
MIN
Output Impedance
PARAMETER
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
V OH @MIN = 1.0 V
12
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
Output Low Current
IOL
Rise Time
tr
VOL = 0.4 V, V OH = 2.4 V
0.5
2
ns
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Group Skew
tskew
VT = 1.5 V
150
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
250
ps
1
VOL @ MAX = 0.4 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 10-30 pF (unless otherwise specified)
1
TYP
Guaranteed by design and characterization, not 100% tested in production.
1076—08/06/09
17
953008
Datasheet
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
Clock period
Tperiod
14.318MHz output nominal
69.8270
69.8550
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-29
-23
mA
1
Output Low Current
IOL
29
27
mA
1
Edge Rate
tslewr/f
Rising/Falling edge rate
1
4
V/ns
1
Rise Time
tr1
V OL = 0.4 V, VOH = 2.4 V
1
2
ns
1
Fall Time
tf1
V OH = 2.4 V, VOL = 0.4 V
1
2
ns
1
Skew
tsk1
VT = 1.5 V
500
ps
1
Duty Cycle
dt1
VT = 1.5 V
55
%
1
Jitter
tjcyc-cyc
VT = 1.5 V
1000
ps
1
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
TYP
45
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
1076—08/06/09
18
953008
Datasheet
56-Lead, 300 mil Body, 25 mil, SSOP
c
N
SYMBOL
L
E1
A
A1
b
c
D
E
E1
e
h
L
N
α
E
INDEX
AREA
1 2
h x 45°
D
A
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
A1
-Ce
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
SEATING
PLANE
b
.10 (.004) C
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
953008yFLFT
Example:
XXXX y F LF T
Designation for tape and reel packaging
RoHS Compliant
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
1076—08/06/09
19
MIN
.720
MAX
.730
953008
Datasheet
1076—08/06/09
20
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