95V842AFLFT

ICS95V842 DDR Phase Lock Loop Clock Driver (60MHz - 220MHz) Recommended Application: 1:2 DDRI Clock Driver Pin Configuration Switching Characteristics: • CYCLE - CYCLE jitter: VDD) . . +/- 50mA Continuous output current: IO (VO = 0 to VDD) . . . . +/- 50mA Package thermal impedance, theta JA: DGG package +89°C/Ω Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS IIH VI = VDD or GND Input High Current 5 IIL VI = VDD or GND Input Low Current Operating Supply Current IDD2.5 -18 µA mA IOL VDD = 2.3V, VOUT = 1.2V 26 mA IOZ VDD=2.7V, Vout=VDD or GND ±10 µA VIK Iin = -18mA VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = VDD or GND VI = VDD or GND -1.2 V IDDPD IOH Output Low Current High-level output voltage Low-level output voltage 5 160 UNITS µA µA mA CL = 0pF, RL = ∞Ω VDD = 2.3V, VOUT = 1V Output High Current High Impedance Output Current Input Clamp Voltage CL = 0pF, RL = ∞Ω MAX VOH VOL 100 VDD - 0.1 V 1.7 V 0.1 0.6 1 CIN Input Capacitance 1 COUT Output Capacitance 1 Guaranteed by design and characterization, not 100% tested in production. 0830B—11/24/08 3 3 3 V pF pF ICS95V842 DC Electrical Characteristics TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Supply Voltage VDDQ, A VDD 2.3 2.5 CLK_INT, CLK_INC, FB_INC, Low level input voltage VIL 0.4 FB_INT CLK_INT, CLK_INC, FB_INC, High level input voltage VIH 2.1 V DD/2 + 0.18 FB_INT DC input signal voltage VIN -0.3 (note 1,2) Differential input signal CLK_INT, CLK_INC, FB_INC, VID 0.36 voltage (note 3) FB_INT Differential output voltage CLK_INT, CLK_INC, FB_INC, VOD 0.7 (note 3) FB_INT Output differential crossVOX VDD/2 - 0.15 voltage (note 4) Input differential crossVIX VDD/2 - 0.2 VDD/2 voltage (note 4) Operating free-air TA 0 temperature MAX 2.7 UNITS V VDD/2 - 0.18 V V VDD + 0.3 V V DD + 0.6 V V DD + 0.6 V VDD/2 + 0.15 V V DD/2 + 0.2 V 85 °C Notes: 1 Unused inputs must be held high or low to prevent them from floating. 2 DC input signal voltage specifies the allowable DC excursion of differential input. 3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing. Timing Requirements TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Max clock frequency 3 Application Frequency Range3 Input clock duty cycle CLK stabilization freqop 33 233 MHz freqApp 60 220 MHz dtin TSTAB 40 60 100 % µs 0830B—11/24/08 4 ICS95V842 Switching Characteristics TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER CONDITION SYMBOL MIN TYP 3 freq 40 Max clock frequency op Application Frequency freqApp 60 3 Range dtin Input clock duty cycle 40 tsl(I) Input clock slew rate 1 TSTAB CLK stabilization Low-to high level propagation 1 CLK_IN to any output tPLH delay time High-to low level propagation 1 CLK_IN to any output tPHL delay time ten Output enable time PD# to any output 5 tdis Output disable time PD# to any output 5 tjit (per) Period jitter -75 tjit(hper) Half-period jitter -75 tsl(o) Over the application Output clock slew rate 1 frequency range tcyc-tcyc Cycle to Cycle Jitter -75 t(spo) Static Phase Offset -50 tskew Output to Output Skew 40 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics are guaranteed for application frequency range. The PLL Locks over the Max Clock Frequency range, but the device doe not necessarily meet other timing parameters. 4. Does not include jitter. 0830B—11/24/08 5 MAX 333 UNITS MHz 220 MHz 60 2 100 % v/ns µs 5.5 ns 5.5 ns 75 75 2.5 75 50 60 ns ns ps ps v/ns ps ps ps ICS95V842 Parameter Measurement Information VDD V(CLKC) R = 60Ω R = 60Ω VDD/2 V(CLKC) ICS95V842 GND Figure 1. IBIS Model Output Load VDD/2 C = 14 pF -V DD/2 ICS95V842 R = 10Ω Z = 60Ω SCOPE Z = 50Ω R = 50Ω V(TT) R = 10Ω Z = 60Ω Z = 50Ω R = 50Ω V(TT) C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) 0830B—11/24/08 Figure 3. Cycle-to-Cycle Jitter 6 ICS95V842 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX # YX YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0830B—11/24/08 7 t ( ) n+1 ICS95V842 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t (hper_n+1) t (hper_n) 1 fo t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID , VOD Clock Inputs and Outputs 20% 20% Rise tsl Fall tsl Figure 8. Input and Output Slew Rates 0830B—11/24/08 8 ICS95V842 16-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .053 .069 A1 0.10 0.25 .004 .010 A2 -1.50 -.059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 D SEE VARIATIONS SEE VARIATIONS E 5.80 6.20 .228 .244 E1 3.80 4.00 .150 .157 e 0.635 BASIC 0.025 BASIC L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° ZD SEE VARIATIONS SEE VARIATIONS VARIATIONS D mm. N MIN 4.80 16 MAX 5.00 ZD (Ref) 0.23 D (inch) MIN .189 Reference Doc.: JEDEC Publication 95, MO-137 10-0032 Ordering Information 95V842yFzLF-T XXXX y F z LF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0°C to +85°C (Commercial) I = -40°C to +85°C (Industrial) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type 0830B—11/24/08 9 MAX .197 ZD (Ref) .009 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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