9DB202CK-01LFT

9DB202-01 PCI Express Jitter Attenuator Data Sheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 GENERAL DESCRIPTION FEATURES The 9DB202-01 is a high performance 1-to-1 Differential-to HCSL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuating device may be necessary in order to reduce high frequency random and deterministic jitter com-ponents from the PLL synthesizer and from the system board. • One 0.7V current mode differential HCSL output pair • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 140MHz • Input frequency range: 90MHz - 140MHz • VCO range: 450MHz - 700MHz • Cycle-to-cycle jitter: 30ps (maximum) • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.31ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in lead-free RoHS compliant package • Industrial temperature information available upon request • For functional replacement use 8714004 BLOCK DIAGRAM nc nc nc GND Loop Filter nc Phase Detector nc CLK Current Set + nc nCLK nc IREF PIN ASSIGNMENT 32 31 30 29 28 27 26 25 VCO PCIEXT0 nPCIEXC0 IREF 1 24 nc nc 2 23 nc VDDA 3 22 nc CLK 4 21 nc nCLK 5 nc 9DB202-01 20 VDD 6 19 nc nc 7 18 nc nc 8 17 nc nc nc nc nc VDD nc PCIEXT0 Internal Feedback PCIEXC0 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View ©2016 Integrated Device Technology, Inc 1 Revision B March 11, 2016 9DB202-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 IREF Input 2, 6, 7, 8, 11, 12, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31, 32 nc Unused 3 VDDA Power 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup/ Inverting differential clock input. VDD/2 default when left floating. Pulldown 9, 10 PCIEXT0, PCIEXC0 Output Differential output pairs. HCSL interface levels. 13, 20 VDD Power Core supply pins. 27 GND Power Power supply ground. A fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode PCIEX clock outputs. No connect. Analog supply pin. Requires 24Ω series resistor. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ©2016 Integrated Device Technology, Inc Test Conditions 2 Minimum Typical Maximum Units Revision B March 11, 2016 9DB202-01 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 34.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter VDD VDDA IDD IDDA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V Power Supply Current 112 mA Analog Supply Current 22 mA Maximum Units 150 µA TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter IIH Input High Current CLK, nCLK VDD = VIN = 3.465V Test Conditions CLK, nCLK VDD = 3.465V, VIN = 0V IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical 150 µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 3C. HCSL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter Minimum Typical Maximum Units I Output Current 12 14 16 mA V Output High Voltage 610 V Output Low Voltage I High Impedance Leakage Current Output Crossover Voltage OH OH OL OZ V OX Test Conditions 780 mV -5 mV -10 10 µA 250 550 mV Maximum Units 140 MHz TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter f Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tjit(cc) Cycle-to-Cycle Jitter t /t Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical MAX R Integration Range: 1.5MHz - 22MHz 20% to 80% 2.31 ps 30 ps 200 700 ps 48 52 % F NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the Phase Noise Plot following this section. ©2016 Integrated Device Technology, Inc 3 Revision B March 11, 2016 9DB202-01 Data Sheet TYPICAL PHASE NOISE AT 100MHZ ➤ 0 -10 -20 PCI Express™ Filter -30 -40 100MHz RMS Phase Jitter (Random) 1.5MHz to 22MHz = 2.31ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 -120 ➤ NOISE POWER dBc Hz -50 -60 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding PCI Express™ Filter to raw data -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under test. Due ©2016 Integrated Device Technology, Inc 4 Revision B March 11, 2016 9DB202-01 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL CYCLE-TO-CYCLE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD HCSL OUTPUT RISE/FALL TIME ©2016 Integrated Device Technology, Inc 5 Revision B March 11, 2016 9DB202-01 Data Sheet APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 9DB202-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 24Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 24Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ©2016 Integrated Device Technology, Inc 6 Revision B March 11, 2016 9DB202-01 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 1.8V 3.3V 3.3V 3.3V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL R1 50 R2 50 3.3V Zo = 50 Ohm R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER 3.3V HiPerClockS Input R3 125 FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Zo = 50 Ohm Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER ©2016 Integrated Device Technology, Inc nCLK 7 Revision B March 11, 2016 9DB202-01 Data Sheet VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/ shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) ©2016 Integrated Device Technology, Inc 8 Revision B March 11, 2016 9DB202-01 Data Sheet SCHEMATIC EXAMPLE has a slightly better signal integrity, is recommended for all other applications. The schematic below illustrates two different terminations. Both are reliable and adequate. The PCI Express termination is recommended for all PCI Express application. The optional termination, which VDD VDD C3 10uF U1 nc nc nc nc nc GND nc nc C4 0.01u 32 31 30 29 28 27 26 25 VDDA R2 24 CLK nCLK 9DB202-01_lqf p32_short VDD C1 10uf (U1-14) C2 0.1uF nc nc nc nc VDD nc nc nc PCIEXT0 PCIEXC0 nc nc VDD nc nc nc IREF nc VDDA CLK nCLK nc nc nc 24 23 22 21 20 19 18 17 Zo = 50 + TL1 HCSL Zo = 50 - TL2 R3 50 R4 50 9 10 11 12 13 14 15 16 R1 475 1 2 3 4 5 6 7 8 (U1-20) C1 0.1uF FIGURE 5. EXAMPLE OF 9DB202-01 ©2016 Integrated Device Technology, Inc 9 Revision B March 11, 2016 9DB202-01 Data Sheet RECOMMENDED TERMINATION Figure 6A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 6A. RECOMMENDED TERMINATION Figure 6B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. FIGURE 6B. RECOMMENDED TERMINATION ©2016 Integrated Device Technology, Inc 10 Revision B March 11, 2016 9DB202-01 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 9DB202-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 9DB202-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (112mA + 22mA) = 464.3mW Power (outputs)MAX = 44.5mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 464.3mW + 44.5mW = 508.81mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 34.8°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.509W * 34.8°C/W = 87.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION θJA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc 34.8C/W 11 Revision B March 11, 2016 9DB202-01 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. VDD IOUT = 17mA VOUT RREF = 475 ± 1% RL 50 IC FIGURE 7. HCSL DRIVER CIRCUIT AND TERMINATION HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT ) * IOUT since VOUT = IOUT * RL Power = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 44.5mW ©2016 Integrated Device Technology, Inc 12 Revision B March 11, 2016 9DB202-01 Data Sheet RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE θJA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W TRANSISTOR COUNT The transistor count for 9DB202-01 is: 2471 ©2016 Integrated Device Technology, Inc 13 Revision B March 11, 2016 9DB202-01 Data Sheet PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM N MAXIMUM 32 A 0.80 1.0 A1 0 0.05 A3 b 0.25 Reference 0.18 0.30 e 0.50 BASIC ND 8 NE 8 D D2 5.0 3.0 E 3.3 5.0 E2 3.0 3.3 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ©2016 Integrated Device Technology, Inc 14 Revision B March 11, 2016 9DB202-01 Data Sheet TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package 9DB202CK-01LF ICS9DB202CK-01L 32 Lead “Lead-Free” VFQFN Tray 0°C to 70°C 9DB202CK-01LFT ICS9DB202CK-01L 32 Lead “Lead-Free” VFQFN Tape & Reel 0°C to 70°C ©2016 Integrated Device Technology, Inc 15 Shipping Packaging Temperature Revision B March 11, 2016 9DB202-01 Data Sheet REVISION HISTORY SHEET Rev Table B T3C HCSL Table -adjusted VOH min from 680mV to 610mV and added VOH max. 12/21/04 Features Section - added Input Frequency Range and VCO Range bullets. 7/14/06 T9 T9 3 3 5 6 8 10 11 - 12 15 15 T9 15 Differential DC Characteristics Table - updated NOTES 1 and 2. AC Characteristics Table - added thermal note. Updated HCSL Output Load Test Circuit Diagram. Updated Power Supply Filtering Techniques from 10ohms to 24ohms. Added VFQFN EPAD Thermal Release Path section. Added HCSL Termination section. Added Power Considerations. Ordering Information Table - Deleted “ICS” prefix from Order/Part number. Ordering Information - removed leaded devices. Updated data sheet format. Ordering Information - Deleted LF note below table. Updated header and footer.. Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02. B B Date 3 T3B T4 B Description of Change 1 B B Page 1 ©2016 Integrated Device Technology, Inc 16 2/18/09 7/22/15 2/10/16 3/11/16 Revision B March 11, 2016 9DB202-01 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.