8440258CK-46LFT

FemtoClock® Crystal/LVCMOS-toLVDS/LVCMOS Frequency Synthesizer ICS8440258-46 DATA SHEET General Description Features The ICS8440258-46 is an eight output synthesizer optimized to generate Ethernet clocks. The device will generate 125MHz and 25MHz clocks from a 25MHz crystal with a very good jitter performance. The ICS8440258-46 uses IDT’s 3RD generation low phase noise VCO technology. The ICS8440258-46 is packaged in a small, 5mm x 5mm VFQFN package. • Four differential LVDS outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 25MHz • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.5ps (typical) • • • Full 2.5V supply mode 32 31 30 29 28 nPLL_SEL 1 24 nc nQ0 2 23 nc GND 3 22 nc 21 GND 20 Q7 VDD 6 19 VDDO2 Q2 7 18 Q6 nQ2 8 17 GND Q5 GND Q4 10 11 12 13 14 15 16 VDDO1 9 nQ3 4 5 Q3 Q1 nQ1 GND Lead-free (RoHS 6) packaging 27 26 25 Q0 VDD 0°C to 70°C ambient operating temperature VDDA VDD MR REF_CLK XTAL_OUT nXTAL_SEL XTAL_IN Pin Assignment ICS8440258-46 32-Lead VFQFN 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm ePad size K Package Top View Block Diagram MR Pulldown nPLL_SEL Pulldown Q0 nQ0 Q1 nQ1 25MHz XTAL_IN OSC Q2 1 0 nQ2 ÷5 XTAL_OUT REF_CLK Pulldown nXTAL_SEL Pulldown Phase Detector VCO 0 Q3 nQ3 1 Q4 ÷25 Q5 Q6 Q7 ICS8440258CK-46 REVISION A OCTOBER 18, 2013 1 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential clock outputs. LVDS interface levels. 3, 12, 16, 17, 21 GND Power Power supply ground. 4, 5 Q1, nQ1 Output Differential clock outputs. LVDS interface levels. 6, 11, 27 VDD Power Core supply pins. 7, 8 Q2, nQ2 Output Differential clock outputs. LVDS interface levels. 9, 10 Q3, nQ3 Output Differential clock outputs. LVDS interface levels. 13, 15, 18, 20 Q4, Q5, Q6, Q7 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14 VDDO1 Power Output supply pin for Q4 and Q5 LVCMOS outputs. 19 VDDO2 Power Output supply pin for Q6 and Q7 LVCMOS outputs. 22, 23, 24 nc Unused 25 VDDA Power Analog supply pin. No connect. 26 nPLL_SEL Input Pulldown PLL Bypass. When LOW, Q[0:3], nQ[0:3], Q4, Q5 is driven from the VCO output. When HIGH, the PLL is bypassed and Q[0:3], nQ[0:3], Q4, Q5 output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. 28 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 29 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 30 nXTAL_SEL Input Pulldown Selects between the crystal or REF_CLK inputs as the PLL reference source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 31, 32 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLDOWN Input Pulldown Resistor ROUT Output Impedance REF_CLK, nXTAL_SEL, MR, nPLL_SEL Minimum Typical Maximum Units 4 pF Q[4:5] VDDO1, VDDO2 = 2.625V 12 pF Q[6:7] VDDO1, VDDO2 = 2.625V 7 pF 51 k Q[4:5] VDDO1, VDDO2 = 2.5V 11  Q[6:7] VDDO1, VDDO2 = 2.5V 22  ICS8440258CK-46 REVISION A OCTOBER 18, 2013 2 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDDOx+ 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Operating Temperature Range, TA 0C to +70C Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDO1 = VDDO2 = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.15 2.5 VDD V VDDO1, VDDO2 Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current Outputs Unterminated 170 187 mA IDDA Analog Supply Current Outputs Unterminated 13 15 mA IDDO1+ IDDO2 Output Supply Current Outputs Unterminated 6 mA Maximum Units Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO1 = VDDO2 = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VIH Input High Voltage 1.7 VDD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current nXTAL_SEL, MR, REF_CLK, nPLL_SEL VDD = VIN = 2.625V 150 µA IIL Input Low Current nXTAL_SEL, MR, REF_CLK, nPLL_SEL VDD = 2.625V, VIN = 0V VOH Output High Voltage Q[4:7] VOL Output Low Voltage Q[4:7] ICS8440258CK-46 REVISION A OCTOBER 18, 2013 VDDO1, VDDO2 = 2.5V±5%; IOH = -12mA VDDO1, VDDO2 = 2.5V±5%; IOL = 12mA 3 Minimum Typical -5 µA 1.8 V 0.5 V ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Table 3C. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 300 400 485 mV 50 mV 1.55 V 50 mV Maximum Units 0.85 1.2 Table 4. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental Frequency 25 MHz Equivalent Series Resistance 50  Shunt Capacitance 7 pF 18 pF Load Capacitance ICS8440258CK-46 REVISION A OCTOBER 18, 2013 12 4 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO1 = VDDO2 = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 2 Test Conditions Minimum Typical Maximum Units Q[0:3], nQ[0:3] 125 MHz Q4, Q5 125 MHz Q6, Q7 25 MHz Q[0:3], nQ[0:3]; NOTE 1A nPLL_SEL = 0 40 ps Q[4:5]; NOTE 1B nPLL_SEL = 0 80 ps 80 ps Q[6:7]; NOTE 1B 125MHz, Integration Range: 1.875MHz - 20MHz 0.5 ps 125MHz, Integration Range: 12kHz - 20MHz 1.149 ps 125MHz, Integration Range: 1.875MHz - 20MHz 0.5 ps 125MHz, Integration Range: 12kHz - 20MHz 1.188 ps Q[0:3], nQ[0:3] tjit(Ø) RMS Phase Noise Jitter (Random); NOTE 3 Q4, Q5 tR / tF odc Output Rise/Fall Time Output Duty Cycle Q[0:3], nQ[0:3] 20% to 80% 330 600 ps Q[4:5] 20% to 80% 250 450 ps Q[6:7] 20% to 80% 0.78 2.7 ns Q[0:3], nQ[0:3] 45 55 % Q[4:5] 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Device characterized with a 25MHz, 12pF quartz crystal. NOTE 1A: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point. NOTE 1B: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to Phase Noise Plots. ICS8440258CK-46 REVISION A OCTOBER 18, 2013 5 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 125MHz @ 2.5V (LVCMOS output), 1.875MHz – 20MHz Offset Frequency (Hz) ICS8440258CK-46 REVISION A OCTOBER 18, 2013 6 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 125MHz @ 2.5V (LVDS output), 1.875MHz – 20MHz Offset Frequency (Hz) ICS8440258CK-46 REVISION A OCTOBER 18, 2013 7 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 125MHz @ 2.5V (LVCMOS output), 12kHz – 20MHz Offset Frequency (Hz) ICS8440258CK-46 REVISION A OCTOBER 18, 2013 8 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 125MHz @ 2.5V (LVDS output), 12kHz – 20MHz Offset Frequency (Hz) ICS8440258CK-46 REVISION A OCTOBER 18, 2013 9 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information 1.25V±5% 1.25V±5% SCOPE 2.5V±5% POWER SUPPLY + Float GND – SCOPE VDD, VDDO1, VDDO2 Qx VDD VDDA VDDA Qx nQx GND -1.25V±5% 2.5V LVCMOS Output Load Test Circuit 2.5V LVDS Output Load Test Circuit nQx V DDOX Qx Qx 2 nQy V DDOX Qy Qy 2 tsk(o) LVCMOS Output Skew LVDS Output Skew nQ[0:3] 80% 80% 80% 80% VOD 20% 20% Q[4:7] tR Q[0:3] tR tF tF LVDS Output Rise/Fall Time LVCMOS Output Rise/Fall Time ICS8440258CK-46 REVISION A OCTOBER 18, 2013 20% 20% 10 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued nQ[0:3] Q[4:7] Q[0:3] LVDS Output Duty Cycle/Pulse Width/Period LVCMOS Output Duty Cycle/Pulse Width/Period RMS Phase Jitter Offset Voltage Setup Differential Output Duty Cycle/Pulse Width/Period ICS8440258CK-46 REVISION A OCTOBER 18, 2013 11 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVDS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVCMOS Outputs REF_CLK Input All unused LVCMOS outputs can be left floating. There should be no trace attached. For applications not requiring the use of a reference clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK input to ground. LVCMOS Control Pins All control pins have internal pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. ICS8440258CK-46 REVISION A OCTOBER 18, 2013 12 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS8440258CK-46 REVISION A OCTOBER 18, 2013 13 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 2A can be used with either type of output structure. Figure 2B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT ZT LVDS Receiver Figure 2A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 2B. Optional Termination LVDS Termination ICS8440258CK-46 REVISION A OCTOBER 18, 2013 14 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8440258CK-46 REVISION A OCTOBER 18, 2013 15 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Schematic Layout Figure 4 shows an example ICS8440258-46 application schematic. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. Input and output terminations shown are intended as examples only and may not represent the exact user configuration. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8440258-46 provides separate VDD, VDDA and VDDO pins to isolate any high speed switching noise at the outputs from coupling into the internal PLL. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors be placed on the ICS8440258-46 side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10uF capacitors and the 0.1uF capacitors connected directly to 2.5V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. In this example an 18pF parallel resonant 25MHz crystal is used with load caps C7 = C6 = 22pF. The load caps are recommended for frequency accuracy, but these may be adjusted for different board layouts. Crystals with different load capacities may be used, but the load capacitors will have to be changed accordingly. If different crystal types are used, please consult IDT for recommendations. The schematic example shows two different LVDS output terminations; the standard termination 100 shunt termination for an LVDS compliant receiver and an AC coupled termination for a non-LVDS differential receiver. The AC coupled termination requires that the designer select the values of R3 and R4 in order to center the LVDS swing within the common mode range of the receiver. In addition the designer must make sure that the target receiver will operate reliably with the LVDS swing, which is reduced relative to other logic families such as HCSL or LVPECL. ICS8440258CK-46 REVISION A OCTOBER 18, 2013 Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. 16 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER 2.5V Place each 0.1uF bypass cap directly adjacent to its corresponding VDD, VDDA or VDDO pin. C16 0.1uF C15 0.1uF F B2 2 VDD BLM18BB221SN1 R5 10 VDDA C7 10uF 28 26 30 25 27 11 VDD VDD nc nc nc C9 0.1uF VDDO1 2.5V FB1 2 S et Logi c Input to '1' VDD BLM18BB221SN1 C3 0.1uF VDDO2 C1 10uF C2 0.1uF C4 0.1uF Logic Control Input Exam ples VDD 1 VDDO 14 19 MR nPLL_SEL nXTAL_SEL 10uF VDDA 22 23 24 VDD U1 MR nPLL_SEL nXTAL_SEL C6 0.1uF C5 6 C8 0. 1uF 1 Zo = 50 Ohm Set Logic Input to '0' 1 Q0 2 nQ0 4 Q1 5 nQ1 7 Q2 8 nQ2 Q0 nQ0 + R6 100 Zo = 50 Ohm RU1 1K RU2 Not Install To Logic Input pins Q1 nQ1 To Lo gic In put pins RD1 Not Ins tall LVDS Termi nation Q2 RD2 1K nQ2 Zo = 50 Ohm 9 Q3 10 nQ3 Q3 nQ3 2.5V LVDS Receiv er + R9 100 Zo = 50 Ohm LVDS Receiv er Ro =7 Ohm R1 Zo = 50 Ohm 29 13 REF _CLK Q4 43 Q5 Q6 20 Q7 LVCMOS Receiv er Q7 XTAL_OUT 3 12 16 17 21 C10 22pF 18 XTAL_IN 31 X1 33 R10 ePAD XTAL_OUT Q6 Zo = 50 Q5 Zo = 50 33 33 25MHz (18pf) 32 GND GND GND GND GND XTAL_IN C11 22pF R8 15 LVCMOS Driv er Q4 LVCMOS Receiv er C13 Zo = 50 Ohm Q 0.1u R7 50 VDD_Rec eiv er R3 + Alternate AC coupled LVDS Termination (S el ect R3 and R4 to center the LVDS swing in the common mode center of the Receiver.) R4 C12 0. 01uF R2 50 Receiv er C14 nQ 0.1u Zo = 50 Ohm Figure 4. ICS8440258-46 Schematic Example ICS8440258CK-46 REVISION A OCTOBER 18, 2013 17 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8440258-46. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8440258-46 is the sum of the core power plus the analog plus the power dissipated into the load. The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Core and LVDS Output Power Dissipation The maximum currents at 70° are as follows: IDD_MAX = 187mA IDDA_MAX = 15mA IDDOX_MAX = 6mA • Power (core, LVDS) = VDDX_MAX * (IDD_MAX + IDDA_MAX + IDDOX_MAX) = 2.625V * (187mA + 15mA + 6mA) = 546mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation into the Load 50 to VDDOX_MAX/2 Output Current IOUT = VDDOX_MAX / [2 * (50 + ROUT)] = 2.625V / [2 * (50 + 11)] = 21.52mA Output Current IOUT = VDDOX_MAX / [2 * (50 + ROUT)] = 2.625V / [2 * (50 + 22)] = 18.23mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 11 * (21.52mA)2 = 5.09mW per output Power (ROUT) = ROUT * (IOUT)2 = 22 * (18.23mA)2 = 7.31mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 5.09mW * 2 = 10.18mW Total Power (ROUT) = 7.31mW * 2 = 14.62mW • Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDDOX_MAX)2 = 12pF * 125MHz * (2.625V)2 = 10.34mW per output Total Power (125MHz) = 10.34mW * 2 = 20.68mW • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDOX_MAX)2 = 7pF * 25MHz * (2.625V)2 = 1.21mW per output Total Power (25MHz) = 1.21mW * 2 = 2.42mW Total Power Dissipation • Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz) = 546mW + 10.18mW + 14.62mW + 20.68mW + 2.42mW = 594mW ICS8440258CK-46 REVISION A OCTOBER 18, 2013 18 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.594W * 33.1°C/W = 89.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8440258CK-46 REVISION A OCTOBER 18, 2013 0 1 3 33.1°C/W 28.1°C/W 25.4°C/W 19 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Reliability Information Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 3 33.1°C/W 28.1°C/W 25.4°C/W Transistor Count The transistor count for ICS8440258-46 is: 2610 ICS8440258CK-46 REVISION A OCTOBER 18, 2013 20 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C D2 C Bottom View w/Type C ID 2 1 2 1 4 Th er mal Ba se D2 2 N &N Odd Bottom View w/Type A ID CHAMFER e N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8440258CK-46 REVISION A OCTOBER 18, 2013 21 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8440258CK-46LF ICS0258C46L “Lead-Free” 32 Lead VFQFN Tray 0C to 70C 8440258CK-46LFT ICS0258C46L “Lead-Free” 32 Lead VFQFN Tape & Reel 0C to 70C ICS8440258CK-46 REVISION A OCTOBER 18, 2013 22 ©2013 Integrated Device Technology, Inc. ICS8440258-46 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.