9DBL411AKLF

DATASHEET ICS9DBL411A Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2 Recommended Application: Features/Benefits: PCI-Express fanout buffer • Low power differential fanout buffer for PCIExpress and CPU clocks • 20-pin MLF or TSSOP packaging Output Features: General Description: • 4 - low power differential output pairs • Individual OE# control of each output pair The ICS9DBL411 is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum input frequency of 400 MHz. Key Specifications: • Output cycle-cycle jitter < 25ps additive • Output to output skew: < 50ps Power Groups Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Funtional Block Diagram 4 OE#(3:0) 4 DIF_INT STOP LOGIC DIF_INC IDT® Four Output Differential Buffer for PCI Express DIF_LPR(3:0) 1250C—06/28/12 1 ICS9DBL411A Four Output Differential Buffer for PCI Express Advance Information Pin Configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ICS9DBL411 OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR DIF0C_LPR DIF0T_LPR OE0# DIF_INC DIF_INT 20-pin TSSOP 20 19 18 17 16 7 8 9 10 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# VDD_IO 6 DIF2T_LPR 9DBL411 DIF2C_LPR 1 2 3 4 5 GND VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 20-pin MLF IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12 2 ICS9DBL411A Four Output Differential Buffer for PCI Express Advance Information TSSOP Pin Description PIN # (TSSOP) PIN NAME 1 OE0# 2 3 4 5 DIF_INC DIF_INT VDDA GNDA 6 OE3# 7 8 9 10 11 12 DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR 13 OE2# 14 15 DIF1C_LPR DIF1T_LPR 16 OE1# 17 18 19 20 GND VDD_IO DIF0C_LPR DIF0T_LPR PIN TYPE IN IN IN PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT DESCRIPTION Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12 3 ICS9DBL411A Four Output Differential Buffer for PCI Express Advance Information MLF Pin Description PIN # (MLF) 1 2 VDDA GNDA PWR GND 3 OE3# IN 4 DIF3C_LPR OUT 5 DIF3T_LPR OUT 6 7 VDD_IO GND PWR GND 8 DIF2C_LPR OUT 9 DIF2T_LPR OUT 10 OE2# 11 DIF1C_LPR OUT 12 DIF1T_LPR OUT 13 OE1# 14 15 GND VDD_IO GND PWR 16 DIF0C_LPR OUT 17 DIF0T_LPR OUT 18 OE0# IN 19 20 DIF_INC DIF_INT IN IN PIN NAME PIN TYPE IN IN DESCRIPTION 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12 4 ICS9DBL411A Four Output Differential Buffer for PCI Express Advance Information Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS Maximum Supply Voltage VDDA Core Supply Voltage MIN Maximum Supply Voltage VDD_IO Low-Voltage Differential I/O Supply Maximum Input Voltage VIH 3.3V LVCMOS Inputs Minimum Input Voltage VIL Any Input Vss - 0.5 Storage Temperature Ts - -65 Input ESD protection ESD prot Human Body Model 2000 0.99 MAX UNITS Notes 4.6 V 1,7 3.8 V 1,7 4.6 V 1,7,8 V 1,7 150 ° C 1,7 V 1,7 Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Ambient Operating Temp Tambient - 0 70 °C 1 Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1 Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.99 3.465 V 1 Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1 Input Low Voltage VILSE VSS - 0.3 0.8 V 1 Differential Input High Voltage VIHDIF 600 1.15 V 1 Differential Input Low Voltage VILDIF VSS - 0.3 300 mV 1 Input Slew Rate - DIF_IN dv/dt Single-ended inputs Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Measured differentially 0.4 8 V/ns 2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1 IDD_3.3V 3.3V supply 25 mA 1 IDD_IO+100M VDD_IO supply @ fOP = 100MHz 15 mA 1 IDD_IO_400M 54 mA 1 1 mA 1 IDD_SBIO VDD_IO supply @ fOP = 400MHz 3.3V supply, Input stopped, OE# pins all high VDD_IO supply, Input stopped 1 Fi VDD = 3.3 V Operating Supply Current Standby Current Input Frequency Pin Inductance Input Capacitance IDD_SB33 Lpin CIN COUT OE# latency TOE#LAT Tdrive_OE# TDROE# Tfall_OE# TFALL Trise_OE# TRISE 33 Logic Inputs 1.5 Output pin capacitance Number of clocks to enable or disable output from assertion/deassertion of OE# Output enable after OE# de-assertion Fall/rise time of OE# inputs IDT® Four Output Differential Buffer for PCI Express 1 0.1 mA 400 MHz 2 7 nH 1 5 pF 1 6 pF 1 3 periods 1 10 ns 1 5 ns 1 5 ns 1 1250C—06/28/12 5 ICS9DBL411A Four Output Differential Buffer for PCI Express Advance Information AC Electrical Characteristics - DIF Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Rising Edge Slew Rate tSLR Differential Measurement 1 2.5 V/ns 1,2 1 Falling Edge Slew Rate tFLR Differential Measurement 2.5 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1 Minimum Output Voltage VLOW Includes undershoot -300 mV 1 Differential Voltage Swing VSWING Differential Measurement 1200 mV 1 Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation VXABSVAR 140 mV 1,3,5 0.5 % 1,6 +5 % 1,6 +7 % 1,6 25 ps 1 50 ps 1 3.5 ns 1 DIF Jitter - Cycle to Cycle DIFJ C2C DIF[3:0] Skew DIFSKEW Single-ended Measurement Differential Measurement, fIN