9DBU0231AKLFT

2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU0231 DATASHEET Description Features/Benefits The 9DBU0231 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. The device has 2 output enables for clock management. • LP-HCSL outputs; save 4 resistors compared to standard • Recommended Application • 1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) • • Output Features • 2 – 1-167MHz Low-Power (LP) HCSL DIF pairs • Key Specifications • • • • • DIF cycle-to-cycle jitter 10MHz 313 350 N/A fs (rms) 1,6 1 Guaranteed by design and characterization, not 100% tested in production. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2] 5 Driven by 9FGU0831 or equivalent 6 Rohde&Schartz SMA100 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 8 REVISION D 04/22/15 9DBU0231 DATASHEET Additive Phase Jitter Plot: 125M (12kHz to 20MHz) RMS additive jitter: 313fs REVISION D 04/22/15 9 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 9DBU0231 DATASHEET General SMBus Serial Interface Information How to Write • • • • • • • • • • How to Read Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit • • • • • • • • • • • • • • Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) T Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address Slave Address WR IDT (Slave/Receiver) starT bit WR WRite WRite ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Data Byte Count = X Repeat starT Slave Address ACK RD Beginning Byte N ReaD ACK ACK O O Data Byte Count=X O ACK O Beginning Byte N O ACK Byte N + X - 1 ACK P X Byte X Byte O O stoP bit O O O O O Byte N + X - 1 Note: SMBus Address is Latched on SADR pin. 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 10 N Not acknowledge P stoP bit REVISION D 04/22/15 9DBU0231 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Reserved Bit 7 Reserved Bit 6 DIF OE1 Output Enable RW Low/Low Bit 5 Reserved Bit 4 DIF OE0 Output Enable RW Low/Low Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 1. A low on these bits will overide the OE# pin and force the differential output Low/Low SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type PLLMODERB1 PLL Mode Readback Bit 1 Bit 7 R PLLMODERB0 PLL Mode Readback Bit 0 Bit 6 R Bit 5 PLLMODE_SWCNTRL Enable SW control of PLL Mode RW PLLMODE1 PLL Mode Control Bit 1 Bit 4 PLLMODE0 PLL Mode Control Bit 0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Reserved Bit 7 Reserved Bit 6 SLEWRATESEL DIF1 Slew Rate Selection Bit 5 Reserved Bit 4 SLEWRATESEL DIF0 Slew Rate Selection Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 SMBus Table: FB Slew Rate Control Register Byte 3 Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 SLEWRATESEL FB Adjust Slew Rate of FB Bit 0 0 1 Enabled Enabled 1 See PLL Operating Mode Table Values in B1[7:6] set PLL Mode Values in B1[4:3] set PLL Mode RW 1 RW 1 See PLL Operating Mode Table RW RW 00 = 0.55V 10= 0.75V 01 = 0.65V 11 = 0.85V Type 0 1 RW Slow Setting Fast Setting RW Slow Setting Fast Setting Type 0 1 RW Slow Setting Fast Setting Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF REVISION D 04/22/15 11 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 9DBU0231 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 12 Type RW RW RW RW RW 0 1 A rev = 0000 0001 = IDT 0 1 00 = FGx, 01 = DBx ZDB/FOB, 10 = DMx, 11= DBx FOB 000100 binary or 02 hex 0 Default 0 0 0 0 0 0 0 1 Default 0 1 0 0 0 0 1 0 1 Default 0 0 0 0 Writing to this register will configure how 1 many bytes will be read back, default is 0 = 8 bytes. 0 0 REVISION D 04/22/15 9DBU0231 DATASHEET Marking Diagrams LOT U21AL YYWW LOT U21AIL YYWW Notes: 1. “LOT” is the lot sequence number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. Line 2: truncated part number 4. “L” denotes RoHS compliant package. 5. “I” denotes industrial temperature range device. Thermal Characteristics PARAMETER SYMBOL CONDITIONS ΘJC Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow Junction to Air, 5 m/s air flow ΘJb Thermal Resistance ΘJA0 ΘJA1 ΘJA3 ΘJA5 PKG NLG20 NLG24 TYP VALUE 62 5.4 50 43 39 38 UNITS NOTES °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 1 ePad soldered to board REVISION D 04/22/15 13 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 9DBU0231 DATASHEET Package Outline and Package Dimensions (NLG24) 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 14 REVISION D 04/22/15 9DBU0231 DATASHEET Package Outline and Package Dimensions (NLG24), cont. REVISION D 04/22/15 15 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 9DBU0231 DATASHEET Ordering Information Part / Order Number Shipping Packaging 9DBU0231AKLF Tubes 9DBU0231AKLFT Tape and Reel 9DBU0231AKILF Tubes 9DBU0231AKILFT Tape and Reel Package 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). Revision History Rev. A B C D Initiator Issue Date Description 1. Updated electrical tables with char data. 2. Added an additive phase jitter plot. RDW 7/14/2014 3. Added 12kHz to 20MHz additive phase jitter spec. 4. Updated Amplitude control bit descriptions in Byte 1. Updated SMBus Input High/Low parameters conditions, MAX values, RDW 9/19/2014 and footnotes. 1. Updated pin out and pin descriptions to show ePad on package connected to ground. RDW 4/3/2015 2. Updated front page text to standard format for these devices. Added explicit bullet indicated Spread Spectrum compatibility. 1. Updated Clock Input Parameters table to be consistent with PCIe Vswing parameter. RDW 4/22/2014 2. Minor updates to front page text for family consistency. 3. Add note about epad to Power Connections table. 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 16 Page # Various 6 1-4 1,5 REVISION D 04/22/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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