9DBV0841AKILF

9DBV0841 8-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 100ohms DATASHEET Description Features/Benefits The 9DBV0841 is a 1.8V member of Renesas’ full featured PCIe family. It has integrated output terminations providing Zo = 100 for direct connection for 100 transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses. • LP-HCSL outputs save 32 resistors; minimal board space Typical Applications • SSD, microServers, WLAN Access points • • Output Features • • • • Eight 1–200MHz Low-Power (LP) HCSL DIF pairs • Key Specifications • • • • • DIF cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps PCIe Gen5 CC additive phase jitter < 40fs RMS 12kHz–20MHz additive phase jitter = 156fs RMS at 156.25M (typical) • • • • • • Block Diagram vOE(7:0)# and BOM cost 62mW typical power consumption in PLL mode; eliminates thermal concerns Spread Spectrum (SS) compatible; allows use of SS for EMI reduction OE# pins; support DIF power management HCSL compatible differential input; can be driven by common clock sources Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application Outputs blocked until PLL is locked; clean system start-up Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications Configuration can be accomplished with strapping pins; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 6 × 6 mm 48-VFQFPN; minimal board space Selectable SMBus addresses; multiple devices can easily share an SMBus segment 8 DIF7 DIF6 CLK_IN SS Compatible PLL CLK_IN# vSADR 9DBV0841 R31DS0070EU0700 JULY 27, 2021 DIF4 DIF3 ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 DIF5 DIF2 Control Logic DIF1 DIF0 1 ©2021 Renesas Electronics Corporation 9DBV0841 DATASHEET vOE5# VDD1.8 VDDIO GND DIF6 DIF6# vOE6# DIF7 DIF7# vOE7# VDDIO ^CKPWRGD_PD# Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR_tri 1 36 DIF5# ^vHIBW_BYPM_LOBW# 2 35 DIF5 FB_DNC 3 34 vOE4# FB_DNC# 4 33 DIF4# 9DBV0841 VDDR1.8 5 CLK_IN 6 32 DIF4 31 VDDIO EPAD should be connected to GND CLK_IN# 7 GNDR 8 30 VDDA1.8 29 GNDA GNDDIG 9 28 vOE3# SCLK_3.3 10 27 DIF3# SDATA_3.3 11 26 DIF3 VDDDIG1.8 12 25 vOE2# DIF2# DIF2 GND VDDIO VDD1.8 DIF1# DIF1 vOE1# DIF0 DIF0# vOE0# VDDIO 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch ^v v ^ prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 M 1 Address 1101011 1101100 1101101 + Read/Write bit x x x Power Management Table SMBus DIFx OEx# Pin True O/P Comp. O/P OEx bit 0 X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. CKPWRGD_PD# CLK_IN Power Connections Pin Number VDD VDDIO GND 13, 21, 31, 39, 47 FSEL Byte3 [4:3] 00 (Default) 01 10 11 Description 9 Input receiver analog Digital Power 22, 29, 40 DIF outputs 29 PLL Analog 8 12 30 Off On1 On1 On1 Frequency Select Table 5 20, 31, 38 PLL CLK_IN (MHz) 100.00 50.00 125.00 Reserved DIFx (MHz) CLK_IN CLK_IN CLK_IN Reserved PLL Operating Mode 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS HiBW_BypM_LoBW# 0 M 1 2 MODE PLL Lo BW Bypass PLL Hi BW Byte1 [7:6] Readback 00 01 11 Byte1 [4:3] Control 00 01 11 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET Pin Descriptions PIN # 1 2 3 4 PIN NAME TYPE DESCRIPTION LATCHED vSADR_tri Tri-level latch to select SMBus Address. See SMBus Address Selection Table. IN LATCHED Trilevel input to select High BW, Bypass or Low BW mode. ^vHIBW_BYPM_LOBW# IN See PLL Operating Mode Table for Details. True clock of differential feedback. The feedback output and feedback input are FB_DNC DNC connected internally on this pin. Do not connect anything to this pin. Complement clock of differential feedback. The feedback output and feedback FB_DNC# DNC input are connected internally on this pin. Do not connect anything to this pin. 5 VDDR1.8 PWR 6 7 8 9 10 11 12 13 CLK_IN CLK_IN# GNDR GNDDIG SCLK_3.3 SDATA_3.3 VDDDIG1.8 VDDIO IN IN GND GND IN I/O PWR PWR 14 vOE0# IN 15 16 DIF0 DIF0# OUT OUT 17 vOE1# IN 18 19 20 21 22 23 24 DIF1 DIF1# VDD1.8 VDDIO GND DIF2 DIF2# OUT OUT PWR PWR GND OUT OUT 25 vOE2# IN 26 27 DIF3 DIF3# OUT OUT 28 vOE3# IN 29 30 31 32 33 GNDA VDDA1.8 VDDIO DIF4 DIF4# 34 vOE4# IN 35 36 DIF5 DIF5# OUT OUT 37 vOE5# IN 38 VDD1.8 PWR R31DS0070EU0700 JULY 27, 2021 GND PWR PWR OUT OUT 1.8V power for differential input clock (receiver). This VDD should be treated as an Analog power rail and filtered appropriately. True Input for differential reference clock. Complementary Input for differential reference clock. Analog Ground pin for the differential input (receiver) Ground pin for digital circuitry Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. 1.8V digital power (dirty power) Power supply for differential outputs Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Power supply, nominal 1.8V Power supply for differential outputs Ground pin. Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Ground pin for the PLL core. 1.8V power for the PLL core. Power supply for differential outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 5. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Power supply, nominal 1.8V 3 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET Pin Descriptions (cont.) PIN # 39 40 41 42 PIN NAME VDDIO GND DIF6 DIF6# TYPE PWR GND OUT OUT 43 vOE6# IN 44 45 DIF7 DIF7# OUT OUT 46 vOE7# IN 47 VDDIO PWR 48 ^CKPWRGD_PD# 49 epad IN GND DESCRIPTION Power supply for differential outputs Ground pin. Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 6. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 7. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Power supply for differential outputs Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. Connect epad to ground Test Loads Low-Power push-pull HCSL Output test load (integrated terminations) L inches Differential Zo 2pF 2pF L = 5 inches Alternate Terminations The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with “Universal” Low-Power HCSL Outputs” for details. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 4 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBV0841. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 1.8V Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VDDxx VIN VIHSMB Ts Tj ESD prot Applies to VDD, VDDA and VDDIO MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model MAX 2.5 VDD+0.5V 3.6V 150 125 2000 UNITS NOTES V V V °C °C V 1,2 1, 3 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. Electrical Characteristics–Clock Input Parameters TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Input Common Mode Voltage - DIF_IN V COM Common Mode Input Voltage 150 Input Swing - DIF_IN V SWING Differential value 300 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 Input Leakage Current IIN V IN = V DD , V IN = GND -5 Input Duty Cycle dtin Measurement from differential waveform 45 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 1 TYP MAX 1000 UNITS NOTES mV 1 mV 1 8 V/ns 1,2 5 uA Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero. R31DS0070EU0700 JULY 27, 2021 5 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Supply Voltage VDDx Supply voltage for core and analog 1.7 1.8 1.9 V Output Supply Voltage VDDIO Ambient Operating Temperature TAMB Supply voltage for Low Power HCSL Outputs Commercial range 0.9975 0 1.05 25 1.9 70 V °C Industrial range -40 25 85 °C Input High Voltage VIH Single-ended inputs, except SMBus 0.75 VDD VDD + 0.3 V Input Mid Voltage VIM Single-ended tri-level inputs ('_tri' suffix) 0.4 VDD 0.6 VDD V Input Low Voltage VIL Single-ended inputs, except SMBus -0.3 0.25 VDD V IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA IINP Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors -200 200 uA Input Current UNITS NOTES VIN = VDD; Inputs with internal pull-down resistors Input Frequency Fiby p Bypass mode 1 200 MHz 2 Fipll 100MHz PLL mode 60 100.00 140 MHz 2 Fipll 125MHz PLL mode 75 125.00 175 MHz 2 Fipll 50MHz PLL mode 30 50.00 65 MHz 2 7 nH 1 Pin Inductance Lpin CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 Capacitance CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,5 6 pF 1 1 ms 1,2 30 33 kHz 0 66 kHz 1 3 clocks 1,3 300 us 1,3 5 ns 2 ns 2 COUT Output pin capacitance Tfall tF From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency for PCIe Applications (Triangular Modulation) Allowable Frequency for non-PCIe Applications (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Trise tR Rise time of single-ended control inputs SMBus Input Low Voltage VILSMB VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V SMBus Input High Voltage VIHSMB VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V SMBus Output Low Voltage VOLSMB @ IPULLUP Clk Stabilization Input SS Modulation Frequency PCIe Input SS Modulation Frequency non-PCIe TSTAB fMODINPCIe fMODIN OE# Latency t LATOE# Tdrive_PD# t DRVPD 0.6 0.6 2.1 SMBus Sink Current IPULLUP @ VOL 4 Nominal Bus Voltage V DDSMB Bus Voltage 1.7 SCLK/SDATA Rise Time tRSMB SCLK/SDATA Fall Time SMBus Operating Frequency V 3.6 V 0.4 V 4 mA 3.6 V (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 fMAXSMB Maximum SMBus operating frequency 400 kHz 6 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are > 200 mV. 4 For V DDSMB < 3.3V, VIHSMB > = 0.8xVDDSMB. 2 5 6 DIF_IN input. The differential input clock must be running for the SMBus to be active. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 6 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET Electrical Characteristics–Low Power HCSL Outputs TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP 2.8 2.1 6.2 4 3.2 20 Voltage High VHIGH 660 789 850 Voltage Low VLOW -150 38 150 Max Voltage Min Voltage Crossing Voltage (abs) Vmax Vmin Vcross_abs Scope averaging on, fast setting Scope averaging on, slow setting Slew rate matching, Scope averaging on Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off 1.7 1.1 Slew rate matching dV/dt dV/dt ΔdV/dt 803 15 417 1150 -300 250 550 mV 7 7 1,5 Crossing Voltage (var) Δ-Vcross Scope averaging off 13 140 mV 1,6 Slew rate 1 MAX UNITS NOTES V/ns V/ns % mV mV 1,2,3 1,2,3 1,2,4 7 7 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 3 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics–Current Consumption TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL IDDA Operating Supply Current 2 MIN TYP 10.6 MAX 15 UNITS mA NOTES 1 1 IDD VDD, All outputs active @100MHz 6.1 10 mA IDDO VDDO, All outputs active @100MHz 30.7 35 mA 1 IDDAPD VDDA+VDDR, PLL Mode, @100MHz 0.58 1 mA 1, 2 IDDPD VDD, Outputs Low/Low 0.81 2 mA 1, 2 IDDOPD VDDO, Outputs Low/Low 0.00 0.01 mA 1, 2 Powerdown Current 1 CONDITIONS VDDA+VDDR, PLL Mode, @100MHz Guaranteed by design and characterization, not 100% tested in production. Input clock stopped. R31DS0070EU0700 JULY 27, 2021 7 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES PLL Bandwidth BW 2 1 t JPEAK tDC -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode 45 2.7 1.4 1.1 50.1 4 2 2 55 MHz MHz dB % 1,5 1,5 1 1 PLL Jitter Peaking Duty Cycle Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -1 0.03 1 % 1,3 Jitter, Cycle to cycle t jcyc-cyc Bypass Mode, VT = 50% PLL Mode VT = 50% VT = 50% PLL mode Additive Jitter in Bypass Mode 2800 -100 Skew, Output to Output t pdBYP t pdPLL t sk3 3625 -4 39 14 0.10 4500 100 50 50 25 ps ps ps ps ps 1 1,4 1,4 1,2 1,2 Skew, Input to Output 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4 All outputs at default slew rate 5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. 2 Electrical Characteristics–Phase Jitter Parameters – 12kHz to 20MHz TAMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum Fan-out Buffer M ode, 12k-20M Additive Phase Jitter, 156 tjph12k-20MFOB SSC OFF, 156.25MHz Fan-out Buffer Mode Notes: 1. Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details. 2. 12kHz to 20M Hz brick wall filter. 2 Specification Limit Units Notes n/a fs (rms) 1, 2, 3 2 3. For RM S values additive jitter is calculated by solving for b where [b = sqrt(c - a )], a is rms input jitter and c is rms total jitter. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 8 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET Electrical Characteristics–Additive PCIe Phase Jitter for Fanout Buffer Mode[7] T AMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum Limit tjphPCIeG1-CC PCIe Gen 1 (2.5 GT/s) 1.7 3.0 86 PCIe Gen 2 Hi Band (5.0 GT/s) 0.033 0.049 3 PCIe Gen 2 Lo Band (5.0 GT/s) 0.122 0.199 3.1 tjphPCIeG3-CC PCIe Gen 3 (8.0 GT/s) 0.059 0.098 1 tjphPCIeG4-CC PCIe Gen 4 (16.0 GT/s) 0.059 0.098 0.5 tjphPCIeG5-CC PCIe Gen 5 (32.0 GT/s) 0.023 0.038 0.15 tjphPCIeG1-SRIS PCIe Gen 1 (2.5 GT/s) 0.175 0.038 n/a tjphPCIeG2-SRIS PCIe Gen 2 (5.0 GT/s) 0.156 0.275 n/a tjphPCIeG3-SRIS PCIe Gen 3 (8.0 GT/s) 0.041 0.247 n/a tjphPCIeG4-SRIS PCIe Gen 4 (16.0 GT/s) 0.043 0.064 n/a tjphPCIeG5-SRIS PCIe Gen 5 (32.0 GT/s) 0.036 0.066 n/a tjphPCIeG2-CC Additive PCIe Phase Jitter, Fan-out Buffer Mode (Common Clocked Architecture) Additive PCIe Phase Jitter, Fan-out Buffer Mode (SRIS Architecture) Units ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) Notes 1, 2 1, 2 1, 2 1, 2 1, 2, 3, 4 1, 2, 3, 5 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 Notes: 1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. The worst case results for each data rate are summarized in this table. If oscilloscope data is used, equipment noise is removed from all results. 2. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 M Hz (at 300 M Hz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RM S jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results the RTO result must be used. 3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 M Hz taking care to minimize removal of any non-SSC content. 4. Note that 0.7 ps RM S is to be used in channel simulations to account for additional noise in a real system. 5. Note that 0.25 ps RM S is to be used in channel simulations to account for additional noise in a real system. 6. The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RM S values, twice as good is equivalent to dividing the CC value by 2. And additional consideration is the value for which to divide by  2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by 2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A "rule-of-thumb" SRIS limit would be either 0.5ps RM S/2 = 0.35ps RM S if the clock chip is far from the clock input, or 0.7ps RM S/ 2 = 0.5ps RM S if the clock chip is near the clock input.. 7. Additive jitter for RM S values is calculated by solving for b where b √ 𝑐2 𝑎2 , and a is rms input jitter and c is rms output jitter. R31DS0070EU0700 JULY 27, 2021 9 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET General SMBus Serial Interface Information How to Write • • Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T • • • • • • • • • • • • • • starT bit Beginning Byte = N ACK Data Byte Count = X WR Beginning Byte = N ACK RT ACK RD Repeat starT Slave Address ReaD X Byte ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 P WRite ACK ACK Beginning Byte N O Renesas starT bit Slave Address ACK O Controller (Host) T WRite O Index Block Read Operation Renesas (Slave/Receiver) Slave Address WR Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit stoP bit X Byte • • • • • • • • How to Read O O O O O Note: SMBus Address is Latched on SADR pin. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS O Byte N + X - 1 N Not acknowledge P stoP bit 10 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 DIF OE7 Output Enable RW Low/Low Bit 7 DIF OE6 Output Enable RW Low/Low Bit 6 DIF OE5 Output Enable RW Low/Low Bit 5 DIF OE4 Output Enable RW Low/Low Bit 4 DIF OE3 Output Enable RW Low/Low Bit 3 DIF OE2 Output Enable RW Low/Low Bit 2 DIF OE1 Output Enable RW Low/Low Bit 1 DIF OE0 Output Enable RW Low/Low Bit 0 1. A low on these bits will override the OE# pin and force the differential output Low/Low SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type PLLMODERB1 PLL Mode Readback Bit 1 Bit 7 R PLLMODERB0 PLL Mode Readback Bit 0 Bit 6 R Bit 5 PLLMODE_SWCNTRL Enable SW control of PLL Mode RW PLLMODE1 PLL Mode Control Bit 1 Bit 4 PLLMODE0 PLL Mode Control Bit 0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 Bit 7 SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 Bit 6 SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 Bit 5 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 Bit 4 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 Bit 3 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 Bit 2 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 1 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 0 SMBus Table: Frequency Select Control Register Byte 3 Name Control Function Reserved Bit 7 Reserved Bit 6 Enable SW selection of FREQ_SEL_EN Bit 5 frequency FSEL1 Freq. Select Bit 1 Bit 4 FSEL0 Freq. Select Bit 0 Bit 3 Reserved Bit 2 Reserved Bit 1 SLEWRATESEL FB Adjust Slew Rate of FB Bit 0 1. B3[5] must be set to a 1 for these bits to have any effect on the part. 1 OE7# control OE6# control OE5# control OE4# control OE3# control OE2# control OE1# control OE0# control Default 1 1 1 1 1 1 1 1 1 Default Latch Latch 0 See PLL Operating Mode Table Values in B1[7:6] set PLL Mode Values in B1[4:3] set PLL Mode RW 1 RW 1 See PLL Operating Mode Table RW RW 00 = 0.6V 10= 0.8V Type RW RW RW RW RW RW RW RW 0 Slow setting Slow setting Slow setting Slow setting Slow setting Slow setting Slow setting Slow setting Type RW RW 1 RW 1 RW 01 = 0.7V 11 = 0.9V 0 0 0 1 1 0 1 setting setting setting setting setting setting setting setting Default 1 1 1 1 1 1 1 1 0 1 Default 1 1 SW frequency change disabled SW frequency change enabled Fast Fast Fast Fast Fast Fast Fast Fast See Frequency Select Table Slow setting Fast setting 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF R31DS0070EU0700 JULY 27, 2021 11 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS Type RW RW RW RW RW 0 1 A rev = 0000 0001 = IDT 0 1 00 = FGx, 01 = DBx, 10 = DMx, 11= Reserved 001000 binary or 08 hex 0 Default 0 0 0 0 0 0 0 1 Default 0 1 0 0 1 0 0 0 Default 0 0 0 0 1 Writing to this register will configure how 0 many bytes will be read back, default is 0 = 8 bytes. 0 12 1 R31DS0070EU0700 JULY 27, 2021 9DBV0841 DATASHEET Marking Diagrams ICS DBV0841AL YYWW COO LOT ICS BV0841AIL YYWW COO LOT Notes: 1. “LOT” is the lot sequence number. 2. “COO” denotes country of origin. 3. YYWW is the last two digits of the year and week that the part was assembled. 4. Line 2: truncated part number 5. “L” denotes RoHS compliant package. 6. “I” denotes industrial temperature range device. Thermal Characteristics 1 PARAMETER SYMBOL CONDITIONS PKG Thermal Resistance θJC θJb θJA0θ θJA1 θJA3 θJA5 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow Junction to Air, 5 m/s air flow NDG48 TYP VALUE 33 2.1 37 30 27 26 UNITS NOTES °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 ePad soldered to board Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 48-VFQFPN (NDG48P1) Ordering Information Part / Order Number Shipping Packaging 9DBV0841AKLF Trays 9DBV0841AKLFT Tape and Reel 9DBV0841AKILF Trays 9DBV0841AKILFT Tape and Reel Package 48-pin VFQFPN 48-pin VFQFPN 48-pin VFQFPN 48-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). R31DS0070EU0700 JULY 27, 2021 13 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0841 DATASHEET Revision History Revision Date August 13, 2012 February 18, 2013 August 12, 2014 March 10, 2016 April 28, 2016 August 28, 2019 July 27, 2021 Description 1. Removed "Differential" from DS title and Recommended Application, corrected typo's in Description. Updated block diagram to show integrated terminations. 2. Removed references to 60KOhm pulldown under pinout. 3. Updated "Phase Jitter Parameters" table by adding "Industry Limit" column and updated all Electrical Tables with characterization data. 4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6] definition. 5. Updated Mark spec with correct part revision (A) and added thermal data to page 13. 6. Added NDG48 to "Package Outline and Package Dimensions" on page 14 and updated Ordering information to correct part revision (A rev). 7. Move to final 1. Changed VIH min. from 0.65*VDD to 0.75*VDD 2. Changed VIL max. from 0.35*VDD to 0.25*VDD 3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to 0.6*VDD. Changed package designator from "MLF" to "VFQFPN" 1. Numerous typographical and grammatical updates for document consistency with other devices in the family, including updated descriptions for Bytes 0 and 2. 2. Fast and slow slew rates were swapped in the "DIF 0.7V Low Power HCSL Outputs" table. 3. Changed PCIe clock source from 9FG432 to 9FGV0841/9FGL0841 for PLL mode phase jitter numbers. New phase jitter numbers are lower. 4. Added epad to pinout diagram and pin descriptions. 5. Updated Clock Input Parameters to be consistent with PCIe Vswing parameter. 6. Updated package drawing to latest format. 1. Updated max frequency of 100MHz PLL mode to 140MHz 2. Updated max frequency of 125MHz PLL mode to 175MHz 3. Updated max frequency of 50MHz PLL mode to 65MHz Updated to PCIe Gen4. 1. Added new Electrical Characteristics–Phase Jitter Parameters tables. 2. Updated datasheet title. 3. Updated Key Specifications. 4. Updated Package Outline Drawings section. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 14 R31DS0070EU0700 JULY 27, 2021 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.1x 4.1 mm, 0.40mm Pitch NDG48P1, PSC-4212-01, Rev 01, Page 1 © Integrated Device Technology, Inc. 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.1 x 4.1 mm, 0.40mm Pitch NDG48P1, PSC-4212-01, Rev 01, Page 2 Package Revision History © Integrated Device Technology, Inc. Description Date Created Rev No. Aug16, 2018 Rev 01 New Format Change QFN to VFQFPN, Recalculate Land Pattern May 6, 2016 Rev 00 Add Chamfer IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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