9FGU0641AKLF

6 O/P 1.5V PCIe Gen1-2-3 Clock Generator w/Zo=100ohms 9FGU0641 DATASHEET Description Features/Benefits The 9FGU0641 is a member of IDT's 1.5V Ultra-Low-Power PCIe clock family with integrated output terminations providing Zo=100ohms. The device has 6 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. • Direct connection to 100ohm transmission lines; saves 24 Recommended Application • • • • 1.5V PCIe Gen1-2-3 clock generator Output Features • • 6 -100MHz Low-power HCSL (LP-HCSL) DIF pairs • • w/Zo=100 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) support • • Key Specifications • • • • • DIF cycle-to-cycle jitter = 0.8xVDDSMB 2 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 6 OCTOBER 18, 2016 9FGU0641 DATASHEET Electrical Characteristics–DIF Low-Power HCSL Outputs TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Slew rate Trf Slew rate matching ΔTrf Voltage High VHIGH CONDITIONS MIN TYP Scope averaging on fast setting Scope averaging on slow setting Slew rate matching, Scope averaging on 1.2 0.8 2.4 1.7 9 3.6 2.5 20 600 750 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs Δ-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns V/ns % 1,2,3 1,2,3 1,2,4 7 mV -150 26 150 763 22 1448 390 11 1150 -300 300 250 550 140 7 7 7 1,2,7 1,5,7 1,6,7 mV mV mV mV 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 2 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus amplitude settings. Electrical Characteristics–DIF Output Phase Jitter Parameters TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS tjphPCIeG1 PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 Common Clock Architecture (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) tjphPCIeG2 Phase Jitter, PLL Mode tjphPCIeG3 MIN tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS) S (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) TYP MAX 27.7 40 IND. LIMIT 86 1.0 1.3 3 1.9 2.2 3.1 0.4 0.6 1 0.4 0.6 0.7 UNITS Notes ps (p-p) ps (rms) ps (rms) ps (rms) 1,2,3,5 ps (rms) 1,2,3,5 1,2,3,5 1,2,3,5 1,2,3,5 1 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Calculated from Intel-supplied Clock Jitter Tool 5 Applies to all differential outputs 2 OCTOBER 18, 2016 7 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 9FGU0641 DATASHEET Electrical Characteristics–REF TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 25 MHz output Rise/Fall Slew Rate t rf1 Byte 3 = 1F, 20% to 80% of VDDREF 0.3 Rise/Fall Slew Rate trf1 Byte 3 = 5F, 20% to 80% of VDDREF 0.5 Rise/Fall Slew Rate trf1 Byte 3 = 9F, 20% to 80% of VDDREF 0.77 Rise/Fall Slew Rate trf1 Byte 3 = DF, 20% to 80% of VDDREF 0.84 Duty Cycle dt1X VT = VDD/2 V 45 0 TYP 0 40 0.7 1.0 1.3 1.4 47.1 MAX 1.1 1.6 1.9 2.0 55 UNITS ppm ns V/ns V/ns V/ns V/ns % Notes 1,2 2 1 1,3 1 1 1,4 Duty Cycle Distortion dtcd V T = VDD/2 V, when driven by XIN/CLKIN_25 pin 2.00 4 % 1,5 Jitter, cycle to cycle Noise floor Noise floor t jcyc-cyc tjdBc1k tjdBc10k VT = VDD/2 V 1kHz offset 10kHz offset to Nyquist 51.2 -126 -139 250 -105 -110 1,4 1,4 1,4 Jitter, phase t jphREF 12kHz to 5MHz 1.11 3 ps dBc dBc ps (rms) 1,4 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 3 Default SMBus Value 4 When driven by a crystal. 2 5 X2 should be floating. Clock Periods–Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC + ppm - ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94900 9.99900 10.00000 10.00100 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.05100 ns 1,2 Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 Measurement Window 1us 0.1s 0.1s 0.1s -SSC + ppm - ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94906 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.10107 ns 1,2 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 2 Clock Periods–Single-ended Outputs 1 Clock SSC OFF Center Freq. MHz REF 25.000 1us 0.1s Measurement Window 0.1s 0.1s -SSC - ppm -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 0 ppm Period Nominal + ppm Long-Term Average Max 39.79880 40.00000 40.00120 39.99880 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 8 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 40.20120 ns 1,2 OCTOBER 18, 2016 9FGU0641 DATASHEET General SMBus Serial Interface Information How to Write • • • • • • • • • • How to Read Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit • • • • • • • • • • • • • • Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite WR ACK WRite ACK Beginning Byte = N Beginning Byte = N ACK ACK Data Byte Count = X RT ACK X Byte Beginning Byte N Repeat starT Slave Address RD ACK ReaD ACK O O O O O Data Byte Count=X O ACK ACK ACK Beginning Byte N Byte N + X - 1 O stoP bit Note: SMBus address is latched on SADR pin. O O O O X Byte P O OCTOBER 18, 2016 9 N Not acknowledge P stoP bit Byte N + X - 1 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 9FGU0641 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 DIF OE5 Output Enable RW Low/Low Bit 7 DIF OE4 Output Enable RW Low/Low Bit 6 Reserved Bit 5 DIF OE3 Output Enable RW Low/Low Bit 4 DIF OE2 Output Enable RW Low/Low Bit 3 DIF OE1 Output Enable RW Low/Low Bit 2 Reserved Bit 1 DIF OE0 Output Enable RW Low/Low Bit 0 1. A low on these bits will overide the OE# pin and force the differential output Low/Low SMBus Table: SS Readback and Control Register Byte 1 Name Control Function SSENRB1 SS Enable Readback Bit1 Bit 7 SSENRB1 SS Enable Readback Bit0 Bit 6 Bit 5 SSEN_SWCNTRL Enable SW control of SS SSENSW1 SS Enable Software Ctl Bit1 Bit 4 SSENSW0 SS Enable Software Ctl Bit0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 Bit 7 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 Bit 6 Reserved Bit 5 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 Bit 4 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 Bit 3 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 2 Reserved Bit 1 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 0 REF Power Down Function Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REF OE Wake-on-Lan Enable for REF REF Output Enable Reserved Reserved Reserved Reserved Enabled Enabled Enabled Enabled Type 0 1 00' for SS_EN_tri = 0, '01' for SS_EN_tri R = 'M', '11 for SS_EN_tri = '1' R RW Values in B1[7:6] Values in B1[4:3] control SS amount control SS amount. RW 1 RW 1 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS RW RW 00 = 0.55V 10= 0.7V 01 = 0.65V 11 = 0.8V Type RW RW 0 Slow Setting Slow Setting 1 Fast Setting Fast Setting RW RW RW Slow Setting Slow Setting Slow Setting Fast Setting Fast Setting Fast Setting RW 2.0V/ns 3.5V/ns SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register Byte 3 Name Control Function Type RW Bit 7 REF Slew Rate Control RW Bit 6 Bit 5 1 Enabled Enabled 0 1 00 = Slowest 01 = Slow 10 = Fast 11 = Faster REF does not run in REF runs in Power RW Power Down Down RW Low Enabled Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 0 1 0 1 1 1 1 1 Byte 4 is Reserved 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 10 OCTOBER 18, 2016 9FGU0641 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Type RW RW RW RW RW Byte Count Programming 0 1 A rev = 0001 0001 = IDT 0 1 00 = FGx, 01 = DBx ZDB/FOB, 10 = DMx, 11= DBx FOB 000110 binary or 06 hex 0 Default 0 0 0 1 0 0 0 1 Default 0 0 0 0 0 1 1 0 1 Default 0 0 0 0 1 Writing to this register will configure how 0 many bytes will be read back, default is 0 = 8 bytes. 0 Recommended Crystal Characteristics (3225 package) PARAMETER Frequency Resonance Mode Frequency Tolerance @ 25°C Frequency Stability, ref @ 25°C Over Operating Temperature Range Temperature Range (commerical) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year Notes: 1. FOX 603-25-150. 2. For I-temp, FOX 603-25-261. OCTOBER 18, 2016 VALUE UNITS NOTES 25 Fundamental ±20 MHz PPM Max 1 1 1 ±20 PPM Max 1 0~70 -40~85 50 7 8 0.3 ±5 °C °C Ω Max pF Max pF Max mW Max PPM Max 1 2 1 1 1 1 1 11 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 9FGU0641 DATASHEET Thermal Characteristics PARAMETER Thermal Resistance SYMBOL CONDITIONS PKG Junction to Case θJC Junction to Base θJb Junction to Air, still air θJA0 NDG40 Junction to Air, 1 m/s air flow θJA1 Junction to Air, 3 m/s air flow θJA3 Junction to Air, 5 m/s air flow θJA5 TYP. 42 2.4 39 33 28 27 UNITS °C/W °C/W °C/W °C/W °C/W °C/W NOTES 1 1 1 1 1 1 1 ePad soldered to board Marking Diagrams ICS GU0641AL YYWW COO LOT ICS U0641AIL YYWW COO LOT Notes: 1. “LOT” is the lot number. 2. “COO” denotes the country of origin. 3. “YYWW” is the last two digits of the year and week that the part was assembled. 4. Line 2: truncated part number. 5. “L” denotes RoHS compliant package. 6. “I” denotes industrial temperature grade. 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 12 OCTOBER 18, 2016 9FGU0641 DATASHEET NDG40 Package Outline and Package Dimensions (40-pin 5mm x 5mm VFQFPN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane A1 Index Area N 1 2 (Ref) ND & NE Even (ND-1)x e (Ref) L A3 e N 1 (Typ) If ND & NE 2 are Even 2 Sawn Singulation E E2 E2 Top View A D 0.08 C Symbol Millimeters Min Max A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.20 Reference 0.18 0.30 0.40 BASIC 40 10 10 5.00 x 5.00 3.55 3.80 3.55 3.80 0.30 0.50 (NE-1)x e (Ref) 2 (Ref) ND & NE Odd C b e Thermal Base D2 2 D2 EP – exposed thermal pad should be externally connected to GND Ordering Information Part / Order Number Shipping Packaging 9FGU0641AKLF Trays 9FGU0641AKLFT Tape and Reel 9FGU0641AKILF Trays 9FGU0641AKILFT Tape and Reel Package 40-pin VFQFPN 40-pin VFQFPN 40-pin VFQFPN 40-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). OCTOBER 18, 2016 13 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 9FGU0641 DATASHEET Revision History Rev. A B Issue Date Intiator Description 1. Updated electrical tables with latest versions for release. 2. Updated SMBus nomenclature for consistency with the family. 3. Removed references to Suspend Mode – and the Suspend Rail. This is replaced by Power Down with Wake-on-LAN modes in the 9/24/2014 RDW current consumption table. 4. Updated GenDes tab for front page consistency. 5. Updated doc with latest template. 6. Move to final. 10/18/2016 RDW Removed IDT crystal part number 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 14 Page # Various OCTOBER 18, 2016 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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