8-output 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0841
DATASHEET
General Description
Features/Benefits
The 9FGU0841 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100Ω. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
• Direct connection to 100ohm transmission lines; saves 32
Recommended Application
• 1.5V PCIe Gen1-2-3 Clock Generator
•
•
Output Features
•
• 8 - 100MHz Low-Power (LP) HCSL DIF pairs
•
•
•
•
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
•
•
Key Specification
•
•
•
•
•
DIF cycle-to-cycle jitter 200 mV
4
For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
2
OCTOBER 18, 2016
7
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0841 DATASHEET
Electrical Characteristics – DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Slew rate
Trf
Slew rate matching
ΔTrf
Voltage High
VHIGH
CONDITIONS
MIN
TYP
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.2
0.8
2.4
1.7
9
3.6
2.5
20
600
750
850
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns
V/ns
%
1,2,3
1,2,3
1,2,4
7
mV
-150
26
150
763
22
1448
390
11
1150
-300
300
250
550
140
7
mV
mV
mV
mV
7
7
1,2,7
1,5,7
1,6,7
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus amplitude settings.
Electrical Characteristics – DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
tjphPCIeG1
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
tjphPCIeG2
Phase Jitter, PLL Mode
tjphPCIeG3
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
MIN
TYP
MAX
27.7
40
IND.
LIMIT
86
1.0
1.3
3
1.9
2.2
3.1
0.4
0.6
1
0.4
0.6
0.7
UNITS
Notes
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
1,2,3,5
ps
(rms)
1,2,3,5
1,2,3,5
1,2,3,5
1,2,3,5
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Calculated from Intel-supplied Clock Jitter Tool
5
Applies to all differential outputs
2
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
8
OCTOBER 18, 2016
9FGU0841 DATASHEET
Electrical Characteristics – REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
25 MHz output
Clock period
Tperiod
Byte 3 = 1F, 20% to 80% of VDDREF
0.3
Rise/Fall Slew Rate
trf1
Byte 3 = 5F, 20% to 80% of VDDREF
0.5
Rise/Fall Slew Rate
trf1
Byte 3 = 9F, 20% to 80% of VDDREF
0.77
Rise/Fall Slew Rate
trf1
Byte 3 = DF, 20% to 80% of VDDREF
0.84
Rise/Fall Slew Rate
trf1
VT = VDD/2 V
45
Duty Cycle
dt1X
TYP
0
40
0.7
1.0
1.3
1.4
47.1
MAX
1.1
1.6
1.9
2.0
55
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
Notes
1,2
2
1
1,3
1
1
1,4
2.00
4
%
1,5
ps
dBc
dBc
ps
(rms)
1,4
1,4
1,4
Duty Cycle Distortion
dtcd
V T = VDD/2 V, when driven by XIN/CLKIN_25 pin
Jitter, cycle to cycle
Noise floor
Noise floor
tjcyc-cyc
tjdBc1k
tjdBc10k
VT = VDD/2 V
1kHz offset
10kHz offset to Nyquist
51.2
-126
-139
250
-105
-110
Jitter, phase
tjphREF
12kHz to 5MHz
1.11
3
0
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3
Default SMBus Value
4
When driven by a crystal.
2
5
X2 should be floating.
Clock Periods - Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
ns
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
AbsPer
Period
Average
Average
Average
Min
Nominal
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
ns
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to
25.00 MHz
2
OCTOBER 18, 2016
9
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0841 DATASHEET
General SMBUS Serial Interface Information
How to Write
•
•
•
•
•
•
•
•
•
•
How to Read
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
IDT (Slave/Receiver)
starT bit
Slave Address
WR
WRite
WRite
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Data Byte Count = X
Repeat starT
Slave Address
ACK
Beginning Byte N
RD
ReaD
ACK
ACK
X Byte
O
O
O
Data Byte Count=X
O
ACK
O
O
Beginning Byte N
Byte N + X - 1
ACK
stoP bit
X Byte
ACK
P
O
O
Note: SMBus address is Latched on SADR pin.
O
O
O
O
Byte N + X - 1
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
10
N
Not acknowledge
P
stoP bit
OCTOBER 18, 2016
9FGU0841 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE7
Output Enable
RW
Low/Low
Bit 7
DIF OE6
Output Enable
RW
Low/Low
Bit 6
DIF OE5
Output Enable
RW
Low/Low
Bit 5
DIF OE4
Output Enable
RW
Low/Low
Bit 4
DIF OE3
Output Enable
RW
Low/Low
Bit 3
DIF OE2
Output Enable
RW
Low/Low
Bit 2
DIF OE1
Output Enable
RW
Low/Low
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: SS Readback and Control Register
Byte 1
Name
Control Function
SSENRB1
SS Enable Readback Bit1
Bit 7
SSENRB1
SS Enable Readback Bit0
Bit 6
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
SSENSW1
SS Enable Software Ctl Bit1
Bit 4
SSENSW0
SS Enable Software Ctl Bit0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
Bit 7
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
Bit 6
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 5
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 4
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 3
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
Type
0
1
00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
R
RW
Values in B1[7:6] Values in B1[4:3]
control SS amount control SS amount.
RW 1
RW 1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
RW
00 = 0.55V
10= 0.7V
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3
Name
Control Function
Type
RW
Bit 7
REF
Slew Rate Control
RW
Bit 6
Bit 5
REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
01 = 0.65V
11 = 0.8V
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
1
Setting
Setting
Setting
Setting
Setting
Setting
Setting
Setting
0
1
00 = Slowest
01 = Slow
10 = Fast
11 = Faster
REF does not run in REF runs in Power
RW
Power Down
Down
RW
Low
Enabled
Default
1
1
1
1
1
1
1
1
Default
Latch
Latch
0
0
0
1
1
0
Default
1
1
1
1
1
1
1
1
Default
0
1
0
1
1
1
1
1
Byte 4 is Reserved
OCTOBER 18, 2016
11
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0841 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Type
Byte Count Programming
RW
RW
RW
RW
RW
0
1
A rev = 0000
0001 = IDT
0
1
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
001000 binary or 08 hex
0
Default
0
0
0
0
0
0
0
1
Default
0
0
0
0
1
0
0
0
1
Default
0
0
0
0
1
Writing to this register will configure how
0
many bytes will be read back, default is
0
= 8 bytes.
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
25
Fundamental
±20
MHz
PPM Max
1
1
1
±20
PPM Max
1
0~70
-40~85
50
7
8
0.3
±5
°C
°C
Ω Max
pF Max
pF Max
mW Max
PPM Max
1
2
1
1
1
1
1
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
12
OCTOBER 18, 2016
9FGU0841 DATASHEET
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
θJC
Thermal Resistance
PKG
TYP.
UNITS
NOTES
Junction to Case
33
°C/W
1
θJb
Junction to Base
2.1
°C/W
1
θJA0
Junction to Air, still air
37
°C/W
1
θJA1
Junction to Air, 1 m/s air flow
30
°C/W
1
θJA3
Junction to Air, 3 m/s air flow
27
°C/W
1
θJA5
Junction to Air, 5 m/s air flow
26
°C/W
1
NDG48
1
ePad soldered to board
Marking Diagrams
ICS
GU0841AIL
YYWW
COO
LOT
ICS
FGU0841AL
YYWW
COO
LOT
Notes:
1. Line 2 is the truncated part number.
2. ‘L’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
5. ‘COO’ denotes country of origin.
6. ‘LOT’ is the lot number.
OCTOBER 18, 2016
13
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0841 DATASHEET
Package Outline and Package Dimensions (NDG48, 48-pin VFQFPN)
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
Anvil
Singulation
1
(Typ)
If ND & NE
2
are Even
2
E
-- or -Top View
E2
Sawn
Singulation
A
E2
2
(Ref)
ND & NE
Odd
D
b
e
C
0.08 C
(NE-1)x e
(Ref)
Symbol
Millimeters
Min
Max
A
A1
A3
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
ND
NE
0.8
1.0
0
0.05
0.20 Reference
0.18
0.3
0.40 BASIC
6.00 x 6.00
3.95
4.25
3.95
4.25
0.30
0.50
12
12
Thermal Base
D2
2
D2
Ordering Information
Part / Order Number Shipping Packaging
9FGU0841AKLF
Trays
9FGU0841AKLFT
Tape and Reel
9FGU0841AKILF
Trays
9FGU0841AKLIFT
Tape and Reel
Package
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” to the suffix are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate to with the datasheet revision).
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
14
OCTOBER 18, 2016
9FGU0841 DATASHEET
Revision History
Rev.
Issue Date Intiator Description
Page #
A
9/24/2014
RDW
1. Updated electrical tables with latest and last versions for release
2. Updated SMBus nomenclature for consistency with the family
3. Removed references to Suspend Mode – and the Suspend Rail.
This is replaced by Power Down with Wake-on-LAN modes in the
current consumption table.
4. Updated GenDes tab for front page consistency.
5. Move to final.
B
C
8/14/2015
10/18/2016
RDW
RDW
Corrected typo in ordering information
Removed IDT crystal part number
OCTOBER 18, 2016
15
Various
14
8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
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