DATASHEET
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Description
Features/Benefits
The 9FGV0441 is an 4-output very low power clock
generator for PCIe Gen 1, 2, 3 and 4 applications with
integrated output terminations providing Zo = 100. The
device has 4 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
• Integrated terminations provide 100 differential Zo;
Recommended Application
•
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
•
Output Features
•
• 4 0.7V low-power HCSL-compatible (LP-HCSL) DIF
•
pairs with Zo=100
1 1.8V LVCMOS REF output with Wake-On-Lan (WOL)
support
Key Specifications
•
•
•
•
•
•
•
•
•
•
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–4 compliant
REF phase jitter is < 1.5ps RMS
•
•
•
reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 5 x 5 mm 32-VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Block Diagram
X1_25
REF1.8
OSC
X2
OE(3:0)#
4
DIF(3:0)
SS Capable PLL
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
1
9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
VDDO1.8
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
vSS_EN_tri
Pin Configuration
32 31 30 29 28 27 26 25
GNDXTAL 1
24 vOE2#
23 DIF2#
XIN/CLKIN_25 2
X2 3
VDDXTAL1.8 4
22 DIF2
21 VDDA1.8
9FGV0441
VDDREF1.8 5
20 GNDA
vSADR/REF1.8 6
GNDREF 7
GNDDIG 8
19 DIF1#
18 DIF1
17 vOE1#
VDDO1.8
GND
DIF0
DIF0#
vOE0#
SCLK_3.3
SDATA_3.3
VDDDIG1.8
9 10 11 12 13 14 15 16
32-VFQFPN, 5 x 5 mm, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor
v prefix indicates internal 120kOhm pull down-resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OEx#
True O/P
Comp. O/P
OE bit
0
X
X
Low
Low
Hi-Z1
1
1
0
Running
Running
Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Pin Descriptions
Pin# Pin Name
1
GNDXTAL
2
3
4
5
XIN/CLKIN_25
X2
VDDXTAL1.8
VDDREF1.8
6
vSADR/REF1.8
7
8
9
10
11
GNDREF
GNDDIG
VDDDIG1.8
SCLK_3.3
SDATA_3.3
12
vOE0#
13
14
15
16
DIF0
DIF0#
GND
VDDO1.8
17
vOE1#
18
19
20
21
22
23
DIF1
DIF1#
GNDA
VDDA1.8
DIF2
DIF2#
24
vOE2#
25
26
27
28
VDDO1.8
GND
DIF3
DIF3#
29
vOE3#
30
GND
31
^CKPWRGD_PD#
32
vSS_EN_tri
Type
GND
IN
OUT
PWR
PWR
LATCHED
I/O
GND
GND
PWR
IN
I/O
Pin Description
GND for XTAL
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
Power supply for XTAL, nominal 1.8V
VDD for REF output. nominal 1.8V.
Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
Ground pin for the REF outputs.
Ground pin for digital circuitry
1.8V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin.
PWR
Power supply for outputs, nominally 1.8V.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin for the PLL core.
PWR
1.8V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for outputs, nominally 1.8V.
GND
Ground pin.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
LATCHED IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
Rs
2pF
Device
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
3.3V
Driving LVDS
Cc
R7a
R7b
R8a
R8b
Rs
Zo
Cc
Rs
Device
LVDS Clock
input
Driving LVDS inputs with the 9FGV0441
Value
Receiver has Receiver does not
Component
termination
have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
4
9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0441. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
VDDx1.8
VIN
VIHSMB
Ts
Tj
ESD prot
Applies to All VDD pins
MIN
-0.5
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
MAX
2.5
VDD+0.3V
3.6V
150
125
2000
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
SYMBOL
CONDITIONS
TYP
MAX
UNITS
NOTES
IDDAOP
VDDA, All outputs active @100MHz
MIN
6
8
mA
1
IDDOP
VDD, All outputs active @100MHz
26
30
mA
1
Suspend Supply Current
I DDSUSP
VDDxxx, PD# = 0, Wake-On-LAN enabled
6
8
mA
1
Powerdown Current
I DDPD
PD#=0
0.6
1
mA
1, 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Assuming REF is not running in power down state
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
tDC
tsk3
Measured differentially, PLL Mode
VT = 50%
PLL mode
45
50
34
14
55
50
50
%
ps
ps
1
1
1,2
t jcyc-cyc
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
1.8V Supply Voltage
VDDx 1.8
Ambient Operating
Temperature
Input High Voltage
CONDITIONS
Supply voltage for core, analog and single-ended
LVCMOS outputs
MIN
TYP
MAX
1.7
1.8
1.9
V
1
Industrial range
-40
25
85
°C
1
TIND
UNITS NOTES
VIH
Single-ended inputs, except SMBus
0.75 V DD
VDD + 0.3
V
1
Input Mid Voltage
VIM
Single-ended tri-level inputs ('_tri' suffix, if present)
0.4 V DD
0.6 VDD
V
1
Input Low Voltage
Schmitt Trigger Positive
Going Threshold Voltage
Schmitt Trigger Negative
Going Threshold Voltage
Hysteresis Voltage
VIL
Single-ended inputs, except SMBus
-0.3
0.25 V DD
V
1
VT+
Single-ended inputs, where indicated
0.4 V DD
0.7 VDD
V
1
VT-
Single-ended inputs, where indicated
0.1 V DD
0.4 VDD
V
1
VH
VT+ - VT-
0.1 VDD
0.4 VDD
V
1
Output High Voltage
VIH
Single-ended outputs, except SMBus. IOH = -2mA
VDD -0.45
V
1
Output Low Voltage
VIL
Single-ended outputs, except SMBus. IOL = -2mA
0.45
V
1
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
-20
20
uA
1
27
7
MHz
nH
1
Input Current
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Fin
Pin Inductance
Lpin
Capacitance
XTAL, or X1 input
CIN
Logic Inputs, except DIF_IN
COUT
Output pin capacitance
23
25
1.5
1
5
pF
1
6
pF
1
0.6
1.8
ms
1,2
31
31.6
32
kHz
1
2
3
4
clocks
1,3
4
300
us
1,3
Tfall
tF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of single-ended control inputs
5
ns
1,2
Trise
tR
Rise time of single-ended control inputs
5
ns
1,2
SMBus Input Low Voltage
VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
0.8
V
1,4
3.6
V
1,5
0.4
V
1
mA
1
Clk Stabilization
TSTAB
SS Modulation Frequency
fMOD
OE# Latency
tLATOE#
Tdrive_PD#
t DRVPD
SMBus Input High Voltage
VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
SMBus Output Low Voltage
VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
2.1
4
Nominal Bus Voltage
VDDSMB
3.6
V
1
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1.7
1000
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
fMAXSMB
Maximum SMBus operating frequency
400
kHz
1
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are > 200mV.
4
For VDDSMB < 3.3V, VILSMB = 0.65VDDSMB.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
6
9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = TCOM or TIND; supply voltage per VDD of normal operation conditions; see Test Loads for loading conditions.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Scope averaging on 3.0V/ns setting.
Scope averaging on 2.0V/ns setting.
Single-ended measurement.
2.3
1.6
3.1
2.3
3
4
3.3
20
660
794
850
-150
21
150
816
-15
1551
397
15
1150
-300
300
300
Slew Rate
Trf
Slew Rate Matching
ΔTrf
Voltage High
VHIGH
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function (scope
averaging on).
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single-ended signal using
absolute value (scope averaging off).
Scope averaging off.
Scope averaging off.
Scope averaging off.
MAX UNITS NOTES
550
140
V/ns
V/ns
%
1, 2, 3
1, 2, 3
1, 4
1, 7
mV
1
1
1
1, 2
1, 5
1, 6
mV
mV
mV
mV
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform.
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL
PARAMETER
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
tjphPCIeG2-CC
PCIe Gen 2 High Band
Phase Jitter,
1.5MHz < f < Nyquist (50MHz)
PLL Mode
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
tjphPCIeG3-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
tjphPCIeG4-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
Notes on PCIe Filtered Phase Jitter Table
1
Applies to all differential outputs, guaranteed by design and characterization.
2
Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
tjphPCIeG1-CC
3
MIN
TYP
MAX
21
25
35
Specification
Limit
86
0.9
0.9
1.1
1.5
1.6
0.3
0.3
UNITS NOTES
ps (p-p)
1, 2, 3
3
ps
(rms)
1, 2
1.9
3.1
ps
(rms)
1, 2
0.37
0.44
1
0.37
0.44
0.5
ps
(rms)
ps
(rms)
1, 2
1, 2
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Electrical Characteristics–REF
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Long Accuracy
ppm
see Tperiod min-max values
0
Clock period
Tperiod
25 MHz output nominal
40
Rise/Fall Slew Rate
t rf1
Byte 3 = 1F, VOH = VDD-0.45V, VOL = 0.45V
0.6
1
Rise/Fall Slew Rate
t rf1
Byte 3 = 5F, VOH = VDD-0.45V, VOL = 0.45V
1.0
1.6
Rise/Fall Slew Rate
t rf1
Byte 3 = 9F, VOH = VDD-0.45V, VOL = 0.45V
1.3
2
Rise/Fall Slew Rate
t rf1
Byte 3 = DF, VOH = VDD-0.45V, VOL = 0.45V
1.4
2.1
Duty Cycle
dt1
VT = VDD/2 V
45
53.2
Duty Cycle Distortion
dtcd
VT = VDD/2 V
0
2
Jitter, cycle to cycle
tjcyc-cyc
VT = VDD/2 V
0
MAX
1.8
2.5
3.0
3.1
55
4
75
Noise floor
Noise floor
t jdBc1k
t jdBc10k
1kHz offset
10kHz offset to Nyquist
-130
-140
-105
-120
Jitter, phase
t jphREF
12kHz to 5MHz
0.68
1.5
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
Notes
1,2
1,2
1,3
1,3
1,3
1,3
1,4
1,5
1,4
dBc
dBc
ps
(rms)
1,4
1,4
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3
Typical value occurs when REF slew rate is set to default value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin. X2 should be floating in this case.
2
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
0 ppm
-c2c jitter
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
ns
1,2
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
0 ppm
-c2c jitter
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
ns
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
2
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
8
9FGV0441
JUNE 6, 2019
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Slave Address
Beginning Byte N
ACK
X Byte
O
O
O
Repeat starT
RD
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
O
O
O
O
O
Note: Read/Write address is latched on SADR pin.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
O
X Byte
P
Byte N + X - 1
N
Not acknowledge
P
stoP bit
9
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4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
SMBus Table: Output Enable Register
Byte 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
DIF OE3
Bit 3
DIF OE3
Bit 2
DIF OE2
Bit 1
DIF OE1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Output Enable
Output Enable
Output Enable
Output Enable
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Name
Control Function
SSENRB1
SS Enable Readback Bit1
Bit 7
SSENRB1
SS Enable Readback Bit0
Bit 6
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
SSENSW1
SS Enable Software Ctl Bit1
Bit 4
SSENSW0
SS Enable Software Ctl Bit0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 3
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF3
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF1
Bit 0
SMBus Table: REF Control Register
Byte 3
Name
Bit 7
REF
Bit 6
Bit 5
REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Control Function
Slew Rate Control
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Type
0
1
RW
RW
RW
RW
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Type
0
1
00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
R
RW
SS control locked
Values in B1[4:3]
control SS amount.
RW 1
RW 1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
RW
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
Type
0
1
RW
RW
RW
RW
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
Type
RW
RW
0
1
00 = Slowest
01 = Slow
10 = Fast
11 = Faster
REF does not run in REF runs in Power
RW
Power Down
Down
RW
Low
Enabled
Default
1
1
1
1
1
1
1
1
Default
Latch
Latch
0
0
0
1
1
0
Default
1
1
1
1
1
1
1
1
Default
0
1
0
1
1
1
1
1
Byte 4 is reserved and reads back 'hFF'.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
10
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4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
0
A rev = 0000
0001 = IDT
0
1
00 = FGV, 01 = DBV,
10 = DMV, 11= Reserved
000100 binary or 04 hex
Type
RW
RW
RW
RW
RW
1
0
1
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Default
0
0
0
0
0
0
0
1
Default
0
0
0
0
0
1
0
0
Default
0
0
0
0
1
0
0
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commercial)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
25
Fundamental
±20
MHz
PPM Max
1
1
1
±20
PPM Max
1
0~70
-40~85
50
7
8
0.3
±5
°C
°C
Ω Max
pF Max
pF Max
mW Max
PPM Max
1
2
1
1
1
1
1
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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Thermal Characteristics
PARAMETER
SYMBOL
Thermal Resistance
θJC
θJb
θJA0
θJA1
θJA3
θJA5
CONDITIONS
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NLG32
TYP.
42
2.4
39
33
28
27
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
1
1
1
1
1
1
1
ePad soldered to board
Marking Diagrams
ICS
V0441AIL
YYWW
COO
LOT
ICS
GV0441AL
YYWW
COO
LOT
Notes:
1. Line 2 is the truncated part number.
2. ‘L’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
5. ‘COO’ denotes country of origin.
6. ‘LOT’ is the lot number.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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Package Outline and Dimensions (NLG32P1)
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
13
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4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Package Outline and Dimensions (NLG32P1), cont.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
14
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4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Ordering Information
Part / Order Number Shipping Packaging
9FGV0441AKLF
Trays
9FGV0441AKLFT
Tape and Reel
9FGV0441AKILF
Trays
9FGV0441AKILFT
Tape and Reel
5x
5x
5x
5x
5 mm,
5 mm,
5 mm,
5 mm,
Package
0.5mm pitch 32-VFQFPN
0.5mm pitch 32-VFQFPN
0.5mm pitch 32-VFQFPN
0.5mm pitch 32-VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Issue Date
Description
October 18, 2016 Removed IDT crystal part number.
Updated front page general description to reflect the PCIe Gen4 updates.
June 22, 2017
Updated Electrical Characteristics - Filtered Phase Jitter Parameters - PCIe Common Clocked (CC)
Architectures and added PCIe Gen4 data.
October 11, 2017 Corrected typographical error in slew rate specifications of differential outputs.
June 6, 2019
Changed Input Current minimum and maximum values from -200/200uA to -20/20uA.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
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SYNTHESIZERS
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