9FGV0241AKLFT

DATASHEET 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Description Features/Benefits The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. • Integrated terminations provide 100 differential Zo; Recommended Application • PCIe Gen1-4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points • Output Features • • • • • 2 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF • • pairs with Zo = 100 1 – 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support • Key Specifications • • • • • DIF cycle-to-cycle jitter = 0.65VDDSMB. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 6 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Slew rate Trf Slew rate matching ΔTrf Voltage High V HIGH Voltage Low VLOW CONDITIONS MIN TYP Scope averaging on 3.0V/ns setting Scope averaging on 2.0V/ns setting Slew rate matching, Scope averaging on 2 1.5 3.1 2.3 3 4.3 3.5 20 Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) 660 794 850 -150 21 150 816 -15 1551 397 15 1150 -300 300 300 Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Measurement on single ended signal using Vmin absolute value. (Scope averaging off) Vswing Scope averaging off Vcross_abs Scope averaging off Scope averaging off Δ-Vcross 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform MAX UNITS NOTES 550 140 V/ns V/ns % 1, 2, 3 1, 2, 3 1,2,4 1,7 mV 1 1 1 1,2 1,5 1,6 mV mV mV mV 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions SYMBOL PARAMETER CONDITIONS t jphPCIeG1-CC PCIe Gen 1 PCIe Gen 2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) t jphPCIeG2-CC PCIe Gen 2 High Band Phase Jitter, 1.5MHz < f < Nyquist (50MHz) PLL Mode (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) PCIe Gen 3 t jphPCIeG3-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) PCIe Gen 4 t jphPCIeG4-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) Notes on PCIe Filtered Phase Jitter Tables 1 Applies to all differential outputs, guaranteed by design and characterization. 2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off. 3 Specification UNITS NOTES Limit 86 ps (p-p) 1, 2, 3 MIN TYP MAX 21 25 35 0.9 0.9 1.1 3 ps (rms) 1, 2 1.5 1.6 1.9 3.1 ps (rms) 1, 2 0.3 0.37 0.44 1 0.3 0.37 0.44 0.5 ps (rms) ps (rms) 1, 2 1, 2 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 7 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Electrical Characteristics–REF TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Long Accuracy ppm see Tperiod min-max values 0 Clock period Tperiod 25 MHz output nominal 40 Rise/Fall Slew Rate t rf1 Byte 3 = 1F, VOH = VDD-0.45V, VOL = 0.45V 0.5 1 Rise/Fall Slew Rate t rf1 Byte 3 = 5F, VOH = VDD-0.45V, VOL = 0.45V 0.5 1.6 Byte 3 = 9F, VOH = VDD-0.45V, VOL = 0.45V 0.5 2 Rise/Fall Slew Rate t rf1 Rise/Fall Slew Rate t rf1 Byte 3 = DF, VOH = VDD-0.45V, VOL = 0.45V 0.5 2.1 Duty Cycle dt1 VT = VDD/2 V 45 53.1 Duty Cycle Distortion dtcd VT = VDD/2 V 0 2 Jitter, cycle to cycle tjcyc-cyc VT = VDD/2 V 19 Noise floor t jdBc1k 1kHz offset -130 Noise floor t jdBc10k 10kHz offset to Nyquist -140 Jitter, phase t jphREF 12kHz to 5MHz 0.63 MAX 2.5 2.5 2.5 2.5 55 4 250 -105 -120 1.5 UNITS ppm ns V/ns V/ns V/ns V/ns % % ps dBc dBc ps (rms) Notes 1,2 1,2 1,3 1,3 1,3 1,3 1,4 1,5 1,4 1,4 1,4 1,4 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 3 Typical value occurs when REF slew rate is set to default value 4 When driven by a crystal. 5 When driven by an external oscillator via the X1 pin. X2 should be floating in this case. 2 Clock Periods–Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm 0 ppm -c2c jitter Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94900 9.99900 10.00000 10.00100 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.05100 ns 1,2 Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm 0 ppm -c2c jitter Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94906 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.10107 ns 1,2 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 2 IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 8 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR General SMBus Serial Interface Information How to Write How to Read • • • • • • • • • • • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR • • • Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite ACK WR WRite ACK Beginning Byte = N ACK Beginning Byte = N ACK Data Byte Count = X ACK RT Slave Address Beginning Byte N ACK X Byte O O O Repeat starT RD ReaD ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit O Note: Read/Write address is determined by SADR latch. O X Byte P O O O O Byte N + X - 1 IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR N Not acknowledge P stoP bit 9 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SMBus Table: Output Enable Register Byte 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DIF OE1 Bit 2 DIF OE0 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Output Enable Output Enable Reserved SMBus Table: SS Readback and Vhigh Control Register Byte 1 Name Control Function SSENRB1 SS Enable Readback Bit1 Bit 7 SSENRB1 SS Enable Readback Bit0 Bit 6 Bit 5 SSEN_SWCNTRL Enable SW control of SS SSENSW1 SS Enable Software Ctl Bit1 Bit 4 SSENSW0 SS Enable Software Ctl Bit0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 2 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 1 Reserved Bit 0 SMBus Table: REF Control Register Byte 3 Name Bit 7 REF Bit 6 Bit 5 REF Power Down Function Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REF OE Control Function Slew Rate Control Wake-on-Lan Enable for REF REF Output Enable Reserved Reserved Reserved Reserved Type 0 1 RW RW Low/Low Low/Low Enabled Enabled Type 0 1 00' for SS_EN_tri = 0, '01' for SS_EN_tri R = 'M', '11 for SS_EN_tri = '1' R RW SS control locked Values in B1[4:3] control SS amount. RW 1 RW 1 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS RW RW 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V Type 0 1 RW RW 2.0V/ns 2.0V/ns 3.0V/ns 3.0V/ns Type RW RW 0 1 00 = Slowest 01 = Slow 10 = Fast 11 = Faster REF does not run in REF runs in Power RW Power Down Down RW Low Enabled Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 0 1 0 1 1 1 1 1 Byte 4 is reserved and reads back 'hFF'. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 10 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 0 A rev = 0000 0001 = IDT 0 1 00 = FGV, 01 = DBV, 10 = DMV, 11= Reserved 00010 binary or 02 hex Type RW RW RW RW RW 1 0 1 Writing to this register will configure how many bytes will be read back, default is = 8 bytes. Default 0 0 0 0 0 0 0 1 Default 0 0 0 0 0 0 1 0 Default 0 0 0 0 1 0 0 0 Recommended Crystal Characteristics (3225 package) PARAMETER VALUE UNITS NOTES Frequency Resonance Mode Frequency Tolerance @ 25°C Frequency Stability, ref @ 25°C Over Operating Temperature Range Temperature Range (commercial) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year Notes: 1. FOX 603-25-150. 2. For I-temp, FOX 603-25-261. 25 Fundamental ±20 MHz PPM Max 1 1 1 ±20 PPM Max 1 0~70 -40~85 50 7 8 0.3 ±5 °C °C Ω Max pF Max pF Max mW Max PPM Max 1 2 1 1 1 1 1 IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 11 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Thermal Characteristics PARAMETER SYMBOL CONDITIONS Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow Junction to Air, 5 m/s air flow TYP UNITS NOTES VALUE 62 °C/W 1 C/W 5.4 ° 1 50 °C/W 1 NLG20 NLG24 43 °C/W 1 39 °C/W 1 38 °C/W 1 PKG 1 ePad soldered to board Marking Diagrams LOT 241AL YYWW LOT 241AIL YYWW Notes: 1. ‘LOT’ is the lot number. 2. ‘YYWW’ is the last two digits of the year and week that the part was assembled. 3. ‘L’ denotes RoHS compliant package. 4. ‘I’ denotes industrial temperature grade. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 12 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Package Outline and Dimensions (NLG24) IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 13 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Package Outline and Dimensions (NLG24), cont. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 14 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Ordering Information Part / Order Number Shipping Packaging 9FGV0241AKLF Tubes 9FGV0241AKLFT Tape and Reel 9FGV0241AKILF Tubes 9FGV0241AKILFT Tape and Reel Package 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). Revision History Issue Date February 3, 2015 November 30, 2015 January 4, 2016 October 18, 2016 June 19, 2017 June 6, 2019 Description Updated IDDAOP and IDDOP typ and max specs per latest characterization review. Updated block diagram Corrected typo in ordering information; changed rev "B" to rev "A" Removed IDT crystal part number Updated front page Gendes to reflect the PCIe Gen4 updates. Updated Electrical Characteristics - Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data Updated Input Current minimum and maximum values from -200/200 uA to -20/20 uA. IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 15 9FGV0241 JUNE 6, 2019 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 www.idt.com/go/sales www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com DDISCLAIMER Integrated Device Technology, Inc. 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