9P935AFLF

DATASHEET ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Pin Configuration DDR I/DDR II Zero Delay Clock Buffer DDRC0 DDRT0 VDD2.5/1.8 DDRT1 DDRC1 GND VDDA2.5/1.8 GND CLK_INT CLK_INC VDD2.5/1.8 DDRT2 DDRC2 GND Output Features • • • • • • • • Low skew, low jitter PLL clock driver Max frequency supported = 400MHz (DDRII 800) I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Programmable skew through SMBus Frequency defect control thorugh SMBus Individual output control programmable through SMBus Key Specifications • • • • • • CYCLE - CYCLE jitter: