2:12 DB1200ZL Derivative for
PCIe Gen1–4 and UPI
9ZML1232E/9ZML1252E
Datasheet
Description
Features
The 9ZML1232E/9ZML1252E are a second generation
2-input/12-output differential mux for Intel Purley and newer
platforms. It exceeds the demanding DB1200ZL performance
specifications and is backwards compatible to the 9ZML1232B. It
utilizes Low-Power HCSL-compatible outputs to reduce power
consumption and termination resistors. It is suitable for
PCI-Express Gen1–4 or QPI/UPI applications, and provides 2
configurable low-drift I2O settings, one for each input channel, to
allow I2O tuning for various topologies.
▪ 2 configurable low drift I2O delays up to 2.9ns; maintain
transport delay for various topologies
▪ LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)
▪ LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
(9ZML1252E)
▪ 9 selectable SMBus addresses; multiple devices can share
same SMBus segment
▪ Separate VDDIO for outputs; allows maximum power savings
▪ PLL or Bypass Mode; PLL can dejitter incoming clock
▪ Hardware or software-selectable PLL BW; minimizes jitter
PCIe Clocking Architectures
peaking in downstream PLLs
▪ Common Clocked (CC)
▪ Separate Reference No Spread (SRNS)
▪ Separate Reference Independent Spread (SRIS)
▪ Spread spectrum compatible; tracks spreading input clock for
EMI reduction
▪ SMBus interface; software can modify device settings without
hardware changes
Typical Applications
▪ 10 × 10 mm 72-VFQFPN package; small board footprint
Servers, Storage, Networking, SSDs
Key Specifications
Output Features
▪
▪
▪
▪
▪
▪
▪ 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)
▪ 12 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout
(9ZML1252E)
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI > 9.6GB/s < 0.1ps rms
Block Diagram
I2O
Delay
^SEL_A_B#
DIF_INA
Low Phase
Noise Z-PLL
(SSCompatible)
12
outputs
CONTROL
^vHIBW_BYPM
_LOBW#
©2021 Renesas Electronics Corporation
DIF_11
Bypass path
DIF_INB
CKPWRGD_PD#
vSMB_A0_tri
vSMB_A1_tri
SMBDAT
SMBCLK
^OE(11:0)#
FBOUT_NC
DIF_0
NOTE: Internal series resistors are
only present on the 9ZML1252
1
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PLL Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power Connections (for pin compatibility with 9ZML12xxB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Skew Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DIF_IN Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Input/Supply/Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DIF HCSL/LP-HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Skew and Differential Jitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Filtered Phase Jitter Parameters - PCIe Separate Reference Independent Spread (SRIS) Architectures . . . . . . . . . . . . . . . . . . . . . . . . 11
Filtered Phase Jitter Parameters - QPI/UPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unfiltered Phase Jitter Parameters - 12kHz to 20MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock Periods–Differential Outputs with Spread Spectrum Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock Periods–Differential Outputs with Spread Spectrum Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
©2021 Renesas Electronics Corporation
2
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
^OE8#
^OE9#
NC
GND
DIF_8
DIF_8#
DIF_9
DIF_9#
GND
VDD
DIF_10
DIF_10#
DIF_11
DIF_11#
NC
GND
^OE10#
^OE11#
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
54 ^OE7#
53 ^OE6#
VDDA 1
GNDA 2
52 VDDIO
51 GND
50 DIF_7#
^SEL_A_B# 3
^vHIBW_BYPM_LOBW# 4
CKPWRGD_PD# 5
49 DIF_7
48 DIF_6#
DIF_INB 6
DIF_INB# 7
GND 8
47 DIF_6
46 GND
9ZML1232E
9ZML1252E
connect epad to GND
VDDR 9
DIF_INA 10
DIF_INA# 11
45 VDD
44 DIF_5#
43 DIF_5
42 DIF_4#
vSADR0_tri 12
SMBDAT 13
41 DIF_4
40 VDDIO
SMBCLK 14
vSADR1_tri 15
39 GND
38 ^OE5#
NC 16
FBOUT_NC# 17
37 ^OE4#
FBOUT_NC 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
^OE3#
^OE2#
GND
NC
DIF_3#
DIF_3
DIF_2#
DIF_2
VDD
GND
DIF_1#
DIF_1
DIF_0#
DIF_0
GND
NC
^OE1#
^OE0#
^ prefix indicates internal 120Kohm Pull Up
v prefix indicates internal 120Kohm Pull down
10mm x 10mm 72-VFQFPN 0.5mm pin pitch
Power Management
Inputs
CKPWRGD_PD#
0
DIF_IN
X
1
Running
Outputs
Control Bits
SMBus
PLL State
EN bit
DIF_x
FBOUT_NC
X
Low/Low
Low/Low
OFF
0
Low/Low
Running
ON
1
Running
Running
ON
Power Connections
PLL Operating Mode
HIBW_BYPM_LOBW#
Low ( PLL Low BW)
Mid (Bypass)
High (PLL High BW)
Byte0[7:6]
00
01
11
Pin Number
VDDIO
VDD
1
9
NOTE: PLL is off in Bypass mode
28, 45, 64
Power Connections (for pin
compatibility with 9ZML12xxB)
VDD
1
9
28, 45, 64
Pin Number
VDDIO
21, 33, 40,
52, 57, 69
GND
2
8
16, 22, 27,
34, 39, 46,
51, 58, 63,
70
©2021 Renesas Electronics Corporation
40, 52
GND
2
8
22, 27, 34,
39, 46, 51,
58, 63, 70
Description
Analog PLL
Analog Input
DIF clocks
Skew Programming
Description
Skew[2:0]
000
001
010
011
100
101
110
111
Analog PLL
Analog Input
DIF clocks
3
Skew Steps
0
1
2
3
4
5
6
7
Skew
(ps)
0
-416.67
-833.33
-1250.00
-1666.67
-2083.33
-2500.00
-2916.67
DIF_INx
tSKEW_PLL
DIF_n
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Pin Descriptions
PIN #
1
2
PIN NAME
VDDA
GNDA
PIN TYPE
PWR
GND
3
^SEL_A_B#
IN
4
^vHIBW_BYPM_LOBW#
5
CKPWRGD_PD#
6
7
8
DIF_INB
DIF_INB#
GND
IN
IN
GND
9
VDDR
PWR
LATCHE
D IN
IN
10
11
DIF_INA
DIF_INA#
IN
IN
12
vSADR0_tri
IN
13
14
SMBDAT
SMBCLK
I/O
IN
15
vSADR1_tri
IN
16
NC
N/A
17
FBOUT_NC#
OUT
18
FBOUT_NC
OUT
19
^OE0#
IN
20
^OE1#
IN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
GND
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
NC
GND
N/A
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
N/A
GND
35
^OE2#
IN
©2021 Renesas Electronics Corporation
DESCRIPTION
Power supply for PLL core.
Ground pin for the PLL core.
Input to select differential input clock A or differential input clock B. This input has
an internal pull-up resistor.
0 = Input B selected, 1 = Input A selected.
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to
VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL
Operating Mode Table for Details.
3.3V input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
True input of differential clock
Complement input of differential clock
Ground pin.
Power supply for differential input clock (receiver). This VDD should be treated
as an analog power rail and filtered appropriately. Nominally 3.3V.
True input of differential clock
Complement input of differential clock
SMBus address bit. This is a tri-level input that works in conjunction with other
SADR pins, if present, to decode SMBus Addresses. It has an internal pull down
resistor. See the SMBus Address Selection Table.
Data pin of SMBUS circuitry
Clock pin of SMBUS circuitry
SMBus address bit. This is a tri-level input that works in conjunction with other
SADR pins, if present, to decode SMBus Addresses. It has an internal pull down
resistor. See the SMBus Address Selection Table.
No connection.
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 propagation delay.
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
Active low input for enabling output 0. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 1. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
No connection.
Ground pin.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
Ground pin.
Power supply, nominally 3.3V.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
No connection.
Ground pin.
Active low input for enabling output 2. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
4
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
Active low input for enabling output 3. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 4. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 5. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Ground pin.
Power supply for differential outputs.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
Power supply, nominally 3.3V.
Ground pin.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
Ground pin.
Power supply for differential outputs.
Active low input for enabling output 6. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 7. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 8. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 9. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
No connection.
Ground pin.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
Ground pin.
Power supply, nominally 3.3V.
HCSL true clock output.
HCSL complementary clock output.
HCSL true clock output.
HCSL complementary clock output.
No connection.
Ground pin.
36
^OE3#
IN
37
^OE4#
IN
38
^OE5#
IN
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND
VDDIO
DIF_4
DIF_4#
DIF_5
DIF_5#
VDD
GND
DIF_6
DIF_6#
DIF_7
DIF_7#
GND
VDDIO
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
53
^OE6#
IN
54
^OE7#
IN
55
^OE8#
IN
56
^OE9#
IN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
NC
GND
DIF_8
DIF_8#
DIF_9
DIF_9#
GND
VDD
DIF_10
DIF_10#
DIF_11
DIF_11#
NC
GND
N/A
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
N/A
GND
71
^OE10#
IN
Active low input for enabling output 10. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
72
^OE11#
IN
Active low input for enabling output 11. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
73
epad
©2021 Renesas Electronics Corporation
GND
Connect to ground
5
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZML1232E/9ZML1252E. These ratings, which are
standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
SYMBOL
VDDx
VIL
VIH
V IHSMB
Storage Temperature
Junction Temperature
Ts
Tj
Input ESD protection
ESD prot
CONDITIONS
MIN
TYP
MAX
3.9
GND-0.5
Except for SMBus interface
SMBus clock and data pins
V DD+0.5
3.9
-65
Human Body Model
150
125
2000
UNITS NOTES
V
1,2
V
1
V
1,3
V
1
°
1
C
°C
1
V
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 3.9V.
2
Electrical Characteristics
DIF_IN Clock Input Parameters
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Input Crossover Voltage
V CROSS
Cross Over Voltage
150
900
UNITS NOTES
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
VSWING
dv/dt
I IN
dtin
Differential value
Measured differentially
VIN = V DD , V IN = GND
Measurement from differential waveform
300
0.35
-5
45
8
5
55
mV
V/ns
uA
%
1
1,2
Input Jitter - Cycle to Cycle
J DIFIn
Differential Measurement
0
125
ps
1
1
2
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
SMBus
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
SMBus Input Low Voltage
VILSMB
SMBus Input High Voltage
V IHSMB
SMBus Output Low Voltage VOLSMB
SMBus Sink Current
I PULLUP
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
t RSMB
SCLK/SDATA Fall Time
t FSMB
SMBus Operating
f MAXSMB
Frequency
CONDITIONS
2.1
@ I PULLUP
@ V OL
MAX
0.8
VDDSMB
0.4
3.6
1000
300
Maximum SMBus operating frequency
400
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
DIF_IN input
5
4
2.7
TYP
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
1
4
MIN
UNITS NOTES
V
V
V
mA
V
1
ns
1
ns
1
kHz
5
The differential input clock must be running for the SMBus to be active
©2021 Renesas Electronics Corporation
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R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Input/Supply/Common Parameters
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDDx
Supply voltage for core and analog
3.135
3.3
3.465
V
VDDIO
Supply voltage for differential outputs
3.135
3.3
3.465
V
Ambient Operating
Temperature
TAMB
Industrial range
-40
85
°C
Input High Voltage
VIH
2
VDD + 0.3
V
Input Low Voltage
VIL
GND - 0.3
0.8
V
Input High Voltage
VIH
Single-ended inputs, except SMBus, tri-level
inputs
Single-ended inputs, except SMBus, tri-level
inputs
Tri-Level Inputs (_tri suffix)
2.2
VDD + 0.3
V
Input Mid Voltage
VIL
Tri-Level Inputs (_tri suffix)
1.2
1.8
V
Input Low Voltage
VIL
Tri-Level Inputs (_tri suffix)
GND - 0.3
0.8
V
I IN
Single-ended inputs, V IN = GND, VIN = VDD
-5
5
uA
I INP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
V IN = VDD; Inputs with internal pull-down resistors
-100
100
uA
400
MHz
102
MHz
5
7
nH
1
Supply Voltage
Input Current
Input Frequency
Pin Inductance
Fibyp
VDD = 3.3 V, Bypass mode
1
Fipll
VDD = 3.3 V, 100MHz PLL mode
98.5
100.00
Lpin
CIN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.2
1.8
ms
1,2
Input SS Modulation
Frequency PCIe
f MODINPCIe
30
31.6
33
kHz
OE# Latency
tLATOE#
4
5
10
clocks
1,2,3
Tdrive_PD#
t DRVPD
85
300
us
1,3
5
ns
2
5
ns
2
Capacitance
Tfall
tF
Allowable Frequency for PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Trise
tR
Rise time of control inputs
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV, PLL mode.
4
DIF_IN input
5
VDD/2
UNITS NOTES
This parameter reflects the operating range after locking to a 100MHz input.
©2021 Renesas Electronics Corporation
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R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
DIF HCSL/LP-HCSL Outputs
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
INDUSTRY
UNITS NOTES
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
LIMIT
V/ns
Slew rate
dV/dt
Scope averaging on
2.0
2.8
4.0
0.6 - 4.0
1,2,3
%
Slew rate matching
Slew rate matching, Scope averaging on
4
15
20
1,2,4,7
ΔdV/dt
Max Voltage
Vmax
660
794
870
1150
7,8
Measurement on single ended signal using
mV
Min Voltage
Vmin
-111
-49
-300
7,8
absolute value. (Scope averaging off)
1
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
302
367
453
250 - 550
mV
1,5,7
32
74
140
mV
1,6,7
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)
allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
8
If driving a receiver with input terminations, the Vmax and Vmin values will be halved.
Current Consumption
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
I DDx
Operating Supply Current
Powerdown Current
1.
I DDA+R
CONDITIONS
All other VDD pins, All outputs @100MHz, CL =
2pF; Zo=85Ω
VDDA+VDDR pins, All outputs @100MHz, CL =
2pF; Zo=85Ω
MIN
TYP
MAX
UNITS NOTES
22
30
mA
2
56
65
mA
1,2
I DDO
VDDIO pins, All outputs @100MHz, CL = 2pF;
Zo=85Ω
84
100
mA
2
I DDx
I DDA+R
I DDO
All other VDD pins, all outputs Low/Low
VDDA+VDDR pins, all outputs Low/Low
VDDIO pins, all outputs Low/Low
0.9
4.3
0.1
2
6
0.2
mA
mA
mA
1,2
1,2
1,2
Includes VDDR if applicable
©2021 Renesas Electronics Corporation
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R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Skew and Differential Jitter Parameters
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CLK_IN, DIF[x:0]
t SKEW_PLL
CLK_IN, DIF[x:0]
t PD_BYP
CLK_IN, DIF[x:0]
t DSPO_PLL
CLK_IN, DIF[x:0]
t DSPO_BYP
DIF[x:0]
t SKEW_ALL
PLL Jitter Peaking
PLL Jitter Peaking
j peak-hibw
j peak-lobw
PLL Bandwidth
PLL Bandwidth
Duty Cycle
Duty Cycle Distortion
pllHIBW
pllLOBW
tDC
t DCD
Jitter, Cycle to cycle
t jcyc-cyc
CONDITIONS
Input-to-Output Skew in PLL mode
@100MHz, nominal temperature and voltage
Input-to-Output Skew in Bypass mode
@100MHz, nominal temperature and voltage
Input-to-Output Skew Variation in PLL mode
@100MHz, across voltage and temperature
Input-to-Output Skew Variation in Bypass mode
@100MHz, across voltage and temperature,
TAMB = 0C to 70C, default slew rate
Input-to-Output Skew Variation in Bypass mode
@100MHz, across voltage and temperature,
TAMB = -40C to 85C, default slew rate
Output-to-Output Skew across all outputs,
common to PLL and Bypass mode, @100MHz,
default slew rate
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode @100MHz
PLL mode
Additive Jitter in Bypass Mode
MIN
TYP
MAX
UNITS NOTES
-100
-4
100
ps
1,2,4,5,6,
8
2.2
2.9
3.6
ns
1,2,3,8
-50
0.0
50
ps
1,2,3,8
-250
0.0
250
ps
1,2,3,8
-350
0.0
350
ps
1,2,3,8
30
50
ps
1,2,3,8
0
0
1.3
1.3
2.5
2
dB
dB
7,8
7,8
2
0.7
45
-1
2.6
1.0
50
-0.2
13
4
1.4
55
0
50
MHz
MHz
%
%
ps
8,9
8,9
1
1,10
1,11
0.2
5
ps
1,11
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
4
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
This parameter is deterministic for a given device
5
Measured with scope averaging on to find mean value.
6.
This value is programmable, see I2O Programming Table.
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform.
©2021 Renesas Electronics Corporation
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R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
LIMIT
PCIe Gen 1
13
30
86
tjphPCIeG1-CC
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.3
0.7
3
(PLL BW of 5-16MHz or 8-5MHz,
CDR = 5MHz)
tjphPCIeG2-CC
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
Phase Jitter,
1.6
3.1
1.0
(PLL BW of 5-16MHz or 8-5MHz,
PLL Mode
CDR = 5MHz)
PCIe Gen 3
0.35
1
(PLL BW of 2-4MHz or 2-5MHz,
0.24
tjphPCIeG3-CC
CDR = 10MHz)
PCIe Gen 4
0.30
0.5
(PLL BW of 2-4MHz or 2-5MHz,
0.24
tjphPCIeG4-CC
CDR = 10MHz)
tjphPCIeG1-CC
PCIe Gen 1
0.01
0.05
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.01
0.05
(PLL BW of 5-16MHz or 8-5MHz,
CDR = 5MHz)
tjphPCIeG2-CC
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
Additive Phase Jitter,
0.000
0.05
n/a
(PLL BW of 5-16MHz or 8-5MHz,
Bypass mode
CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz,
0.01
0.05
tjphPCIeG3-CC
CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz,
0.01
0.05
tjphPCIeG4-CC
CDR = 10MHz)
1
Applies to all outputs, when driven by 9SQL4958 or equivalent.
2
Based on PCIe Base Specification Rev4.0 version 0.7 draft. See http://www.pcisig.com for latest specifications.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
UNITS
Notes
ps (p-p)
1,2,3
ps
(rms)
1,2
ps
(rms)
1,2
ps
(rms)
1,2
ps
(rms)
1,2
ps (p-p)
1,2
ps
(rms)
1,2,4
ps
(rms)
1,2,4
ps
(rms)
1,2,4
ps
(rms)
1,2,4
4
For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2 ] where "a" is rms input jitter and "c" is rms
total jitter.
©2021 Renesas Electronics Corporation
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R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Filtered Phase Jitter Parameters - PCIe Separate Reference Independent
Spread (SRIS) Architectures
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
LIMIT
tjphPCIeG1n/a
PCIe Gen 1
n/a
UNITS
Notes
ps (p-p)
1,2,3
SRIS
tjphPCIeG2Phase Jitter, PLL
Mode
SRIS
tjphPCIeG3SRIS
tjphPCIeG4SRIS
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz,
CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz,
CDR = 10MHz)
tjphPCIeG1-
0.8
1.2
2
ps
(rms)
1,2
0.6
0.68
0.7
ps
(rms)
1,2
n/a
ps
(rms)
1,2
ps (p-p)
1,2,5
ps
(rms)
1,2,4
ps
(rms)
1,2,4
ps
(rms)
1,2,4,5
n/a
n/a
PCIe Gen 1
SRIS
tjphPCIeG2Additive Phase Jitter,
Bypass mode
SRIS
tjphPCIeG3SRIS
tjphPCIeG4SRIS
1
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz,
CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz,
CDR = 10MHz)
0.0
0.02
0.0
0.02
n/a
n/a
Applies to all outputs, when driven by 9SQL4958 or equivalent
2
Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest
specifications. 0.7ps is the Intel specified limit, which may differ from the PCI SIG limit.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
4
For RMS values, additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2 ] where "a" is rms input jitter and "c" is rms
total jitter.
5
SRIS is not currently defined for PCIe Gen1 and Gen4.
Filtered Phase Jitter Parameters - QPI/UPI
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
IND.LIMIT
QPI & SMI
0.15
0.3
0.5
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
Phase Jitter, PLL
0.08
0.1
0.3
t jphQPI_UPI
(100MHz, 8.0Gb/s, 12UI)
Mode
QPI & SMI
0.07
0.1
0.2
(100MHz, 9.6Gb/s, 12UI)
QPI & SMI
0.00
0.05
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)
Additive Phase
QPI & SMI
n/a
t jphQPI_UPI
0.02
0.09
Jitter, Bypass mode
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
0.02
0.08
(100MHz, ? 9.6Gb/s, 12UI)
1
Applies to all outputs, when driven by 9SQL4958 or equivalent
2
Calculated from Intel-supplied Clock Jitter Tool
UNITS
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2
1,2
1,2
1,2,3
1,2,3
1,2,3
3
For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2 ] where "a" is rms input jitter and "c" is rms
total jitter.
©2021 Renesas Electronics Corporation
11
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Unfiltered Phase Jitter Parameters - 12kHz to 20MHz
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
IND.LIMIT
Phase Jitter, PLL
PLL High BW, SSC OFF, 100MHz
171
250
n/a
t jph12k-20MHi
Mode
Phase Jitter, PLL
PLL Low BW, SSC OFF, 100MHz
183
250
n/a
t jph12k-20MLo
Mode
Additive Phase
t
Bypass Mode, SSC OFF, 100MHz
109
150
n/a
Jitter, Bypass mode jph12k-20MByp
1
Applies to all outputs. Wenzel clock source.
2
12kHz to 20MHz brick wall filter.
UNITS
fs
(rms)
fs
(rms)
fs
(rms)
Notes
1,2
1,2
1,2,3
3
For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2 ] where "a" is rms input jitter and "c" is rms
total jitter.
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
1 Clock
1us
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94900
9.99900
Measurement Window
0.1s
0.1s
+ ppm
0 ppm
Long-Term
Period
Average
Nominal
Max
10.00000
10.00100
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
10.05100
Units Notes
ns
1,2,3
Clock Periods–Differential Outputs with Spread Spectrum Enabled
SSC ON
DIF
Notes:
1
Center
Freq.
MHz
99.75
1 Clock
1us
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94906
9.99906
10.02406
Measurement Window
0.1s
0.1s
+ ppm
0 ppm
Long-Term
Period
Average
Nominal
Max
10.02506
10.02607
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter
AbsPer
Max
10.10107
Units Notes
ns
1,2,3
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy
requirements (+/-100ppm). The 9ZML12xx does not contribute to ppm error.
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
Test Loads
9ZML Differential Test Loads
Zo = 85 Dif.,
10 inches
Rs
2pF
Rs
LP-HCSL
Differential
Output
2pF
Differential Output Terminations*
Device
DIF Zo (Ω) Rs (Ω)
9ZML123x
85
27
9ZML123x
100
33
9ZML125x
85
Internal
9ZML125x
100
7.5
*Contact factory for versions of this device with Zo=100Ω
Rs are external on 9ZML123x devices
and internal on 9ZML125x devices
©2021 Renesas Electronics Corporation
12
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
General SMBus Serial Interface Information
How to Write
How to Read
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Controller (host) sends a start bit
Controller (host) sends the write address
Renesas clock will acknowledge
Controller (host) sends the beginning byte location = N
Renesas clock will acknowledge
Controller (host) sends the byte count = X
Renesas clock will acknowledge
Controller (host) starts sending Byte N through Byte N+X-1
Renesas clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Renesas (Slave/Receiver)
Controller (host) will send a start bit
Controller (host) sends the write address
Renesas clock will acknowledge
Controller (host) sends the beginning byte location = N
Renesas clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
Renesas clock will acknowledge
Renesas clock will send the data byte count = X
Renesas clock sends Byte N+X-1
Renesas clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
▪ Controller (host) will need to acknowledge each byte
▪ Controller (host) will send a not acknowledge bit
▪ Controller (host) will send a stop bit
starT bit
Slave Address
WR
WRite
ACK
Index Block Read Operation
Beginning Byte = N
T
starT bit
Slave Address
WR
WRite
Data Byte Count = X
ACK
Beginning Byte N
ACK
ACK
X Byte
O
O
O
Renesas
Controller (Host)
ACK
Beginning Byte = N
ACK
O
O
O
RT
Repeat starT
Slave Address
RD
ReaD
Byte N + X - 1
ACK
ACK
stoP bit
Data Byte Count=X
ACK
9ZML1232E/9ZML1252E SMBus Addressing
SMB_A(1:0)_tri
00
0M
01
M0
MM
M1
10
1M
11
Beginning Byte N
ACK
SMBus Address (Rd/Wrt bit = 0)
D8
DA
DE
C2
C4
C6
CA
CC
CE
©2021 Renesas Electronics Corporation
O
O
O
X Byte
P
O
O
O
Byte N + X - 1
N
P
13
Not acknowledge
stoP bit
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0
Pin #
Name
Control Function
PLL Mode bit [1]
PLL Operating Mode Rd back 1
Bit 7
PLL Mode bit [0]
PLL Operating Mode Rd back 0
Bit 6
SEL_A_B#
Input Select Readback
Bit 5
Reserved
Bit 4
Enable S/W control of PLL BW and
PLL_InSEL_SW_EN
Bit 3
Input select
PLL Mode bit [1]
PLL Operating Mode 1
Bit 2
PLL Mode bit [0]
PLL Operating Mode 1
Bit 1
Bit 0
SEL_A_B#
Input Select Status or Control
Type
R
R
R
RW
RW
RW
RW
0
1
See PLL Operating Mode
Readback Table
DIF_INB
DIF_INA
Pin Control
SMBus Control
See PLL Operating Mode
Readback Table1
DIF_INB
DIF_INA
Default
Latch
Latch
Pin
0
0
1
1
1
Note: Setting bit 3 to '1' allows the user to override the latch value from pin 5 via use of bits 2 and 1. The system may require a warm
system reset if the user changes these bits. The clock itself does not require a reset. Setting bit 3 to a '1' also allows the user to use bit 0
to control the input select.
SMBusTable: Output Disable Register
Byte 1
Pin #
Name
DIF_7_En
Bit 7
DIF_6_En
Bit 6
DIF_5_En
Bit 5
DIF_4_En
Bit 4
DIF_3_En
Bit 3
DIF_2_En
Bit 2
DIF_1_En
Bit 1
DIF_0_En
Bit 0
Output
Output
Output
Output
Output
Output
Output
Output
Control Function
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Control overrides OE# pin
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBusTable: Output Disable Register
Byte 2
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
DIF_11_En
Bit 3
DIF_10_En
Bit 2
DIF_9_En
Bit 1
DIF_8_En
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
SMBusTable: Reserved Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Reserved Register
Byte 4
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
©2021 Renesas Electronics Corporation
0
1
Low/Low
Pin Control
Type
0
1
RW
RW
RW
RW
Low/Low
Pin Control
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
14
Default
1
1
1
1
1
1
1
1
Default
0
0
0
0
1
1
1
1
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
SMBusTable: Vendor & Revision ID Register
Byte 5
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBusTable: DEVICE ID
Pin #
Name
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Byte Count Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Control Function
Reserved
Reserved
Reserved
Writing to this register configures how
many bytes will be read back.
SMBusTable:Output Skew RegisterA (when Input Clock A is selected)
Pin #
Name
Control Function
Byte 8
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
I2O_FB_ASkew2
Bit 2
Channel A Output delay programming
I2O_FB_ASkew1
Bit 1
(early)
I2O_FB_ASkew0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
-
Type
R
R
R
R
R
R
R
R
0
1
Type
0
RW
RW
RW
RW
RW
Type
RW
RW
1
E rev = 0100
9ZML1232=EC
9ZML1233=ED
9ZML1252=FC
9ZML1253=FD
1
Default value is 8 hex, so 9
bytes (0 to 8) will be read back
by default.
0
Default
0
1
0
0
0
0
0
1
Default
1
1
1
X
1
1
0
X
Default
0
0
0
0
1
0
0
0
1
Default
0
0
0
0
0
0
Binary value of number of VCO
0
periods that outputs will be
pulled earlier than input.
0
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will
pull the output a early by that number of VCO periods. Writing '110' 4 times would pull the output back in phase with the input. Writing '001'
twice will accomplish the same result as writing '010' once - pulling the output 2 VCO periods earlier.
SMBusTable:Output Skew RegisterA (when Input Clock B is selected)
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Type
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
I2O_FB_BSkew2
I2O_FB_BSkew1
I2O_FB_BSkew0
Channel B Output delay programming
(early)
RW
RW
RW
Binary value of number of VCO
periods that outputs will be
earlier than input. Default is 0.
Default
0
0
0
0
0
0
0
0
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will
pull the output a early by that number of VCO periods. Writing '110' 4 times would pull the output back in phase with the input. Writing '001'
twice will accomplish the same result as writing '010' once - pulling the output 2 VCO periods earlier.
©2021 Renesas Electronics Corporation
15
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering
Information for POD links). The package information is the most current data available and is subject to change without revision of this
document.
Ordering Information
Orderable Part Number
Package
9ZML1232EKILF
9ZML1232EKILFT
9ZML1252EKILF
10.0 10.0 0.90 mm, 72-VFQFPN
9ZML1252EKILFT
Carrier Type
Temperature
Tray
-40° to +85°C
Tape and Reel
-40° to +85°C
Tray
-40° to +85°C
Tape and Reel
-40° to +85°C
“LF” designates PB-free configuration, RoHS compliant.
“E” is the device revision designator (will not correlate with the datasheet revision).
Marking Diagrams
▪ Line 2: part number.
▪ Line 3: “LOT” denotes the lot number.
▪ Line 4: “COO” denotes country of origin; “YYWW” denotes the last two digits of the year and
work week the part was assembled.
©2021 Renesas Electronics Corporation
16
R31DS0025EU0500 May 12, 2021
9ZML1232E/9ZML1252E Datasheet
Revision History
Revision Date
Description of Change
May 12, 2021
Updates to Byte 0, bit 0 and bit 5 defaults.
May 3, 2021
▪
▪
▪
▪
April 19, 2017
Added missing Byte 0, bit 0. Updated Byte 0 footnote.
Updated Package Outline Drawings section.
Updated Marking Diagrams section.
Updated Ordering Information table.
▪ Update Features and Key Specifications.
▪ Updated PCIe Common Clocked, PCIe Separate Clocked, and QPI/UPI to latest format, added IF-UPI spec
to QPI/UPI tables.
▪ Updated Test Loads drawing to latest version.
April 17, 2017
January 31, 2017
▪ Reverted back to original Device ID Scheme, byte 6 updated accordingly:
•
•
▪
▪
▪
▪
9ZML1232 = EC
9ZML1252 = FC
Finalized electrical tables.
Removed Byte 0, bit 0 from SMBus - only Hardware can select A or B input.
Added notes about functionality of Byte 0 [2:1].
Move to final.
©2021 Renesas Electronics Corporation
17
R31DS0025EU0500 May 12, 2021
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.95 x 5.95 mm 0.50mm Pitch
NLG72P1, PSC-4208-01, Rev 03, Page 1
© Integrated Device Technology, Inc.
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.95 x 5.95 mm 0.50mm Pitch
NLG72P1, PSC-4208-01, Rev 03, Page 2
Package Revision History
Date Created
© Integrated Device Technology, Inc.
Rev No.
Description
Sept 3, 2019
Rev 03
Update P1 Dimension from 5. 8 to 5.95 mm SQ
May 8, 2017
Rev 02
Change Package Code QFN to VFQFPN
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