DATASHEET
EL7554
FN7360
Rev 5.00
November 5, 2007
Monolithic 4A DC/DC Step-Down Regulator
The EL7554 is a full-feature synchronous 4A step-down
regulator capable of up to 96% efficiency. This device
operates from 3V to 6V VIN input supply. With internal CMOS
power FETs, the device can operate at up to 100% duty ratio,
allowing for output voltage range from 0.8V up to nearly
VIN.The adjustable high switching frequency of up to 1MHz
enables the use of small components, making the whole
converter occupy less than 0.58 square inch with components
on one side of the PCB. The EL7554 operates at constant
frequency PWM mode, making external synchronization
possible. The EL7554 features soft-start and full start-up
control, which eliminates the in-rush current and enables
users to control the start-up of multiple converters to any
configuration with ease. The EL7554 also offers a ±5%
voltage margining capability that allows raising and lowering
of the supplies derived from the EL7554 to validate the
performance and reliability of system cards quickly and easily
during manufacturing testing. A junction temperature indicator
conveniently monitors the silicon die temperature, saving
designers time in the tedious thermal characterization.
An easy-to-use simulation tool is available for download and
can be used to modify design parameters such as switching
frequency, voltage ripple, ambient temperature, as well as
view schematics waveforms, efficiency graphs, and
complete BOM with Gerber layout.
The EL7554 is available in a 28 Ld HTSSOP package and is
specified for operation over the -40°C to +85°C temperature
range.
PART
NUMBER
PART
MARKING
• 4A continuous output current
• Up to 96% efficiency
• All ceramic capacitors
• Multiple supply start-up tracking
• Built-in ±5% voltage margining
• 3V to 6V input voltage
• 0.58 in2 footprint with components on one side of PCB
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• 100% duty ratio
• Junction temperature indicator
• Over-temperature protection
• Internal soft-start
• Variable output voltage down to 0.8V
• Power-good indicator
• 28 Ld HTSSOP package
• Pb-free available (RoHS compliant)
Applications
• FPGA Core and I/O supplies
PACKAGE
PKG.
DWG. #
EL7554IRE*
7554IRE
-40 to +85 28 Ld HTSSOP MDP0048
EL7554IREZ*
(See Note)
7554IREZ
-40 to +85 28 Ld HTSSOP MDP0048
(Pb-free)
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FN7360 Rev 5.00
November 5, 2007
• Integrated MOSFETs
• Point-of-regulation power supplies
Ordering Information
TEMP.
RANGE
(°C)
Features
• DSP, CPU Core, and IO supplies
• Logic/Bus supplies
• Portable equipment
Related Documentation
• Technical Brief 418 - Using the EL7554 Demo Board
• Easy to use applications software simulation tool available
at www.intersil.com/dc-dc
Page 1 of 14
EL7554
Typical Application Diagram
CC
R2
10.2K
RC
1 COMP
SGND 28
2 VREF
COSC 27
0.018µF 2.32K
0.018µF
R1
12.7K
3 FB
STN 26
4 VO
STP 25
5 VTJ
EN 24
6 TM
PG 23
7 SEL
2.2µH
VOUT
(1.8V, 4A)
47µF
FN7360 Rev 5.00
November 5, 2007
COUT
220pF
COSC
0.22µF
VDD 22
8 LX
VIN 21
9 LX
VIN 20
10 LX
VIN 19
11 LX
PGND 18
12 LX
PGND 17
13 LX
PGND 16
14 NC
NC 15
VIN
(3V TO
6V)
CIN
2x10µF
Page 2 of 14
EL7554
Absolute Maximum Ratings (TA = +25°C)
VIN, VDD to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN +0.3V
SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
COMP, VREF, FB, VO, VTJ, TM,
SEL, PG, EN, STP, STN, COSC to SGND . . . . . -0.3V to VDD +0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VDD = VIN = 3.3V, TA = TJ = +25°C, COSC = 390pF, Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
VIN
Input Voltage Range
3
VREF
Reference Accuracy
1.24
VREFTC
Reference Temperature Coefficient
VREFLOAD
Reference Load Regulation
VRAMP
Oscillator Ramp Amplitude
IOSC_CHG
Oscillator Charge Current
IOSC_DIS
TYP
1.26
MAX
UNIT
6
V
1.28
V
50
0 < IREF < 50µA
ppm/°C
-1
%
1.15
V
0.1V < VOSC < 1.25V
200
µA
Oscillator Discharge Current
0.1V < VOSC < 1.25V
8
mA
IVDD
VDD Supply Current
VEN = 1 (L disconnected)
IVDD_OFF
VDD Standby Current
EN = 0
VDD_OFF
VDD for Shutdown
VDD_ON
VDD for Startup
TOT
Over-temperature Threshold
135
°C
THYS
Over-temperature Hysteresis
20
°C
ILEAK
Internal FET Leakage Current
ILMAX
Peak Current Limit
RDSON1
PFET On Resistance
35
70
m
RDSONTC2
NFET On Resistance
30
60
m
RDSONTC
RDSON Tempco
0.2
m/°C
ISTP
STP Pin Input Pull-down Current
VSTP = VIN/2
2.5
µA
ISTN
STN Pin Input Pull-up Current
VSTN = VIN/2
VPGP
Positive Power Good Threshold
With respect to target output voltage
VPGN
Negative Power Good Threshold
VPG_HI
2
2.7
5
mA
1
1.5
mA
2.4
2.65
V
2.6
2.95
V
EN = 0, LX = 6V (low FET), LX = 0V (high FET)
10
6
-4
µA
A
4
µA
6
14
%
With respect to target output voltage
-14
-6
%
Power Good Drive High
IPG = 1mA
2.6
VPG_LO
Power Good Drive Low
IPG = -1mA
VOVP
Output Over-voltage Protection
VFB
Output Initial Accuracy
ILOAD = 0A
VFB_LINE
Output Line Regulation
VIN = 3.3V, VIN = 10%, ILOAD = 0A
GMEA
Error Amplifier Transconductance
VCC = 0.65V
VFB_TC
Output Temperature Stability
0°C < TA < +85°C, ILOAD = 3A
FS
Switching Frequency
IFB
Feedback Input Pull-up Current
FN7360 Rev 5.00
November 5, 2007
2.5
V
0.5
10
0.79
85
VFB = 0V
%
0.8
0.81
V
0.2
0.5
%
125
165
µs
±1
300
V
%
370
440
kHz
100
200
nA
Page 3 of 14
EL7554
DC Electrical Specifications
PARAMETER
VDD = VIN = 3.3V, TA = TJ = +25°C, COSC = 390pF, Unless Otherwise Specified
DESCRIPTION
VEN_HI
EN Input High Level
VEN_LO
EN Input Low Level
IEN
Enable Pull-up Current
TM, SEL_HI
Input High Level
TM, SEL_LO
Input Low Level
CONDITIONS
MIN
TYP
MAX
UNIT
2.6
V
1
VEN = 0
-4
-2.5
V
µA
2.6
V
1
V
Pin Descriptions
PIN NUMBER
PIN NAME
1
COMP
Error amplifier output; place loop compensation components here
2
VREF
Bandgap reference bypass capacitor; typically 0.01µF to 0.047µF to SGND
3
FB
Voltage feedback input; connected to external resistor divider between VOUT and SGND for adjustable
output; also used for speed-up capacitor connection
4
VO
Output sense for fixed output; also used for speed-up capacitor connection
5
VTJ
Junction temperature monitor output, connected to a 0.01µF - 0.047µF to SGND
6
TM
Stress test enable; allows ±5% output movement; needs a pull-down resistor (1k - 100k); connect to
SGND if function is not used
7
SEL
Positive or negative voltage margining set pin; needs a pull-down resistor (1k - 100k); connect to SGND
if function is not used
8, 9, 10, 11, 12, 13
LX
Inductor drive pin; high current output whose average voltage equals the regulator output voltage
14, 15
NC
Not used
16, 17, 18
PGND
19, 20, 21
VIN
Power supply input of the regulator; connected to the drain of the high-side PMOS Power FET
22
VDD
Control circuit positive supply; connected to VIN through an internal 20 resistor
23
PG
Power-good window comparator output; logic 1 when regulator output is within ±10% of target output
voltage
24
EN
Chip enable, active high; a 2µA internal pull-up current enables the device if the pin is left open; a
capacitor can be added at this pin to delay the start of a converter
25
STP
Auxilliary supply tracking positive input; tied to regulator output to synchronize start-up with a second
supply; leave open for standalone operation; 2µA internal pull-up current
26
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start-up;
leave open for standalone operation; 2µA internal pull-up current
27
COSC
Oscillator timing capacitor (see performance curves)
28
SGND
Control circuit negative supply or signal ground
FN7360 Rev 5.00
November 5, 2007
PIN FUNCTION
Ground return of the regulator; connected to the source of the low-side synchronous NMOS Power FET
Page 4 of 14
EL7554
Block Diagram
TM
0.018µF
SEL
COSC
VREF
VTJ
VDD
2.2nF
JUNCTION
TEMPERATURE
VOLTAGE
REFERENCE
220pF
OSCILLATOR
VDD
EN
20
0.22µF
VIN
STP
POWER
TRACKING
STN
PWM
CONTROLLER
VIN
2x10µF
POWER
FET
2.2µH
DRIVERS
VOUT
(UP TO 4A)
POWER
FET
47µF
PGND
EA
CURRENT
SENSE
COMP
VDD
RC
VREF
CC
SGND
FB
R2
+
PG
VO
R1
FN7360 Rev 5.00
November 5, 2007
Page 5 of 14
EL7554
Typical Performance Curves
VIN = VD = 3.3V, VO = 1.8V, IO = 4A, L = 2.2µH, CIN = 2x10µF, COUT = 47µF, COSC = 220pF, TA = +25°C unless otherwise noted.
1
VO=3.3V
0.95
100
VO=2.5V
90
EFFICIENCY (%)
0.9
EFFICIENCY (%)
VO=2.5V
95
0.85
VO=0.8V
0.8
VO=1V
0.75
VO=1.2V
VO=1.8V
0.7
85
VO=0.8V
80
VO=1V
75
VO=1.2V
VO=1.8V
70
0.65
65
0.6
60
0
2
1
3
4
0
2
1
IO (A)
FIGURE 2. EFFICIENCY (VIN = 3.3V)
1.266
1.6
1.264
1.5
VDD=3.3V
1.26
VDD=3.3V
1.4
1.258
1.3
VTJ
VREF
4
IO (A)
FIGURE 1. EFFICIENCY (VIN = 5V)
1.262
3
1.256
1.254
VDD=5V
1.252
1.2
VDD=5V
1.1
1.25
1
1.248
1.246
-50
0
100
50
0.9
-50
150
0
FIGURE 4. VTJ vs TEMPERATURE
FIGURE 3. VREF vs TEMPERATURE
4
1200
3.5
1000
VEN_HI
FS (kHz)
800
2.5
VEN_LOW
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 5. VEN_HI & VEN_LOW vs VDD
FN7360 Rev 5.00
November 5, 2007
VDD=3.3V
200
1
3
VDD=5V
600
500
2
1.5
150
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
3
100
50
6
0
100
200
300
400
500
600
700
COSC (pF)
FIGURE 6. FS vs COSC
Page 6 of 14
EL7554
Typical Performance Curves
(Continued)
VIN = VD = 3.3V, VO = 1.8V, IO = 4A, L = 2.2µH, CIN = 2x10µF, COUT = 47µF, COSC = 220pF, TA = +25°C unless otherwise noted.
0.8
610
0.6
605
VIN=5V
(%)
FS (KHz)
0.4
600
0.2
595
0.0
VIN=3.3V
590
-0.2
-0.4
585
0
0.5
1
1.5
2
2.5
3
3.5
1
0
4
2
FIGURE 7. FS vs IO
FIGURE 8. LOAD REGULATIONS
CONDITION:
3
4
5
6
7
8
9
JA (°C/W)
1.5
1.0
0.5
0
0
25
PCB AREA (in2)
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA
(NO AIR FLOW)
1.00
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.90
0.80
8
P2 W
/
S O °C
T S 10
H
=1
A
J
ALLOWABLE POWER DISSIPATION (W)
8
P2
/W
C
0°
2
=3
25
2.0
SO
30
A
35
2.5
J
40
3.0
TS
28 Ld HTSSOP THERMAL PAD
SOLDERED TO 2-LAYER PCB
WITH 0.039" THICKNESS AND
1 OZ. COPPER ON BOTH SIDES
3.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
H
ALLOWABLE POWER DISSIPATION (W)
50
1
4
IO (A)
IO (A)
45
3
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7360 Rev 5.00
November 5, 2007
Page 7 of 14
EL7554
Waveforms
VIN = VD = 3.3V, VO = 1.8V, IO = 4A, L = 2.2µH, CIN = 2x10µF, COUT = 47µF, COSC = 220pF, TA = +25°C unless otherwise noted.
VIN (2V/DIV)
VIN (100mV/DIV)
IIN (1A/DIV)
VO (1V/DIV)
VLX (2V/DIV)
PG (2V/DIV)
VO (10mV/DIV)
1µs/DIV
0.5ms/DIV
FIGURE 13. STEADY-STATE OPERATION
FIGURE 12. START-UP
3A
1.0A
VEN
IO
IIN (2A/DIV)
VO (100mV/DIV)
VO (2V/DIV)
100µs/DIV
50µs/DIV
FIGURE 14. SHUT-DOWN
FIGURE 15. TRANSIENT RESPONSE
PG
TM
VO (2V/DIV)
SEL
VO (200mV/DIV)
1ms/DIV
FIGURE 16. VOLTAGE MARGINING
FN7360 Rev 5.00
November 5, 2007
VLX (5V/DIV)
0.5ms/DIV
FIGURE 17. OVER-VOLTAGE SHUT-DOWN
Page 8 of 14
EL7554
Waveforms
(Continued)
VIN = VD = 3.3V, VO = 1.8V, IO = 4A, L = 2.2µH, CIN = 2x10µF, COUT = 47µF, COSC = 220pF, TA = +25°C unless otherwise noted.
VIN (2V/DIV)
VIN (5V/DIV)
IIN (2A/DIV)
VO1=2.5V
VO (1V/DIV)
VO2=1.8V
CIN = 100µF,
COUT = 150µF
CIN = 100µF,
COUT = 150µF
5ms/DIV
2ms/DIV
FIGURE 19. TRACKING START-UP
FIGURE 18. ADJUSTABLE START-UP
Detailed Description
The EL7554 is a full-feature synchronous 6A step-down
regulator capable of up to 96% efficiency. This device
operates from 3V to 6V VIN input supply. With internal
CMOS power FETs, the device can operate at up to 100%
duty ratio, allowing for output voltage range from 0.8V up to
nearly VIN.The adjustable high switching frequency of up to
1MHz enables the use of small components, making the
whole converter occupy less than 0.58 square inch with
components on one side of the PCB. The EL7554 operates
at constant frequency PWM mode, making external
synchronization possible. Patented on-chip resistorless
current-sensing enables current mode control, which
provides over-current protection, and excellent step load
response. The EL7554 features soft-start and full start-up
control, which eliminate the in-rush current and enables
users to control the start-up of multiple converters to any
configuration with ease. The EL7554 also offers a ±5%
voltage margining capability that allows raising and lowering
of the supplies derived from the EL7554 to validate the
performance and reliability of system cards quickly and
easily during manufacturing testing. A junction temperature
indicator conveniently monitors the silicon die temperature,
saving designers time in the tedious thermal
characterization.
Start-Up
The EL7554 employs a special soft-start to suppress the inrush current (see Figure 12). The start-up process takes
about 2ms and begins when the input voltage reaches about
2.8V and EN pin voltage 2V. When EN is released from
LOW, or the converter comes out of thermal shut-down
mode, the soft-start process repeats. When the input voltage
ramps up too slowly, slight over- current at the input can
occur. Connecting a small capacitor at EN will delay the
start-up. The delay time TD can be calculated by:
V EN_HI
T D = C EN -------------------I EN
where:
• CEN is the capacitance at EN pin
• VEN_HI is the EN input high level (function of VDD voltage,
see Figure 5)
• IEN is the EN pin pull-up current, nominal 2.5µA
If a slower than 2ms soft start-up is needed, please refer to
Full Start-Up Control section.
Steady-State Operation
The converter always operates at fixed frequency
continuous-conduction mode. For fast transient response,
peak current control method is employed. The inductor
current is sensed from the upper PFET. This current signal,
the slope compensation, and the compensated error signal
are fed to the PWM comparator to generate the PWM signal
for the internal power switches. When the upper PFET is on,
the low-side NFET is off and input voltage charges the
inductor. When PFET is off, the NFET is on and energy
stored in the inductor is dumped to the output to maintain
constant output voltage. Therefore, the LX waveform is
always a stable square waveform (see Figure 13) with peak
close to VIN. So LX is a good indication that the converter is
operating properly.
100% Duty Ratio
EL7554 uses CMOS as internal synchronous power
switches. The upper switch is a PMOS and the lower switch
an NMOS. This not only saves a boot capacitor, it also
allows 100% turn-on of the upper PFET switch, achieving
FN7360 Rev 5.00
November 5, 2007
Page 9 of 14
EL7554
VO close to VIN. The maximum achievable VO is:
100pF
V O = V IN – R L + R DSON1 I O
EL7554
Where RL is the DC resistance on the inductor and RDSON1
is the PFET on-resistance, nominal 35m at room
temperature with tempco of 0.2m/°C.
Output Voltage Selection
The output voltage can be as high as the input voltage minus
the PMOS and inductor voltage drops. Use R1 and R2 to set
the output voltage according to the following formula:
R 1
V O = 0.8 1 + -------
R
2
Standard values of R1 and R2 are listed in Table 1.
TABLE 1.
VO (V)
R1 (k)
R2 (k)
0.8
2
Open
1
2.49
10
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
36
11.5
FIGURE 20. EXTERNAL SYNC CIRCUIT
Thermal Protection and Junction Temperature
Indicator
An internal temperature sensor continuously monitors the
junction temperature. In the event that the junction
temperature exceeds +135°C, the regulator is in a fault
condition and will shut down. When the temperature falls
back below +110°C, the regulator goes through the soft-start
procedure again.
The VTJ pin is an accurate indicator of the internal silicon
junction temperature TJ, which can be determined by the
following formula. This saves engineering time.
1.2 – V TJ
T J = 75 + -----------------------0.00384
Under-Voltage Lockout (UVLO)
When VDD falls bellow 2.5V, the regulator shuts down. When
VDD rises above 2.8V, converter goes through soft-start
process again.
Power Good Indicator (PG) and Over-Voltage
Protection
The EL7554 has built-in 5% load stress test (commonly
called voltage margining) function. Combinations of TM and
SEL set the margins shown in Table 2. When this function is
not used, both pins should be connected to SGND, either
directly or through a 10k resister. Figure 16 shows this
feature.
TABLE 2.
TM
SEL
Normal
0
X
Nominal
High Margin
1
1
Nominal + 5%
Low Margin
1
0
Nominal - 5%
VO
Switching Frequency
The regulator operates from 200kHz to 1MHz. The switching
frequency is generated by a relaxation comparator and
adjusted by a COSC. The triangle waveform has 95% duty
ratio and runs from 0.2V to 1.2V. Please refer to Figure 6 for
a specific frequency.
When external synchronization is required, use the following
circuit for connection. Always choose the converter selfswitching frequency 20% lower than the sync frequency to
accommodate component variations.
FN7360 Rev 5.00
November 5, 2007
EXTERNAL SYNC
SOURCE
where VTJ is the voltage at VTJ pin.
Voltage Margining
CONDITION
COSC
When the output reaches 10% of the preset voltage, the PG
pin outputs a HI signal as shown in the start-up waveform
(Figure 12). If the output voltage is higher than 10% of the
preset value for any reason, PG will go low and the regulator
will shut down. In addition to the indication power is good,
the PG pin can be used for multiple regulators’ start-up
control as described in the next section.
Full Start-Up Control
The EL7554 offers full start-up control. The core of this
control is a start-up comparator in front of the main PWM
controller. The STP and STN are the inputs to the
comparator, whose HI output forces the PWM comparator to
skip switching cycles. The user can choose any of the
following control configurations:
1. ADJUSTABLE SOFT-START
In this configuration, the ramp-up time is adjustable to any
time longer than the building soft-start time of 2ms. The
approximate ramp-up time, TST, is:
VO
T ST = RC ---------
V IN
Figure 18 shows the waveforms.
Page 10 of 14
EL7554
goes HI, where VREF is the regulator reference voltage.
VREF=1.26.
+
VO
STN
C
STP
R
200K
EL7554
0.1µF
VO
VREF
VIN
TST
VO2
EL7554
FIGURE 21. ADJUSTABLE START-UP
RB
+
RA
VIN
In this application, CIN and COUT may be increased to
reduce input/output ripple because the pulse skipping nature
of the method.
VO1
EL7554
VIN
VREF(1+RB/RA)
VO1
2. CASCADE START-UP
VO2
In this configuration, EN pin of Regulator 2 is connected to
the PG pin of Regulator 1 (Figure 22). VO2 will only start
after VO1 is good.
FIGURE 24. OFFSET START-UP TRACKING
Component Selection
EN
VO2
INPUT CAPACITOR
PG
VO1
VIN
EL7554
EL7554
The main functions of the input capacitor(s) are to maintain
the input voltage steady and to filter out the pulse current
passing through the upper switch. The root-mean-square
value of this current is:
V O V IN – V O
I IN,RMS = ----------------------------------------------- I O 1/2 I O
V IN
VO1
VO2
for a wide range of VIN and VO.
FIGURE 22. CASCADE START-UP
3. LINEAR START-UP
In the linear start-up tracking configuration, the regulator with
lower output voltage, VO2, tracks the one with higher output
voltage, VO1. The waveform is shown in Figure 19.
+
VO2
+
STN
STP
VO1
EL7554
VIN
EL7554
C
R
VIN
For long-term reliability, the input capacitor or combination of
capacitors must have the current rating higher than IIN,RMS.
Use X5R or X7R type ceramic capacitors, or SPCAP or
POSCAP types of Polymer capacitors for their high current
handling capability.
INDUCTOR
The NFET positive current limit is set at about 5A. For
optimal operation, the peak-to-peak inductor current ripple
IL should be less than 1A. The following equation gives the
inductance value:
V IN – V O V O
L = -------------------------------------------V IN I L F S
The peak current the inductor sees is:
VO1
VO2
FIGURE 23. LINEAR START-UP TRACKING
I L
I LPK = I O + -------2
When inductor is chosen, make sure the inductor can handle
this peak current and the average current of IO.
4. OFFSET START-UP
OUTPUT CAPACITOR
Compared with the cascade start-up, this configuration
allows Regulator 2 to begin the start-up process when VO1
reaches a particular value of VREF*(1+RB/RA) before PG
If there is no holding time requirement for output; output
voltage ripple and transient response are the main deciding
factors in choosing the output capacitor. Initially, choose the
FN7360 Rev 5.00
November 5, 2007
Page 11 of 14
EL7554
output capacitor with the ESR to satisfy the output ripple
VO requirement:
V O = I L ESR
When output has a step load change IO, the initial voltage
drop is ESR*IO. Then VO will drop even further before the
loop has the chance to respond. The higher the output
capacitance, the lower the voltage drop is. Also, higher loop
bandwidth will generate less voltage drop. Experiment with
the transient response (see Figure 15) to determine the final
values of output capacitance.
Like the input capacitor, it is recommended to use X5R or
X7R type of ceramic capacitors, or SPCAP or POSCAP type
of Polymer capacitors for the low ESR and high capacitance.
Generally, the AC current rating of the output capacitor is not
a concern because the RMS current is only 1/12 of IL.
This is easily satisfied.
LOOP COMPENSATION
Current mode converter forces the inductor current
proportional to the error signal, thus gets rid of the 2nd order
effect formed by the inductor and output capacitor. The PWM
comparator and the inductor form an equivalent
transconductance amplifier. So, a simple Type 1
compensator is good enough to generate a high bandwidth
stable converter. The compensation capacitor and resister
are decided by:
V FB GM PWM GM EA
C C = ---------------------------------------------------------------- F C I OUT
C OUT
R C = 2 R OUT ---------------CC
Design Example
A 5V to 1.8V converter at 4A is needed.
1. Choose the input capacitor
The input capacitor or combination of capacitors has to be
able to take about 1/2 of the output current, e.g., 2A. TDK’s
C3216X5RIA106M is rated at 2.7A, 6.3V, meeting the above
criteria using 2 generators less input voltage ripple.
2. Choose the inductor. Set the converter switching
frequency at 600kHz:
V IN – V O V O
L = -------------------------------------------V IN I L F S
IL = 1A yields 1.72µH. Leave some margin and choose
L = 2.2µH. TDK RLF7030-2R2M5R4 has the required
current rating.
3. Choose the output capacitor
L = 2.2µH yields about 0.9A inductor ripple current. 47µF
ceramic capacitor has less than 5m of ESR easily
satisfying by the requirement. ESR is not the only factor
deciding the output capacitance. As discussed earlier, output
voltage droops less with more capacitance when converter is
in load transient. Multiple iterations may be needed before
final components are chosen.
4. Loop compensation
50kHz is the intended crossover frequency. With the
conditions RC and CC are calculated as:
RC = 2.32k and CC = 0.018pF
For convenience, Table 3 lists the compensation values for
frequently used output voltages.
TABLE 3. COMPENSATION VALUES
where:
• GMPWM is the transconductance of the PWM comparator,
GMPWM = 120s
V OUT
R OUT = ---------------I OUT
VO (V)
RC (k)
CC (µF)
3.3
4.22
0.018
2.5
3.24
0.018
1.8
2.32
0.018
• VOUT output voltage
1.5
1.91
0.018
• IOUT output current
1.2
1.54
0.018
1
1.27
0.018
0.8
1.02
0.018
• COUT is output capacitance
• GMEA is the transconductance of the error amplifier,
GMEA = 120µs
• FC is the intended crossover frequency of the loop. For
best performance, set this value to about one-tenth of the
switching frequency.
FN7360 Rev 5.00
November 5, 2007
Page 12 of 14
EL7554
Thermal Management
Layout Considerations
The EL7554IRE is packaged in a thermally-efficient
HTSSOP-28 package, which utilizes the exposed thermal
pad at the bottom to spread heat through PCB metal.
The layout is very important for the converter to function
properly. Follow these tips for best performance:
Therefore:
1. The thermal pad must be soldered to the PCB
2. Maximize the PCB area
3. If a multiple layer PCB is used, thermal vias (13 to 25 mil)
must be placed underneath the thermal pad to connect to
ground plane(s). Do not place thermal reliefs on the vias.
Figure 25 shows a typical connection.
The thermal resistance for this package is as low as +26°C/W
for 2 layer PCB of 0.39" thickness (see Figure 9). The actual
junction temperature can be measured at VTJ pin.
The thermal performance of the IC is heavily dependent on
the layout of the PCB. The user should exercise care during
the design phase to ensure the IC will operate within the
recommended environmental conditions.
COMPONENT SIDE
CONNECTION
1. Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the SGND pin
2. Place the input capacitor(s) as close to VIN and PGND
pins as possible
3. Make as small as possible the loop from LX pins to L to
CO to PGND pins
4. Place R1 and R2 pins as close to the FB pin as possible
5. Maximize the copper area around the PGND pins; do not
place thermal relief around them
6. Thermal pad should be soldered to PCB. Place several
via holes under the chip to the ground plane to help heat
dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7554 Application Brief.
GROUND PLANE
CONNECTION
FIGURE 25. PCB LAYOUT - 28 Ld HTSSOP PACKAGE
© Copyright Intersil Americas LLC 2004-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7360 Rev 5.00
November 5, 2007
Page 13 of 14
EL7554
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
0.25 M C A B
D
HTSSOP (HEAT-SINK TSSOP) FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
PIN #1 I.D.
E
E1
1
0.20 C B A
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
1.20
1.20
1.20
1.20
Max
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
NOTES:
0.05
e
1.20
0.075
Rev. 3 2/07
BOTTOM VIEW
C
A
A1
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN7360 Rev 5.00
November 5, 2007
Page 14 of 14
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