EL8102IW-T7

EL8102, EL8103 500MHz Rail-to-Rail Amplifiers The EL8102, EL8103 represent single rail-to-rail amplifiers with a -3dB bandwidth of 500MHz and slew rate of 600V/µs. Running off a very low 5.6mA supply current, the EL8102, EL8103 also feature inputs that go to 0.15V below the VSrail. The EL8102 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8102 is ideal for multiplexing applications. The EL8102, EL8103 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8102 is available in 8 Ld SOIC and 6 Ld SOT-23 packages and the EL8103 is available in a 5 Ld SOT-23 package. All are specified for operation over the -40°C to +85°C temperature range. Ordering Information PART NUMBER PART MARKING DATASHEET CT PRODU ODUCT E T E L R OBSO UTE P UBSTIT EL8101 S E L POSSIBEL8100 AND FN7104 Rev 7.00 August 10, 2007 Features • 500MHz -3dB bandwidth • 600V/µs slew rate • Low supply current = 5.6mA • Supplies from 3V to 5.0V • Rail-to-rail output • Input to 0.15V below VS• Fast 25ns disable (EL8102 only) • Low cost • Pb-Free available (RoHS compliant) Applications • Video amplifiers PACKAGE PKG. DWG. # • Portable/hand-held products EL8102IS 8102IS 8 Ld SOIC MDP0027 • Communications devices EL8102IS-T7 8102IS 8 Ld SOIC MDP0027 Pinouts EL8102IS-T13 8102IS 8 Ld SOIC MDP0027 EL8102ISZ (Note) 8102ISZ 8 Ld SOIC (Pb-free) MDP0027 EL8102ISZ-T7 (Note) 8102ISZ 8 Ld SOIC (Pb-free) MDP0027 EL8102ISZ-T13 (Note) 8102ISZ 8 Ld SOIC (Pb-free) MDP0027 IN- 2 EL8102IW-T7 4 6 Ld SOT-23 MDP0038 IN+ 3 EL8102IW-T7A 4 6 Ld SOT-23 MDP0038 VS- 4 EL8102IWZ-T7 (Note) BAVA 6 Ld SOT-23 (Pb-free) MDP0038 EL8102IWZ-T7A BAVA (Note) 6 Ld SOT-23 (Pb-free) MDP0038 EL8103IW-T7 5 5 Ld SOT-23 MDP0038 EL8103IW-T7A 5 5 Ld SOT-23 MDP0038 EL8103IWZ-T7 (Note) BAWA 5 Ld SOT-23 (Pb-free) MDP0038 EL8103IWZ-T7A BAWA (Note) 5 Ld SOT-23 (Pb-free) MDP0038 EL8102 (8 LD SOIC) TOP VIEW NC 1 FN7104 Rev 7.00 August 10, 2007 + 7 VS+ 6 OUT 5 NC EL8102 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 6 VS+ + - IN+ 3 5 ENABLE 4 IN- EL8103 (5 LD SOT-23) TOP VIEW *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 8 ENABLE OUT 1 VS- 2 IN+ 3 5 VS+ + 4 IN- Page 1 of 14 EL8102, EL8103 EL8102, EL8103 Absolute Maximum Ratings (TA = 25°C) Thermal Information Supply Voltage from VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION:Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = +25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT -8 -0.8 +8 mV INPUT CHARACTERISTICS VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V IOS Input Offset Current VIN = 0V TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V CMIR Common Mode Input Range RIN Input Resistance CIN Input Capacitance AVOL Open Loop Gain 3 -9 -6 0.1 70 µA 0.6 µA 2 nA/°C 95 dB VS- -0.15 Common Mode µV/°C VS+ -1.5 V 3.5 M 0.5 pF 90 dB VOUT = +1.5V to +3.5V, RL = 150 to GND 80 dB 30 m 4.9 V VOUT = +1.5V to +3.5V, RL = 1k to GND 75 OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 VOP Positive Output Voltage Swing RL = 1k 4.85 RL = 150 4.6 VON Negative Output Voltage Swing RL = 150 100 150 mV RL = 1k 25 50 mV IOUT Linear Output Current ISC (source) Short Circuit Current RL = 10 ISC (sink) Short Circuit Current 4.7 V 65 mA 70 80 mA RL = 10 120 150 mA VS+ = 4.5V to 5.5V 70 95 dB POWER SUPPLY PSRR Power Supply Rejection Ratio IS-ON Supply Current - Enabled 5.6 IS-OFF Supply Current - Disabled 30 µA 6 mA ENABLE (EL8102 ONLY) tEN Enable Time 200 ns tDS Disable Time 25 ns VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-down 2 V FN7104 Rev 7.00 August 10, 2007 Page 2 of 14 EL8102, EL8103 EL8102, EL8103 Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = +25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. (Continued) DESCRIPTION MIN (Note 1) CONDITIONS TYP MAX (Note 1) UNIT IIH-ENB ENABLE Pin Input Current High 8.6 µA IIL-ENB ENABLE Pin Input for Current Low 0.01 µA AV = +1, RF = 0, CL = 5pF 500 MHz AV = -1, RF = 1k, CL = 5pF 140 MHz AV = +2, RF = 1k, CL = 5pF 165 MHz AV = +10, RF = 1k, CL = 5pF 18 MHz AC PERFORMANCE BW -3dB Bandwidth BW ±0.1dB Bandwidth AV = +1, RF = 0, CL = 5pF 35 MHz Peak Peaking AV = +1, RL = 1k, CL = 5pF 1 dB GBWP Gain Bandwidth Product 200 MHz PM Phase Margin RL = 1k, CL = 5pF 55 ° SR Slew Rate AV = 2, RL = 100, VOUT = 0.5V to 4.5V 600 V/µs tR Rise Time 2.5VSTEP, 20% to 80% 4 ns tF Fall Time 2.5VSTEP, 20% to 80% 2 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 1 ns tS 0.1% Settling Time 200mV step 15 ns dG Differential Gain AV = +2, RF = 1k, RL = 150 0.01 % dP Differential Phase AV = +2, RF = 1k, RL = 150 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/Hz iN+ Positive Input Noise Current f = 10kHz 1.7 pA/Hz iN- Negative Input Noise Current f = 10kHz 1.3 pA/Hz 500 NOTE: 1. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. Pin Descriptions PIN EL8102IS EL8102IW EL8103IW 1 NAME FUNCTION NC Not connected 2 4 4 IN- Inverting input 3 3 3 IN+ Non-inverting input 4 2 2 VS- Negative power supply NC Not connected 5 6 1 1 OUT Amplifier output 7 6 5 VS+ Positive power supply 8 5 FN7104 Rev 7.00 August 10, 2007 ENABLE Enable and disable input Page 3 of 14 EL8102, EL8103 EL8102, EL8103 Simplified Schematic Diagram VS+ I1 I2 Q5 Q7 R2 Q1 IN+ R8 VBIAS1 Q6 R3 R1 R7 R6 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- Typical Performance Curves 3 GAIN (dB) 5 VS = 5V AV = 1 RL = 1k CL = 5pF NORMALIZED GAIN (dB) 5 VOP-P = 200mV 1 -1 VOP-P = 1V -3 VOP-P = 2V -5 100k 1M 10M 100M 3 RF = RG = 1k 1 -1 -3 RF = RG = 500 VS = 5V AV = 2 RL = 1k CL = 5pF -5 100k 1G 1M FREQUENCY (Hz) AV = 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 AV = 1 0 AV = 5 -2 AV = 10 -4 -6 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS FN7104 Rev 7.00 August 10, 2007 100M 1G FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE vs RF AND RG 4 VS = 5V CL = 5pF RL = 1k 10M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS 4 RF = RG = 2k 2 VS = 5V CL = 5pF RL = 1k RF = 1k AV = -1 0 AV = -5 -2 -4 -6 100k AV = -10 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS Page 4 of 14 EL8102, EL8103 EL8102, EL8103 Typical Performance Curves (Continued) GAIN (dB) 3 VS = 5V AV = 1 CL = 5pF VOP-P = 200mV 11 9 RL = 100 RL = 1k GAIN (dB) 5 1 -1 RL = 500 -3 VS = 5V AV = 2 CL = 5pF RF = RG = 1k RL = 500 7 5 RL = 1k, 150 3 -5 100k 1M 10M 100M 1 100k 1G 1M FREQUENCY (Hz) FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD GAIN (dB) 3 11 VS = 5V AV = 1 RL = 1k VOP-P = 200mV CL = 10pF CL = 5pF 1 -1 CL = 1.5pF -3 -5 100k 1M 10M 100M 9 CL = 14pF 5 CL = 9pF 3 CL = 5pF 1M 405 -10 315 -30 225 RL = 150 -10 135 RL = 1k 45 1M 10M 100M -45 1G FREQUENCY (Hz) FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY FN7104 Rev 7.00 August 10, 2007 GAIN (dB) 30 PHASE (°) GAIN (dB) RL = 150 100k 100M 1G FIGURE 8. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL RL = 1k 10k 10M FREQUENCY (Hz) 110 -90 1k CL = 20pF 7 1 100k 1G FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs CL -50 1G CL=30pF VS = 5V AV = 2 RL = 1k RF = RG = 1k FREQUENCY (Hz) 70 100M FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs VARIOUS RLOAD NORMALIZED GAIN (dB) 5 10M FREQUENCY (Hz) VS = 5V AV = 1 RL = 1k -50 -70 -90 -110 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 10. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE Page 5 of 14 EL8102, EL8103 EL8102, EL8103 Typical Performance Curves (Continued) -10 550 500 BANDWIDTH (MHz) PSRR (dB) -30 PSRR- -50 -70 PSRR+ -90 450 AV = 1 RL = 1k CL = 5pF 400 350 300 250 200 -110 1k 10k 100k 1M 10M AV = 2 150 3.0 100M 3.5 RL = 1k CL = 5pF 2.0 PEAKING (dB) IMPEDANCE () 2.5 10 1 0.1 1.5 AV = 1 1.0 AV = 2 0.5 100k 1M 10M 0 3.0 100M 4.0 3.5 FREQUENCY (Hz) 5.0 5.5 FIGURE 14. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE -15 10 -35 8 -55 6 IS (mA) CMRR (dB) 4.5 VS (V) FIGURE 13. OUPUT IMPEDANCE vs FREQUENCY -75 4 2 -95 1M 10M 100M FREQUENCY (Hz) FIGURE 15. COMMON-MODE REJECTION RATIO vs FREQUENCY FN7104 Rev 7.00 August 10, 2007 5.5 FIGURE 12. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE 100 -115 100k 5.0 VS (V) FIGURE 11. POWER SUPPLY REJECTION RATIO vs FREQUENCY 0.01 10k 4.5 4.0 FREQUENCY (Hz) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VS (V) FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE Page 6 of 14 EL8102, EL8103 EL8102, EL8103 Typical Performance Curves (Continued) -70 -80 HD2 -90 -100 -70 VS = 5V RL = 1k CL = 5pF AV = 2 HD2@5MHz Hz @ 1M H HD3@10M MHz HD3@ 5 1 -75 HD2@10MHz DISTORTION (dBc) DISTORTION (dBc) -60 z 3 -80 4 -85 VS = 5V f = 5MHz -90 H D 3@ VO = 1VP-P FOR AV = 1 VO = 2VP-P FOR AV = 2 AV =1 2K RLOAD () FIGURE 17. HARMONIC DISTORTION vs OUTPUT VOLTAGE FIGURE 18. HARMONIC DISTORTION vs LOAD RESISTANCE -50 1k -70 AV=2 HD2 @ -80 -90 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz), VS = 5V RL = 1k CL = 5pF VO = 1VP-P FOR AV = 1 VO = 2VP-P FOR AV = 2 -60 DISTORTION (dBc) AV =2 1K VO(P-P) (V) -100 H D 3@ -100 100 5 AV =2 HD2 @ AV =1 -95 HD3@1MHz 2 HD2@ HD2@AV=1 HD3@AV=2 @ HD3 AV=1 1 10 100 eN 10 IN+ 1 10 40 FREQUENCY (MHz) FIGURE 19. HARMONIC DISTORTION vs FREQUENCY 10k 100k 1M 10M FIGURE 20. VOLTAGE AND CURRENT NOISE vs FREQUENCY VS = 5V, AV = 1, RL = 1k TO 2.5V, CL = 5pF 3.5 3.5 2.5 2.5 1.5 2ns/DIV FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE - RISING FN7104 Rev 7.00 August 10, 2007 1k FREQUENCY (Hz) VS = 5V, AV = 1, RL = 1k TO 2.5V, CL = 5pF 1.5 100 IN- 2ns/DIV FIGURE 22. LARGE SIGNAL TRANSIENT RESPONSE - FALLING Page 7 of 14 EL8102, EL8103 EL8102, EL8103 Typical Performance Curves (Continued) VS = 5V, AV = 1, RL = 1k TO 2.5V, CL= 5pF VS = 5V, AV = 5, RL = 1k TO 2.5V VIN 2.6 5.0 2.5 2.4 2.5 2.6 VOUT 2.5 0 2.4 10ns/DIV 2µs/DIV FIGURE 23. SMALL SIGNAL TRANSIENT REPONSE FIGURE 24. OUTPUT SWING VS = 5V, AV = 5, RL = 1k TO 2.5V CH1 ENABLE INPUT 5.0 2.5 CH2 VOUT 0 CH1, CH2, 1V/DIV, M=100ns 2µs/DIV FIGURE 25. OUTPUT SWING FIGURE 26. ENABLED RESPONSES JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD CH1 CH2 ENABLE INPUT VOUT POWER DISSIPATION (W) 1.4 1.2 1.0 909mW 0.8 0.6 FIGURE 27. DISABLED RESPONSE FN7104 Rev 7.00 August 10, 2007 435mW 0.4 SOT23-5/6 JA = +230°C/W 0.2 0 CH1, CH2, 0.5V/DIV, M = 20ns SO8 JA = +110°C/W 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 8 of 14 EL8102, EL8103 EL8102, EL8103 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.0 0.9 0.8 0.7 625mW 0.6 0.5 SO8 JA = +160°C/W 391mW 0.4 0.3 0.2 SOT23-5/6 JA = +256°C/W 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Description of Operation and Application Information Product Description The EL8102, EL8103 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1k load, the EL8102, EL8103 have a -3dB bandwidth of 500MHz. Driving a 150 load, the bandwidth is about 350MHz while maintaining a 600V/µs slew rate. The EL8102 is available with a power-down pin to reduce power to 30µA typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8102, EL8103 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8102, EL8103 can swing rail-to-rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1k, the output swing is about 4.9V at a 5V supply. For the load resistor 150, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier’s phase margin is reduced. This causes ringing in the time domain FN7104 Rev 7.00 August 10, 2007 and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few pF range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For a gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300 to 1k. The EL8102, EL8103 have a gain bandwidth product of 200MHz. For gains 5, its bandwidth can be predicted by the Equation 1: (EQ. 1) Gain  BW = 200MHz Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150 because the change in output current with DC level. Special circuitry has been incorporated in the EL8102, EL8103 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.01% and 0.01, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. Driving Capacitive Loads and Cables The EL8102, EL8103 can drive 10pF loads in parallel with 1k with less than 5dB of peaking at a gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the Page 9 of 14 EL8102, EL8103 EL8102, EL8103 output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier’s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. The EL8102 can be disabled and its output placed in a high impedance state. The turn-off time is about 25ns and the turn-on time is about 200ns. When disabled, the amplifier’s supply current is reduced to 30µA typically, thereby effectively eliminating the power consumption. The amplifier’s power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-. Output Drive Capability The EL8102, EL8103 do not have internal short circuit protection circuitry. They have a typical short circuit current of 80mA sourcing and 150mA sinking for the output is connected to half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL8102, EL8103, It is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 2: FN7104 Rev 7.00 August 10, 2007 TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing, Equation 3: V OUT PDMAX = V S  I SMAX +  V S – V OUT   ---------------R (EQ. 3) L For sinking, Equation 4: Disable/Power-Down T JMAX – T AMAX PD MAX = -------------------------------------------- JA Where: (EQ. 2) PD MAX = V S  I SMAX +  V OUT – V S-   I LOAD (EQ. 4) Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Page 10 of 14 EL8102, EL8103 EL8102, EL8103 Typical Applications +2.5V VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 30 shows a gain of 2 connections for EL8102, EL8103. Figure 31 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. B 2MHz 1VP-P + 75 -2.5V 1k 1k 75 VOUT +2.5V A 2MHz 2VP-P 75 + - 75 -2.5V 5V VIN VS+ + - VS- 75 1k 75 1k VOUT ENABLE 75 1k 1k FIGURE 32. TWO TO ONE MULTIPLEXER FIGURE 30. SYNC PULSE REMOVER 0V -0.5V ENABLE -1.5V -2.5V 1V VIN 0.5V 1V 0V 0V 1V VOUT B A -1V 0.5V 0V M = 50ns/DIV FIGURE 33. M = 10µs/DIV FIGURE 31. VIDEO SIGNAL MULTIPLEXER Besides the normal power-down usage, the ENABLE pin of the EL8102 can be used for multiplexing applications. Figure 32 shows two EL8102 with the outputs tied together, driving a back terminated 75 video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 33 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the breakbefore-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on and VIN2 is passed through to the output. The break-before-make operation ensures that more than one amplifier isn’t trying to drive the bus at the same time. FN7104 Rev 7.00 August 10, 2007 SINGLE SUPPLY VIDEO LINE DRIVER The EL8102 and EL8103 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 34 is the single supply non-inverting video line driver configuration and Figure 35 is the inverting video line driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal. Page 11 of 14 EL8102, EL8103 EL8102, EL8103 5V RF 1k VIN C1 47µF R1 10k + RT 75 R3 C3 470µF 75 VOUT VIN C1 RG 47µF 500 - R2 10k 75 RT 75 5V 5V - R3 C3 470µF 75 VOUT + R1 10k 75 RF 1k RG 1k R2 10k C2 220µF NORMALIZED GAIN (dB) FIGURE 34. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER C2 220µF FIGURE 35. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER 4 3 2 1 AV = 2 0 -1 -2 AV = -2 -3 -4 -5 -6 100K 1M 10M 100M 500M FREQUENCY (Hz) FIGURE 36. VIDEO LINE DRIVER FREQUENCY RESPONSE FN7104 Rev 7.00 August 10, 2007 Page 12 of 14 EL8102, EL8103 EL8102, EL8103 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 NOTES: Rev. M 2/07 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN7104 Rev 7.00 August 10, 2007 Page 13 of 14 EL8102, EL8103 EL8102, EL8103 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference Rev. F 2/07 D 2X NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) A GAUGE PLANE c 6. SOT23-5 version has no center lead (shown as a dashed line). H L 0.25 0° +3° -0° © Copyright Intersil Americas LLC 2003-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7104 Rev 7.00 August 10, 2007 Page 14 of 14