H8S-2345

REJ09B0291-0400 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2345 Group, H8S/2345 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2345 HD6432345, HD6472345, HD64F2345 HD6432344 HD6432341 HD64F2340 H8S/2344 H8S/2341 H8S/2340 Rev. 4.00 Revision Date: Feb 15, 2006 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 4.00 Feb 15, 2006 page ii of xxiv General Precautions on the Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system’s operation is not guaranteed if they are accessed. Rev. 4.00 Feb 15, 2006 page iii of xxiv Rev. 4.00 Feb 15, 2006 page iv of xxiv Preface The H8S/2345 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM and RAM. With regard to on-chip ROM* , 2 2 single power supply flash memory (F-ZTAT™* ), PROM (ZTAT®* ), and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through fullscale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2345 Group enables compact, high-performance systems to be implemented easily. This manual describes the hardware of the H8S/2345 Group. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes: 1. The H8S/2345, H8S/2344, H8S/2343, and H8S/2341 have on-chip ROM. The H8S/2340 does not have on-chip ROM. 2. F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp. ZTAT is a registered trademark of Renesas Technology Corp. 1 Rev. 4.00 Feb 15, 2006 page v of xxiv Rev. 4.00 Feb 15, 2006 page vi of xxiv Main Revisions in This Edition Item All Page — Revision (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Figure 9.57 amended TCNT write cycle T1 T2 φ 9.7 Usage Notes Figure 9.57 Contention between TCNT Write and Overflow 370 Address TCNT address Write signal TCNT write data H'FFFF Prohibited M TCNT TCFV flag 11.2.2 Timer Control/Status Register (TCSR) 399 Table amended [Clearing condition] Cleared by reading TCSR when OVF = 1*, then writing 0 to OVF Note * added Note: * When OVF is polled and the interval timer interrupt is disabled. OVF = 1 must be read at least twice. 14.4.3 Input Sampling 521 and A/D Conversion Time Figure 14.5 A/D Conversion Timing Figure 14.5 amended (1) φ Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Rev. 4.00 Feb 15, 2006 page vii of xxiv Item 20.1.6 Flash Memory Characteristics Table 20.10 Flash Memory Characteristics Page 648 Revision (See Manual for Details) Table 20.10 amended Item Programming time*1 *2 *4 Erase time*1 *3 *5 Reprogramming count Data retention time*9 Programming Wait time after setting SWE bit*1 Symbol tP tE NWEC tDRP x Min — — 100*7 10 10 Typ 10 100 Max 200 1200 Unit ms/ 32 bytes ms/block Times Years µs Test Conditions 10,000*8 — — — — — 649 Notes 7 to 9 amended Notes: 7. Minimum number of times for which all characteristics are guaranteed after rewriting. (Guarantee range is 1 to minimum value.) 8. Reference value for 25°C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. Appendix G Package Dimensions Figure G.1 TFP-100B Package Dimensions 897 Figure G.1 replaced Figure G.2 TFP-100G 898 Package Dimensions Figure G.3 FP-100A Package Dimensions Figure G.4 FP-100B Package Dimensions 899 900 Figure G.2 replaced Figure G.3 replaced Figure G.4 replaced Rev. 4.00 Feb 15, 2006 page viii of xxiv Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 6 Pin Description.................................................................................................................. 7 1.3.1 Pin Arrangement .................................................................................................. 7 1.3.2 Pin Functions in Each Operating Mode ............................................................... 9 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 21 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU ............................................................................ 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function ....................................................... 2.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode................................................................................................. 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State...................................................................................... 2.8.5 Bus-Released State............................................................................................... 21 21 22 23 23 24 29 30 30 31 32 34 35 35 37 38 38 39 41 48 49 49 52 56 56 57 58 61 61 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev. 4.00 Feb 15, 2006 page ix of xxiv 2.9 2.8.6 Power-Down State ............................................................................................... Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 External Address Space Access Timing .............................................................. 61 62 62 62 64 65 Section 3 MCU Operating Modes .................................................................................. 67 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection (F-ZTAT™ Version)................................................. 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, and ROMless Versions) .......... 3.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) ......................... Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 (ZTAT, Mask ROM, and ROMless Versions Only)............................... 3.3.2 Mode 2 (ZTAT and Mask ROM Versions Only)................................................. 3.3.3 Mode 3 (ZTAT and Mask ROM Versions Only)................................................. 3.3.4 Mode 4 ................................................................................................................. 3.3.5 Mode 5 ................................................................................................................. 3.3.6 Mode 6 ................................................................................................................. 3.3.7 Mode 7 ................................................................................................................. 3.3.8 Modes 8 and 9 (F-ZTAT Version Only) .............................................................. 3.3.9 Mode 10 (F-ZTAT Version Only) ....................................................................... 3.3.10 Mode 11 (F-ZTAT Version Only) ....................................................................... 3.3.11 Modes 12 and 13.................................................................................................. 3.3.12 Mode 14 (F-ZTAT Version Only) ....................................................................... 3.3.13 Mode 15 (F-ZTAT Version Only) ....................................................................... Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ 67 67 68 69 70 70 71 72 73 73 73 73 73 74 74 74 75 75 75 75 75 75 76 77 3.2 3.3 3.4 3.5 Section 4 Exception Handling ......................................................................................... 89 4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table ....................................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Types.......................................................................................................... 89 89 90 90 92 92 92 4.2 Rev. 4.00 Feb 15, 2006 page x of xxiv 4.3 4.4 4.5 4.6 4.7 4.2.3 Reset Sequence .................................................................................................... 4.2.4 Interrupts after Reset............................................................................................ 4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. Traces................................................................................................................................ Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack ................................................................................................. 93 94 94 95 96 97 98 99 Section 5 Interrupt Controller .......................................................................................... 101 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0 ..................................................................................... 5.4.3 Interrupt Control Mode 2 ..................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts ...................................................................... 5.5.3 Times when Interrupts Are Disabled ................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... DTC Activation by Interrupt............................................................................................. 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram ..................................................................................................... 5.6.3 Operation ............................................................................................................. 101 101 102 103 103 104 104 105 106 107 108 109 109 110 110 114 114 117 119 121 123 124 124 125 125 126 126 126 127 127 5.2 5.3 5.4 5.5 5.6 Rev. 4.00 Feb 15, 2006 page xi of xxiv Section 6 Bus Controller ................................................................................................... 129 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Bus Width Control Register (ABWCR)............................................................... 6.2.2 Access State Control Register (ASTCR) ............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 6.2.4 Bus Control Register H (BCRH).......................................................................... 6.2.5 Bus Control Register L (BCRL) .......................................................................... Bus Control ....................................................................................................................... 6.3.1 Area Divisions ..................................................................................................... 6.3.2 Bus Specifications................................................................................................ 6.3.3 Memory Interfaces ............................................................................................... 6.3.4 Advanced Mode................................................................................................... 6.3.5 Areas in Normal Mode (ZTAT, Mask ROM, and ROMless Versions Only) ...... 6.3.6 Chip Select Signals .............................................................................................. Basic Bus Interface ........................................................................................................... 6.4.1 Overview.............................................................................................................. 6.4.2 Data Size and Data Alignment............................................................................. 6.4.3 Valid Strobes........................................................................................................ 6.4.4 Basic Timing........................................................................................................ 6.4.5 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 6.5.1 Overview.............................................................................................................. 6.5.2 Basic Timing........................................................................................................ 6.5.3 Wait Control ........................................................................................................ Idle Cycle .......................................................................................................................... 6.6.1 Operation ............................................................................................................. 6.6.2 Pin States in Idle Cycle ........................................................................................ Bus Release....................................................................................................................... 6.7.1 Overview.............................................................................................................. 6.7.2 Operation ............................................................................................................. 6.7.3 Pin States in External Bus Released State............................................................ 6.7.4 Transition Timing ................................................................................................ 6.7.5 Usage Note........................................................................................................... Bus Arbitration.................................................................................................................. 6.8.1 Overview.............................................................................................................. 6.8.2 Operation ............................................................................................................. 129 129 130 131 131 132 132 133 134 137 139 140 140 142 143 143 144 145 146 146 146 148 149 157 159 159 159 161 162 162 165 165 165 165 166 167 168 168 168 168 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Rev. 4.00 Feb 15, 2006 page xii of xxiv 6.9 6.8.3 Bus Transfer Timing ............................................................................................ 169 6.8.4 External Bus Release Usage Note........................................................................ 169 Resets and the Bus Controller ........................................................................................... 169 Section 7 Data Transfer Controller................................................................................. 171 7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 7.2.1 DTC Mode Register A (MRA) ............................................................................ 7.2.2 DTC Mode Register B (MRB)............................................................................. 7.2.3 DTC Source Address Register (SAR).................................................................. 7.2.4 DTC Destination Address Register (DAR).......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR)........................................................................ 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... Operation .......................................................................................................................... 7.3.1 Overview.............................................................................................................. 7.3.2 Activation Sources ............................................................................................... 7.3.3 DTC Vector Table................................................................................................ 7.3.4 Location of Register Information in Address Space ............................................ 7.3.5 Normal Mode....................................................................................................... 7.3.6 Repeat Mode ........................................................................................................ 7.3.7 Block Transfer Mode ........................................................................................... 7.3.8 Chain Transfer ..................................................................................................... 7.3.9 Operation Timing................................................................................................. 7.3.10 Number of DTC Execution States........................................................................ 7.3.11 Procedures for Using DTC................................................................................... 7.3.12 Examples of Use of the DTC ............................................................................... Interrupts ........................................................................................................................... Usage Notes ...................................................................................................................... 171 171 172 173 174 174 176 177 177 178 178 179 180 181 182 182 184 185 188 189 190 191 193 194 195 197 198 200 200 7.2 7.3 7.4 7.5 Section 8 I/O Ports .............................................................................................................. 201 8.1 8.2 Overview........................................................................................................................... Port 1................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Configuration......................................................................................... 8.2.3 Pin Functions ....................................................................................................... 201 206 206 207 209 Rev. 4.00 Feb 15, 2006 page xiii of xxiv 8.3 Port 2................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Configuration......................................................................................... 8.3.3 Pin Functions ....................................................................................................... 8.4 Port 3................................................................................................................................. 8.4.1 Overview.............................................................................................................. 8.4.2 Register Configuration......................................................................................... 8.4.3 Pin Functions ....................................................................................................... 8.5 Port 4................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Configuration......................................................................................... 8.5.3 Pin Functions ....................................................................................................... 8.6 Port A................................................................................................................................ 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration......................................................................................... 8.6.3 Pin Functions ....................................................................................................... 8.6.4 MOS Input Pull-Up Function............................................................................... 8.7 Port B ................................................................................................................................ 8.7.1 Overview.............................................................................................................. 8.7.2 Register Configuration......................................................................................... 8.7.3 Pin Functions ....................................................................................................... 8.7.4 MOS Input Pull-Up Function............................................................................... 8.8 Port C ................................................................................................................................ 8.8.1 Overview.............................................................................................................. 8.8.2 Register Configuration......................................................................................... 8.8.3 Pin Functions ....................................................................................................... 8.8.4 MOS Input Pull-Up Function............................................................................... 8.9 Port D................................................................................................................................ 8.9.1 Overview.............................................................................................................. 8.9.2 Register Configuration......................................................................................... 8.9.3 Pin Functions ....................................................................................................... 8.9.4 MOS Input Pull-Up Function............................................................................... 8.10 Port E ................................................................................................................................ 8.10.1 Overview.............................................................................................................. 8.10.2 Register Configuration......................................................................................... 8.10.3 Pin Functions ....................................................................................................... 8.10.4 MOS Input Pull-Up Function............................................................................... 8.11 Port F................................................................................................................................. 8.11.1 Overview.............................................................................................................. 8.11.2 Register Configuration......................................................................................... 8.11.3 Pin Functions ....................................................................................................... 217 217 218 220 228 228 228 231 233 233 233 234 234 234 235 239 240 241 241 242 244 246 247 247 248 250 252 253 253 254 257 258 259 259 260 262 264 265 265 266 268 Rev. 4.00 Feb 15, 2006 page xiv of xxiv 8.12 Port G................................................................................................................................ 8.12.1 Overview.............................................................................................................. 8.12.2 Register Configuration......................................................................................... 8.12.3 Pin Functions ....................................................................................................... 270 270 271 274 Section 9 16-Bit Timer Pulse Unit (TPU) .................................................................... 277 9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagram ..................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 9.2.1 Timer Control Register (TCR) ............................................................................. 9.2.2 Timer Mode Register (TMDR) ............................................................................ 9.2.3 Timer I/O Control Register (TIOR) ..................................................................... 9.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 9.2.5 Timer Status Register (TSR)................................................................................ 9.2.6 Timer Counter (TCNT)........................................................................................ 9.2.7 Timer General Register (TGR) ............................................................................ 9.2.8 Timer Start Register (TSTR)................................................................................ 9.2.9 Timer Synchro Register (TSYR) ......................................................................... 9.2.10 Module Stop Control Register (MSTPCR) .......................................................... Interface to Bus Master ..................................................................................................... 9.3.1 16-Bit Registers ................................................................................................... 9.3.2 8-Bit Registers ..................................................................................................... Operation .......................................................................................................................... 9.4.1 Overview.............................................................................................................. 9.4.2 Basic Functions.................................................................................................... 9.4.3 Synchronous Operation........................................................................................ 9.4.4 Buffer Operation .................................................................................................. 9.4.5 Cascaded Operation ............................................................................................. 9.4.6 PWM Modes ........................................................................................................ 9.4.7 Phase Counting Mode .......................................................................................... Interrupts ........................................................................................................................... 9.5.1 Interrupt Sources and Priorities............................................................................ 9.5.2 DTC Activation.................................................................................................... 9.5.3 A/D Converter Activation.................................................................................... Operation Timing.............................................................................................................. 9.6.1 Input/Output Timing ............................................................................................ 9.6.2 Interrupt Signal Timing........................................................................................ Usage Notes ...................................................................................................................... 277 277 281 282 284 286 286 291 293 310 313 316 317 318 319 320 321 321 321 323 323 324 330 332 336 338 344 350 350 352 352 353 353 357 361 9.2 9.3 9.4 9.5 9.6 9.7 Rev. 4.00 Feb 15, 2006 page xv of xxiv Section 10 8-Bit Timers ..................................................................................................... 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 10.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 10.2.6 Module Stop Control Register (MSTPCR) .......................................................... 10.3 Operation .......................................................................................................................... 10.3.1 TCNT Incrementation Timing ............................................................................. 10.3.2 Compare Match Timing....................................................................................... 10.3.3 Timing of External RESET on TCNT ................................................................. 10.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 10.3.5 Operation with Cascaded Connection.................................................................. 10.4 Interrupts ........................................................................................................................... 10.4.1 Interrupt Sources and DTC Activation ................................................................ 10.4.2 A/D Converter Activation.................................................................................... 10.5 Sample Application........................................................................................................... 10.6 Usage Notes ...................................................................................................................... 10.6.1 Contention between TCNT Write and Clear........................................................ 10.6.2 Contention between TCNT Write and Increment ................................................ 10.6.3 Contention between TCOR Write and Compare Match ...................................... 10.6.4 Contention between Compare Matches A and B ................................................. 10.6.5 Switching of Internal Clocks and TCNT Operation............................................. 10.6.6 Usage Note........................................................................................................... Section 11 Watchdog Timer ............................................................................................. 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Timer Counter (TCNT)........................................................................................ 11.2.2 Timer Control/Status Register (TCSR) ................................................................ 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ Rev. 4.00 Feb 15, 2006 page xvi of xxiv 371 371 371 372 373 373 374 374 374 375 375 378 381 382 382 383 385 385 386 387 387 387 388 389 389 390 391 392 392 394 395 395 395 396 397 397 398 398 399 401 11.2.4 Notes on Register Access..................................................................................... 11.3 Operation .......................................................................................................................... 11.3.1 Watchdog Timer Operation ................................................................................. 11.3.2 Interval Timer Operation ..................................................................................... 11.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 11.4 Interrupts ........................................................................................................................... 11.5 Usage Notes ...................................................................................................................... 11.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 11.5.2 Changing Value of CKS2 to CKS0...................................................................... 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 11.5.4 System Reset by WDTOVF Signal...................................................................... 11.5.5 Internal Reset in Watchdog Timer Mode............................................................. 402 404 404 405 406 407 408 408 408 409 409 409 410 Section 12 Serial Communication Interface (SCI) .................................................... 411 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Receive Shift Register (RSR) .............................................................................. 12.2.2 Receive Data Register (RDR) .............................................................................. 12.2.3 Transmit Shift Register (TSR) ............................................................................. 12.2.4 Transmit Data Register (TDR)............................................................................. 12.2.5 Serial Mode Register (SMR)................................................................................ 12.2.6 Serial Control Register (SCR).............................................................................. 12.2.7 Serial Status Register (SSR) ................................................................................ 12.2.8 Bit Rate Register (BRR) ...................................................................................... 12.2.9 Smart Card Mode Register (SCMR) .................................................................... 12.2.10 Module Stop Control Register (MSTPCR) .......................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Overview.............................................................................................................. 12.3.2 Operation in Asynchronous Mode ....................................................................... 12.3.3 Multiprocessor Communication Function............................................................ 12.3.4 Operation in Clocked Synchronous Mode ........................................................... 12.4 SCI Interrupts.................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 411 411 413 414 415 416 416 416 417 417 418 421 425 429 438 439 440 440 442 453 461 470 471 Section 13 Smart Card Interface ..................................................................................... 477 13.1 Overview........................................................................................................................... 477 Rev. 4.00 Feb 15, 2006 page xvii of xxiv 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram ..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Smart Card Mode Register (SCMR) .................................................................... 13.2.2 Serial Status Register (SSR) ................................................................................ 13.2.3 Serial Mode Register (SMR)................................................................................ 13.2.4 Serial Control Register (SCR).............................................................................. 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Pin Connections ................................................................................................... 13.3.3 Data Format ......................................................................................................... 13.3.4 Register Settings .................................................................................................. 13.3.5 Clock.................................................................................................................... 13.3.6 Data Transfer Operations..................................................................................... 13.3.7 Operation in GSM Mode ..................................................................................... 13.4 Usage Note........................................................................................................................ 477 478 479 480 481 481 482 484 485 486 486 486 488 490 492 494 501 502 Section 14 A/D Converter ................................................................................................. 507 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 14.2.3 A/D Control Register (ADCR) ............................................................................ 14.2.4 Module Stop Control Register (MSTPCR) .......................................................... 14.3 Interface to Bus Master ..................................................................................................... 14.4 Operation .......................................................................................................................... 14.4.1 Single Mode (SCAN = 0) .................................................................................... 14.4.2 Scan Mode (SCAN = 1)....................................................................................... 14.4.3 Input Sampling and A/D Conversion Time ......................................................... 14.4.4 External Trigger Input Timing............................................................................. 14.5 Interrupts ........................................................................................................................... 14.6 Usage Notes ...................................................................................................................... 507 507 508 509 510 511 511 512 514 515 516 517 517 519 521 522 523 523 Section 15 D/A Converter ................................................................................................. 529 15.1 Overview........................................................................................................................... 529 Rev. 4.00 Feb 15, 2006 page xviii of xxiv 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 15.2.2 D/A Control Register (DACR) ............................................................................ 15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 15.3 Operation .......................................................................................................................... 15.4 Usage Notes ...................................................................................................................... 529 530 531 531 532 532 532 534 535 536 537 537 538 538 539 539 539 539 541 541 541 542 542 542 543 543 546 546 546 549 549 549 553 554 555 555 556 557 562 Section 16 RAM .................................................................................................................. 16.1 Overview........................................................................................................................... 16.1.1 Block Diagram ..................................................................................................... 16.1.2 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 System Control Register (SYSCR) ...................................................................... 16.3 Operation .......................................................................................................................... 16.4 Usage Note........................................................................................................................ Section 17 ROM .................................................................................................................. 17.1 Overview........................................................................................................................... 17.1.1 Block Diagram ..................................................................................................... 17.1.2 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 Mode Control Register (MDCR) ......................................................................... 17.2.2 Bus Control Register L (BCRL) .......................................................................... 17.3 Operation .......................................................................................................................... 17.4 PROM Mode..................................................................................................................... 17.4.1 PROM Mode Setting............................................................................................ 17.4.2 Socket Adapter and Memory Map ....................................................................... 17.5 Programming..................................................................................................................... 17.5.1 Overview.............................................................................................................. 17.5.2 Programming and Verification............................................................................. 17.5.3 Programming Precautions.................................................................................... 17.5.4 Reliability of Programmed Data .......................................................................... 17.6 Overview of Flash Memory .............................................................................................. 17.6.1 Features................................................................................................................ 17.6.2 Block Diagram ..................................................................................................... 17.6.3 Flash Memory Operating Modes ......................................................................... 17.6.4 Pin Configuration................................................................................................. Rev. 4.00 Feb 15, 2006 page xix of xxiv 17.6.5 Register Configuration......................................................................................... 17.7 Register Descriptions ........................................................................................................ 17.7.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 17.7.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 17.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 17.7.4 System Control Register 2 (SYSCR2) ................................................................. 17.7.5 RAM Emulation Register (RAMER)................................................................... 17.8 On-Board Programming Modes........................................................................................ 17.8.1 Boot Mode ........................................................................................................... 17.8.2 User Program Mode............................................................................................. 17.9 Programming/Erasing Flash Memory ............................................................................... 17.9.1 Program Mode ..................................................................................................... 17.9.2 Program-Verify Mode.......................................................................................... 17.9.3 Erase Mode .......................................................................................................... 17.9.4 Erase-Verify Mode .............................................................................................. 17.10 Flash Memory Protection.................................................................................................. 17.10.1 Hardware Protection ............................................................................................ 17.10.2 Software Protection.............................................................................................. 17.10.3 Error Protection.................................................................................................... 17.11 Flash Memory Emulation in RAM ................................................................................... 17.11.1 Emulation in RAM............................................................................................... 17.11.2 RAM Overlap ...................................................................................................... 17.12 Interrupt Handling when Programming/Erasing Flash Memory....................................... 17.13 Flash Memory Writer Mode ............................................................................................. 17.13.1 Writer Mode Setting ............................................................................................ 17.13.2 Socket Adapters and Memory Map ..................................................................... 17.13.3 Writer Mode Operation........................................................................................ 17.13.4 Memory Read Mode ............................................................................................ 17.13.5 Auto-Program Mode ............................................................................................ 17.13.6 Auto-Erase Mode................................................................................................. 17.13.7 Status Read Mode ................................................................................................ 17.13.8 Status Polling ....................................................................................................... 17.13.9 Writer Mode Transition Time .............................................................................. 17.13.10 Notes On Memory Programming..................................................................... 17.14 Flash Memory Programming and Erasing Precautions..................................................... 17.15 Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions 563 564 564 566 568 569 570 572 573 577 579 580 581 583 583 585 585 586 587 589 589 590 591 592 592 593 594 596 600 602 603 605 606 607 608 613 Section 18 Clock Pulse Generator .................................................................................. 615 18.1 Overview........................................................................................................................... 615 18.1.1 Block Diagram ..................................................................................................... 615 18.1.2 Register Configuration......................................................................................... 616 Rev. 4.00 Feb 15, 2006 page xx of xxiv 18.2 Register Descriptions ........................................................................................................ 18.2.1 System Clock Control Register (SCKCR) ........................................................... 18.3 Oscillator........................................................................................................................... 18.3.1 Connecting a Crystal Resonator........................................................................... 18.3.2 External Clock Input ............................................................................................ 18.4 Duty Adjustment Circuit................................................................................................... 18.5 Medium-Speed Clock Divider .......................................................................................... 18.6 Bus Master Clock Selection Circuit .................................................................................. 616 616 617 617 619 621 621 621 Section 19 Power-Down Modes ...................................................................................... 623 19.1 Overview........................................................................................................................... 19.1.1 Register Configuration......................................................................................... 19.2 Register Descriptions ........................................................................................................ 19.2.1 Standby Control Register (SBYCR) .................................................................... 19.2.2 System Clock Control Register (SCKCR) ........................................................... 19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 19.3 Medium-Speed Mode........................................................................................................ 19.4 Sleep Mode ....................................................................................................................... 19.5 Module Stop Mode ........................................................................................................... 19.5.1 Module Stop Mode .............................................................................................. 19.5.2 Usage Notes ......................................................................................................... 19.6 Software Standby Mode.................................................................................................... 19.6.1 Software Standby Mode....................................................................................... 19.6.2 Clearing Software Standby Mode ........................................................................ 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 19.6.4 Software Standby Mode Application Example.................................................... 19.6.5 Usage Notes ......................................................................................................... 19.7 Hardware Standby Mode .................................................................................................. 19.7.1 Hardware Standby Mode ..................................................................................... 19.7.2 Hardware Standby Mode Timing......................................................................... 19.8 φ Clock Output Disabling Function .................................................................................. 623 624 625 625 627 628 628 629 630 630 631 632 632 632 633 634 634 635 635 635 636 Section 20 Electrical Characteristics.............................................................................. 637 20.1 Electrical Characteristics of F-ZTAT Version .................................................................. 20.1.1 Absolute Maximum Ratings ................................................................................ 20.1.2 DC Characteristics ............................................................................................... 20.1.3 AC Characteristics ............................................................................................... 20.1.4 A/D Conversion Characteristics........................................................................... 20.1.5 D/A Conversion Characteristics........................................................................... 20.1.6 Flash Memory Characteristics ............................................................................. 20.2 Electrical Characteristics of ZTAT, Mask ROM, and ROMless Versions........................ 637 637 638 641 646 647 648 650 Rev. 4.00 Feb 15, 2006 page xxi of xxiv 20.2.1 Absolute Maximum Ratings ................................................................................ 20.2.2 DC Characteristics ............................................................................................... 20.2.3 AC Characteristics ............................................................................................... 20.2.4 A/D Conversion Characteristics........................................................................... 20.2.5 D/A Conversion Characteristics........................................................................... 20.3 Operation Timing.............................................................................................................. 20.3.1 Clock Timing ....................................................................................................... 20.3.2 Control Signal Timing ......................................................................................... 20.3.3 Bus Timing .......................................................................................................... 20.3.4 Timing for On-Chip Supporting Modules............................................................ 20.4 Usage Note........................................................................................................................ 650 651 656 663 664 665 665 666 667 673 676 Appendix A Instruction Set .............................................................................................. 677 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .................................................................................................................. Instruction Codes .............................................................................................................. Operation Code Map......................................................................................................... Number of States Required for Instruction Execution ...................................................... Bus States during Instruction Execution ........................................................................... Condition Code Modification ........................................................................................... 677 701 715 719 733 747 Appendix B Internal I/O Register ................................................................................... 753 B.1 B.2 Addresses .......................................................................................................................... 753 Functions........................................................................................................................... 760 Appendix C I/O Port Block Diagrams........................................................................... 862 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Port 1 Block Diagram ....................................................................................................... Port 2 Block Diagram ....................................................................................................... Port 3 Block Diagram ....................................................................................................... Port 4 Block Diagram ....................................................................................................... Port A Block Diagram....................................................................................................... Port B Block Diagram....................................................................................................... Port C Block Diagram....................................................................................................... Port D Block Diagram....................................................................................................... Port E Block Diagram ....................................................................................................... Port F Block Diagram ....................................................................................................... Port G Block Diagram....................................................................................................... 862 866 870 873 874 875 876 877 878 879 887 Appendix D Pin States ....................................................................................................... 891 D.1 Port States in Each Mode .................................................................................................. 891 Rev. 4.00 Feb 15, 2006 page xxii of xxiv Appendix E Timing of Transition to and Recovery from Hardware Standby Mode .............................................................................................. 895 Appendix F Product Code Lineup ................................................................................. 896 Appendix G Package Dimensions .................................................................................. 897 Rev. 4.00 Feb 15, 2006 page xxiii of xxiv Rev. 4.00 Feb 15, 2006 page xxiv of xxiv Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2345 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), an 8-bit timer, a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, and I/O ports. 1 2 The on-chip ROM* is either single power supply flash memory (F-ZTAT™* ), PROM 2 (ZTAT®* ), or mask ROM, with a capacity of 128, 96, 64, or 32 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and single-chip mode or external expansion mode. The features of the H8S/2345 Group are shown in table 1.1. Notes: 1. The H8S/2345, H8S/2344, H8S/2343, and H8S/2341 have on-chip ROM. The H8S/2340 does not have on-chip ROM. 2. F-ZTAT is a trademark of Renesas Technology Corp. ZTAT is a registered trademark of Renesas Technology Corp. Rev. 4.00 Feb 15, 2006 page 1 of 900 REJ09B0291-0400 Section 1 Overview Table 1.1 Item CPU Overview Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 × 16-bit register-register multiply : 1000 ns 32 ÷ 16-bit register-register divide : 1000 ns • Instruction set suitable for high-speed operation  Sixty-five basic instructions  8/16/32-bit move/arithmetic and logic instructions  Unsigned/signed multiply and divide instructions  Powerful bit-manipulation instructions • Two CPU operating modes  Normal mode: 64-kbyte address space (ZTAT, mask ROM, and ROMless versions only)  Advanced mode: 16-Mbyte address space Bus controller • • • • • • • Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for areas 0 to 3 Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer is possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC Data transfer controller (DTC) • • • • Rev. 4.00 Feb 15, 2006 page 2 of 900 REJ09B0291-0400 Section 1 Overview Item 16-bit timer-pulse unit (TPU) Specification • • • 8-bit timer 2 channels • • • Watchdog timer Serial communication interface (SCI) 2 channels A/D converter • • • • • • • • • • D/A converter I/O ports Memory • • • • • 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins' Automatic 2-phase encoder count capability 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels High-speed conversion: 6.7 µs minimum conversion time (at 20-MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 71 I/O pins, 8 input-only pins Flash memory, PROM, or mask ROM High-speed static RAM ROM 128 kbytes 96 kbytes 64 kbytes 32 kbytes — RAM 4 kbytes 4 kbytes 2 kbytes 2 kbytes 2 kbytes Product Name H8S/2345 H8S/2344 H8S/2343 H8S/2341 H8S/2340 Interrupt controller • • • Nine external interrupt pins (NMI, IRQ0 to IRQ7) 43 internal interrupt sources Eight priority levels settable Rev. 4.00 Feb 15, 2006 page 3 of 900 REJ09B0291-0400 Section 1 Overview Item Power-down state Specification • • • • • Operating modes • Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Eight MCU operating modes (F-ZTAT version) External Data Bus On-Chip Initial ROM Value — — Maximum Value — CPU Operating Mode Mode Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Advanced User-programmable mode — — Advanced Boot mode — — — Advanced On-chip ROM disabled Disabled 16 bits expansion mode 8 bits On-chip ROM enabled expansion mode Single-chip mode — — Enabled — Enabled Enabled 8 bits — — 8 bits — — 8 bits — 16 bits 16 bits 16 bits — — 16 bits — — 16 bits — Rev. 4.00 Feb 15, 2006 page 4 of 900 REJ09B0291-0400 Section 1 Overview Item Operating modes Specification • Seven MCU operating modes (ZTAT, mask ROM, and ROMless versions) External Data Bus On-Chip Initial ROM Value Maximum Value 16 bits 16 bits CPU Operating Mode Mode Description 1 2* 3* 4 5 6* 7* Note: Clock pulse generator Packages Product lineup Mask ROM Version HD6432345 HD6432344 HD6432343 HD6432341 HD6412340 (ROMless versions) • • • * Normal On-chip ROM disabled Disabled 8 bits expansion mode On-chip ROM enabled expansion mode Single-chip mode Enabled Enabled 8 bits — Advanced On-chip ROM disabled Disabled 16 bits expansion mode On-chip ROM disabled Disabled 8 bits expansion mode On-chip ROM enabled expansion mode Single-chip mode Not used on ROMless versions. Enabled Enabled 8 bits — 16 bits 16 bits 16 bits Built-in duty correction circuit 100-pin plastic TQFP (TFP-100B, TFP-100G) 100-pin plastic QFP (FP-100A, FP-100B) Model Name F-ZTAT HD64F2345 — — — — ZTAT HD6472345 — — — — ROM/RAM (Bytes) 128 k/4 k 96 k/4 k 64 k/2 k 32 k/2 k —/2 k Packages TFP-100B TFP-100G FP-100A FP-100B Rev. 4.00 Feb 15, 2006 page 5 of 900 REJ09B0291-0400 Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2345 Group. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC VCC VCC VSS VSS VSS VSS VSS VSS Port D Port E H8S/2000 CPU Internal address bus Internal data bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF (FWE)*1 NMI Clock pulse generator Port A PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16 Interrupt controller PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR/ IRQ3 PF2 / WAIT/ IRQ2 PF1 / BACK/ IRQ1 PF0 / BREQ/ IRQ0 PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3/ IRQ7 PG0 / ADTRG/ IRQ6 DTC ROM*2 Port F Peripheral address bus Port B Peripheral data bus PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8 PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 P35 /SCK1/IRQ5 P34 /SCK0/IRQ4 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 Port C RAM Port G WDT 8-bit timer Port 3 SCI TPU D/A converter A/D converter Port 1 Port 2 Vref AVCC AVSS Port 4 P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 P10 / TIOCA0 / A 2 0 P11 / TIOCB0 / A 2 1 P12 / TIOCC0 / TCLKA/A2 2 P13 / TIOCD0 / TCLKB/A2 3 P14 / TIOCA1 P15 / TIOCB1 / TCLKC P16 / TIOCA2 P17 / TIOCB2 / TCLKD Notes: 1. Functions as WDTOVF pin on ZTAT, mask ROM, and ROMless versions. Functions as FWE pin on F-ZTAT version, not as WDTOVF pin. 2. Not present on ROMless version. Figure 1.1 Block Diagram Rev. 4.00 Feb 15, 2006 page 6 of 900 REJ09B0291-0400 P20 / TIOCA3 P21 / TIOCB3 P22 / TIOCC3 / T M R I 0 P23 / TIOCD3 / T M C I 0 P24 / TIOCA4 / T M R I 1 P25 / TIOCB4 / T M C I 1 P26 / TIOCA5 / T M O 0 P27 / TIOCB5 / T M O 1 Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement Figures 1.2 and 1.3 show the pin arrangement of the H8S/2345 Group. P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0 WDTOVF (FWE*) PF1/BACK/IRQ1 PF2/WAIT/IRQ2 PF3/LWR/IRQ3 P21/TIOCB3 PF4/HWR P20/TIOCA3 PA3/A19 53 PA2/A18 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PF0/BREQ/IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC P10/TIOCA0/A20 P11/TIOCB0/A21 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 51 PA1/A17 PF5/RD PF6/AS EXTAL STBY PF7/φ XTAL RES MD2 MD1 MD0 VCC NMI VSS 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PA0/A16 VSS PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 VCC PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 VSS PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 P15/TIOCB1/TCLKC P17/TIOCB2/TCLKD P14/TIOCA1 P16/TIOCA2 P30/TxD0 P31/TxD1 P34/SCK0/IRQ4 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P35/SCK1/IRQ5 P32/RxD0 P33/RxD1 PD1/D9 Note: * Functions as WDTOVF pin on ZTAT, mask ROM, and ROMless versions. Functions as FWE pin on F-ZTAT version, not as WDTOVF pin. Figure 1.2 Pin Arrangement (FP-100B, TFP-100B, TFP-100G: Top View) Rev. 4.00 Feb 15, 2006 page 7 of 900 REJ09B0291-0400 PD2/D10 VSS VSS Section 1 Overview Note: * Functions as WDTOVF pin on ZTAT, mask ROM, and ROMless versions. Functions as FWE pin on F-ZTAT version, not as WDTOVF pin. Figure 1.3 Pin Arrangement (FP-100A: Top View) Rev. 4.00 Feb 15, 2006 page 8 of 900 REJ09B0291-0400 P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Vref AVCC PF0/BREQ/IRQ0 PF1/BACK/IRQ1 PF2/WAIT/IRQ2 PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/φ VSS EXTAL XTAL VCC STBY NMI RES MD2 WDTOVF (FWE*) P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 PA0/A16 VSS 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 VCC PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 VSS PD7/D15 PD6/D14 Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2345 Group in each of the operating modes. Table 1.2 Pin No. FP-100B, TFP-100B, TFP-100G FP-100A 1 3 Pin Functions in Each Operating Mode Pin Name Flash Memory Writer Mode*4 NC Mode 1*1 P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Mode 2*1 *2 P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Mode 3*1 *2 P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0 PE1 PE2 PE3 Mode 4 P12/ TIOCC0/ TCLKA/ A22 P13/ TIOCD0/ TCLKB/ A23 P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Mode 5 P12/ TIOCC0/ TCLKA/ A22 P13/ TIOCD0/ TCLKB/ A23 P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Mode 6*2 P12/ TIOCC0/ TCLKA/ A22 P13/ TIOCD0/ TCLKB/ A23 P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Mode 7*2 P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB P14/ TIOCA1 P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PE0 PE1 PE2 PE3 PROM Mode*3 NC 2 4 NC NC 3 4 5 6 NC NC NC NC 5 6 7 8 NC NC NC NC 7 8 9 10 11 12 9 10 11 12 13 14 VSS NC NC NC NC NC VSS NC NC NC NC NC 13 15 NC NC 14 15 16 17 16 17 18 19 NC NC NC NC NC NC NC NC Rev. 4.00 Feb 15, 2006 page 9 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Name Flash Memory Writer Mode*4 VSS NC NC NC NC FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 VSS FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 VCC FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 VSS FA16 Mode 1*1 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 VSS PA0 Mode 2*1 *2 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VCC PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 VSS PA0 Mode 3*1 *2 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS PA0 Mode 4 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 Mode 5 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 Mode 6*2 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VCC PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 VSS PA0/A16 Mode 7*2 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS PA0 PROM Mode*3 VSS NC NC NC NC EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 VSS EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 VCC EA8 OE EA10 EA11 EA12 EA13 EA14 EA15 VSS EA16 Rev. 4.00 Feb 15, 2006 page 10 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A 51 52 53 54 55 56 53 54 55 56 57 58 Pin Name Flash Memory Writer Mode*4 NC NC NC OE CE WE Mode 1*1 PA1 PA2 PA3 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 2*1 *2 PA1 PA2 PA3 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 3*1 *2 PA1 PA2 PA3 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 4 A17 A18 A19 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 5 A17 A18 A19 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 6*2 PA1/A17 PA2/A18 PA3/A19 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 Mode 7*2 PA1 PA2 PA3 P20/ TIOCA3 P21/ TIOCB3 P22/ TIOCC3/ TMRI0 MD0 MD1 P23/ TIOCD3/ TMCI0 PROM Mode*3 VCC VCC NC NC NC NC 57 58 59 59 60 61 VSS VSS NC VSS VSS VCC 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC (FWE*5) (FWE*5) (FWE*5) (FWE*5) MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ AS RD HWR LWR PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ AS RD HWR LWR PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ PF6 PF5 PF4 PF3/IRQ3 PF2/IRQ2 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ AS RD HWR LWR PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ AS RD HWR LWR PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ AS RD HWR LWR PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ PF6 PF5 PF4 PF3/IRQ3 PF2/IRQ2 VSS VPP EA9 VSS VCC NC NC VSS NC NC NC NC NC CE FWE VSS RES VCC VCC VCC XTAL EXTAL VSS NC NC NC NC NC VCC 75 77 PF1/IRQ1 PF1/IRQ1 PGM VSS Rev. 4.00 Feb 15, 2006 page 11 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A 76 78 Pin Name Flash Memory Writer Mode*4 VSS Mode 1*1 PF0/ BREQ/ IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG Mode 2*1 *2 PF0/ BREQ/ IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG Mode 3*1 *2 PF0/IRQ0 Mode 4 PF0/ BREQ/ IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG Mode 5 PF0/ BREQ/ IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC Mode 6*2 PF0/ BREQ/ IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC Mode 7*2 PF0/IRQ0 PROM Mode*3 NC 77 78 79 80 81 82 83 84 85 86 87 88 89 79 80 81 82 83 84 85 86 87 88 89 90 91 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P24/ TIOCA4/ TMRI1 P25/ TIOCB4/ TMCI1 P26/ TIOCA5/ TMO0 P27/ TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG VCC VCC NC NC NC NC NC NC NC NC VSS VSS NC VCC VCC NC NC NC NC NC NC NC NC VSS VSS NC 90 92 NC VCC 91 93 NC NC 92 94 NC NC 93 95 NC NC 94 95 96 97 98 96 97 98 99 100 PG1/IRQ7 PG1/IRQ7 PG1/IRQ7 PG1/CS3/ IRQ7 PG2 PG3 PG4/CS0 VCC PG2 PG3 PG4/CS0 VCC PG2 PG3 PG4 VCC PG2/CS2 PG3/CS1 PG4/CS0 VCC PG1/IRQ7 NC PG2 PG3 PG4 VCC NC NC NC VCC NC NC NC NC VCC Rev. 4.00 Feb 15, 2006 page 12 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A 99 1 Pin Name Flash Memory Writer Mode*4 NC Mode 1*1 P10/ TIOCA0 P11/ TIOCB0 Mode 2*1 *2 P10/ TIOCA0 P11/ TIOCB0 Mode 3*1 *2 P10/ TIOCA0 P11/ TIOCB0 Mode 4 P10/ TIOCA0/ A20 P11/ TIOCB0/ A21 Mode 5 P10/ TIOCA0/ A20 P11/ TIOCB0/ A21 Mode 6*2 P10/ TIOCA0/ A20 P11/ TIOCB0/ A21 Mode 7*2 P10/ TIOCA0 P11/ TIOCB0 PROM Mode*3 NC 100 2 NC NC Notes: 1. 2. 3. 4. 5. Modes 1 to 3 are not available on the F-ZTAT version. Modes 2, 3, 6, and 7 are not available on the ROMless version. ZTAT version only. F-ZTAT version only. The FWE pin is only used on the F-ZTAT version. It cannot be used as a WDTOVF pin on the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 13 of 900 REJ09B0291-0400 Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2345 Group. Table 1.3 Pin Functions Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type Power supply Symbol VCC I/O Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). Connects to a crystal oscillator. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. 40, 65, 98 42, 67, 100 VSS 7, 18, 31, 49, 68, 88 66 9, 20, 33, 51, 70, 90 68 Input Clock XTAL Input EXTAL 67 69 Input φ 69 71 Output System clock: Supplies the system clock to an external device. Rev. 4.00 Feb 15, 2006 page 14 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type Symbol I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2345 Group is operating. • F-ZTAT Version Operating FWE MD2 MD1 MD0 Mode 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 — — — — Mode 4 Mode 5 Mode 6 Mode 7 — — Mode 10 Mode 11 — — Mode 14 Mode 15 Operating mode MD2 to control MD0 61, 58, 57 63, 60, 59 Rev. 4.00 Feb 15, 2006 page 15 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type Symbol I/O Input Name and Function • ZTAT, mask ROM, and ROMless versions MD1 0 1 1 0 1 Note: * MD0 0 1 0 1 0 1 0 1 Operating Mode — Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7* Operating mode MD2 to control MD0 61, 58, 57 63, 60, 59 MD2 0 Not used on ROMless version. System control RES 62 64 Input Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2345 Group. STBY 64 66 Input BREQ 76 78 Input BACK 75 77 Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Flash write enable: Enables or disables writing to flash memory. 1 FWE* 60 62 Rev. 4.00 Feb 15, 2006 page 16 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type Interrupts Symbol NMI I/O Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. 63 65 IRQ7 to IRQ0 Address bus A23 to A0 94, 93, 13, 12, 73 to 76 2, 1, 100, 99, 53 to 50, 48 to 41, 39 to 32 30 to 19, 17 to 14 94 to 97 70 96, 95, 15, 14, 75 to 78 4 to 1, 55 to 52, 50 to 43, 41 to 34 32 to 21, 19 to 16 96 to 99 72 Input Output Address bus: These pins output an address. Data bus Bus control D15 to D0 CS3 to CS0 AS I/O Data bus: These pins constitute a bidirectional data bus. Output Chip select: Signals for selecting areas 3 to 0. Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. RD 71 73 HWR 72 74 LWR 73 75 WAIT 74 76 Rev. 4.00 Feb 15, 2006 page 17 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type 16-bit timerpulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 I/O Input I/O Name and Function Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. 6, 4, 2, 1 99, 100, 1, 2 8, 6, 4, 3 1 to 4 3, 4 5, 6 I/O TIOCA2, TIOCB2 5, 6 7, 8 I/O TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 54 to 56, 59 56 to 58, 61 I/O 89, 90 91, 92 I/O TIOCA5, TIOCB5 91, 92 93, 94 I/O 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 91, 92 59, 90 93, 94 61, 92 Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins. 56, 89 2 58, 91 62 Input Watchdog timer (WDT) WDTOVF* 60 Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Rev. 4.00 Feb 15, 2006 page 18 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type Serial communication interface (SCI) Smart Card interface Symbol TxD1, TxD0 RxD1, RxD0 SCK1 SCK0 I/O Name and Function 9, 8 11, 10 13, 12 86 to 79 93 11, 10 13, 12 15, 14 88 to 81 95 Output Transmit data (channel 0, 1): Data output pins. Input I/O Input Input Receive data (channel 0, 1): Data input pins. Serial clock (channel 0, 1): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. A/D converter AN7 to AN0 ADTRG D/A converter A/D converter and D/A converters DA1, DA0 AVCC 86, 85 77 88, 87 79 Output Analog output: D/A converter analog output pins. Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). AVSS 87 89 Input Vref 78 80 Input I/O ports P17 to P10 6 to 1, 100, 99 8 to 1 I/O P27 to P20 92 to 89, 59, 56 to 54 94 to 91, 61, 58 to 56 I/O Rev. 4.00 Feb 15, 2006 page 19 of 900 REJ09B0291-0400 Section 1 Overview Pin No. FP-100B, TFP-100B, TFP-100G FP-100A Type I/O ports Symbol P35 to P30 I/O I/O Name and Function Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port A: An 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). 13 to 8 15 to 10 P47 to P40 PA3 to PA0 86 to 79 53 to 50 88 to 81 55 to 52 Input I/O PB7 to PB0 48 to 41 50 to 43 I/O PC7 to PC0 39 to 32 41 to 34 I/O PD7 to PD0 30 to 23 32 to 25 I/O PE7 to PE0 22 to 19, 17 to 14 24 to 21, 19 to 16 I/O PF7 to PF0 69 to 76 71 to 78 I/O PG4 to PG0 97 to 93 99 to 95 I/O Notes: 1. F-ZTAT version only. 2. Applies to ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 20 of 900 REJ09B0291-0400 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H object programs • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-five basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions • Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8] • 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes (4 Gbytes architecturally) Rev. 4.00 Feb 15, 2006 page 21 of 900 REJ09B0291-0400 Section 2 CPU • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate  8 × 8-bit register-register multiply  16 ÷ 8-bit register-register divide  16 × 16-bit register-register multiply  32 ÷ 16-bit register-register divide • Two CPU operating modes  Normal mode (Supported on ZTAT, mask ROM, and ROMless versions only)  Advanced mode • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU : 20 MHz : 600 ns : 600 ns : 1000 ns : 1000 ns  8/16/32-bit register-register add/subtract : 50 ns The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of execution states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, CCR and EXR register functions, power-down state, etc., depending on the product. Rev. 4.00 Feb 15, 2006 page 22 of 900 REJ09B0291-0400 Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space  Normal mode supports the same 64-kbyte address space as the H8/300 CPU. (ZTAT, mask ROM, and ROMless versions only)  Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been added.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register  One 8-bit control register has been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. Rev. 4.00 Feb 15, 2006 page 23 of 900 REJ09B0291-0400 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Maximum 64 kbytes, program and data areas combined Normal mode (Supported on ZTAT, mask ROM, and ROMless versions only) CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Figure 2.1 CPU Operating Modes (1) Normal Mode (ZTAT, Mask ROM, and ROMless Versions Only) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev. 4.00 Feb 15, 2006 page 24 of 900 REJ09B0291-0400 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev. 4.00 Feb 15, 2006 page 25 of 900 REJ09B0291-0400 Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev. 4.00 Feb 15, 2006 page 26 of 900 REJ09B0291-0400 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev. 4.00 Feb 15, 2006 page 27 of 900 REJ09B0291-0400 Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.5 Stack Structure in Advanced Mode Rev. 4.00 Feb 15, 2006 page 28 of 900 REJ09B0291-0400 Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode*, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. Note: * ZTAT, mask ROM, and ROMless versions only. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2345 Group H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * ZTAT, mask ROM, and ROMless versions only. Figure 2.6 Memory Map Rev. 4.00 Feb 15, 2006 page 29 of 900 REJ09B0291-0400 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * In the H8S/2345 Group, this bit cannot be used as an interrupt mask. Figure 2.7 CPU Registers Rev. 4.00 Feb 15, 2006 page 30 of 900 REJ09B0291-0400 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) (E0 to E7) • 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Rev. 4.00 Feb 15, 2006 page 31 of 900 REJ09B0291-0400 Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. Rev. 4.00 Feb 15, 2006 page 32 of 900 REJ09B0291-0400 Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2345 Group, this bit cannot be used as an interrupt mask bit. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Rev. 4.00 Feb 15, 2006 page 33 of 900 REJ09B0291-0400 Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 4.00 Feb 15, 2006 page 34 of 900 REJ09B0291-0400 Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don’t care 1-bit data RnL Don’t care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don’t care 4-bit BCD data RnL Don’t care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don’t care LSB 7 Don’t care Byte data RnL 0 LSB MSB Figure 2.10 General Register Data Formats Rev. 4.00 Feb 15, 2006 page 35 of 900 REJ09B0291-0400 Section 2 CPU Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Rev. 4.00 Feb 15, 2006 page 36 of 900 REJ09B0291-0400 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 4.00 Feb 15, 2006 page 37 of 900 REJ09B0291-0400 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* LDM, STM 3 MOVFPE, MOVTPE* Size BWL WL L B BWL B BWL L BW WL B BWL BWL B — — — Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS 19 Logic operations Shift Bit manipulation Branch System control Block data transfer Legend: AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 4 8 14 5 9 1 B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2345 Group. Rev. 4.00 Feb 15, 2006 page 38 of 900 REJ09B0291-0400 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @(d:8,PC) Function Instruction @ERn @(d:16,PC) @@aa:8 — — — — — — — — — — — — — — — — — — — — — @aa:16 @aa:24 @aa:32 @aa:8 #xx Rn Data transfer MOV POP, PUSH LDM, STM MOVFPE*, MOVTPE* BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — — — — — — — — B — — — B — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — B — — — — — — — — — — — — — — — — — B — — — BWL — — B — — — — — — — — — — — — — — B — — — — — — — — — — — — — — — — — — — — — — — BWL — — — — — — — — — — — — — — — — — B — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — WL L — — — — — — — — — — — — — — — — — — Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS BWL BWL WL B — — — — — — — — BWL B L BWL B BW BW BWL WL — Logic operations AND, OR, XOR NOT BWL BWL — — — — — — BWL BWL B — — — Shift Bit manipulation Branch Bcc, BSR JMP, JSR RTS — — — — — — Rev. 4.00 Feb 15, 2006 page 39 of 900 REJ09B0291-0400 — Section 2 CPU Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 — — — — — — — — @aa:16 @aa:24 @aa:32 @aa:8 Rn System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP — — — B — B — — — — — B B — — — — — — W W — — — — — — W W — — — — — — W W — — — — — — W W — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — Block data transfer BW Legend: B: Byte W: Word L: Longword Note: * Cannot be used in the H8S/2345 Group. Rev. 4.00 Feb 15, 2006 page 40 of 900 REJ09B0291-0400 — Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 4.00 Feb 15, 2006 page 41 of 900 REJ09B0291-0400 Section 2 CPU Table 2.3 Type Instructions Classified by Function Instruction Size* B/W/L Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2345 Group. Cannot be used in the H8S/2345 Group. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Data transfer MOV MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Arithmetic operations ADD SUB L L B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS L Rev. 4.00 Feb 15, 2006 page 42 of 900 REJ09B0291-0400 Section 2 CPU Type Arithmetic operations Instruction DAA DAS Size* B Function Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd – 0, 1 → ( of @Erd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MULXU B/W MULXS B/W DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B Rev. 4.00 Feb 15, 2006 page 43 of 900 REJ09B0291-0400 Section 2 CPU Type Logic operations Instruction AND Size* B/W/L Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. OR B/W/L XOR B/W/L NOT Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BitBSET manipulation instructions BCLR B/W/L B/W/L B/W/L B/W/L B/W/L B B BNOT B BTST B Rev. 4.00 Feb 15, 2006 page 44 of 900 REJ09B0291-0400 Section 2 CPU Type Instruction Size* B Function C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. BitBAND manipulation instructions BIAND B BOR B BIOR B BXOR B BIXOR B BLD B BILD B BST B BIST B Rev. 4.00 Feb 15, 2006 page 45 of 900 REJ09B0291-0400 Section 2 CPU Type Branch instructions Instruction Bcc Size* — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS System control instructions TRAPA RTE SLEEP LDC — — — — — — — B/W Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z∨(N ⊕ V) = 0 Z∨(N ⊕ V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. Rev. 4.00 Feb 15, 2006 page 46 of 900 REJ09B0291-0400 Section 2 CPU Type System control instructions Instruction STC Size* B/W Function CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, wordsize transfers are performed between them and memory. The upper 8 bits are valid. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Note: * Size refers to the operand size. B: Byte W: Word L: Longword ANDC B ORC B XORC B NOP Block data transfer instruction EEPMOV.B — — EEPMOV.W — Rev. 4.00 Feb 15, 2006 page 47 of 900 REJ09B0291-0400 Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. Rev. 4.00 Feb 15, 2006 page 48 of 900 REJ09B0291-0400 Section 2 CPU 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 4.00 Feb 15, 2006 page 49 of 900 REJ09B0291-0400 Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address Note: * 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 50 of 900 REJ09B0291-0400 Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode* the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 51 of 900 REJ09B0291-0400 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * ZTAT, mask ROM, and ROMless versions only. (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 52 of 900 REJ09B0291-0400 Section 2 CPU Table 2.6 No. 1 Effective Address Calculation Effective Address Calculation Effective Address (EA) Operand is general register contents. Addressing Mode and Instruction Format Register direct (Rn) op rm rn 2 Register indirect (@ERn) 31 General register contents op r 0 31 24 23 0 Don’t care 3 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 31 General register contents 31 op r disp 31 Sign extension disp 0 24 23 0 Don’t care 0 4 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don’t care op r 1, 2, or 4 • Register indirect with pre-decrement @–ERn 31 General register contents 31 op r Operand Size Byte Word Longword Value Added 1 2 4 1, 2, or 4 24 23 0 Don’t care 0 Rev. 4.00 Feb 15, 2006 page 53 of 900 REJ09B0291-0400 Section 2 CPU Addressing Mode and Instruction Format Absolute address @aa:8 op abs 31 24 23 H'FFFF 87 0 Don’t care No. 5 Effective Address Calculation Effective Address (EA) @aa:16 op abs 31 Don’t care 24 23 16 15 Sign extension 0 @aa:24 op abs 31 24 23 0 Don’t care @aa:32 op abs 31 24 23 0 Don’t care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don’t care Rev. 4.00 Feb 15, 2006 page 54 of 900 REJ09B0291-0400 Section 2 CPU Addressing Mode and Instruction Format Memory indirect @@aa:8 • Normal mode* op abs No. 8 Effective Address Calculation Effective Address (EA) 31 H'000000 87 abs 0 31 24 23 16 15 0 Don’t care 15 Memory contents 0 H'00 • Advanced mode op abs 31 H'000000 87 abs 0 31 Memory contents 0 31 24 23 0 Don’t care Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 55 of 900 REJ09B0291-0400 Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2.14 Processing States Rev. 4.00 Feb 15, 2006 page 56 of 900 REJ09B0291-0400 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with SSBY = 1 SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11, Watchdog Timer. Rev. 4.00 Feb 15, 2006 page 57 of 900 REJ09B0291-0400 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 3 executed* Trace End of instruction execution or end of exception-handling 1 sequence* End of instruction execution or end of exception-handling 2 sequence* When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev. 4.00 Feb 15, 2006 page 58 of 900 REJ09B0291-0400 Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. Rev. 4.00 Feb 15, 2006 page 59 of 900 REJ09B0291-0400 Section 2 CPU Normal mode*1 SP SP CCR CCR*2 PC (16 bits) EXR Reserved*2 CCR CCR*2 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*2 CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. ZTAT, mask ROM, and ROMless versions only. 2. Ignored when returning. (d) Interrupt control mode 2 Figure 2.16 Stack Structure after Exception Handling (Examples) Rev. 4.00 Feb 15, 2006 page 60 of 900 REJ09B0291-0400 Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 19, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Rev. 4.00 Feb 15, 2006 page 61 of 900 REJ09B0291-0400 Section 2 CPU 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 φ Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.17 On-Chip Memory Access Cycle Rev. 4.00 Feb 15, 2006 page 62 of 900 REJ09B0291-0400 Section 2 CPU Bus cycle T1 φ Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.18 Pin States during On-Chip Memory Access Rev. 4.00 Feb 15, 2006 page 63 of 900 REJ09B0291-0400 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 T2 φ Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.19 On-Chip Supporting Module Access Cycle Rev. 4.00 Feb 15, 2006 page 64 of 900 REJ09B0291-0400 Section 2 CPU Bus cycle T1 T2 φ Unchanged Address bus AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. Rev. 4.00 Feb 15, 2006 page 65 of 900 REJ09B0291-0400 Section 2 CPU Rev. 4.00 Feb 15, 2006 page 66 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection (F-ZTAT™ Version) The H8S/2345 Group has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3.1. Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 1 1 0 0 1 1 0 1 MCU Operating Mode Selection (F-ZTAT™ Version) CPU Operating Mode — External Data Bus Description — On-Chip ROM — Initial Width — Max. Width — FWE MD2 0 0 MD1 0 MD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Advanced On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Disabled 16 bits 8 bits 16 bits 16 bits 16 bits — — Enabled 8 bits — — — — — Advanced Boot mode Enabled 8 bits — 16 bits — — — — — — Advanced User program mode Enabled 8 bits — 16 bits — The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2345 Group actually accesses a maximum of 16 Mbytes. Rev. 4.00 Feb 15, 2006 page 67 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. Modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. For details, see section 17, ROM. The H8S/2345 Group can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, and ROMless Versions) The H8S/2345 Group has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.2 lists the MCU operating modes. Rev. 4.00 Feb 15, 2006 page 68 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Table 3.2 MCU Operating Mode 0 1 2* 3* 4 5 6* 7* 1 MCU Operating Mode Selection CPU Operating Mode — Normal External Data Bus Description — On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Advanced On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Disabled On-Chip ROM — Disabled Enabled Initial Width — 8 bits 8 bits — 16 bits 8 bits Enabled 8 bits — 16 bits 16 bits 16 bits 16 bits 16 bits Max. Width MD2 0 MD1 0 MD0 0 1 1 0 1 0 0 1 1 0 1 Note: * Not used on ROMless version. The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2345 Group actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2345 Group can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.3 Register Configuration The H8S/2345 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 2 (SYSCR2)* that control the operation of the H8S/2345 Group. Table 3.3 summarizes these registers. Rev. 4.00 Feb 15, 2006 page 69 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Table 3.3 Name MCU Registers Abbreviation MDCR SYSCR SYSCR2 R/W R R/W R/W Initial Value Undetermined H'01 H'00 1 Address* Mode control register System control register 2 System control register 2* H'FF3B H'FF39 H'FF42 Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the F-ZTAT version. In the ZTAT, mask ROM, and ROMless versions, this register cannot be written to and will return an undefined value of read. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value: R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2345 Group. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. Rev. 4.00 Feb 15, 2006 page 70 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.2.2 Bit System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 R/W 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 R/W 1 — 0 R/W 0 RAME 1 R/W Initial value: R/W : Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bits 2 and 1—Reserved: Only 0 should be written to these bits. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev. 4.00 Feb 15, 2006 page 71 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.2.3 Bit System Control Register 2 (SYSCR2) (F-ZTAT Version Only) : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return an undefined value if read. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 17, ROM. Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: Read-only bits, always read as 0. Rev. 4.00 Feb 15, 2006 page 72 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 (ZTAT, Mask ROM, and ROMless Versions Only) The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.2 Mode 2* (ZTAT and Mask ROM Versions Only) 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set. immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.3 Mode 3* (ZTAT and Mask ROM Versions Only) 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.4 Mode 4* 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as inputs immediately after a reset. Each of these pins can be set to output addresses by setting the corresponding bit in the data direction register (DDR) to 1. Rev. 4.00 Feb 15, 2006 page 73 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.5 Mode 5* 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, ports A, B, and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as inputs immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6* 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, ports A, B, and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if any area is designated as 16-bit access space by the bus controller, 16-bit bus mode is set and port E becomes a data bus. 3.3.7 Mode 7* 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Notes: 1. Not used on ROMless version. 2. The upper address pins (A23 to A20) cannot be used as outputs in mode 4 or 5 immediately after a reset. To use the upper address pins (A23 to A20) as outputs, it is necessary to first set the corresponding bits in the port 1 data direction register (P1DDR) to 1. Rev. 4.00 Feb 15, 2006 page 74 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.3.8 Modes 8 and 9 (F-ZTAT Version Only) Modes 8 and 9 are not supported in the H8S/2345 Group, and must not be set. 3.3.9 Mode 10 (F-ZTAT Version Only) This is a flash memory boot mode. For details, see section 17, ROM. MCU operation is the same as in mode 6. 3.3.10 Mode 11 (F-ZTAT Version Only) This is a flash memory boot mode. For details, see section 17, ROM. MCU operation is the same as in mode 7. 3.3.11 Modes 12 and 13 Modes 12 and 13 are not supported in the H8S/2345 Group, and must not be set. 3.3.12 Mode 14 (F-ZTAT Version Only) This is a flash memory user program mode. For details, see section 17, ROM. MCU operation is the same as in mode 6. 3.3.13 Mode 15 (F-ZTAT Version Only) This is a flash memory user program mode. For details, see section 17, ROM. MCU operation is the same as in mode 7. Rev. 4.00 Feb 15, 2006 page 75 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Pin Functions in Each Mode 3 3 Mode 6* Mode 7* 4 4 Mode 10* Mode 11* *4 Mode 15*4 Mode 14 1 P* /T/A 1 P* /A 1 P* /A 1 P* /A 1 P* /T Port Port 1 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF3 PF2 to PF0 P13 to P10 PA3 to PA0 Mode 1* Mode 2* Mode 3* Mode 4 2 3 3 1 P* /T 1 P* /T 1 P* /T 1 P* /T/A Mode 5 1 P* /T/A P A A D 1 P* /D 1 P/C* P 1 P* /A 1 P* /A P P P P P 1 P* /C P A A A D P/D 1 P/C* C 1 P* /C A A A D 1 P* /D 1 P/C* P P P P P 1 P* /C P D 1 P* /D 1 P/C* D 1 P* /D 1 P/C* C 1 P* /C C 1 P* /C C 1 P* /C C 1 P* /C Legend: P: I/O port T: Timer I/O A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. 2. 3. 4. After reset Not used on F-ZTAT. Not used on ROMless version. Applies to F-ZTAT version only. Rev. 4.00 Feb 15, 2006 page 76 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes 3.5 Memory Map in Each Operating Mode Memory maps for the H8S/2345, H8S/2344, H8S/2343, H8S/2341, and H8S/2340 are shown in figure 3.1 to figure 3.5. The address space is 64 kbytes in modes 1 to 3 (normal modes)*, and 16 Mbytes in modes 4 to 7, 10, 11, 14, and 15 (advanced modes). The on-chip ROM capacity of the H8S/2345 is 128 kbytes, that of the H8S/2344 96 kbytes, and that of the H8S/2343 64 kbytes. However, only 56 kbytes are available in modes 2 and 3 (normal modes)*. The address space is divided into eight areas for modes 4 to 6, 10, and 14. For details, see section 6, Bus Controller. Note: * Not available on F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 77 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 1*2 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2*2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3*2 (normal single-chip mode) H'0000 External address space On-chip ROM On-chip ROM H'EC00 On-chip RAM*1 H'FC00 External address space H'DFFF H'E000 External address space H'EC00 On-chip RAM*1 H'DFFF H'EC00 On-chip RAM H'FBFF H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers External address H'FF08 space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 2. Not available on F-ZTAT version. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2345 Rev. 4.00 Feb 15, 2006 page 78 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'FFEC00 On-chip RAM*3 H'FFFC00 External address space H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3 H'01FFFF H'FFEC00 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. When the EAE bit in BCRL is set to 1, this area is reserved. When the EAE bit is cleared to 0, it is on-chip ROM. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2345 (cont) Rev. 4.00 Feb 15, 2006 page 79 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 10*4 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11*4 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3 H'01FFFF H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. When the EAE bit in BCRL is set to 1, this area is reserved. When the EAE bit is cleared to 0, it is on-chip ROM. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0 in SYSCR. 4. Modes 10 and 11 are provided in the F-ZTAT version only. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2345 (cont) Rev. 4.00 Feb 15, 2006 page 80 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 14*4 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15*4 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3 H'01FFFF H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. When the EAE bit in BCRL is set to 1, this area is reserved. When the EAE bit is cleared to 0, it is on-chip ROM. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0 in SYSCR. 4. Modes 14 and 15 are provided in the F-ZTAT version only. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2345 (cont) Rev. 4.00 Feb 15, 2006 page 81 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 External address space On-chip ROM On-chip ROM H'EC00 On-chip RAM* H'FC00 External address space H'DFFF H'E000 External address space H'EC00 On-chip RAM* H'FC00 External address space H'DFFF H'EC00 On-chip RAM H'FBFF H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 Memory Map in Each Operating Mode in the H8S/2344 Rev. 4.00 Feb 15, 2006 page 82 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 On-chip ROM/ external address space*1 H'017FFF H'018000 Reserved area/ external address space*2 H'01FFFF H'020000 External address space H'FFEC00 H'00FFFF H'010000 On-chip ROM/ reserved area*3 H'017FFF H'018000 Reserved area H'01FFFF H'FFEC00 On-chip RAM*4 H'FFFC00 External address space H'FFEC00 On-chip RAM H'FFFBFF On-chip RAM*4 H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is a reserved area. 3. This area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when the EAE bit is cleared to 0. 4. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 Memory Map in Each Operating Mode in the H8S/2344 (cont) Rev. 4.00 Feb 15, 2006 page 83 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 On-chip ROM External address space On-chip ROM H'EC00 H'F400 H'FC00 Reserved area* On-chip RAM* External address space H'DFFF H'E000 External address space H'EC00 Reserved area* H'F400 On-chip RAM* H'FC00 External address space H'DFFF H'F400 H'FBFF On-chip RAM H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 Memory Map in Each Operating Mode in the H8S/2343 Rev. 4.00 Feb 15, 2006 page 84 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF External address space/reserved area*1 H'FFEC00 H'FFF400 H'FFFC00 Reserved area*2 On-chip RAM*2 External address space H'01FFFF H'020000 External address space H'FFEC00 Reserved area*2 H'FFF400 H'FFFC00 On-chip RAM*2 External address space H'FFF400 H'FFFBFF On-chip RAM H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 Memory Map in Each Operating Mode in the H8S/2343 (cont) Rev. 4.00 Feb 15, 2006 page 85 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'7FFF H'8000 H'7FFF Reserved area H'EC00 H'F400 H'FC00 Reserved area* On-chip RAM* External address space H'DFFF H'E000 External address space H'EC00 Reserved area* H'F400 On-chip RAM* H'FC00 External address space H'F400 H'FBFF On-chip RAM H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 Memory Map in Each Operating Mode in the H8S/2341 Rev. 4.00 Feb 15, 2006 page 86 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'007FFF H'008000 Reserved area External address space H'007FFF H'00FFFF H'010000 External address space/reserved area*1 H'FFEC00 H'FFF400 H'FFFC00 Reserved area*2 On-chip RAM*2 External address space H'01FFFF H'020000 External address space H'FFEC00 Reserved area*2 H'FFF400 H'FFFC00 On-chip RAM*2 External address space H'FFF400 H'FFFBFF On-chip RAM H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 Memory Map in Each Operating Mode in the H8S/2341 (cont) Rev. 4.00 Feb 15, 2006 page 87 of 900 REJ09B0291-0400 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 H'EC00 H'F400 Reserved area* On-chip RAM* External address space H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF H'FFEC00 H'FFF400 Reserved area* On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 Memory Map in Each Operating Mode in the H8S/2340 (Modes 1, 4, and 5 Only) Rev. 4.00 Feb 15, 2006 page 88 of 900 REJ09B0291-0400 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has 2 been issued* 3 1 Trace* Interrupt Low Trap instruction (TRAPA)* Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 4.00 Feb 15, 2006 page 89 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Trace Exception sources Interrupts Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 43 interrupt sources in on-chip supporting modules Trap instruction Figure 4.1 Exception Sources In modes 6 and 7 in the H8S/2345, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte area comprising addresses H'000000 to H'01FFFF to be used. Rev. 4.00 Feb 15, 2006 page 90 of 900 REJ09B0291-0400 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Power-on reset Manual reset Reserved for system use Vector Number 0 1 2 3 4 Normal Mode* 3 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063  H'015C to H'015F H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0006 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031  H'00AE to H'00AF Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) 5 6 7 8 9 10 11 Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24  87 2 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 3. ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 91 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2345 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2345 Group can also be reset by overflow of the watchdog timer. For details see section 11, Watchdog Timer. 4.2.2 Reset Types A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4.3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4.3 Reset Types Reset Transition Conditions Type Power-on reset Manual reset NMI High Low RES Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. Rev. 4.00 Feb 15, 2006 page 92 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.2.3 Reset Sequence The H8S/2345 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2345 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2345 Group during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2345 Group starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. Vector Internal Prefetch of first program fetch processing instruction φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) (2) (1) (3) High (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.2 Reset Sequence (Modes 2 and 3) Rev. 4.00 Feb 15, 2006 page 93 of 900 REJ09B0291-0400 Section 4 Exception Handling Vector fetch Internal Prefetch of first processing program instruction * * φ RES Address bus RD HWR, LWR D15 to D0 * (1) (3) (5) High (2) (4) (6) (1) (3) (2) (4) (5) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCR is initialized to H'3FFF and all modules except the DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev. 4.00 Feb 15, 2006 page 94 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR I 1 UI — I2 to I0 — EXR T 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Trace exception handling cannot be used. Rev. 4.00 Feb 15, 2006 page 95 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 43 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) Internal interrupts WDT* (1) TPU (26) 8-bit timer (6) SCI (8) DTC (1) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts Rev. 4.00 Feb 15, 2006 page 96 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling CCR I 1 1 UI — — I2 to I0 — — EXR T — 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Rev. 4.00 Feb 15, 2006 page 97 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes) (ZTAT, Mask ROM, and ROMless Versions Only) SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes) Rev. 4.00 Feb 15, 2006 page 98 of 900 REJ09B0291-0400 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2345 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd Rev. 4.00 Feb 15, 2006 page 99 of 900 REJ09B0291-0400 Section 4 Exception Handling Rev. 4.00 Feb 15, 2006 page 100 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2345 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.  NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses  All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts  NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI.  Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC control  DTC activation is performed by means of interrupts. Rev. 4.00 Feb 15, 2006 page 101 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI I2 to I0 Interrupt request Vector number CPU Internal interrupt request WOVI to TEI CCR EXR IPR Interrupt controller Legend: ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 4.00 Feb 15, 2006 page 102 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ7 to IRQ0 Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 1 Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 103 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 R/W 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 R/W 1 — 0 R/W 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Rev. 4.00 Feb 15, 2006 page 104 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value: R/W : The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Note: * 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer —* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 —* SCI channel 1 Reserved bits. Only 1 should be written to these bits. 2 to 0 IRQ1 IRQ4 IRQ5 DTC —* A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 —* Rev. 4.00 Feb 15, 2006 page 105 of 900 REJ09B0291-0400 Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit : 7 IRQ7E Initial value: R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) Rev. 4.00 Feb 15, 2006 page 106 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W : ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input Rev. 4.00 Feb 15, 2006 page 107 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value: R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] • • • • 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) [Setting conditions] • • • • Rev. 4.00 Feb 15, 2006 page 108 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2345 Group from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n: 7 to 0 IRQn interrupt S R Q request Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Rev. 4.00 Feb 15, 2006 page 109 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 43 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Rev. 4.00 Feb 15, 2006 page 110 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source External pin Vector Address*1 Vector Number 7 16 17 18 19 20 21 22 23 DTC Watchdog timer — A/D — 24 25 26 27 28 29 30 31 32 33 34 35 36 — 37 38 39 Normal Mode*2 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to 4 IPRE2 to 0 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPRC2 to 0 IPRD6 to 4 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) Reserved ADI (A/D conversion end) Reserved TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved TPU channel 0 Low Rev. 4.00 Feb 15, 2006 page 111 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Origin of Interrupt Source TPU channel 1 Vector Address*1 Vector Number 40 41 42 43 TPU channel 2 44 45 46 47 TPU channel 3 48 49 50 51 52 — 53 54 55 56 57 58 59 TPU channel 5 60 61 62 63 Normal Mode*2 H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC Low IPRH2 to 0 IPRH6 to 4 IPRG2 to 0 IPRG6 to 4 IPR IPRF2 to 0 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 1) Reserved TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) TPU channel 4 Rev. 4.00 Feb 15, 2006 page 112 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Origin of Interrupt Source 8-bit timer channel 0 Vector Address*1 Vector Number 64 65 66 — 8-bit timer channel 1 67 68 69 70 — 71 72 73 74 75 76 77 78 79 80 81 82 83 SCI channel 1 84 85 86 87 Normal Mode*2 H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C Low IPRK6 to 4 IPRI2 to 0 IPR IPRI6 to 4 Priority High Interrupt Source CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) SCI channel 0 IPRJ2 to 0 Notes: 1. Lower 16 bits of the start address. 2. ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 113 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2345 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes SYSCR Priority Setting INTM1 INTM0 Registers 0 0 1 1 0 — — IPR Interrupt Mask Bits I — I2 to I0 Interrupt Control Mode 0 — 2 Description Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited — 1 — — Rev. 4.00 Feb 15, 2006 page 114 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 2 Legend: *: Don't care I 0 1 * Selected Interrupts All interrupts NMI interrupts All interrupts Rev. 4.00 Feb 15, 2006 page 115 of 900 REJ09B0291-0400 Section 5 Interrupt Controller (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Rev. 4.00 Feb 15, 2006 page 116 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Table 5.8 Interrupt Control Mode Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 INTM0 Interrupt Acceptance Control I 8-Level Control I2 to I0 IPR Default Priority T (Trace) Determination 0 2 0 1 0 0 X IM 1 —* X — IM —* 2 — T PR Legend: : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. — : Not used. Note: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. Rev. 4.00 Feb 15, 2006 page 117 of 900 REJ09B0291-0400 Section 5 Interrupt Controller [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes TEI1 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 4.00 Feb 15, 2006 page 118 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 4.00 Feb 15, 2006 page 119 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0 Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 4.00 Feb 15, 2006 page 120 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 4.00 Feb 15, 2006 page 121 of 900 REJ09B0291-0400 Interrupt acceptance Interrupt level determination Wait for end of instruction Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Section 5 Interrupt Controller φ Interrupt request signal Rev. 4.00 Feb 15, 2006 page 122 of 900 REJ09B0291-0400 Internal address bus (1) (3) (7) (5) (9) (11) (13) Internal read signal Internal write signal Internal data us (2) (4) (6) (8) (10) (12) (14) Figure 5.7 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2345 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Normal Mode* No. 1 2 3 4 5 6 Execution Status 1 Interrupt priority determination* 5 Advanced Mode INTM1 = 0 3 1 to 19+2·SI 2·SK 2·SI 2·SI 2 12 to 32 INTM1 = 1 3 1 to 19+2·SI 3·SK 2·SI 2·SI 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 1 to 19+2·SI 3·SK SI 2·SI 2 12 to 32 Number of wait states until executing 1 to 2 instruction ends* 19+2·SI PC, CCR, EXR stack save Vector fetch 3 Instruction fetch* 4 Internal processing* 2·SK SI 2·SI 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 123 of 900 REJ09B0291-0400 Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m 16-Bit Bus 2-State Access 2 3-State Access 3+m Legend: m: Number of wait states in an external device access. 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.8 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0. Rev. 4.00 Feb 15, 2006 page 124 of 900 REJ09B0291-0400 Section 5 Interrupt Controller TCR write cycle by CPU CMIA exception handling φ Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 4.00 Feb 15, 2006 page 125 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.6 5.6.1 DTC Activation by Interrupt Overview The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 7, Data Transfer Controller. Rev. 4.00 Feb 15, 2006 page 126 of 900 REJ09B0291-0400 Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5.9 Interrupt Control for DTC and DMAC 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCEA to DTCEE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Rev. 4.00 Feb 15, 2006 page 127 of 900 REJ09B0291-0400 Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCEA to DTCEE in the DTC and the DISEL bit of MRB in the DTC. Table 5.11 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 Interrupt Source Selection/Clearing Control DTC X CPU ∆ ∆ X ∆ Legend: ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Notes on Use SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. Rev. 4.00 Feb 15, 2006 page 128 of 900 REJ09B0291-0400 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8S/2345 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units  In advanced mode, manages the external space as 8 areas of 2-Mbytes  In normal mode*, manages the external space as a single area  Bus specifications can be set independently for each area • Basic bus interface  Chip select (CS0 to CS3) can be output for areas 0 to 3  8-bit access or 16-bit access can be selected for each area  2-state access or 3-state access can be selected for each area  Program wait states can be inserted for each area • Burst ROM interface  Burst ROM interface can be set for area 0  Choice of 1- or 2-state burst access • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Bus arbitration function  Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC • Other features  External bus release function Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 129 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS3 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller Internal data bus Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev. 4.00 Feb 15, 2006 page 130 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Name Address strobe Read High write Low write Chip select 0 to 3 Wait Bus request Bus request acknowledge Bus Controller Pins Symbol AS RD HWR LWR CS0 to CS3 WAIT BREQ BACK I/O Output Output Output Output Output Input Input Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that areas 0 to 3 are selected. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL R/W R/W R/W R/W R/W R/W R/W Power-On Reset 2 H'FF/H'00* Manual Reset Retained Retained Retained Retained Retained Retained Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 1 H'FF H'FF H'FF H'D0 H'3C Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. Rev. 4.00 Feb 15, 2006 page 131 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 1 to 3*, 5 to 7 Initial value : 1 RW Mode 4 Initial value : RW : 0 R/W : R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode*, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1, 2, 3*, and 5, 6, 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode*, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access. Note: * ZTAT, mask ROM, and ROMless versions only. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev. 4.00 Feb 15, 2006 page 132 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode*, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode*, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time. Note: * ZTAT, mask ROM, and ROMless versions only. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev. 4.00 Feb 15, 2006 page 133 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode*, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space . The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. Note: * ZTAT, mask ROM, and ROMless versions only. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev. 4.00 Feb 15, 2006 page 134 of 900 REJ09B0291-0400 Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev. 4.00 Feb 15, 2006 page 135 of 900 REJ09B0291-0400 Section 6 Bus Controller (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev. 4.00 Feb 15, 2006 page 136 of 900 REJ09B0291-0400 Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W BRSTRM BRSTS1 BRSTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Rev. 4.00 Feb 15, 2006 page 137 of 900 REJ09B0291-0400 Section 6 Bus Controller Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode*, the selection can be made from the entire external space. Burst ROM interface and PSRAM burst operation cannot be set at the same time. Note: * ZTAT, mask ROM, and ROMless versions only. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Rev. 4.00 Feb 15, 2006 page 138 of 900 REJ09B0291-0400 Section 6 Bus Controller Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0—Reserved: Only 0 should be written to these bits. 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 — 0 R/W 5 EAE 1 R/W 4 — 1 R/W 3 — 1 R/W 2 — 1 R/W 1 — 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ and BACK can be used as I/O ports. (Initial value) External bus release is enabled. Bit 6—Reserved: Only 0 should be written to this bit. Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode*. Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 139 of 900 REJ09B0291-0400 Section 6 Bus Controller Bit 5 EAE 0 Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2345) Addresses H'010000 to H'017FFF are in on-chip ROM and addresses H'018000 to H'01FFFF are a reserved area (in the H8S/2344) Addresses H'010000 to H'01FFFF are a reserved area (in the H8S/2343 and H8S/2341) 1 Note: * Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode) (Initial value) Reserved areas should not be accessed. Bits 4 to 2—Reserved: Only 1 should be written to these bits. Bit 1—Reserved: Only 0 should be written to this bit. Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) 6.3 6.3.1 Bus Control Area Divisions In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS3) can be output for areas 0 to 3. Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 140 of 900 REJ09B0291-0400 Section 6 Bus Controller H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF H'0000 H'FFFF (1) Advanced mode (2) Normal mode* Note: * ZTAT, mask ROM, and ROMless versions only. Figure 6.2 Overview of Area Partitioning Rev. 4.00 Feb 15, 2006 page 141 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area. Rev. 4.00 Feb 15, 2006 page 142 of 900 REJ09B0291-0400 Section 6 Bus Controller Table 6.3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 — 0 1 Wn0 — 0 1 0 1 — 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3 1 0 1 — 0 6.3.3 Memory Interfaces The H8S/2345 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows direct connection of burst ROM. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, Basic Bus Interface and 6.5, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Rev. 4.00 Feb 15, 2006 page 143 of 900 REJ09B0291-0400 Section 6 Bus Controller Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. When area 1 to 3 external space is accessed, the CS1 to CS3 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7 memory interface. 6.3.5 Areas in Normal Mode (ZTAT, Mask ROM, and ROMless Versions Only) In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When external space is accessed, the CS0 signal can be output. The basic bus interface or burst ROM interface can be selected. Rev. 4.00 Feb 15, 2006 page 144 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.3.6 Chip Select Signals The H8S/2345 Group can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being driven low when the corresponding external space area is accessed. In normal mode*, only the CS0 signal can be output. Figure 6.3 shows an example of CSn (n = 0 to 3) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS3. In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3. For details, see section 8, I/O Ports. Note: * ZTAT, mask ROM, and ROMless versions only. Bus cycle T1 φ T2 T3 Address bus Area n external address CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 3) CSn Rev. 4.00 Feb 15, 2006 page 145 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte; a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 4.00 Feb 15, 2006 page 146 of 900 REJ09B0291-0400 Section 6 Bus Controller 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev. 4.00 Feb 15, 2006 page 147 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Write Read Write Word Read Write Address — — Even Odd Even Odd — — HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored. Rev. 4.00 Feb 15, 2006 page 148 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed , the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 6.6 Bus Timing for 8-Bit 2-State Access Space Rev. 4.00 Feb 15, 2006 page 149 of 900 REJ09B0291-0400 Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 3 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space Rev. 4.00 Feb 15, 2006 page 150 of 900 REJ09B0291-0400 Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev. 4.00 Feb 15, 2006 page 151 of 900 REJ09B0291-0400 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 3 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 4.00 Feb 15, 2006 page 152 of 900 REJ09B0291-0400 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 3 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev. 4.00 Feb 15, 2006 page 153 of 900 REJ09B0291-0400 Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 3 Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev. 4.00 Feb 15, 2006 page 154 of 900 REJ09B0291-0400 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 3 Valid Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev. 4.00 Feb 15, 2006 page 155 of 900 REJ09B0291-0400 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 3 Valid Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev. 4.00 Feb 15, 2006 page 156 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the H8S/2345 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of BWCRH and BWCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Rev. 4.00 Feb 15, 2006 page 157 of 900 REJ09B0291-0400 Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. By program wait T1 φ T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. Rev. 4.00 Feb 15, 2006 page 158 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.5 6.5.1 Burst ROM Interface Overview With the H8S/2345 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.15 (a) and (b). The timing shown in figure 6.15 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.15 (b) is for the case where both these bits are cleared to 0. Rev. 4.00 Feb 15, 2006 page 159 of 900 REJ09B0291-0400 Section 6 Bus Controller Full access T1 φ T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev. 4.00 Feb 15, 2006 page 160 of 900 REJ09B0291-0400 Section 6 Bus Controller Full access T1 φ Burst access T1 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev. 4.00 Feb 15, 2006 page 161 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.6 6.6.1 Idle Cycle Operation When the H8S/2345 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.16 Example of Idle Cycle Operation (1) Rev. 4.00 Feb 15, 2006 page 162 of 900 REJ09B0291-0400 Section 6 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.17 Example of Idle Cycle Operation (2) Rev. 4.00 Feb 15, 2006 page 163 of 900 REJ09B0291-0400 Section 6 Bus Controller (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A φ Address bus CS (area A) CS (area B) RD T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6.18 Relationship between Chip Select (CS) and Read (RD) Rev. 4.00 Feb 15, 2006 page 164 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.6.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High High High 6.7 6.7.1 Bus Release Overview The H8S/2345 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. 6.7.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2345 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. Rev. 4.00 Feb 15, 2006 page 165 of 900 REJ09B0291-0400 Section 6 Bus Controller In the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 6.7.3 Pin States in External Bus Released State Table 6.6 shows pin states in the external bus released state. Table 6.6 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance Rev. 4.00 Feb 15, 2006 page 166 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.7.4 Transition Timing Figure 6.19 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 φ T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [2] [3] [4] [5] [1] Low level of BREQ pin is sampled at rise of T2 state. [2] BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. [3] BREQ pin state is still sampled in external bus released state. [4] High level of BREQ pin is sampled. [5] BACK pin is driven high, ending bus release cycle. Figure 6.19 Bus-Released State Transition Timing Rev. 4.00 Feb 15, 2006 page 167 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.7.5 Usage Note When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep mode. 6.8 6.8.1 Bus Arbitration Overview The H8S/2345 Group has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.8.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev. 4.00 Feb 15, 2006 page 168 of 900 REJ09B0291-0400 Section 6 Bus Controller 6.8.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 6.8.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal and CS0 to CS3 signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD and CS0 to CS3 signals may change from the low level to the high-impedance state. 6.9 Resets and the Bus Controller In a power-on reset, the H8S/2345, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed. Rev. 4.00 Feb 15, 2006 page 169 of 900 REJ09B0291-0400 Section 6 Bus Controller Rev. 4.00 Feb 15, 2006 page 170 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller Section 7 Data Transfer Controller 7.1 Overview The H8S/2345 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features The features of the DTC are: • Transfer possible over any number of channels  Transfer information is stored in memory  One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes  Normal, repeat, and block transfer modes available  Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible  24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC  An interrupt request can be issued to the CPU after one data transfer ends  An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible • Module stop mode can be set  The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev. 4.00 Feb 15, 2006 page 171 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERE DTVECR DTC service request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to E : DTC vector register Figure 7.1 Block Diagram of DTC Rev. 4.00 Feb 15, 2006 page 172 of 900 REJ09B0291-0400 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTVECR DTCERA to DTCERE Section 7 Data Transfer Controller 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W —* 2 —* 2 2 —* 2 —* 2 —* Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF 1 Address* 3 —* 3 —* 3 —* 3 —* 3 —* 3 —* —* 2 R/W R/W R/W H'FF30 to H'FF34 H'FF37 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev. 4.00 Feb 15, 2006 page 173 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2 7.2.1 Register Descriptions DTC Mode Register A (MRA) MRA is an 8-bit register that controls the DTC operating mode. Bit : 7 SM1 Initial value : R/W : Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined — Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev. 4.00 Feb 15, 2006 page 174 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer Rev. 4.00 Feb 15, 2006 page 175 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined — 6 DISEL Undefined — 5 — Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined — Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2345 Group, and should always be written with 0 in a write. Rev. 4.00 Feb 15, 2006 page 176 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 4.00 Feb 15, 2006 page 177 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 7.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev. 4.00 Feb 15, 2006 page 178 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated for each interrupt controller. Rev. 4.00 Feb 15, 2006 page 179 of 900 REJ09B0291-0400 Section 7 Data Transfer Controller 7.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] • • • When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation (Initial value) Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs. Bit 3 OS3 0 1 Bit 2 OS2 0 1 0 1 Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) (Initial value) Bit 1 OS1 0 1 Bit 0 OS0 0 1 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value) Rev. 4.00 Feb 15, 2006 page 380 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12—Module Stop (MSTP12): Specifies the 8-bit timer stop mode. Bit 12 MSTP12 0 1 Description 8-bit timer module stop mode cleared 8-bit timer module stop mode set (Initial value) Rev. 4.00 Feb 15, 2006 page 381 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.3 10.3.1 Operation TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 10.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 10.3 shows the timing of incrementation at both edges of an external clock signal. Rev. 4.00 Feb 15, 2006 page 382 of 900 REJ09B0291-0400 Section 10 8-Bit Timers φ External clock input Clock input to TCNT TCNT N–1 N N+1 Figure 10.3 Count Timing for External Clock Input 10.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 10.4 shows this timing. φ TCNT N N+1 TCOR Compare match signal N CMF Figure 10.4 Timing of CMF Setting Rev. 4.00 Feb 15, 2006 page 383 of 900 REJ09B0291-0400 Section 10 8-Bit Timers Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 10.5 Timing of Timer Output Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.6 shows the timing of this operation. φ Compare match signal TCNT N H'00 Figure 10.6 Timing of Compare Match Clear Rev. 4.00 Feb 15, 2006 page 384 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 10.7 Timing of External Reset 10.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 10.8 shows the timing of this operation. φ TCNT H'FF H'00 Overflow signal OVF Figure 10.8 Timing of OVF Setting Rev. 4.00 Feb 15, 2006 page 385 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. • Setting of compare match flags  The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs.  The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. • Counter clear specification  If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set.  The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. • Pin output  Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions.  Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Note on Usage: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes. Rev. 4.00 Feb 15, 2006 page 386 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.4 10.4.1 Interrupts Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 10.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 10.3 8-Bit Timer Interrupt Sources Interrupt Source CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 10.4.2 A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev. 4.00 Feb 15, 2006 page 387 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 10.9 Example of Pulse Output Rev. 4.00 Feb 15, 2006 page 388 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 10.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 10.10 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 10.10 Contention between TCNT Write and Clear Rev. 4.00 Feb 15, 2006 page 389 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 10.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 10.11 Contention between TCNT Write and Increment Rev. 4.00 Feb 15, 2006 page 390 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 10.12 shows this operation. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Disabled Figure 10.12 Contention between TCOR Write and Compare Match Rev. 4.00 Feb 15, 2006 page 391 of 900 REJ09B0291-0400 Section 10 8-Bit Timers 10.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 10.4. Table 10.4 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 10.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 10.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 10.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks. Rev. 4.00 Feb 15, 2006 page 392 of 900 REJ09B0291-0400 Section 10 8-Bit Timers Table 10.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from 1 low to low* Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from 2 low to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from 3 high to low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev. 4.00 Feb 15, 2006 page 393 of 900 REJ09B0291-0400 Section 10 8-Bit Timers Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock No. 4 TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 10.6.6 Usage Note Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 4.00 Feb 15, 2006 page 394 of 900 REJ09B0291-0400 Section 11 Watchdog Timer Section 11 Watchdog Timer 11.1 Overview The H8S/2345 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF)* if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2345 Group. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 11.1.1 Features WDT features are listed below. • Switchable between watchdog timer mode and interval timer mode • WDTOVF output* when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF.* It is possible to select whether or not the entire H8S/2345 Group is reset at the same time. This internal reset can be a power-on reset or a manual reset. • Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. • Choice of eight counter clock sources. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 395 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select WDTOVF*2 Internal reset signal*1 Reset control φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources Internal bus RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Notes: 1. The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. 2. The WDTOVF pin function is not supported by the F-ZTAT version. Figure 11.1 Block Diagram of WDT Rev. 4.00 Feb 15, 2006 page 396 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.1.3 Pin Configuration Table 11.1 describes the WDT output pin. Table 11.1 WDT Pin Name Watchdog timer overflow Note: * Symbol WDTOVF* I/O Output Function Outputs counter overflow signal in watchdog timer mode The WDTOVF pin function is not supported by the F-ZTAT version. 11.1.4 Register Configuration The WDT has three registers, as summarized in table 11.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 11.2 WDT Registers Address* Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W 3 R/(W)* 1 Initial Value H'18 H'00 3 Write* 2 Read H'FFBC H'FFBD H'FFBF H'FFBC H'FFBC H'FFBE R/W R/(W)* H'1F Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 11.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. Rev. 4.00 Feb 15, 2006 page 397 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.2 11.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : 1 TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from 2 H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)* or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: 1. The method for writing to TCNT is different from that for general registers to prevent inadvertent overwriting. For details see section 11.2.4, Notes on Register Access. 2. The WDTOVF pin function is not supported by the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 398 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.2.2 Bit Timer Control/Status Register (TCSR) : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * Can only be written with 0 for flag clearing. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * The method for writing to TCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 11.2.4, Notes on Register Access. Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 1 Note: * Description [Clearing condition] Cleared by reading TCSR when OVF = 1*, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode When OVF is polled and the interval timer interrupt is disabled. OVF = 1 must be read at least twice. (Initial value) Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal* when TCNT overflows. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 399 of 900 REJ09B0291-0400 Section 11 Watchdog Timer Bit 6 WT/IT 0 1 Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) 1 2 Watchdog timer: Generates the WDTOVF signal* when TCNT overflows* Notes: 1. The WDTOVF pin function is not supported by the F-ZTAT version. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) Bits 4 and 3—Reserved: Read-only bits, always read as 1. Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (φ), for input to TCNT. Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Note: * Bit 0 CKS0 0 1 0 1 0 1 0 1 Description Clock φ/2 (initial value) φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Overflow Period (when φ = 20 MHz)* 25.6 µs 819.2 µs 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Rev. 4.00 Feb 15, 2006 page 400 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : Note: * Can only be written with 0 for flag clearing. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * The method for writing to RSTCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 11.2.4, Notes on Register Access. Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 1 Description [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value) Rev. 4.00 Feb 15, 2006 page 401 of 900 REJ09B0291-0400 Section 11 Watchdog Timer Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2345 Group if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Note: * Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows The modules within the H8S/2345 Group are not reset, but TCNT and TCSR within the WDT are reset. (Initial value) Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Power-on reset Manual reset (Initial value) Bits 4 to 0—Reserved: Read-only bits, always read as 1. 11.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 11.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. Rev. 4.00 Feb 15, 2006 page 402 of 900 REJ09B0291-0400 Section 11 Watchdog Timer TCNT write 15 Address: H'FFBC H'5A 87 Write data 0 TCSR write 15 Address: H'FFBC H'A5 87 Write data 0 Figure 11.2 Format of Data Written to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 11.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit. Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FFBE H'5A 87 Write data 0 Figure 11.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. Rev. 4.00 Feb 15, 2006 page 403 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.3 11.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal* is output. This is shown in figure 11.4. This WDTOVF signal* can be used to reset the system. The WDTOVF signal* is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2345 Group internally is generated at the same time as the WDTOVF signal*. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 404 of 900 REJ09B0291-0400 Section 11 Watchdog Timer TCNT count Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF=1 WDTOVF*3 and internal reset are generated WT/IT = 1 H'00 written TME = 1 to TCNT Time WDTOVF signal*3 132 states*2 Internal reset signal*1 518 states Legend: WT/IT : Timer mode select bit TME : Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF pin function is not supported by the F-ZTAT version. Figure 11.4 Watchdog Timer Operation 11.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 11.5. This function can be used to generate interrupt requests at regular intervals. Rev. 4.00 Feb 15, 2006 page 405 of 900 REJ09B0291-0400 Section 11 Watchdog Timer TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 11.5 Interval Timer Operation 11.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 11.6. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 11.6 Timing of Setting of OVF Rev. 4.00 Feb 15, 2006 page 406 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2345 Group chip. Figure 11.7 shows the timing in this case. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. φ TCNT H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal* Internal reset signal 132 states 518 states Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Figure 11.7 Timing of Setting of WOVF Rev. 4.00 Feb 15, 2006 page 407 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 11.5 11.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.8 Contention between TCNT Write and Increment Rev. 4.00 Feb 15, 2006 page 408 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 11.5.4 System Reset by WDTOVF Signal WDTOVF If the WDTOVF output signal* is input to the RES pin of the H8S/2345 Group, the H8S/2345 Group will not be initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal*, use the circuit shown in figure 11.9. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. H8S/2345 RES Reset input Reset signal to entire system WDTOVF * Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Figure 11.9 Circuit for System Reset by WDTOVF Signal (Example) WDTOVF Rev. 4.00 Feb 15, 2006 page 409 of 900 REJ09B0291-0400 Section 11 Watchdog Timer 11.5.5 Internal Reset in Watchdog Timer Mode The H8S/2345 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag. Note: * The WDTOVF pin function is not supported by the F-ZTAT version. Rev. 4.00 Feb 15, 2006 page 410 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) 12.1 Overview The H8S/2345 Group is equipped with a 2-channel serial communication interface (SCI). Both channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 Features SCI features are listed below. • Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode  Serial data communication executed using asynchronous system in which synchronization is achieved character by character  Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA)  A multiprocessor communication function is provided that enables serial data communication with a number of processors  Choice of 12 serial data transfer formats Data length Stop bit length Parity Multiprocessor bit  Break detection : 7 or 8 bits : 1 or 2 bits : Even, odd, or none : 1 or 0 : Break can be detected by reading the RxD pin level directly in case of a framing error  Receive error detection : Parity, overrun, and framing errors Clocked Synchronous mode  Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function  One serial data transfer format Data length : 8 bits  Receive error detection : Overrun errors detected Rev. 4.00 Feb 15, 2006 page 411 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • On-chip baud rate generator allows any bit rate to be selected • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin • Four interrupt sources  Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive error — that can issue requests independently  The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) to execute data transfer • Choice of LSB-first or MSB-first transfer  Can be selected regardless of the communication mode* (except in the case of asynchronous mode bit data) • Module stop mode can be set  As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Note: * Descriptions in this section refer to LSB-first transfer. Rev. 4.00 Feb 15, 2006 page 412 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: SCMR : Smart Card mode register : Receive shift register RSR : Receive data register RDR : Transmit shift register TSR : Transmit data register TDR : Serial mode register SMR : Serial control register SCR : Serial status register SSR : Bit rate register BRR Figure 12.1 Block Diagram of SCI Rev. 4.00 Feb 15, 2006 page 413 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.1.3 Pin Configuration Table 12.1 shows the serial pins for each SCI channel. Table 12.1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output Rev. 4.00 Feb 15, 2006 page 414 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.1.4 Register Configuration The SCI has the internal registers shown in table 12.2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver. Table 12.2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 All Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 R/W R/W R/W R/W R/W 2 R/(W)* Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF3C 1 R R/W R/W R/W R/W R/W 2 R/(W)* Smart card mode register 0 SCMR0 R R/W R/W Smart card mode register 1 SCMR1 Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 415 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2 12.2.1 Bit R/W Register Descriptions Receive Shift Register (RSR) : : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 12.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode. Rev. 4.00 Feb 15, 2006 page 416 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.3 Bit R/W Transmit Shift Register (TSR) : : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 12.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. Rev. 4.00 Feb 15, 2006 page 417 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* (Initial value) When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Rev. 4.00 Feb 15, 2006 page 418 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Rev. 4.00 Feb 15, 2006 page 419 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of each transmitted character before it is sent (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of each transmitted character before it is sent In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 1 Bit 0 CKS0 0 1 0 1 Description φ clock φ/4 clock φ/16 clock φ/64 clock (Initial value) Rev. 4.00 Feb 15, 2006 page 420 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Note: * Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. (Initial value) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Note: * Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Rev. 4.00 Feb 15, 2006 page 421 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* 2 Transmission enabled* 1 (Initial value) Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description 1 Reception disabled* 2 Reception enabled* (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Rev. 4.00 Feb 15, 2006 page 422 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • • 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. (Initial value) Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Note: * Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Rev. 4.00 Feb 15, 2006 page 423 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 12.9. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 2 External clock/SCK pin functions as serial clock input 3 External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev. 4.00 Feb 15, 2006 page 424 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] Rev. 4.00 Feb 15, 2006 page 425 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] • • 1 When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and reads data from RDR (Initial value) [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1* 2 1 (Initial value)* Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Rev. 4.00 Feb 15, 2006 page 426 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when 2 reception ends, and the stop bit is 0* Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 1 (Initial value)* Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not 2 match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Rev. 4.00 Feb 15, 2006 page 427 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Note: * Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. (Initial value)* Rev. 4.00 Feb 15, 2006 page 428 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 12.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR settings in clocked synchronous mode. Rev. 4.00 Feb 15, 2006 page 429 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ = 2 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 — — 0.00 — n 1 1 0 0 0 0 0 0 0 0 0 φ = 2.097152 MHz N 148 108 217 108 54 26 13 6 2 1 1 Error (%) –0.04 0.21 0.21 0.21 –0.70 1.14 –2.48 –2.48 — — — n 1 1 0 0 0 0 0 0 0 0 0 φ = 2.4576 MHz N 174 127 255 127 63 31 15 7 3 1 1 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 1 1 1 0 0 0 0 0 0 0 — φ = 3 MHz N 212 155 77 155 77 38 19 9 4 2 — Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 — φ = 3.6864 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 1 1 0 0 0 0 0 0 0 0 φ = 4 MHz N 70 207 103 207 103 51 25 12 6 3 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 — 0.00 — n 2 1 1 0 0 0 0 0 0 0 0 φ = 4.9152 MHz N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 φ = 5 MHz N 88 64 129 64 129 64 32 15 7 4 3 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 Rev. 4.00 Feb 15, 2006 page 430 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) φ = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0.00 –2.34 n 2 2 1 1 0 0 0 0 0 0 0 φ = 6.144 MHz N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 φ = 7.3728 MHz N 130 95 191 95 191 95 47 23 11 6 5 Error (%) –0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 2 1 1 0 0 0 0 0 0 0 φ = 8 MHz N 141 103 207 103 207 103 51 25 12 7 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 — φ = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) n φ = 10 MHz N 177 129 64 129 64 129 64 32 15 9 7 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 φ = 12 MHz N 212 155 77 155 77 155 77 38 19 11 9 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.00 –2.34 n 2 2 2 1 1 0 0 0 0 0 0 φ = 12.288 MHz N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 –0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 –1.70 0 0.00 0 Rev. 4.00 Feb 15, 2006 page 431 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) φ = 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 10 Error (%) –0.17 0.16 0.16 0.16 0.16 0.16 0.16 –0.93 –0.93 0.00 — n 3 2 2 1 1 0 0 0 0 0 0 φ = 14.7456 MHz N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 φ = 16 MHz N 70 207 103 207 103 207 103 51 25 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 φ = 17.2032 MHz N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 φ = 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) –0.12 0.16 0.16 0.16 0.16 0.16 0.16 –0.69 1.02 0.00 –2.34 n 3 2 2 1 1 0 0 0 0 0 0 φ = 19.6608 MHz N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 φ = 20 MHz N 88 64 129 64 129 64 129 64 32 19 15 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 0.00 1.73 Note: Settings with an error of 1% or less are recommended. Legend: —: Setting possible, but error occurs Rev. 4.00 Feb 15, 2006 page 432 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 φ = 2 MHz N 70 124 249 124 199 99 49 19 9 4 1 0* n — 2 2 1 1 0 0 0 0 0 0 0 0 φ = 4 MHz N — 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 — 124 249 124 199 99 199 79 39 19 7 3 1 — — — — 1 1 0 0 0 0 0 0 — 0 — — — 249 124 249 99 49 24 9 4 — 0* 3 3 2 2 1 1 0 0 0 0 0 0 — — 249 124 249 99 199 99 159 79 39 15 7 3 — — — — 2 1 1 0 0 0 0 0 0 0 0 — — 124 249 124 199 99 49 19 9 4 1 0* n φ = 8 MHz N φ = 10 MHz n N φ = 16 MHz n N n φ = 20 MHz N Legend: Blank : Cannot be set. — : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Rev. 4.00 Feb 15, 2006 page 433 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= φ 64 × 22n–1 ×B × 106 – 1 Clocked synchronous mode: N= φ 8 × 22n–1 × B × 106 – 1 Where B: N: φ: n: Bit rate (bit/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock φ φ/4 φ/16 φ/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: φ × 106 (N + 1) × B × 64 × 22n–1 – 1 × 100 Error (%) = Rev. 4.00 Feb 15, 2006 page 434 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 4.00 Feb 15, 2006 page 435 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Rev. 4.00 Feb 15, 2006 page 436 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 Rev. 4.00 Feb 15, 2006 page 437 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.9 Bit Smart Card Mode Register (SCMR) : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 13.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. The transmit/receive format is valid for 8-bit data. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2—Smart Card Data Invert (SINV): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Rev. 4.00 Feb 15, 2006 page 438 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bit MSTP6 or MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value) Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) Rev. 4.00 Feb 15, 2006 page 439 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.3 12.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 12.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9. Asynchronous Mode • Data length: Choice of 7 or 8 bits • Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing, parity, and overrun errors, and breaks, during reception • Choice of internal or external clock as SCI clock source  When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output  When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode • Transfer format: Fixed 8-bit data • Detection of overrun errors during reception • Choice of internal or external clock as SCI clock source  When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip  When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock Rev. 4.00 Feb 15, 2006 page 440 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 — — 1 — — 1 — — — 0 1 0 1 — Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode SCI Transfer Format Multiprocessor Bit No Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 12.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Clocked synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock Inputs serial clock Rev. 4.00 Feb 15, 2006 page 441 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 4.00 Feb 15, 2006 page 442 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 12.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 — — — — MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit Rev. 4.00 Feb 15, 2006 page 443 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI initialization (asynchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Rev. 4.00 Feb 15, 2006 page 444 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Figure 12.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 12.4 Sample SCI Initialization Flowchart Rev. 4.00 Feb 15, 2006 page 445 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Serial data transmission (asynchronous mode): Figure 12.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 12.5 Sample Serial Transmission Flowchart Rev. 4.00 Feb 15, 2006 page 446 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Rev. 4.00 Feb 15, 2006 page 447 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 4.00 Feb 15, 2006 page 448 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Serial data reception (asynchronous mode): Figure 12.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER ∨ FER ∨ ORER = 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by an RXI interrupt and the RDR value is read. Figure 12.7 Sample Serial Reception Data Flowchart Rev. 4.00 Feb 15, 2006 page 449 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes No Break? Yes Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.7 Sample Serial Reception Data Flowchart (cont) Rev. 4.00 Feb 15, 2006 page 450 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 12.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Rev. 4.00 Feb 15, 2006 page 451 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Table 12.11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR. When the stop bit is 0 Receive data is transferred from RSR to RDR. Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Figure 12.8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 4.00 Feb 15, 2006 page 452 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 12.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 12.10. Rev. 4.00 Feb 15, 2006 page 453 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Clock See the section on asynchronous mode. Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 12.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations Multiprocessor serial data transmission: Figure 12.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev. 4.00 Feb 15, 2006 page 454 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart Rev. 4.00 Feb 15, 2006 page 455 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. Rev. 4.00 Feb 15, 2006 page 456 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Figure 12.11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor serial data reception: Figure 12.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev. 4.00 Feb 15, 2006 page 457 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ∨ ORER = 1 No Read RDRF flag in SSR Yes [4] No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 12.12 Sample Multiprocessor Serial Reception Flowchart Rev. 4.00 Feb 15, 2006 page 458 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev. 4.00 Feb 15, 2006 page 459 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Figure 12.13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station’s ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt service routine (b) Data matches station’s ID Figure 12.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 4.00 Feb 15, 2006 page 460 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB MSB Serial data Don’t care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t care Note: * High except in continuous transfer Figure 12.14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Rev. 4.00 Feb 15, 2006 page 461 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Rev. 4.00 Feb 15, 2006 page 462 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Data Transfer Operations SCI initialization (clocked synchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 12.15 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [1] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) Set data transfer format in SMR and SCMR [2] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set value in BRR Wait [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: When transmitting and receiving data simultaneously, the TE and RE bits should be cleared to 0 and then set to 1 at the same time. Figure 12.15 Sample SCI Initialization Flowchart Rev. 4.00 Feb 15, 2006 page 463 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Serial data transmission (clocked synchronous mode): Figure 12.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 12.16 Sample Serial Transmission Flowchart Rev. 4.00 Feb 15, 2006 page 464 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Rev. 4.00 Feb 15, 2006 page 465 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Figure 12.17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 12.17 Example of SCI Operation in Transmission Serial data reception (clocked synchronous mode): Figure 12.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev. 4.00 Feb 15, 2006 page 466 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] [5] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 12.18 Sample Serial Reception Flowchart Rev. 4.00 Feb 15, 2006 page 467 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 12.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 12.19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.19 Example of SCI Operation in Reception Simultaneous serial data transmission and reception (clocked synchronous mode): Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev. 4.00 Feb 15, 2006 page 468 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Initialization Start transmission/reception [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER = 1 No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE and RE bits to 0, then set both of these bits to 1. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 4.00 Feb 15, 2006 page 469 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 12.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 12.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. Table 12.12 SCI Interrupt Sources Channel 0 Interrupt Source ERI RXI TXI TEI 1 ERI RXI TXI TEI Note: * Description Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of ICR and IPR. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the Rev. 4.00 Feb 15, 2006 page 470 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 12.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 12.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 12.13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Rev. 4.00 Feb 15, 2006 page 471 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 12.21. Rev. 4.00 Feb 15, 2006 page 472 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = (0.5 – 1 2N ) – (L – 0.5) F – D – 0.5 N (1 + F) × 100% . . . . . . . . Formula (1) Where M : Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% . . . . . . . . Formula (2) = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Rev. 4.00 Feb 15, 2006 page 473 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 12.22) • When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 12.22 Example of Clocked Synchronous Transmission by DTC Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 4.00 Feb 15, 2006 page 474 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) Switching from SCK Pin Function to Port Pin Function • Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 12.23) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output 3. C/A = 0 Figure 12.23 Operation when Switching from SCK Pin Function to Port Pin Function Rev. 4.00 Feb 15, 2006 page 475 of 900 REJ09B0291-0400 Section 12 Serial Communication Interface (SCI) • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level outputTE SCK/port 1. End of transmission Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 12.24 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 4.00 Feb 15, 2006 page 476 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Section 13 Smart Card Interface 13.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 13.1.1 Features Features of the Smart Card interface supported by the H8S/2345 Group are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking  Transmission of error signal (parity error) in receive mode  Error signal detection and automatic data retransmission in transmit mode  Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources  Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently  The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC) to execute data transfer Rev. 4.00 Feb 15, 2006 page 477 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend: SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register Figure 13.1 Block Diagram of Smart Card Interface Rev. 4.00 Feb 15, 2006 page 478 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.1.3 Pin Configuration Table 13.1 shows the Smart Card interface pin configuration. Table 13.1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output Rev. 4.00 Feb 15, 2006 page 479 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.1.4 Register Configuration Table 13.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function; see the register descriptions in section 12, Serial Communication Interface (SCI). Table 13.2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 All Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 R/W R/W R/W R/W R/W 2 R/(W)* Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF 2 Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF3C 1 R R/W R/W R/W R/W R/W R/(W)* R R/W R/W H'84 H'00 H'F2 H'3FFF Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 480 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 13.2.1 Bit Smart Card Mode Register (SCMR) : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev. 4.00 Feb 15, 2006 page 481 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 13.3.4, Register Settings. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) 13.2.2 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). Rev. 4.00 Feb 15, 2006 page 482 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description Indicates that data was received normally and no error signal was sent [Clearing conditions] • • 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) Indicates that an error signal was sent from the receiving side showing that a parity error was detected [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description Indicates data transmission in progress [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) Indicates that data transmission is finished [Setting conditions] • • • • Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is transmitted when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is transmitted when GM = 1. Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 4.00 Feb 15, 2006 page 483 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.2.3 Bit Serial Mode Register (SMR) : 7 GM 0 GM R/W 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/E 0 O/E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W Initial value : Set value* : R/W : Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. Bit 7 of SMR has a different function in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation • • 1 • • TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) (Initial value) GSM mode smart card interface mode operation Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0—Operate in the same way as for the normal SCI. For details, see section 12.2.5, Serial Mode Register (SMR). Rev. 4.00 Feb 15, 2006 page 484 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.2.4 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : Bits 1 and 0 of SCR have a different function in smart card interface mode. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 12.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable (CKE1, CKE0): Selects the clock source, and enables or disables clock output from the SCK pin. In smart card interface mode, it is possible to switch between enabling and disabling of the normal clock output, and specify a fixed high level or fixed low level for the clock output. SCMR SMIF 0 1 0 1 1 0 0 1 0 1 0 1 SMR C/A, GM SCR Setting CKE1 CKE0 SCK Pin Function Description Refer to SCI designation The pin functions as an I/O port The pin outputs the clock as the SCK output pin The pin outputs fixed low level as the SCK output pin The pin outputs the clock as the SCK output pin The pin outputs fixed high level as the SCK output pin The pin outputs the clock as the SCK output pin Rev. 4.00 Feb 15, 2006 page 485 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3 13.3.1 Operation Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. • If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. • Only start-stop asynchronous communication is supported; there is no clocked synchronous communication function. 13.3.2 Pin Connections Figure 13.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Rev. 4.00 Feb 15, 2006 page 486 of 900 REJ09B0291-0400 Section 13 Smart Card Interface VCC TxD I/O RxD SCK Px (port) H8S/2345 Group Connected equipment Clock line Reset line CLK RST IC card Figure 13.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev. 4.00 Feb 15, 2006 page 487 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3.3 Data Format Figure 13.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Legend: Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Figure 13.3 Smart Card Interface Data Format Rev. 4.00 Feb 15, 2006 page 488 of 900 REJ09B0291-0400 Section 13 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. Rev. 4.00 Feb 15, 2006 page 489 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3.4 Register Settings Table 13.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 13.3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 — Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — Bit 4 O/E BRR4 RE TDR4 ERS RDR4 — Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: — : Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 13.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 13.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 12, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Rev. 4.00 Feb 15, 2006 page 490 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). • Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. • Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2345 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). Rev. 4.00 Feb 15, 2006 page 491 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= φ 1488 × 22n–1 × (N + 1) × 106 Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bit/s) φ = Operating frequency (MHz) n = See table 13.4 Table 13.4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 13.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) φ (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. Rev. 4.00 Feb 15, 2006 page 492 of 900 REJ09B0291-0400 Section 13 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ 1488 × 22n–1 × B × 106 – 1 Table 13.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) φ (MHz) 7.1424 bit/s 9600 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 N Error N Error N Error N Error N Error N Error N Error N Error 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60 Table 13.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = φ 1488 × 22n-1 × B × (N + 1) × 106 – 1 × 100 Rev. 4.00 Feb 15, 2006 page 493 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 4.00 Feb 15, 2006 page 494 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 13.4 shows an example of the transmission processing flow. Also, figure 13.5 shows the relationship between transmission operations and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND timing is shown in figure 13.6. If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DTC below. Rev. 4.00 Feb 15, 2006 page 495 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 13.4 Example of Transmission Processing Flow Rev. 4.00 Feb 15, 2006 page 496 of 900 REJ09B0291-0400 Section 13 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 13.5 Relation between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 1 11.0etu Legend: Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Figure 13.6 TEND Flag Generation Timing in Transmission Operation Rev. 4.00 Feb 15, 2006 page 497 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 13.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 13.7 Example of Reception Processing Flow Rev. 4.00 Feb 15, 2006 page 498 of 900 REJ09B0291-0400 Section 13 Smart Card Interface With the above processing, interrupt servicing or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 13.8 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 13.8 Timing for Fixing Clock Output Level Rev. 4.00 Feb 15, 2006 page 499 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Interrupt Operation: There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 13.8. Table 13.8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Receive Mode Normal operation Error Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DTC Activation Possible Not possible Possible Not possible Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 7, Data Transfer Controller. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. The DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Rev. 4.00 Feb 15, 2006 page 500 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 13.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state. • When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 13.9 Clock Halt and Restart Procedure Rev. 4.00 Feb 15, 2006 page 501 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 13.4 Usage Note The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 13.10. Rev. 4.00 Feb 15, 2006 page 502 of 900 REJ09B0291-0400 Section 13 Smart Card Interface 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.10 Receive Data Sampling Timing in Smart Card Mode Thus the reception margin in smart card interface mode is given by the following formula. M = (0.5 – 1 2N ) – (L – 0.5) F – D – 0.5 N (1 + F) × 100% Where M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 372) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% Rev. 4.00 Feb 15, 2006 page 503 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Transfer frame n+1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 [4] [3] Figure 13.11 Retransfer Operation in SCI Receive Mode Rev. 4.00 Feb 15, 2006 page 504 of 900 REJ09B0291-0400 Section 13 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 13.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 13.12 Retransfer Operation in SCI Transmit Mode Rev. 4.00 Feb 15, 2006 page 505 of 900 REJ09B0291-0400 Section 13 Smart Card Interface Rev. 4.00 Feb 15, 2006 page 506 of 900 REJ09B0291-0400 Section 14 A/D Converter Section 14 A/D Converter 14.1 Overview The H8S/2345 Group incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 14.1.1 Features A/D converter features are listed below • 10-bit resolution • Eight input channels • Settable analog conversion voltage range  Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage • High-speed conversion  Minimum conversion time: 6.7 µs per channel (at 20-MHz operation) • Choice of single mode or scan mode  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers  Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start  Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin • A/D conversion end interrupt generation  A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion • Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode Rev. 4.00 Feb 15, 2006 page 507 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter. Module data bus Internal data bus AVCC Vref AVSS 10-bit D/A Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 + Multiplexer – Comparator Sample-andhold circuit ADI interrupt Control circuit ADTRG Conversion start trigger from 8-bit timer or TPU Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 14.1 Block Diagram of A/D Converter Rev. 4.00 Feb 15, 2006 page 508 of 900 REJ09B0291-0400 Bus interface Section 14 A/D Converter 14.1.3 Pin Configuration Table 14.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 14.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Group 0 analog inputs Rev. 4.00 Feb 15, 2006 page 509 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.1.4 Register Configuration Table 14.2 summarizes the registers of the A/D converter. Table 14.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R 2 R/(W)* Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF 1 Address* H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C R/W R/W Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 510 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.2 14.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 14.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 14.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 14.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 4.00 Feb 15, 2006 page 511 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] • • 1 • • When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value) [Setting conditions] Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Rev. 4.00 Feb 15, 2006 page 512 of 900 REJ09B0291-0400 Section 14 A/D Converter Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description A/D conversion stopped • • (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 14.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while ADST = 0. Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped. Rev. 4.00 Feb 15, 2006 page 513 of 900 REJ09B0291-0400 Section 14 A/D Converter Group Selection CH2 0 Channel Selection CH1 0 1 CH2 0 1 0 1 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 14.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — 3 — 1 R/W 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped. Bit 7 TRGS1 0 1 Bit 6 TRGS0 0 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled (Initial value) Bits 5 to 0—Reserved: These bits are reserved; write as 1 in a write. Rev. 4.00 Feb 15, 2006 page 514 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev. 4.00 Feb 15, 2006 page 515 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 14.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 14.2 ADDR Access Operation (Reading H'AA40) Rev. 4.00 Feb 15, 2006 page 516 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 14.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev. 4.00 Feb 15, 2006 page 517 of 900 REJ09B0291-0400 Section 14 A/D Converter Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 4.00 Feb 15, 2006 page 518 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 14.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 4.00 Feb 15, 2006 page 519 of 900 REJ09B0291-0400 Section 14 A/D Converter Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 4.00 Feb 15, 2006 page 520 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing. Table 14.4 indicates the A/D conversion time. As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.4. In scan mode, the values given in table 14.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) φ Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1) : (2) : tD : tSPL : tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 14.5 A/D Conversion Timing Rev. 4.00 Feb 15, 2006 page 521 of 900 REJ09B0291-0400 Section 14 A/D Converter Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 10 — 259 Typ — 63 — Max 17 — 266 Min 6 — 131 CKS = 1 Typ — 31 — Max 9 — 134 Note: Values in the table are the number of states. 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 14.6 shows the timing. φ ADTRG Internal trigger signal ADST A/D conversion Figure 14.6 External Trigger Input Timing Rev. 4.00 Feb 15, 2006 page 522 of 900 REJ09B0291-0400 Section 14 A/D Converter 14.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 14.5. Table 14.5 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible 14.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set, AVCC = VCC and AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref ≤ AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Rev. 4.00 Feb 15, 2006 page 523 of 900 REJ09B0291-0400 Section 14 A/D Converter Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 14.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 14.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 µF AVSS 100 Ω AN0 to AN7 Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 14.7 Example of Analog Input Protection Circuit Rev. 4.00 Feb 15, 2006 page 524 of 900 REJ09B0291-0400 Section 14 A/D Converter Table 14.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Note: * Min — — Max 20 10* Unit pF kΩ When VCC = 4.0 V to 5.5 V and φ ≤ 12 MHz 10 kΩ AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 14.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2345 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 14.10). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 14.10). • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.9). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 4.00 Feb 15, 2006 page 525 of 900 REJ09B0291-0400 Section 14 A/D Converter Digital output H'3FF H'3FE H'3FD Ideal A/D conversion characteristic H'002 H'001 H'000 Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 14.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 14.10 A/D Conversion Precision Definitions (2) Rev. 4.00 Feb 15, 2006 page 526 of 900 REJ09B0291-0400 Section 14 A/D Converter Permissible Signal Source Impedance: H8S/2345 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8/2345 Group Sensor output impedance to 10 kΩ Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF A/D converter equivalent circuit 10 kΩ 20 pF Note: Values are reference values. Figure 14.11 Example of Analog Input Circuit Rev. 4.00 Feb 15, 2006 page 527 of 900 REJ09B0291-0400 Section 14 A/D Converter Rev. 4.00 Feb 15, 2006 page 528 of 900 REJ09B0291-0400 Section 15 D/A Converter Section 15 D/A Converter 15.1 Overview The H8S/2345 Group includes a two-channel D/A converter. 15.1.1 Features D/A converter features are listed below • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode Rev. 4.00 Feb 15, 2006 page 529 of 900 REJ09B0291-0400 Section 15 D/A Converter 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the D/A converter. Module data bus Bus interface DACR Internal data bus Vref AVCC DADR0 DA1 DA0 AVSS 8-bit D/A Control circuit Figure 15.1 Block Diagram of D/A Converter Rev. 4.00 Feb 15, 2006 page 530 of 900 REJ09B0291-0400 DADR1 Section 15 D/A Converter 15.1.3 Pin Configuration Table 15.1 summarizes the input and output pins of the D/A converter. Table 15.1 Pin Configuration Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage 15.1.4 Register Configuration Table 15.2 summarizes the registers of the D/A converter. Table 15.2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Note: * Abbreviation DADR0 DADR1 DACR MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C Lower 16 bits of the address. Rev. 4.00 Feb 15, 2006 page 531 of 900 REJ09B0291-0400 Section 15 D/A Converter 15.2 15.2.1 Bit Register Descriptions D/A Data Registers 0 and 1 (DADR0, DADR1) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 15.2.2 Bit D/A Control Register (DACR) : 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel 1. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value) Rev. 4.00 Feb 15, 2006 page 532 of 900 REJ09B0291-0400 Section 15 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel 0. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 * Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled *: Don’t care If the H8S/2345 Group enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear the DAE, DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: Read-only bits, always read as 1. Rev. 4.00 Feb 15, 2006 page 533 of 900 REJ09B0291-0400 Section 15 D/A Converter 15.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter module stop mode. Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value) Rev. 4.00 Feb 15, 2006 page 534 of 900 REJ09B0291-0400 Section 15 D/A Converter 15.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 15.2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents × Vref 256 The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin. Rev. 4.00 Feb 15, 2006 page 535 of 900 REJ09B0291-0400 Section 15 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 15.2 Example of D/A Converter Operation 15.4 Usage Notes Setting range for pins other than analog power pin (1) Relationship between AVCC, VCC, AVSS, and Vss The relationship between AVCC, VCC, AVSS, and VSS is AVCC = VCC and AVSS = VSS. Also, the AVCC and AVSS pins should never be left open, even if the D/A converter is not used. (2) Vref setting range The setting range for the reference voltage from the Vref pin is Vref ≤ AVCC. Note: Failure to observe (1) and (2) above could have an adverse effect on the reliability of the LSI. Rev. 4.00 Feb 15, 2006 page 536 of 900 REJ09B0291-0400 Section 16 RAM Section 16 RAM 16.1 Overview The H8S/2345 and H8S/2344 have 4 kbytes of on-chip high-speed static RAM, and the H8S/2343, H8S/2341, and H8S/2340 have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM of the H8S/2345 and H8S/2344 is allocated addresses H'EC00 to H'FBFF (4 kbytes) in the normal modes (modes 1 to 3)*, and addresses H'FFEC00 to H'FFFBFF (4 kbytes) in the advanced modes (modes 4 to 7). The on-chip RAM of the H8S/2343, H8S/2341, and H8S/2340 is allocated addresses H'F400 to H'FBFF (2 kbytes) in the normal modes (modes 1 to 3)*, and addresses H'FFF400 to H'FFFBFF (2 kbytes) in the advanced modes (modes 4 to 7). The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). Note: * ZTAT, mask ROM, and ROMless versions only. Rev. 4.00 Feb 15, 2006 page 537 of 900 REJ09B0291-0400 Section 16 RAM 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFEC00 H'FFEC02 H'FFEC04 H'FFEC01 H'FFEC03 H'FFEC05 H'FFFBFE H'FFFBFF Figure 16.1 Block Diagram of RAM (H8S/2345, Advanced Mode) 16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 16.1 shows the address and initial value of SYSCR. Table 16.1 RAM Register Name System control register Note: * Abbreviation SYSCR Lower 16 bits of the address. R/W R/W Initial Value H'01 Address* H'FF39 Rev. 4.00 Feb 15, 2006 page 538 of 900 REJ09B0291-0400 Section 16 RAM 16.2 16.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 R/W 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 R/W 1 — 0 R/W 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 16.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFEC00 to H'FFFBFF (in the case of the H8S/2345 and H8S/2344) or addresses H'FFF400 to H'FFFBFF (in the case of the H8S/2343, H8S/2341, and H8S/2340) are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 16.4 Usage Note DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0. Rev. 4.00 Feb 15, 2006 page 539 of 900 REJ09B0291-0400 Section 16 RAM Rev. 4.00 Feb 15, 2006 page 540 of 900 REJ09B0291-0400 Section 17 ROM Section 17 ROM 17.1 Overview The H8S/2345 has 128 kbytes of on-chip ROM (flash memory, PROM, or mask ROM); the H8S/2344 has 96 kbytes of on-chip ROM (mask ROM); the H8S/2343 has 64 kbytes of on-chip ROM (mask ROM); and the H8S/2341 has 32 kbytes of on-chip ROM (mask ROM). The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. The flash memory versions of the H8S/2345 Group can be erased and programmed on-board as well as with a PROM programmer. The PROM version of the H8S/2345 Group can be programmed with a PROM programmer, by setting PROM mode. 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 17.1 Block Diagram of ROM (H8S/2345) Rev. 4.00 Feb 15, 2006 page 541 of 900 REJ09B0291-0400 Section 17 ROM 17.1.2 Register Configuration The H8S/2345’s on-chip ROM is controlled by the mode pins and register BCRL. The register configuration is shown in table 17.1. Table 17.1 ROM Register Name Mode control register Bus control register L Note: * Abbreviation MDCR BCRL R/W R/W R/W Initial Value Undefined Undefined Address* H'FF3B H'FED5 Lower 16 bits of the address. 17.2 17.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W Note: * : Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2345 Group. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. Rev. 4.00 Feb 15, 2006 page 542 of 900 REJ09B0291-0400 Section 17 ROM 17.2.2 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 — 0 R/W 5 EAE 1 R/W 4 — 1 R/W 3 — 1 R/W 2 — 1 R/W 1 — 0 R/W 0 WAITE 0 R/W Initial value : R/W : Enabling or disabling of part of the H8S/2345’s on-chip ROM area can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. Bit 5 EAE 0 Description Addresses H'010000 to H'01FFFF are in on-chip ROM (H8S/2345). Addresses H'010000 to H'017FFF are in on-chip ROM and addresses H'018000 to H'01FFFF are a reserved area (in the H8S/2344). Addresses H'010000 to H'01FFFF are a reserved area (in the H8S/2343 and H8S/2341). 1 Note: * Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode). (Initial value) Reserved areas should not be accessed. 17.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in tables 17.2 and 17.3. Rev. 4.00 Feb 15, 2006 page 543 of 900 REJ09B0291-0400 Section 17 ROM Table 17.2 Operating Modes and ROM Area (F-ZTAT) Mode Pin Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Boot mode (advanced expanded mode with 3 on-chip ROM enabled)* Mode 11 Boot mode (advanced 4 single-chip mode)* Mode 12 — Mode 13 Mode 14 User program mode (advanced expanded mode 3 with on-chip ROM enabled)* Mode 15 User program mode (advanced single-chip 4 mode)* 1 1 0 1 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode — 1 0 0 1 1 0 1 — FWE MD2 0 0 MD1 0 MD0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 1 Enabled (128 kbytes)* BCRL EAE — On-Chip ROM — — Disabled 0 1 0 1 — 1 Enabled (128 kbytes)* Enabled (64 kbytes) Enabled (128 kbytes)* Enabled (64 kbytes) — Enabled (128 kbytes)* Enabled (64 kbytes) 2 Enabled (128 kbytes)* 2 1 0 1 — Enabled (64 kbytes) — Enabled (64 kbytes) Enabled (128 kbytes)* Enabled (64 kbytes) 1 Notes: 1. Note that in modes 6, 7, 14, and 15, the on-chip ROM that can be used after a poweron reset is the 64-kbyte area from H'000000 to H'00FFFF. 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev. 4.00 Feb 15, 2006 page 544 of 900 REJ09B0291-0400 Section 17 ROM Table 17.3 Operating Modes and ROM Area (ZTAT or Mask ROM) Mode Pin Operating Mode Mode 0 Mode 1 — Normal expanded mode with on-chip ROM disabled 1 MD2 MD1 MD0 0 0 0 1 BCRL EAE — On-Chip ROM H8S/2345 — H8S/2344 — H8S/2343 — H8S/2341 — Mode 2*1 Normal expanded mode with on-chip ROM enabled Mode 3*1 Normal single-chip mode Mode 4 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled 1 0 Disabled Disabled Disabled Disabled 1 0 0 — Enabled Enabled Enabled Enabled (56 kbytes) (56 kbytes) (56 kbytes) (32 kbytes) Disabled Disabled Disabled Disabled Mode 5 1 Mode 6*1 Advanced expanded mode with on-chip ROM enabled Mode 7*1 Advanced singlechip mode 1 0 0 Enabled (128 kbytes)*2 Enabled*2 Enabled Enabled (96 kbytes) (64 kbytes) (32 kbytes) 1 1 0 Enabled Enabled (64 kbytes) (64 kbytes) Enabled (128 kbytes)*2 Enabled*2 (96 kbytes) 1 Enabled Enabled (64 kbytes) (64 kbytes) Notes: 1. Not used on ROMless version. 2. In H8S/2345 modes 6 and 7, the on-chip ROM available after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Rev. 4.00 Feb 15, 2006 page 545 of 900 REJ09B0291-0400 Section 17 ROM 17.4 17.4.1 PROM Mode PROM Mode Setting The PROM version of the H8S/2345 suspends its microcontroller functions when placed in PROM mode, enabling the on-chip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 EPROM (VPP = 12.5 V). Use of a 100-pin/32-pin socket adapter enables programming with a commercial PROM programmer. Note that the PROM programmer should not be set to page mode as the H8S/2345 does not support page programming. Table 17.4 shows how PROM mode is selected. Table 17.4 Selecting PROM Mode Pin Names MD2, MD1, MD0 STBY PA2, PA1 High Setting Low 17.4.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a socket adapter to the PROM programmer to convert from a 100-pin arrangement to a 32-pin arrangement. Table 17.5 gives ordering information for the socket adapter, and figure 17.2 shows the wiring of the socket adapter. Figure 17.3 shows the memory map in PROM mode. Rev. 4.00 Feb 15, 2006 page 546 of 900 REJ09B0291-0400 Section 17 ROM H8S/2345 Group FP-100B, TFP-100B, TFP-100G 62 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 41 63 43 44 45 46 47 48 50 74 42 75 40, 65, 98 77 78 51 52 7, 18, 31, 49, 68, 88 87 64 57 58 61 FP-100A 64 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 43 65 45 46 47 48 49 50 52 76 44 77 42, 67, 100 79 80 53 54 9, 20, 33 51, 70, 90 89 66 59 60 63 AVSS STBY MD0 MD1 MD2 Legend: VPP Pin RES PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS VSS Pin VPP EPROM socket HN27C101 (32 Pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC 16 Note: Pins not shown in this figure should be left open. : Programming power supply (12.5 V) EO7 to EO0 : Data input/output EA16 to EA0 : Address input : Output enable OE : Chip enable CE : Program PGM Figure 17.2 Wiring of 100-Pin/32-Pin Socket Adapter Rev. 4.00 Feb 15, 2006 page 547 of 900 REJ09B0291-0400 Section 17 ROM Table 17.5 Socket Adapter Socket Adapter Microcontroller H8S/2345 Package 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) MINATO ELECTRONICS INC. ME2345ESNS1H ME2345ESMS1H ME2345ESFS1H ME2345ESHS1H DATA I/O CO. H72345T100D3201 H7234GT100D3201 H7234AQ100D3201 H7234BQ100D3201 Addresses in MCU mode H'000000 Addresses in PROM mode H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 17.3 Memory Map in PROM Mode Rev. 4.00 Feb 15, 2006 page 548 of 900 REJ09B0291-0400 Section 17 ROM 17.5 17.5.1 Programming Overview Table 17.6 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 17.6 Mode Selection in PROM Mode Pins Mode Program Verify Program-inhibit CE L L L L H H Legend: L: Low voltage level H: High voltage level VPP: VPP voltage level VCC: VCC voltage level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input Programming and verification should be carried out using the same specifications as for the standard HN27C101 EPROM. However, do not set the PROM programmer to page mode, as the H8S/2345 does not support page programming. A PROM programmer that only supports page programming cannot be used. When choosing a PROM programmer, check that it supports high-speed programming in byte units. Always set addresses within the range H'00000 to H'1FFFF. 17.5.2 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 17.4 shows the basic high-speed programming flowchart. Tables 17.7 and 17.8 list the electrical characteristics of the chip during programming. Figure 17.5 shows a timing chart. Rev. 4.00 Feb 15, 2006 page 549 of 900 REJ09B0291-0400 Section 17 ROM Start Set programming/verification mode VCC = 6.0V±0.25V, VPP = 12.5V±0.3V Address = 0 n=0 n + 1→ n Yes No n 12 MHz Min 10 — — — — — — — — — Typ 10 — — — — — — — — — Max 10 6.7 20 10* 2 5* 1 Unit bits µs pF kΩ LSB LSB LSB LSB LSB ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 Rev. 4.00 Feb 15, 2006 page 646 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.1.5 D/A Conversion Characteristics Table 20.9 lists the D/A conversion characteristics. Table 20.9 D/A Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Unit bit µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions Rev. 4.00 Feb 15, 2006 page 647 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.1.6 Flash Memory Characteristics Table 20.10 lists the flash memory characteristics. Table 20.10 Flash Memory Characteristics Conditions: VCC = AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = 0 to +75°C (flash memory programming/erase operating temperature range; regular specifications), Ta = 0 to +85°C (flash memory programming/erase operating temperature range; wide-range specifications) Item Programming time*1 *2 *4 Erase time*1 *3 *5 Reprogramming count Programming Wait time after setting SWE bit*1 Wait time after setting PSU bit*1 Wait time after setting P bit*1 *4 Wait time after clearing P bit*1 Wait time after clearing PSU bit*1 Wait time after setting PV bit*1 Wait time after clearing PV bit*1 Max. number of programmings*1 *4 Erase Wait time after setting SWE bit *1 Wait time after setting ESU bit*1 Wait time after setting E bit*1 *6 Wait time after clearing E bit*1 Wait time after clearing ESU bit*1 Wait time after setting EV bit*1 Wait time after clearing EV bit*1 Max. number of erases*1 *6 Symbol tP tE NWEC x y z α β γ η N x y z α β γ η N Min — — — 10 50 150 10 10 4 2 4 — 10 200 5 10 10 20 2 5 120 Typ 10 100 — — — — — — — — — — — — — — — — — — — Max 200 1200 100 — — 200 — — — — — — — 10 — — — — — 240 Unit ms/ 32 bytes ms/block Times µs µs µs µs µs µs µs µs z = 200 µs µs µs µs µs µs µs µs µs Times Test Conditions Wait time after H'FF dummy write*1 ε 1000*5 Times Wait time after H'FF dummy write*1 ε Notes: 1. Time settings should be made in accordance with the programming/erase algorithm. 2. Programming time per 32 bytes. (Indicates the total time the P bit in the flash memory control register 1 (FLMCR1) is set. The program verification time is not included.) 3. Time to erase one block. (Indicates the total time the E bit in FLMCR1 is set. The erase verification time is not included.) Rev. 4.00 Feb 15, 2006 page 648 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 4. Write time maximum value (tP (max.) = wait time after P bit setting (z) × maximum number of programmings (N)). 5. Number of times when the wait time after P bit setting (z) = 200 µs. The maximum number of writes (N) should be set according to the actual set value of z so as not to exceed the maximum programming time (tP (max)). 6. For the maximum erase time (tE (max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): tE (max) = Wait time after E bit setting (z) × maximum number of erases (N) The values of z and N should be set so as to satisfy the above formula. Examples: When z = 5 [ms], N = 240 times When z = 10 [ms], N = 120 times Rev. 4.00 Feb 15, 2006 page 649 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.2 Electrical Characteristics of ZTAT, Mask ROM, and ROMless Versions Absolute Maximum Ratings 20.2.1 Table 20.11 lists the absolute maximum ratings. Table 20.11 Absolute Maximum Ratings Item Power supply voltage Programming voltage* Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC VPP Vin Vin Vref AVCC VAN Topr Tstg Value –0.3 to +7.0 –0.3 to +13.5 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 –55 to +125 Unit V V V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Note: * ZTAT version only. Rev. 4.00 Feb 15, 2006 page 650 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.12 lists the DC characteristics. Table 20.13 lists the permissible output currents. Table 20.12 DC Characteristics (1) 1 Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* , Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, IRQ0 to IRQ7 RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, A to G Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3, 4, A to G Output high voltage Output low voltage Input leakage current All output pins All output pins Ports 1, A to C RES STBY, NMI, MD2 to MD0 Port 4 Symbol VT VT – + + – Min 1.0 — 0.4 VCC – 0.7 Typ — — — — Max — VCC × 0.7 — VCC + 0.3 Unit V V V V Test Conditions VT – VT VIH VCC × 0.7 2.0 2.0 VIL –0.3 –0.3 — — — — — VCC + 0.3 VCC + 0.3 V V AVCC + 0.3 V 0.5 0.8 V V VOH VOL | Iin | VCC – 0.5 3.5 — — — — — — — — — — — — — — 0.4 1.0 10.0 1.0 1.0 V V V V µA µA µA IOH = –200 µA IOH = –1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V Vin = 0.5 to VCC – 0.5 V Three-state leakage current (off state) Ports 1 to 3, A to G ITSI — — 1.0 µA Rev. 4.00 Feb 15, 2006 page 651 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Item MOS input pull-up current Input capacitance Ports A to E Symbol – IP Min 50 Typ — Max 300 Unit µA Test Conditions Vin = 0 V RES NMI All input pins except RES and NMI Cin — — — — — — 80 50 15 pF pF pF Vin = 0 V f = 1 MHz Ta = 25°C Current 2 dissipation* Normal operation Sleep mode Standby 3 mode* 4 ICC* — — — — 60 89 (5.0 V) 40 73 (5.0 V) 0.01 — 5.0 20 mA mA µA mA f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta Analog power supply current Reference current During A/D and D/A conversion Idle During A/D and D/A conversion Idle AlCC — 0.8 2.0 (5.0 V) 0.01 5.0 — AlCC — µA mA Vref = 5.0 V 1.9 3.0 (5.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V RAM standby voltage Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.80 (mA/(MHz × V)) × VCC × f [normal mode] ICC max = 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f [sleep mode] Rev. 4.00 Feb 15, 2006 page 652 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Table 20.12 DC Characteristics (2) 1 Conditions: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V* , Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, IRQ0 to IRQ7 Symbol VT VT – + + – Min VCC × 0.2 — VCC × 0.9 Typ — — — Max — VCC × 0.7 — VCC +0.3 Unit V V V V Test Conditions VT – VT RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, A to G Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3, 4, A to G Output high voltage Output low voltage All output pins All output pins Ports 1, A to C VOH VOL VIL VIH VCC × 0.07 — VCC × 0.7 VCC × 0.7 VCC × 0.7 –0.3 –0.3 — — — — — VCC +0.3 VCC +0.3 V V AVCC +0.3 V VCC × 0.1 VCC × 0.2 V V VCC < 4.0 V 0.8 VCC – 0.5 VCC – 1.0 — — — — — — — — 0.4 1.0 V V V V VCC = 4.0 to 5.5 V IOH = –200 µA IOH = –1 mA IOL = 1.6 mA VCC ≤ 4 V IOL = 5 mA 4.0 < VCC ≤ 5.5 V IOL = 10 mA Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V Vin = 0.5 to VCC – 0.5 V Input leakage current RES STBY, NMI, MD2 to MD0 Port 4 | Iin | — — — — — — — 10.0 1.0 1.0 1.0 µA µA µA µA Three-state leakage current (off state) Ports 1 to 3, A to G ITSI — Rev. 4.00 Feb 15, 2006 page 653 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Item MOS input pull-up current Input capacitance Ports A to E Symbol – IP Min 10 Typ — Max 300 Unit µA Test Conditions VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C RES NMI All input pins except RES and NMI Cin — — — — — — 80 50 15 pF pF pF Current Normal 2 dissipation* operation Sleep mode Standby 3 mode* Analog power supply current Reference current During A/D and D/A conversion Idle During A/D and D/A conversion Idle RAM standby voltage 4 ICC* — — — — 18 45 (3.0 V) 11 37 (3.0 V) 0.01 — 5.0 20 mA mA µA mA f = 10 MHz f = 10 MHz Ta ≤ 50°C 50°C < Ta AlCC — 0.2 2.0 (3.0 V) 0.01 5.0 — AlCC — µA mA Vref = 3.0 V 1.2 3.0 (3.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and VIL max = 0.3V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.80 (mA/(MHz × V)) × VCC × f [normal mode] ICC max = 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f [sleep mode] Rev. 4.00 Feb 15, 2006 page 654 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Table 20.13 Permissible Output Currents Conditions: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Port 1, A to C Other output pins Total of 28 pins including port 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –IOH ∑ –IOH ∑ IOL Symbol IOL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA — — 120 mA — — — — 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 20.13. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 20.4 and 20.5. H8S/2345 Group 2 kΩ Port Darlington Pair Figure 20.4 Darlington Pair Drive Circuit (Example) Rev. 4.00 Feb 15, 2006 page 655 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics H8S/2345 Group 600 Ω Ports 1, A to C LED Figure 20.5 LED Drive Circuit (Example) 20.2.3 AC Characteristics Figure 20.6 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V C RH Figure 20.6 Output Load Circuit Rev. 4.00 Feb 15, 2006 page 656 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Clock Timing: Table 20.14 lists the clock timing Table 20.14 Clock Timing Condition A: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 100 35 35 — — 20 8 500 Max 500 — — 15 15 — — — Condition B Min 50 20 20 — — 10 8 500 Max 500 — — 5 5 — — — Unit ns ns ns ns ns ms ms µs Figure 20.8 Figure 19.2 Figure 20.8 Test Conditions Figure 20.7 Rev. 4.00 Feb 15, 2006 page 657 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Control Signal Timing: Table 20.15 lists the control signal timing. Table 20.15 Control Signal Timing Condition A: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol tRESS tRESW tNMIRS tNMIRH tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min 200 20 250 200 250 10 200 250 10 200 Max — — — — — — — — — — Condition B Min 200 20 200 200 150 10 200 150 10 200 Max — — — — — — — — — — Unit ns tcyc ns ns ns ns ns ns ns ns Figure 20.10 Test Conditions Figure 20.9 Rev. 4.00 Feb 15, 2006 page 658 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Bus Timing: Table 20.16 lists the bus timing. Table 20.16 Bus Timing Condition A: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 Symbol tAD tAS tAH tCSD1 tASD tRSD1 tRSD2 tCASD tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 Min — Max 40 Condition B Min — Max 20 Unit ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 20.11 to Figure 20.15 0.5 × — tcyc – 30 — 0.5 × tcyc – 20 — — — — — 30 0 — — — — — 40 40 40 40 40 — — 1.0 × tcyc – 50 1.5 × tcyc – 50 2.0 × tcyc – 50 2.5 × tcyc – 50 3.0 × tcyc – 50 0.5 × — tcyc – 15 0.5 × — tcyc – 10 — — — — — 15 0 — — — — — 20 20 20 20 20 — — 1.0 × ns tcyc – 25 1.5 × ns tcyc – 25 2.0 × ns tcyc – 25 2.5 × ns tcyc – 25 3.0 × ns tcyc – 25 Rev. 4.00 Feb 15, 2006 page 659 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Condition A Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH tBRQS tBACD tBZD Min — — Max 40 40 Condition B Min — — Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns Figure 20.16 Figure 20.13 Test Conditions Figure 20.11 to Figure 20.15 — 1.0 × tcyc – 40 — 1.5 × tcyc – 40 — 60 — 0.5 × tcyc – 40 0.5 × — tcyc – 20 60 10 60 — — — — — 30 100 1.0 × — tcyc – 20 1.5 × — tcyc – 20 — 30 0.5 × — tcyc – 20 0.5 × — tcyc – 10 30 5 30 — — — — — 15 50 Rev. 4.00 Feb 15, 2006 page 660 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Timing of On-Chip Supporting Modules: Table 20.17 lists the timing of on-chip supporting modules. Table 20.17 Timing of On-Chip Supporting Modules Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item I/O port Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL Min — 50 50 — 50 50 1.5 2.5 — 50 50 1.5 2.5 Max 100 — — 100 — — — — 100 — — — — Condition B Min — 30 30 — 30 30 1.5 2.5 — 30 30 1.5 2.5 Max 50 — — 50 — — — — 50 — — — — ns ns ns tcyc Figure 20.20 Figure 20.22 Figure 20.21 ns tcyc Figure 20.19 ns Figure 20.18 Unit ns Test Conditions Figure 20.17 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Rev. 4.00 Feb 15, 2006 page 661 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics Condition A Item WDT SCI Overflow output delay time Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tWOVD tScyc Min — 4 6 0.4 — — — 100 100 50 Max 100 — — 0.6 1.5 1.5 100 — — — Condition B Min — 4 6 0.4 — — — 50 50 30 Max 50 — — 0.6 1.5 1.5 50 — — — ns ns ns ns Figure 20.26 Figure 20.25 tScyc tcyc Unit ns tcyc Test Conditions Figure 20.23 Figure 20.24 Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time Rev. 4.00 Feb 15, 2006 page 662 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.2.4 A/D Conversion Characteristics Table 20.18 lists the A/D conversion characteristics. Table 20.18 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Notes: 1. 2. 3. 4. 4.0 V ≤ AVCC ≤ 5.5 V 2.7 V ≤ AVCC < 4.0 V φ ≤ 12 MHz φ > 12 MHz Min 10 — — — — — — — — — Typ 10 — — — — — — — — — Max 10 13.4 20 1 10* Condition B Min 10 — — — — — — — — — Typ 10 — — — — — — — — — Max 10 6.7 20 3 10* Unit bits µs pF kΩ LSB LSB LSB LSB LSB 5* 2 5* 4 ±7.5 ±7.5 ±7.5 ±0.5 ±8.0 ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 Rev. 4.00 Feb 15, 2006 page 663 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.2.5 D/A Conversion Characteristics Table 20.19 lists the D/A conversion characteristics. Table 20.19 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Min 8 — — — Condition B Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Unit bit µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions Rev. 4.00 Feb 15, 2006 page 664 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.3 Operation Timing The operation timing is described below. 20.3.1 Clock Timing The clock timing is shown below. System Clock Timing: Figure 20.7 shows the system clock timing. tcyc tCH φ tCL tCr tCf Figure 20.7 System Clock Timing Oscillator Settling Timing: Figure 20.8 shows the oscillator settling timing. EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC1 φ Figure 20.8 Oscillator Settling Timing Rev. 4.00 Feb 15, 2006 page 665 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics 20.3.2 Control Signal Timing The control signal timing is shown below. Reset Input Timing: Figure 20.9 shows the reset input timing. Interrupt Input Timing: Figure 20.10 shows the interrupt input timing for NMI and IRQ. φ tRESS RES tRESW tNMIRS NMI tMDS MD2 to MD0 tMDS FWE tRESS tRESS tNMIRH Figure 20.9 Reset Input Timing Rev. 4.00 Feb 15, 2006 page 666 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics φ tNMIS NMI tNMIW tNMIH IRQi (i = 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input tIRQW tIRQH Figure 20.10 Interrupt Input Timing 20.3.3 Bus Timing The bus timing is shown below. Basic Bus Timing (Two-State Access): Figure 20.11 shows the basic bus timing for external twostate access. Basic Bus Timing (Three-State Access): Figure 20.12 shows the basic bus timing for external three-state access. Basic Bus Timing (Three-State Access with One Wait State): Figure 20.13 shows the basic bus timing for external three-state access with one wait state. Burst ROM Access Timing (Two-State Access): Figure 20.14 shows the burst ROM access timing for two-state access. Burst ROM Access Timing (One-State Access): Figure 20.15 shows the burst ROM access timing for one-state access. External Bus Release Timing: Figure 20.16 shows the external bus release timing. Rev. 4.00 Feb 15, 2006 page 667 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics T1 φ tAD A23 to A0 tCSD1 CS3 to CS0 tASD AS tAS T2 tAH tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 20.11 Basic Bus Timing (Two-State Access) Rev. 4.00 Feb 15, 2006 page 668 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics T1 φ T2 T3 tAD A23 to A0 tCSD1 CS3 to CS0 tASD AS tASD tAS tAH tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 20.12 Basic Bus Timing (Three-State Access) Rev. 4.00 Feb 15, 2006 page 669 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics T1 φ T2 TW T3 A23 to A0 CS3 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 20.13 Basic Bus Timing (Three-State Access with One Wait State) Rev. 4.00 Feb 15, 2006 page 670 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics T1 φ T2 or T3 T1 T2 tAD A23 to A0 tAS CS3 to CS0 tASD AS tASD tAH tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 20.14 Burst ROM Access Timing (Two-State Access) Rev. 4.00 Feb 15, 2006 page 671 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics T1 φ T2 or T3 T1 tAD A23 to A0 CS3 to CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 20.15 Burst ROM Access Timing (One-State Access) Rev. 4.00 Feb 15, 2006 page 672 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics φ tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS3 to CS0, AS, RD, HWR, LWR tBACD tBZD Figure 20.16 External Bus Release Timing 20.3.4 Timing for On-Chip Supporting Modules Figure 20.17 to figure 20.26 show the timings for on-chip peripheral modules. T1 φ T2 tPRS Ports 1 to 4, A to G (read) tPRH tPWD Ports 1 to 3, A to G (write) Figure 20.17 I/O Port Input/Output Timing Rev. 4.00 Feb 15, 2006 page 673 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 20.18 TPU Input/Output Timing φ tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 20.19 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 20.20 8-Bit Timer Output Timing Rev. 4.00 Feb 15, 2006 page 674 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics φ tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 20.21 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 20.22 8-Bit Timer Reset Input Timing φ tWOVD WDTOVF tWOVD Figure 20.23 WDT Output Timing (ZTAT Version, Mask ROM Version, and ROMless Version Only) tSCKW SCK0 and SCK1 tScyc tSCKr tSCKf Figure 20.24 SCK Clock Input Timing Rev. 4.00 Feb 15, 2006 page 675 of 900 REJ09B0291-0400 Section 20 Electrical Characteristics SCK0 and SCK1 tTXD TxD0 and TxD1 transit data tRXS RxD0 and RxD1 receive data tRXH Figure 20.25 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 20.26 A/D Converter External Trigger Input Timing 20.4 Usage Note Although the F-ZTAT, ZTAT, mask ROM, and ROMless versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is estimated using the F-ZTAT or ZTAT version, a similar evaluation should also be performed using the mask ROM version. Rev. 4.00 Feb 15, 2006 page 676 of 900 REJ09B0291-0400 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation General register (destination)* 1 General register (source)* 1 General register* General register (32-bit register) 2 Multiply-and-accumulate register (32-bit register)* Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ¬ Logical NOT (logical complement) ( ) Contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2345 Group. Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → 1 Rev. 4.00 Feb 15, 2006 page 677 of 900 REJ09B0291-0400 Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of instruction * 0 1 — Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction Rev. 4.00 Feb 15, 2006 page 678 of 900 REJ09B0291-0400 (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Table A.1 Condition Code No. of States*1 Advanced 0— 0— 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic MOV MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd W W 2 2 W4 B B B 2 4 6 B 2 B 8 B 4 B 2 B 6 B 4 B 2 @aa:8→Rd8 @aa:16→Rd8 @aa:32→Rd8 Rs8→@ERd Rs8→@(d:16,ERd) Rs8→@(d:32,ERd) ERd32-1→ERd32,Rs8→@ERd Rs8→@aa:8 Rs8→@aa:16 Rs8→@aa:32 #xx:16→Rd16 Rs16→Rd16 @ERs→Rd16 B 2 B 8 @(d:32,ERs)→Rd8 @ERs→Rd8,ERs32+1→ERs32 B 4 @(d:16,ERs)→Rd8 B 2 @ERs→Rd8 B 2 Rs8→Rd8 MOV.B #xx:8,Rd B2 #xx:8→Rd8 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— Instruction Set Operation IHNZVC 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 679 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0— 0— 0— 3 5 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic MOV MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd L L L L 10 4 6 8 L 6 L 4 L 2 L6 W 6 W 4 W 2 W 8 W 4 W 2 Rs16→@ERd Rs16→@(d:16,ERd) Rs16→@(d:32,ERd) W 6 @aa:32→Rd16 W 4 @aa:16→Rd16 W 2 W 8 @(d:32,ERs)→Rd16 MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 —— —— Appendix A Instruction Set Operation IHNZVC @ERs→Rd16,ERs32+2→ERs32 — — —— —— —— —— —— 0— 0— 0— 0— 0— 0— —— 0— 3 4 2 3 5 3 3 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ERd32-2→ERd32,Rs16→@ERd — — Rs16→@aa:16 Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 @(d:16,ERs)→ERd32 @(d:32,ERs)→ERd32 @ERs→ERd32,ERs32+4→@ERs32 @aa:16→ERd32 @aa:32→ERd32 —— —— —— —— —— —— —— —— —— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 680 of 900 REJ09B0291-0400 0— 0— 0— 0— 0— 0— 0— 0— 0— 4 3 1 4 5 7 5 5 6 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0— 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.L ERn PUSH PUSH.L ERn LDM LDM @SP+,(ERm-ERn) L 4 L 4 PUSH.W Rn W 2 L 4 POP.W Rn W 2 L 8 ERs32→@aa:32 @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) Repeated for each register restored STM STM (ERm-ERn),@-SP L 4 (SP-4→SP,ERn32→@SP) Repeated for each register saved MOVFPE MOVTPE MOVTPE Rs,@aa:16 MOVFPE @aa:16,Rd Cannot be used in the H8S/2345 Group Cannot be used in the H8S/2345 Group L 6 ERs32→@aa:16 L 4 10 ERs32→@(d:32,ERd) 6 ERs32→@(d:16,ERd) L 4 ERs32→@ERd —— —— —— Operation IHNZVC 0— 0— 0— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— —————— 5 7 5 5 6 3 5 3 5 7/9/11 [1] ↔↔↔↔↔↔↔↔↔↔ ERd32-4→ERd32,ERs32→@ERd — — —————— ↔↔↔↔↔↔↔↔↔↔ 7/9/11 [1] [2] [2] Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 681 of 900 REJ09B0291-0400 (2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic ADD ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX Rs,Rd ADDS ADDS #2,ERd ADDS #4,ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA SUB SUB.W #xx:16,Rd SUB.B Rs,Rd B W4 DAA Rd B L 2 2 2 L 2 W 2 W 2 INC.B Rd B 2 L 2 L 2 ADDS #1,ERd L 2 B 2 ADDX #xx:8,Rd B2 L 2 L6 W 2 Rd16+Rs16→Rd16 ERd32+#xx:32→ERd32 ERd32+ERs32→ERd32 Rd8+#xx:8+C→Rd8 Rd8+Rs8+C→Rd8 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 W4 Rd16+#xx:16→Rd16 B 2 Rd8+Rs8→Rd8 ADD.B #xx:8,Rd B2 Rd8+#xx:8→Rd8 Operation IHNZVC — — ↔ ↔ ↔ ↔ 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 [5] 1 [5] 1 —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —* — * 1 1 1 1 1 1 1 1 1 1 — [3] 2 ↔↔ ↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔↔↔ ↔ ↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔ ↔↔ ↔↔↔↔↔ ↔↔↔ ↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 682 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Operation Rd16-Rs16→Rd16 ERd32-#xx:32→ERd32 2 Rd8-#xx:8-C→Rd8 2 2 2 2 2 2 2 2 2 2 2 2 ERd32-1→ERd32 ERd32-2→ERd32 ERd32-4→ERd32 Rd8-1→Rd8 Rd16-1→Rd16 Rd16-2→Rd16 ERd32-1→ERd32 ERd32-2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8-C→Rd8 ERd32-ERs32→ERd32 SUB SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX SUBX Rs,Rd SUBS SUBS #2,ERd SUBS #4,ERd DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS MULXU MULXU.W Rs,ERd W MULXU.B Rs,Rd B DAS Rd B L L W W DEC.B Rd B L L SUBS #1,ERd L B SUBX #xx:8,Rd B2 L L6 SUB.W Rs,Rd W 2 IHNZVC — [3] — [4] — [4] 3 1 ↔↔↔↔↔ ↔↔↔ — — ↔↔ [5] ↔↔↔↔↔ ↔↔↔↔↔ [5] 1 1 —————— —————— —————— —— —— —— —— —— —* — — — — — *— 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔ Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — Rd16×Rs16→ERd32 (unsigned multiplication) —————— 12 20 MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 (signed multiplication) Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 683 of 900 REJ09B0291-0400 MULXS MULXS.B Rs,Rd B 4 —— ↔↔ ↔↔ —— Rd8×Rs8→Rd16 (signed multiplication) —— —— 13 21 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 12 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic DIVXU RdL: quotient) (unsigned division) DIVXU.W Rs,ERd W 2 DIVXU.B Rs,Rd B 2 Operation IHNZVC Appendix A Instruction Set Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — — Rd: quotient) (unsigned division) 20 DIVXS divxs.B Rs,Rd B 4 Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — — RdL: quotient) (signed division) NEG.L ERd EXTU EXTU.L ERd L EXTU.W Rd W L 2 2 2 0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32) — ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔ —— 0 ↔↔↔ ↔↔ ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 684 of 900 REJ09B0291-0400 13 DIVXS.W Rs,ERd Rd8-#xx:8 2 Rd8-Rs8 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 W 4 ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — — Rd: quotient) (signed division) CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.W Rd W NEG.B Rd B L L6 W W4 B CMP.B #xx:8,Rd B2 — — 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 1 1 1 —— 0 0— 0— 1 1 21 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic EXTS ( of Rd16) EXTS.W Rd W 2 ( of Rd16)→ Operation IHNZVC ( of ERd32) @ERd-0→CCR set, (1)→ ( of @ERd) MAC CLRMAC LDMAC LDMAC ERs,MACL STMAC STMAC MACL,ERd STMAC MACH,ERd LDMAC ERs,MACH CLRMAC MAC @ERn+, @ERm+ Cannot be used in the H8S/2345 Group [2] ↔ ↔ TAS TAS @ERd B 4 —— ↔ ↔ EXTS.L ERd L 2 ( of ERd32)→ —— ↔ ↔ —— 0— 1 0— 1 0— 4 Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 685 of 900 REJ09B0291-0400 (3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd L B W L L6 4 2 2 2 W 2 W4 B 2 B2 L 4 L6 W 2 W4 B 2 B2 L 4 L6 W 2 Rd16∧Rs16→Rd16 ERd32∧#xx:32→ERd32 ERd32∧ERs32→ERd32 Rd8∨#xx:8→Rd8 Rd8∨Rs8→Rd8 Rd16∨#xx:16→Rd16 Rd16∨Rs16→Rd16 ERd32∨#xx:32→ERd32 ERd32∨ERs32→ERd32 Rd8⊕#xx:8→Rd8 Rd8⊕Rs8→Rd8 Rd16⊕#xx:16→Rd16 Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 ERd32⊕ERs32→ERd32 ¬ Rd8→Rd8 ¬ Rd16→Rd16 ¬ ERd32→ERd32 W4 Rd16∧#xx:16→Rd16 B 2 Rd8∧Rs8→Rd8 B2 Rd8∧#xx:8→Rd8 Operation IHNZVC —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 686 of 900 REJ09B0291-0400 (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L L W 2 2 2 W 2 C MSB LSB B 2 0 B 2 L 2 L 2 W 2 W 2 MSB LSB C B 2 B 2 L 2 L 2 W 2 C MSB W 2 LSB B 2 0 B 2 Operation IHNZVC —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 687 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0 0 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L L 2 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 — — — — — — — MSB — — LSB C W 2 — C MSB LSB B 2 — B 2 — L 2 — L 2 — W 2 — MSB LSB W 2 — 0 C B 2 — B 2 — Operation IHNZVC —— 0 Appendix A Instruction Set —— 0 —— 0 0 —— 0 0 —— 0 0 —— 0 —— —— —— —— —— —— —— —— —— —— —— —— 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 688 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd C MSB ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L 2 L 2 W 2 — 1 W 2 — MSB LSB C B 2 — B 2 — L 2 L 2 W 2 W 2 LSB B 2 B 2 —— —— —— —— —— —— —— —— —— —— —— —— Operation IHNZVC 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 689 of 900 REJ09B0291-0400 (5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B B B B 2 4 4 6 B B B 4 6 8 B 4 BCLR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←1 (Rn8 of @ERd)←1 (Rn8 of @aa:8)←1 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 (#xx:3 of @ERd)←0 (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 (#xx:3 of @aa:32)←0 (Rn8 of Rd8)←0 (Rn8 of @ERd)←0 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 B 8 B 6 (#xx:3 of @aa:16)←1 (#xx:3 of @aa:32)←1 B 4 (#xx:3 of @aa:8)←1 B 4 (#xx:3 of @ERd)←1 BSET #xx:3,Rd B 2 (#xx:3 of Rd8)←1 Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 Rev. 4.00 Feb 15, 2006 page 690 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 6 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BCLR BNOT BNOT #xx:3,@ERd [¬ (#xx:3 of @ERd)] BNOT #xx:3,@aa:8 [¬ (#xx:3 of @aa:8)] BNOT #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)← [¬ (#xx:3 of @aa:16)] BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)← [¬ (#xx:3 of @aa:32)] BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] B 4 (#xx:3 of @aa:8)← B 4 (#xx:3 of @ERd)← BNOT #xx:3,Rd B 2 BCLR Rn,@aa:32 B 8 (Rn8 of @aa:32)←0 Operation IHNZVC —————— (#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — —————— 4 —————— 4 —————— 5 —————— 6 —————— (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← [¬ (Rn8 of @aa:16)] —————— 1 4 4 5 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32)← [¬ (Rn8 of @aa:32)] —————— 6 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B B B BTST #xx:3,Rd B 2 4 4 6 ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z ——— ——— ——— ——— —— —— —— —— 1 3 3 4 ↔↔↔↔ Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 691 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced —— —— 5 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BTST BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,@ERd BST #xx:3,@aa:8 B B BST #xx:3,Rd B 2 4 4 B B B 4 6 8 B 4 BILD #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 B 8 (#xx:3 of Rd8)→C (#xx:3 of @ERd)→C (#xx:3 of @aa:8)→C (#xx:3 of @aa:16)→C (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C ¬ (#xx:3 of @ERd)→C ¬ (#xx:3 of @aa:8)→C ¬ (#xx:3 of @aa:16)→C ¬ (#xx:3 of @aa:32)→C C→(#xx:3 of Rd8) C→(#xx:3 of @ERd) C→(#xx:3 of @aa:8) B 6 ¬ (Rn8 of @aa:16)→Z ¬ (Rn8 of @aa:32)→Z B 4 ¬ (Rn8 of @aa:8)→Z B 4 ¬ (Rn8 of @ERd)→Z B 2 ¬ (Rn8 of Rd8)→Z B 8 ¬ (#xx:3 of @aa:32)→Z Operation IHNZVC ——— ——— ——— ——— ——— ——— Appendix A Instruction Set —— —— —— —— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 3 3 4 5 1 3 3 4 5 1 3 3 4 5 —————— —————— —————— 1 4 4 ↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 692 of 900 REJ09B0291-0400 ↔↔↔↔↔↔ Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 5 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,@ERd B BOR #xx:3,Rd B B 2 4 B B B 4 4 6 8 BIAND #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 B 8 B 6 B 4 ¬ C→(#xx:3 of @aa:8) ¬ C→(#xx:3 of @aa:16) ¬ C→(#xx:3 of @aa:32) C∧(#xx:3 of Rd8)→C C∧(#xx:3 of @ERd)→C C∧(#xx:3 of @aa:8)→C C∧(#xx:3 of @aa:16)→C C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @ERd)]→C C∧[¬ (#xx:3 of @aa:8)]→C C∧[¬ (#xx:3 of @aa:16)]→C C∧[¬ (#xx:3 of @aa:32)]→C C∨(#xx:3 of Rd8)→C C∨(#xx:3 of @ERd)→C B 4 ¬ C→(#xx:3 of @ERd) B 2 ¬ C→(#xx:3 of Rd8) B 8 C→(#xx:3 of @aa:32) B 6 C→(#xx:3 of @aa:16) Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 ↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 693 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 3 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BOR BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B B B 4 4 6 8 BIXOR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 BXOR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 C∨[¬ (#xx:3 of Rd8)]→C C∨[¬ (#xx:3 of @ERd)]→C C∨[¬ (#xx:3 of @aa:8)]→C C∨[¬ (#xx:3 of @aa:16)]→C C∨[¬ (#xx:3 of @aa:32)]→C C⊕(#xx:3 of Rd8)→C C⊕(#xx:3 of @ERd)→C C⊕(#xx:3 of @aa:8)→C C⊕(#xx:3 of @aa:16)→C C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C C⊕[¬ (#xx:3 of @ERd)]→C C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C C⊕[¬ (#xx:3 of @aa:32)]→C B 8 C∨(#xx:3 of @aa:32)→C B 6 C∨(#xx:3 of @aa:16)→C B 4 C∨(#xx:3 of @aa:8)→C Operation IHNZVC ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— Appendix A Instruction Set 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 4.00 Feb 15, 2006 page 694 of 900 REJ09B0291-0400 (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Bcc BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 — — — — — — — 4 2 4 2 4 2 4 V=0 Z=1 Z=0 — 2 — 4 C=1 — 2 — 4 C=0 — 2 — 4 C∨Z=1 — 2 — 4 C∨Z=0 — 2 else next; — 4 PC←PC+d Never BRA d:8(BT d:8) — 2 if condition is true then Always IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 695 of 900 REJ09B0291-0400 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Bcc BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 — — 2 4 — 4 — 2 — 4 — 2 — 4 N⊕V=1 — 2 — 4 N⊕V=0 — 2 — 4 N=1 — 2 N=0 — 4 BVS d:8 — 2 V=1 IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— Appendix A Instruction Set 2 3 2 3 2 3 2 3 Rev. 4.00 Feb 15, 2006 page 696 of 900 REJ09B0291-0400 Z∨(N⊕V)=0 — — — — — — —————— Z∨(N⊕V)=1 — — — — — — —————— 2 3 2 3 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 2 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic JMP JMP @aa:24 JMP @@aa:8 BSR BSR d:16 JSR JSR @aa:24 JSR @@aa:8 RTS RTS — — 2 2 PC←@SP+ — 4 JSR @ERn — 2 — 4 PC→@-SP,PC←ERn PC→@-SP,PC←aa:24 PC→@-SP,PC←@aa:8 BSR d:8 — 2 PC→@-SP,PC←PC+d:8 PC→@-SP,PC←PC+d:16 — 2 PC←@aa:8 — 4 PC←aa:24 JMP @ERn — 2 PC←ERn Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— 3 5 4 5 4 5 6 5 Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 697 of 900 REJ09B0291-0400 (7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 8 [9] Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic TRAPA EXR→@-SP,→PC PC←@SP+ SLEEP LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W W W W W W W 10 4 4 6 6 8 8 W 10 W 6 W 6 W 4 W 4 B 2 B 2 Rs8→CCR Rs8→EXR @ERs→CCR @ERs→EXR @(d:16,ERs)→CCR @(d:16,ERs)→EXR @(d:32,ERs)→CCR @(d:32,ERs)→EXR @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR @aa:32→EXR B4 #xx:8→EXR LDC #xx:8,CCR B2 #xx:8→CCR SLEEP — Transition to power-down state EXR←@SP+,CCR←@SP+, TRAPA #xx:2 — PC→@-SP,CCR→@-SP, Operation IHNZVC 1 ————— ↔ ↔ ↔ ↔ ↔ ↔ RTE RTE — 5 [9] ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev. 4.00 Feb 15, 2006 page 698 of 900 REJ09B0291-0400 —————— 2 1 —————— 2 1 —————— 1 3 —————— 3 4 —————— 4 6 —————— 6 4 —————— 4 4 —————— 4 5 —————— 5 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,EXR ORC ORC #xx:8,EXR XORC XORC #xx:8,EXR NOP NOP XORC #xx:8,CCR B4 B2 B4 — ORC #xx:8,CCR B2 B4 ANDC #xx:8,CCR B2 W 8 W 8 W 6 W 6 W 4 W 4 W 10 W 10 W 6 EXR→@(d:16,ERd) CCR→@(d:32,ERd) EXR→@(d:32,ERd) W 6 CCR→@(d:16,ERd) W 4 EXR→@ERd W 4 CCR→@ERd B 2 EXR→Rd8 B 2 CCR→Rd8 Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— 1 3 3 4 4 6 6 4 —————— 4 ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd CCR→@aa:16 EXR→@aa:16 CCR→@aa:32 EXR→@aa:32 CCR∧#xx:8→CCR EXR∧#xx:8→EXR CCR∨#xx:8→CCR EXR∨#xx:8→EXR CCR⊕#xx:8→CCR EXR⊕#xx:8→EXR 2 PC←PC+2 —————— —————— —————— —————— 4 4 5 5 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— 2 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— 2 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— —————— 2 1 Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 699 of 900 REJ09B0291-0400 (8) Block Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic EEPMOV EEPMOV.B — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; Operation IHNZVC —————— Rev. 4.00 Feb 15, 2006 page 700 of 900 REJ09B0291-0400 EEPMOV.W — —————— 4+2n*2 4+2n*2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2345 Group. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. A.2 Instruction Mnemonic Size 1st byte 8 0 7 IMM 0 7 IMM 0 0 0 0 9 IMM rs IMM rs 6 IMM rs 6 0 erd IMM 6 6 0 ers 0 erd 0 IMM 4 IMM 0 IMM 0 erd abs 1 abs abs 3 disp 0 disp 1 0 disp 0 disp 0 0 7 6 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 0 6 0 IMM 0 7 rd 1 0 6 F rd rd rd rd 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 1 0 erd 9 rs rd 9 1 rd 8 rs rd rd IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L L L L B B B B W W L L B B B B B B B — — — — ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #2,ERd ADDS #4,ERd ADDX ADDX Rs,Rd AND AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,EXR BAND BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BRA d:8 (BT d:8) BAND #xx:3,Rd ANDC #xx:8,CCR AND.B #xx:8,Rd ADDX #xx:8,Rd ADDS #1,ERd ADD Table A.2 Instruction Format Instruction Codes Table A.2 shows the instruction codes. Instruction Codes Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 701 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D 0 disp E disp F 0 disp 0 disp disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 8 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Bcc Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 702 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 7 7 0 IMM 0 IMM abs 0 IMM 7 2 0 IMM abs 7 2 0 0 0 7 abs 1 3 rn 0 erd abs 1 abs abs 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 7 6 0 1 IMM 0 7 6 1 IMM 0 abs 1 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 0 7 7 1 IMM 0 7 7 1 IMM 0 abs 1 3 1 IMM 0 erd abs 1 3 0 0 7 0 7 4 4 rd 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 0 0 7 7 0 7 7 0 rd 0 0 7 6 0 7 6 0 rd 8 8 6 2 rn 0 6 2 rn 0 6 2 rn 0 0 6 2 rn 0 rd 8 8 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 A A E C 4 A A E C 7 A A E C 6 A A F D 2 A A F 7 2 D 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIOR #xx:3,Rd BILD #xx:3,Rd BIAND #xx:3,Rd BCLR Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 703 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 6 1 IMM 0 erd abs 1 abs abs 6 1 IMM 7 0 1 IMM 3 1 IMM 0 erd abs 1 abs abs 7 1 IMM 3 0 IMM 0 erd abs 1 abs abs 3 0 IMM 0 erd abs 1 abs abs 3 rn 0 erd abs 1 3 8 8 6 0 6 1 1 abs abs rd rn rn 0 0 6 1 rn 0 6 1 rn 0 8 8 7 0 IMM 1 0 7 1 0 IMM 0 7 1 0 IMM 0 0 0 IMM 7 1 0 rd 0 0 7 7 7 0 IMM 7 0 0 IMM 0 7 7 0 IMM 0 0 0 IMM 7 7 0 rd 0 0 7 5 0 5 1 IMM 0 7 1 IMM 5 0 0 1 IMM 7 5 0 rd 8 8 6 7 0 6 1 IMM 7 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BNOT #xx:3,Rd BLD #xx:3,Rd BIXOR #xx:3,Rd BIST Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 704 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 7 7 7 6 abs abs 7 4 0 IMM 6 7 7 7 6 abs abs 6 6 7 0 erd abs 1 abs abs 3 disp 0 disp 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 3 C 0 erd 0 0 rd 0 6 3 rn 0 0 rd 7 7 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 6 7 0 6 7 0 IMM 0 IMM abs abs rd 0 0 6 7 0 IMM 0 6 7 0 IMM 0 0 8 8 6 0 6 0 rn 0 rn 0 6 0 rn 0 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 A A E C 3 A A F D 7 C 5 A A F D 0 6 0 rn 0 0 rn rd A 3 8 A 0 IMM 1 8 7 0 0 7 0 0 IMM 0 F abs 0 IMM 7 0 0 D 0 erd 0 IMM 0 7 0 0 0 0 IMM rd A 3 0 A 0 IMM 1 0 7 4 0 0 E abs 0 IMM 7 4 0 C 0 erd 0 IMM 0 7 4 0 4 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:16 BST BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST #xx:3,Rd BST #xx:3,Rd BSR d:8 BSET #xx:3,Rd BOR Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 705 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 7 abs 1 abs abs 6 3 rn 0 3 0 IMM 0 erd 0 IMM 0 IMM abs abs 7 5 7 0 IMM 5 0 0 IMM 0 0 abs 1 3 0 0 7 5 0 7 5 0 rd 0 0 6 3 rn 0 6 6 7 7 7 6 6 Cannot be used in the H8S/2345 Group A IMM rs 2 IMM rs 2 0 erd IMM 1 ers 0 erd 0 0 0 5 D 7 0 erd 0 erd 0 0 rd 0 erd C 5 D 4 5 5 9 9 8 8 F F 5 5 1 3 rs rs rd 0 erd F D D rs rs rd rd rd rd rd rd rd rd 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B B 3 1 1 1 B B B B A F F F A D 9 C rd A A E C 5 A A E 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B — B B W W L L B B B W W L L B W B W — — BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.W Rs,ERd DIVXU DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W DIVXU.B Rs,Rd DIVXS.B Rs,Rd DEC.B Rd DAS Rd DAA Rd CMP.B #xx:8,Rd BTST Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 706 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 4 4 4 4 4 4 4 4 1 1 4 1 0 1 0 1 0 1 6 7 7 6 6 6 6 0 6 F F 8 8 D D B B 1 6 9 0 6 9 rs 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 0 0 0 0 0 0 0 disp disp 6 6 B B disp disp 2 2 0 0 disp disp rs 1 0 7 0 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 0 ern B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L — — — — — — B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU EXTU.L ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @aa:24 JMP @@aa:8 JSR JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC #xx:8,CCR JSR @ERn JMP @ERn EXTU.W Rd EXTS Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 707 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 0 0 0 0 ern+1 0 ern+2 0 ern+3 0 0 Cannot be used in the H8S/2345 Group 1 3 0 6 D 7 1 2 0 6 D 7 1 1 0 6 D 7 1 0 abs 4 1 6 B 2 1 0 abs 4 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L — B IMM rs 0 ers 0 ers 0 ers 0 ers abs 0 abs abs 2 1 erd 1 erd 0 erd 1 erd abs 8 A 0 rs 0 ers 0 ers 0 ers rd rd rd rd 0 8 6 B disp 2 rd disp rs IMM rs abs abs rs 0 6 A A rs disp rs disp rs rd rd rd 0 rd 6 A 2 rd disp disp rd rd B B B B B B B B B B B B B B B W W W W W 7 6 F 6 9 0 D 7 9 6 A 6 A 3 rs 6 C 7 8 6 E 6 8 6 A 6 A 2 rd 6 C 7 8 6 E 6 8 0 C F rd LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV LDC Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 708 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 6 0 ers 0 abs abs 2 1 erd 1 erd disp 6 disp B A rs 0 erd 1 erd 8 abs abs IMM A 0 0 erd 1 ers 0 erd 0 0 ers 0 erd 0 ers 0 erd 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 1 erd 0 ers B B 6 8 A 0 ers 0 ers abs abs 6 B disp A 0 ers disp abs abs 0 6 B disp 2 0 erd disp 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 6 D 0 7 8 0 6 F 0 6 9 0 6 B 0 6 B 0 6 D 0 7 8 0 6 F 0 6 9 rs rs rs 0 rs rs rd rd 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 F A B B D 8 F 9 B B D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)* L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.W Rs,ERd MULXU MULXU.W Rs,ERd W 5 2 MULXU.B Rs,Rd B 5 0 W 0 1 C rs rs MULXS.B Rs,Rd B 0 1 C B 0 0 rd 0 erd 5 5 0 2 rs rs rd 0 erd B L L L MOV Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 709 of 900 REJ09B0291-0400 Cannot be used in the H8S/2345 Group Instruction Mnemonic Size 1st byte 1 1 1 0 erd 0 rd rd 0 erd IMM rs 4 IMM rs 4 0 erd 0 6 4 0 ers 0 erd IMM 4 0 4 IMM 7 0 6 D 7 0 ern F 0 6 D F 8 C 9 D B 0 erd 0 erd F rd rd rd rd 0 rn 0 ern 0 rn 1 IMM F rd rd rd 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 3 7 1 7 0 0 0 7 B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L — B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,EXR POP POP.L ERn PUSH PUSH.L ERn ROTL ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd ROTL.B Rd PUSH.W Rn POP.W Rn ORC #xx:8,CCR NOT.B Rd NOP NEG Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 710 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — — B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd RTS SHAL ROTXR.B Rd ROTXL.B Rd ROTR Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 711 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 6 6 6 6 0 1 4 4 4 1 0 1 7 7 6 6 1 0 1 9 9 F F 8 8 D D 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 4 1 4 1 4 1 4 1 4 2 1 2 0 1 8 1 7 1 3 1 5 1 1 1 4 1 0 0 7 0 3 0 5 0 1 0 4 0 0 1 F 1 B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd W W STC SHLL.B Rd SHAR Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 712 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 0 0 0 0 0 0 0 Cannot be used in the H8S/2345 Group 1 0 ern 3 0 6 D F 1 0 ern 2 0 6 D F 1 0 ern 1 0 6 D F 1 abs 4 1 6 B A 0 1 abs 4 0 6 B A 0 1 abs 4 1 6 B 8 0 1 abs 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B 1 7 IMM 1 7 IMM 1 1 1 1 B IMM rs E 00 IMM IMM rs 5 rs 5 F rd 0 erd 0 6 5 IMM 0 ers 0 erd rd rd IMM 0 0 7 B rd 0 erd C 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 3 0 erd 9 rs rd 9 3 rd W W L L L L L B B B — B B W W L L 8 rs rd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #2,ERd SUBS #4,ERd SUBX SUBX Rs,Rd TAS TRAPA XOR XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XOR.B #xx:8,Rd TRAPA #x:2 TAS @ERd SUBX #xx:8,Rd SUBS #1,ERd STC Instruction Format 10th byte Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 713 of 900 REJ09B0291-0400 Instruction Mnemonic Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B XORC #xx:8,CCR XORC #xx:8,EXR XORC Instruction Format 10th byte Appendix A Instruction Set Note: * Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) Rev. 4.00 Feb 15, 2006 page 714 of 900 REJ09B0291-0400 The register fields specify general registers as follows. Address Register 32-Bit Register 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 0000 0001 • • • 0111 1000 1001 • • • 1111 General Register Register Field General Register R0H R1H • • • R7H R0L R1L • • • R7L 8-Bit Register Register Field 000 001 • • • 111 ER0 ER1 • • • ER7 General Register A.3 Table A.3 Instruction when most significant bit of BH is 0. Instruction code AH AL BH BL Instruction when most significant bit of BH is 1. 1st byte 2nd byte AL AH 0 NOP Table A.3(2) OR MOV.B 3 4 BRA BVS JMP BPL MULXU MOV MOV Table A.3(2) BSET 7 8 ADD ADDX CMP SUBX OR XOR AND MOV 9 A B C D E F Note: * Cannot be used in the H8S/2345 Group. BNOT BCLR BTST DIVXU RTS BSR RTE TRAPA MULXU DIVXU Table A.3(2) BRN BCC BNE BEQ BVC BHI BLS BCS 5 6 BMI BGE BSR BLT XOR AND SUB Table A.3(2) ORC XORC ANDC LDC ADD 1 2 MOV CMP 0 9 A 1 4 5 6 7 8 B C D 2 3 E ADDX SUBX F Table A.3(2) Table A.3(2) Operation Code Map Table A.3 shows the operation code map. Operation Code Map (1) LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) BGT JSR MOV EEPMOV Table A.3(3) BLE BST XOR AND OR BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND Table A.3(2) Table A.3(2) Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 715 of 900 REJ09B0291-0400 Table A.3 Instruction code AH AL BH BL 1st byte 2nd byte BH AH AL 01 MOV STM STC SLEEP ADD INC INC ADDS MOV SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU ROTL ROTR NEG NEG SUB DEC DEC SUBS CMP BRN BHI BCS MOV CMP OR OR CMP SUB SUB Table * A.3(4) MOVFPE XOR XOR AND AND BCC Table A.3(4) ADD ADD BLS BNE BEQ BVC MOV BVS BPL MOV BMI BGE SHAR SHAL SHLR ROTXL ROTXR NOT DEC SUBS DAS BRA MOV MOV MOV NOT ROTXR ROTXL SHLR SHLL SHAL SHAR ROTL ROTR INC ADDS DAA 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 6A 79 7A Note: * Cannot be used in the H8S/2345 Group. LDM LDC MAC* CLRMAC * 0 5 7 8 B 1 2 6 9 C Table A.3(3) A 3 4 D Table A.3(3) E TAS Appendix A Instruction Set F Table A.3(3) Operation Code Map (2) INC INC Rev. 4.00 Feb 15, 2006 page 716 of 900 REJ09B0291-0400 SHAL ROTL EXTS EXTS DEC DEC BLT MOVTPE* BGT BLE SHAR ROTR Table A.3 Instruction code AH AL BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL AH AL BH BL CH 0 MULXS DIVXS OR BTST BTST BSET BSET BTST BTST BSET BSET BNOT BCLR BNOT BCLR BNOT BCLR BNOT BCLR XOR AND DIVXS MULXS 1 2 3 4 5 6 7 8 9 A B C D E F Operation Code Map (3) 01C05 01D05 01F06 7Cr06*1 7Cr07*1 7Dr06*1 7Dr07*1 7Eaa6*2 7Eaa7 7Faa6*2 7Faa7*2 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. *2 BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 717 of 900 REJ09B0291-0400 Table A.3 Instruction code AH AL BH BL CH CL DH DL EH EL FH FL 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. EL AHALBHBLCHCLDHDLEH Appendix A Instruction Set 0 4 5 6 7 8 9 A B BTST 1 2 3 C D E F 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BSET 6A18aaaa7* BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Operation Code Map (4) Rev. 4.00 Feb 15, 2006 page 718 of 900 REJ09B0291-0400 Instruction code AH AL BH BL CH CL DH DL EH EL 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte FH FL 7th byte GH GL 8th byte HH HL GL AHALBHBL ... FHFLGH Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. 0 1 4 5 BTST 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET 6A38aaaaaaaa7* Note: * aa is the absolute address specification. BNOT BCLR 2 3 6 7 8 9 A B C D E F 6A30aaaaaaaa6* BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 Rev. 4.00 Feb 15, 2006 page 719 of 900 REJ09B0291-0400 Appendix A Instruction Set Table A.4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 2-State 3-State Access Access 4 6 + 2m 16-Bit Bus 2-State 3-State Access Access 2 3+m Cycle Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM SN On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 Branch address read SJ 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev. 4.00 Feb 15, 2006 page 720 of 900 REJ09B0291-0400 Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 J K L ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 Rev. 4.00 Feb 15, 2006 page 721 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction Bcc Mnemonic BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 722 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BIAND Mnemonic BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 723 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BNOT Mnemonic BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 J K L Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 724 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N Cannot be used in the H8S/2345 Group 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 11 19 11 19 Rev. 4.00 Feb 15, 2006 page 725 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 1 1 1 J K L 2n+2*2 2n+2*2 Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 726 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction LDM Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd Cannot be used in the H8S/2345 Group 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 2 2 2 J K 4 6 8 L Word Data Access M Internal Operation N 1 1 1 Cannot be used in the H8S/2345 Group Rev. 4.00 Feb 15, 2006 page 727 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction MOV Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd 2 2 1 1 1 1 1 1 1 1 1 11 19 11 19 I 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Can not be used in the H8S/2345 Group 2 2 2 2 2 2 2 2 2 2 2 2 1 1 J K L Word Data Access M 1 1 1 1 1 1 Internal Operation N Rev. 4.00 Feb 15, 2006 page 728 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction OR Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd I 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 J K L Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 729 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction ROTXR Mnemonic ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3*1 2 1 1 J K L Word Data Access M Internal Operation N Rev. 4.00 Feb 15, 2006 page 730 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 J K L Word Data Access M Internal Operation N STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA TAS @ERd TRAPA #x:2 Advanced 1 2 1 3 1 1 1 1 2 2 2 2/3*1 2 2 2 3 3 4 4 2 2 2 Cannot be used in the H8S/2345 Group 2 Rev. 4.00 Feb 15, 2006 page 731 of 900 REJ09B0291-0400 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 1 3 2 1 2 J K L Word Data Access M Internal Operation N Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. Rev. 4.00 Feb 15, 2006 page 732 of 900 REJ09B0291-0400 Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev. 4.00 Feb 15, 2006 page 733 of 900 REJ09B0291-0400 Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.1 Address Bus, RD, HWR, and LWR Timing RD HWR LWR (8-Bit Bus, Three-State Access, No Wait States) Rev. 4.00 Feb 15, 2006 page 734 of 900 REJ09B0291-0400 2 3 4 5 6 7 8 9 Table A.6 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Instruction Execution Cycles Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 735 of 900 REJ09B0291-0400 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:B:M EA R:B:M EA R:W 3rd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 736 of 900 REJ09B0291-0400 1 R:W NEXT R:W 2nd 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 4 5 6 7 8 9 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 737 of 900 REJ09B0291-0400 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 738 of 900 REJ09B0291-0400 Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 4 R:W:M NEXT R:B EA R:W:M NEXT 5 6 7 8 9 R:W:M NEXT R:B EA R:W:M NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC R:W:M NEXT R:B EA R:W:M NEXT 1 2 3 R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th Cannot be used in the H8S/2345 Group R:W NEXT R:W 3rd R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 ← Repeated n times*2 → R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 739 of 900 REJ09B0291-0400 R:W NEXT R:W NEXT Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W EA Internal operation, R:W EA 1 state JMP @@aa:8 R:W NEXT JSR @ERn R:W NEXT JSR @aa:24 R:W 2nd JSR @@aa:8 R:W:M aa:8 R:W NEXT R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA Internal operation, R:W EA 1 state W:W:M stack (H) W:W stack (L) R:W EA W:W:M stack (H) W:W stack (L) R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 740 of 900 REJ09B0291-0400 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W NEXT R:W NEXT LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA R:W EA Instruction LDM.L @SP+,(ERn–ERn+2) LDM.L @SP+,(ERn–ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL 1 R:W 2nd 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W 2nd R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Cannot be used in the H8S/2345 Group 2 R:W NEXT 6 7 8 9 MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:B EA R:W NEXT R:B EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W EA Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 741 of 900 REJ09B0291-0400 MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA 4 R:W NEXT W:W EA Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd 1 R:W 2nd R:W 2nd R:W NEXT 3 W:W EA R:E 4th W:W EA 5 6 7 8 9 Appendix A Instruction Set 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W EA+2 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd Rev. 4.00 Feb 15, 2006 page 742 of 900 REJ09B0291-0400 R:W EA+2 MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA W:W:M EA R:W NEXT R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA W:W:M EA W:W EA+2 R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the H8S/2345 Group W:W EA+2 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd 2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd W:W EA+2 R:W NEXT R:W 2nd R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state R:W EA+2 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT 3 4 5 6 7 8 9 Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 743 of 900 REJ09B0291-0400 2 R:W stack (EXR) R:W stack (H) R:W:M stack (H) R:W stack (L) R:W stack (L) Instruction ROTXR.L #2,ERd RTE RTS R:W NEXT Internal operation, R:W*4 1 state Internal operation, R:W*4 1 state Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 744 of 900 REJ09B0291-0400 1 R:W NEXT R:W NEXT 3 4 5 6 7 8 9 SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd 5 R:W NEXT R:W NEXT W:W EA W:W EA Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn–ERn+1),@–SP STM.L(ERn–ERn+2),@–SP STM.L(ERn–ERn+3),@–SP W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W EA 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the H8S/2345 Group 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 745 of 900 REJ09B0291-0400 XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd 1 R:W 2nd R:W NEXT R:W 2nd R:W:M VEC R:W NEXT R:W VEC+2 W:W stack (EXR) R:W:M VEC R:W VEC+2 R:W*6 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Internal operation, R:W*7 1 state Appendix A Instruction Set Rev. 4.00 Feb 15, 2006 page 746 of 900 REJ09B0291-0400 Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Reset exception handling Interrupt exception handling 2 R:W NEXT 3 4 5 6 7 8 9 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn — The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev. 4.00 Feb 15, 2006 page 747 of 900 REJ09B0291-0400 Appendix A Instruction Set Table A.7 Instruction ADD Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS ADDX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. ———— ————— ————— ———— ———— ———— ————— ———— ———— ————— ———— ————— ————— ————— —— —— C = C' · Dn C = C' · Dn C = Dn C = C' + Dn C = C' · Dn + C' · Dn C = Dn C = C' + Dn Z = Dn C = C' · Dn + C' · Dn ———— Rev. 4.00 Feb 15, 2006 page 748 of 900 REJ09B0291-0400 Appendix A Instruction Set Instruction CLRMAC CMP H N Z V C Definition Cannot be used in the H8S/2345 Group H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS DIVXU EEPMOV EXTS EXTU INC — — —— —— N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 N = Sm Z = Sm · Sm–1 · ...... · S0 ————— — —0 — 0 0 — — — N = Rm Z = Rm · Rm–1 · ...... · R0 Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm JMP JSR LDC LDM ————— ————— ————— Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev. 4.00 Feb 15, 2006 page 749 of 900 REJ09B0291-0400 Appendix A Instruction Set Instruction LDMAC MAC MOV MOVFPE MOVTPE MULXS MULXU NEG — —— N = R2m Z = R2m · R2m–1 · ...... · R0 ————— H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL — — — 0 0 0 — — ————— — — 0 0 — — N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Can not be used in the H8S/2345 Group H N Z V C Definition Cannnot be used in the H8S/2345 Group Rev. 4.00 Feb 15, 2006 page 750 of 900 REJ09B0291-0400 Appendix A Instruction Set Instruction ROTXL H — N Z V 0 C Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ————— — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift) C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR —0 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ————— ————— ————— Cannot be used in the H8S/2345 Group Stores the corresponding bits of the result. Rev. 4.00 Feb 15, 2006 page 751 of 900 REJ09B0291-0400 Appendix A Instruction Set Instruction SUB H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS SUBX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS TRAPA XOR XORC — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 ————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev. 4.00 Feb 15, 2006 page 752 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Appendix B Internal I/O Register B.1 Addresses Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Data Bus Width 1 16/32* bit Address Register (low) Name Bit 7 H'F800 to H'FBFF MRA SAR SM1 MRB DAR CHNE DISEL — — — — — — CRA CRB H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 CCLR2 — IOB3 IOD3 TTGE — CCLR1 — IOB2 IOD2 — — CCLR0 BFB IOB1 IOD1 — — CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16 bit TGR3A TGR3B TGR3C TGR3D Rev. 4.00 Feb 15, 2006 page 753 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF P1DDR P2DDR P3DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR — — — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR — — PA3DDR PA2DDR PA1DDR PA0DDR 8 bit TGR5B TGR5A TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 16 bit TGR4B TGR4A TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 — — IOB3 TTGE TCFD Module Name TPU4 Data Bus Width 16 bit Bit 6 CCLR1 — IOB2 — — Bit 5 CCLR0 — IOB1 TCIEU TCFU Bit 4 CKEG1 — IOB0 TCIEV TCFV Bit 3 CKEG0 MD3 IOA3 — — Bit 2 TPSC2 MD2 IOA2 — — Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Rev. 4.00 Feb 15, 2006 page 754 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FEDB H'FF2C H'FF2D H'FF2E H'FF2F H'FF30 to H'FF34 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF3C H'FF3D H'FF42 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ABWCR ASTCR WCRH WCRL BCRH BCRL RAMER ISCRH ISCRL IER ISR DTCER — — — — — — — — — — — ABW7 AST7 W71 W31 ICIS1 BRLE — Module Name Interrupt controller Data Bus Width 8 bit Bit 6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 — — Bit 5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 BRSTR M EAE — Bit 4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 Bit 3 — — — — — — — — — — — ABW3 AST3 W51 W11 Bit 2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 — ABW2 AST2 W50 W10 Bit 1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 — ABW1 AST1 W41 W01 — — RAM1 Bit 0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 — ABW0 AST0 W40 W00 — WAITE RAM0 Bus controller 8 bit BRSTS1 BRSTS0 — — — — — — RAMS IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA 8 bit controller IRQ7E IRQ7F DTCE7 IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC 8 bit DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 SBYCR SYSCR SCKCR MDCR SSBY — PSTOP — STS2 — — — STS1 INTM1 — — STS0 INTM0 — — OPE NMIEG — — — — SCK2 MDS2 — — SCK1 MDS1 — RAME SCK0 MDS0 MSTP8 MSTP0 — Power-down mode MCU Clock pulse generator MCU Power-down mode MCU 8 bit 8 bit 8 bit 8 bit 8 bit MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6 — MSTP5 — MSTP4 — MSTP3 FLSHE MSTP2 — MSTP1 — SYSCR2 — 8 bit Rev. 4.00 Feb 15, 2006 page 755 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FF44 H'FF45 H'FF50 H'FF51 H'FF52 H'FF53 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 Reserved — Reserved — PORT1 PORT2 PORT3 PORT4 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR P17 P27 — P47 — PB7 PC7 PD7 PE7 PF7 — P17DR P27DR — — PB7DR PC7DR PD7DR PE7DR PF7DR — — Module Name Reserved Data Bus Width — Bit 6 — — P16 P26 — P46 — PB6 PC6 PD6 PE6 PF6 — P16DR P26DR — — PB6DR PC6DR PD6DR PE6DR PF6DR — — Bit 5 — — P15 P25 P35 P45 — PB5 PC5 PD5 PE5 PF5 — P15DR P25DR P35DR — PB5DR PC5DR PD5DR PE5DR PF5DR — — Bit 4 — — P14 P24 P34 P44 — PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR — PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR — Bit 3 — — P13 P23 P33 P43 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR Bit 2 — — P12 P22 P32 P42 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR Bit 1 — — P11 P21 P31 P41 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR Bit 0 — — P10 P20 P30 P40 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR Port 8 bit PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR — — — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR — — PA3ODR PA2ODR PA1ODR PA0ODR Rev. 4.00 Feb 15, 2006 page 756 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF90 H'FF91 H'FF92 H'FF93 H"FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA4 H'FFA5 H'FFA6 SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 — — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 — AD7 — AD7 — AD7 — AD7 — ADST — — AD6 — AD6 — AD6 — AD6 — SCAN — SDIR AD5 — AD5 — AD5 — AD5 — CKS — SINV AD4 — AD4 — AD4 — AD4 — — — — AD3 — AD3 — AD3 — AD3 — CH1 — SMIF AD2 — AD2 — AD2 — AD2 — CH0 — D/A converter 8 bit A/D converter 8 bit TDRE RDRF ORER FER/ ERS*3 PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 — C/A/ GM*2 — CHR — PE — O/E SDIR STOP SINV MP — CKS1 SMIF CKS0 SCI1, Smart card interface 1 8 bit TDRE RDRF ORER FER/ ERS*3 PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A/ 2 GM* Module Name SCI0, Smart card interface 0 Data Bus Width 8 bit Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR DADR0 DADR1 DACR DAOE1 ADF TRGS1 DAOE0 DAE — — — — — Rev. 4.00 Feb 15, 2006 page 757 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBC (read) H'FFBD (read) H'FFBF (read) H'FFC0 H'FFC1 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB TGR0B TGR0A TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR TCNT RSTCSR WOVF TSTR TSYR — — RSTE — — SWE — — EB6 CCLR1 — IOB2 IOD2 — — RSTS CST5 SYNC5 — — — EB5 CCLR0 BFB IOB1 IOD1 — — — CST4 SYNC4 — — — EB4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV — CST3 SYNC3 EV — — EB3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD — CST2 SYNC2 PV — — EB2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC — CST1 SYNC1 E ESU EB9 EB1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB — CST0 SYNC0 P PSU EB8 EB0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16 bit FLASH 8 bit TPU 16 bit OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT 16 bit CMIEB CMIEB CMFB CMFB Module Name 8-bit timer channel 0, 1 Data Bus Width 16 bit Bit 6 CMIEA CMIEA CMFA CMFA Bit 5 OVIE OVIE OVF OVF Bit 4 CCLR1 CCLR1 ADTE — Bit 3 CCLR0 CCLR0 OS3 OS3 Bit 2 CKS2 CKS2 OS2 OS2 Bit 1 CKS1 CKS1 OS1 OS1 Bit 0 CKS0 CKS0 OS0 OS0 FLMCR1 FWE FLMCR2 FLER EBR1 EBR2 TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 — EB7 CCLR2 — IOB3 IOD3 TTGE — Rev. 4.00 Feb 15, 2006 page 758 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Address Register (low) Name Bit 7 H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 16 bit TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TGR0D TGR0C Module Name TPU1 Data Bus Width 16 bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. Functions as C/A for SCI use, and as GM for smart card interface use. 3. Functions as FER for SCI use, and as ERS for smart card interface use. Rev. 4.00 Feb 15, 2006 page 759 of 900 REJ09B0291-0400 Appendix B Internal I/O Register B.2 Functions H'F800—H'FBFF 5 DM1 — 4 DM0 — 3 MD1 — 2 MD0 — 1 DTS — 0 Sz — MRA—DTC Mode Register A Bit : 7 SM1 Initial value : Read/Write : — 6 SM0 — DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 — 0 1 Source Address Mode 0 1 — 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode — Destination side is repeat area or block area Source side is repeat area or block area Rev. 4.00 Feb 15, 2006 page 760 of 900 REJ09B0291-0400 Appendix B Internal I/O Register MRB—DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : — 6 DISEL — 5 — — 4 — — H'F800—H'FBFF 3 — — 2 — — 1 — — 0 DTC — — Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reserved Only 0 should be written to these bits DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer SAR—DTC Source Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies transfer data source address DAR—DTC Destination Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies transfer data destination address Rev. 4.00 Feb 15, 2006 page 761 of 900 REJ09B0291-0400 Appendix B Internal I/O Register CRA—DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'F800—H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'F800—H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Specifies the number of DTC block data transfers Rev. 4.00 Feb 15, 2006 page 762 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR3—Timer Control Register 3 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 H'FE80 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU3 CKEG0 0 R/W Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096 Rev. 4.00 Feb 15, 2006 page 763 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR3—Timer Mode Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W H'FE81 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU3 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev. 4.00 Feb 15, 2006 page 764 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR3H—Timer I/O Control Register 3H Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FE82 1 IOA1 0 R/W 0 IOA0 0 R/W TPU3 Initial value : TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don’t care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 *: Don’t care Note: 1. If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur. TGR3B Output disabled is output compare Initial output is register 0 output TGR3A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 4.00 Feb 15, 2006 page 765 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR3L—Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 H'FE83 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 IOC2 0 R/W TRG3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C is input 1 capture * register * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * *: Don’t care Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is input capture register Capture input source is TIOCD3 pin Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 TGR3D Output disabled is output Initial output is 0 0 output at compare match compare register output 1 output at compare match Toggle output at compare match *: Don’t care Notes: When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 4.00 Feb 15, 2006 page 766 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER3—Timer Interrupt Enable Register 3 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 H'FE84 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU3 TGIED 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 767 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR3—Timer Status Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* H'FE85 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT=TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 768 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT3—Timer Counter 3 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FE86 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU3 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE88 H'FE8A H'FE8C H'FE8E 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU3 TPU3 TPU3 TPU3 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 769 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR4—Timer Control Register 4 H'FE90 TPU4 Bit : 7 — 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Initial value : Read/Write : Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Counter Clear 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev. 4.00 Feb 15, 2006 page 770 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR4—Timer Mode Register 4 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FE91 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU4 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 4.00 Feb 15, 2006 page 771 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR4—Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FE92 1 IOA1 0 R/W 0 IOA0 0 R/W TPU4 IOA2 0 R/W TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture *: Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture *: Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 Rev. 4.00 Feb 15, 2006 page 772 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER4—Timer Interrupt Enable Register 4 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FE94 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TPU4 TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 773 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR4—Timer Status Register 4 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FE95 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 774 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT4—Timer Counter 4 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FE96 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU4 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE98 H'FE9A 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU4 TPU4 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 775 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR5—Timer Control Register 5 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W H'FEA0 2 TPSC2 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 TPU5 1 TPSC1 0 R/W 0 TPSC0 0 R/W External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 5 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev. 4.00 Feb 15, 2006 page 776 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR5—Timer Mode Register 5 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FEA1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU5 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 4.00 Feb 15, 2006 page 777 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR5—Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FEA2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU5 IOA2 0 R/W TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Capture input source is TIOCA5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Capture input source is TIOCB5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care TGR5B Output disabled is output compare Initial output is 0 register output 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 4.00 Feb 15, 2006 page 778 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER5—Timer Interrupt Enable Register 5 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FEA4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TPU5 TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 779 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR5—Timer Status Register 5 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FEA5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU5 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 780 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT5—Timer Counter 5 H'FEA6 TPU5 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FEA8 H'FEAA 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU5 TPU5 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1DDR—Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB0 3 0 W 2 0 W 1 0 W Port 1 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : Specify input or output for individual port 1 pins Rev. 4.00 Feb 15, 2006 page 781 of 900 REJ09B0291-0400 Appendix B Internal I/O Register P2DDR—Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB1 3 0 W 2 0 W 1 0 W Port 2 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register Bit : 7 — Initial value : Read/Write : — 6 — — 5 0 W 4 0 W H'FEB2 3 0 W 2 0 W 1 0 W Port 3 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined Specify input or output for individual port 3 pins PADDR—Port A Data Direction Register Bit Initial value Read/Write : : : 7 — — 6 — — 5 — — 4 — — H'FEB9 3 0 W 2 0 W 1 0 W Port A 0 0 W PA3DDR PA2DDR PA1DDR PA0DDR Undefined Undefined Undefined Undefined Specify input or output for individual port A pins Rev. 4.00 Feb 15, 2006 page 782 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PBDDR—Port B Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBA 3 0 W 2 0 W 1 0 W Port B 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Specify input or output for individual port B pins PCDDR—Port C Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBB 3 0 W 2 0 W 1 0 W Port C 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Specify input or output for individual port C pins PDDDR—Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBC 3 0 W 2 0 W 1 0 W Port D 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specify input or output for individual port D pins Rev. 4.00 Feb 15, 2006 page 783 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PEDDR—Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBD 3 0 W 2 0 W 1 0 W Port E 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specify input or output for individual port E pins PFDDR—Port F Data Direction Register Bit : 7 6 5 4 H'FEBE 3 2 1 Port F 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4 to 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for individual port F pins Rev. 4.00 Feb 15, 2006 page 784 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PGDDR—Port G Data Direction Register Bit Modes 1, 4, 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : — — — 1 W 0 W : 7 — 6 — 5 — 4 H'FEBF 3 2 1 Port G 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 2, 3, 6, 7 : Undefined Undefined Undefined : — — — Specify input or output for individual port G pins Rev. 4.00 Feb 15, 2006 page 785 of 900 REJ09B0291-0400 Appendix B Internal I/O Register IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Interrupt Priority Register I IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K Bit : 7 — Initial value : Read/Write : 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE 3 — 0 — 2 IPR2 1 R/W Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 WDT —* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 —* SCI channel 1 IRQ1 IRQ4 IRQ5 DTC —* A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 —* 2 to 0 Note: * Reserved bits. May be read or written, but the setting is ignored. Rev. 4.00 Feb 15, 2006 page 786 of 900 REJ09B0291-0400 Appendix B Internal I/O Register ABWCR—Bus Width Control Register Bit : 7 ABW7 Modes 1 to 3, 5 to 7 Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 Bus Controller 0 ABW0 1 R/W 0 R/W ABW4 ABW1 1 R/W 0 R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR—Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 1 Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0) Rev. 4.00 Feb 15, 2006 page 787 of 900 REJ09B0291-0400 Appendix B Internal I/O Register WCRH—Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 H'FED2 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bus Controller W51 1 R/W Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev. 4.00 Feb 15, 2006 page 788 of 900 REJ09B0291-0400 Appendix B Internal I/O Register WCRL—Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 H'FED3 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bus Controller W11 1 R/W Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev. 4.00 Feb 15, 2006 page 789 of 900 REJ09B0291-0400 Appendix B Internal I/O Register BCRH—Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 — 0 R/W 1 — 0 Bus Controller 0 — 0 R/W BRSTRM BRSTS1 BRSTS0 R/W Reserved Only 0 should be written to these bits Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Rev. 4.00 Feb 15, 2006 page 790 of 900 REJ09B0291-0400 Appendix B Internal I/O Register BCRL—Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 EAE 1 R/W 4 — 1 R/W H'FED5 3 — 1 R/W 2 — 1 R/W 1 Bus Controller 0 WAITE 0 R/W — 0 R/W Reserved Only 0 should be written to this bit WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Wait input by WAIT pin enabled Reserved Only 1 should be written to these bits External Addresses H'010000 to H'01FFFF Enable 0 1 On-chip ROM (H8S/2345) or reserved area* (H8S/2343) External addresses (in external expansion mode) or reserved area (in single-chip mode) Note: * Do not access a reserved area. Reserved Only 0 should be written to this bit Bus Release Enable 0 1 External bus release is disabled External bus release is enabled Rev. 4.00 Feb 15, 2006 page 791 of 900 REJ09B0291-0400 Appendix B Internal I/O Register RAMER—RAM Emulation Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 — 0 — 4 — 0 — H'FEDB 3 — 0 — 2 RAMS 0 R/W 1 Bus Controller 0 RAM0 0 R/W RAM1 0 R/W RAM Select, Flash Memory Area Select RAMS RAM1 RAM0 0 1 * 0 1 *: Don’t care * 0 1 0 1 RAM Area H'FFEC00–H'FFEFFF H'000000–H'0003FF H'000400–H'0007FF H'000800–H'000BFF H'000C00–H'000FFF Rev. 4.00 Feb 15, 2006 page 792 of 900 REJ09B0291-0400 Appendix B Internal I/O Register ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FF2C H'FF2D Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n = 7 to 0) Rev. 4.00 Feb 15, 2006 page 793 of 900 REJ09B0291-0400 Appendix B Internal I/O Register IER—IRQ Enable Register Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 H'FF2E 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ4E 0 R/W IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) ISR—IRQ Status Register Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 H'FF2F 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ4F 0 R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 794 of 900 REJ09B0291-0400 Appendix B Internal I/O Register DTCERA to DTCERF—DTC Enable Registers Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W H'FF30 to H'FF34 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE0 0 R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 Correspondence between Interrupt Sources and DTCER Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE 7 IRQ0 — TGI2A — — 6 IRQ1 ADI TGI2B — — 5 IRQ2 TGI0A TGI3A TGI5A — 4 IRQ3 TGI0B TGI3B TGI5B — 3 IRQ4 TGI0C TGI3C CMIA0 RXI0 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 0 IRQ7 TGI1B TGI4B CMIB1 TXI1 Rev. 4.00 Feb 15, 2006 page 795 of 900 REJ09B0291-0400 Appendix B Internal I/O Register DTVECR—DTC Vector Register Bit : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W H'FF37 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended • During data transfer due to software activation 1 Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. Rev. 4.00 Feb 15, 2006 page 796 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SBYCR—Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FF38 3 OPE 1 R/W 2 — 0 — Power-Down State 1 — 0 — 0 — 0 R/W Reserved Only 0 should be written to this bit Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state 1 Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states Rev. 4.00 Feb 15, 2006 page 797 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SYSCR—System Control Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 INTM1 0 R/W 4 H'FF39 3 NMIEG 0 R/W 2 — 0 R/W 1 — 0 R/W 0 MCU INTM0 0 R/W RAME 1 R/W Reserved Only 0 should be written to this bit RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled NMI Input Edge Select 0 1 Falling edge Rising edge Interrupt Control Mode Selection 0 0 1 1 0 1 Reserved Only 0 should be written to this bit Interrupt control mode 0 — Interrupt control mode 2 — Rev. 4.00 Feb 15, 2006 page 798 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SCKCR—System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 — 0 — 4 — 0 — H'FF3A 3 — 0 — 2 SCK2 0 R/W Clock Pulse Generator 1 SCK1 0 R/W 0 SCK0 0 R/W Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 φ Clock Output Control PSTOP 0 1 Normal Operation φ output Fixed high Sleep Mode φ output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance — Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — Rev. 4.00 Feb 15, 2006 page 799 of 900 REJ09B0291-0400 Appendix B Internal I/O Register MDCR—Mode Control Register Bit : 7 — Initial value : Read/Write : 1 — 6 — 0 — 5 — 0 — 4 — 0 — H'FF3B 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MCU MDS0 —* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH—Module Stop Control Register H MSTPCRL—Module Stop Control Register L MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 H'FF3C H'FF3D Power-Down State Power-Down State MSTPCRL 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set SYSCR2 — System Control Register 2 Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 — 0 — 4 — 0 — H'FF42 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 MCU — 0 — Flash Memory Control Register Enable 0 1 Flash memory control register is not selected Flash memory control register is selected Rev. 4.00 Feb 15, 2006 page 800 of 900 REJ09B0291-0400 Appendix B Internal I/O Register Reserved Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 — 0 R/W 4 — 0 — H'FF44 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Reserved Only 0 should be written to these bits Reserved Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 — 0 R/W 4 — 0 R/W H'FF45 3 — 1 R/W 2 — 1 R/W 1 — 1 R/W 0 — 1 R/W Reserved PORT1—Port 1 Register Bit : 7 P17 Initial value : Read/Write : —* R 6 P16 —* R 5 P15 —* R 4 P14 —* R H'FF50 3 P13 —* R 2 P12 —* R 1 P11 —* R Port 1 0 P10 —* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. Rev. 4.00 Feb 15, 2006 page 801 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PORT2—Port 2 Register Bit : 7 P27 Initial value : Read/Write : —* R 6 P26 —* R 5 P25 —* R 4 P24 —* R H'FF51 3 P23 —* R 2 P22 —* R 1 P21 —* R Port 2 0 P20 —* R State of port 2 pins Note: * Determined by the state of pins P27 to P20. PORT3—Port 3 Register Bit : 7 — Read/Write : — 6 — — 5 P35 —* R 4 P34 —* R H'FF52 3 P33 —* R 2 P32 —* R 1 P31 —* R 0 Port 3 P30 —* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. PORT4—Port 4 Register Bit : 7 P47 Initial value : Read/Write : —* R 6 P46 —* R 5 P45 —* R 4 P44 —* R H'FF53 3 P43 —* R 2 P42 —* R 1 P41 —* R Port 4 0 P40 —* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. Rev. 4.00 Feb 15, 2006 page 802 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PORTA—Port A Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 — — H'FF59 3 PA3 —* R 2 PA2 —* R 1 PA1 —* R Port A 0 PA0 —* R Initial value : Undefined Undefined Undefined Undefined State of port A pins Note: * Determined by the state of pins PA3 to PA0. PORTB—Port B Register Bit : 7 PB7 Initial value : Read/Write : —* R 6 PB6 —* R 5 PB5 —* R 4 PB4 —* R H'FF5A 3 PB3 —* R 2 PB2 —* R 1 PB1 —* R Port B 0 PB0 —* R State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC—Port C Register Bit : 7 PC7 Initial value : Read/Write : —* R 6 PC6 —* R 5 PC5 —* R 4 PC4 —* R H'FF5B 3 PC3 —* R 2 PC2 —* R 1 PC1 —* R Port C 0 PC0 —* R State of port C pins Note: * Determined by the state of pins PC7 to PC0. Rev. 4.00 Feb 15, 2006 page 803 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PORTD—Port D Register Bit : 7 PD7 Initial value : Read/Write : —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R H'FF5C 3 PD3 —* R 2 PD2 —* R 1 PD1 —* R Port D 0 PD0 —* R State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE—Port E Register Bit : 7 PE7 Initial value : Read/Write : —* R 6 PE6 —* R 5 PE5 —* R 4 PE4 —* R H'FF5D 3 PE3 —* R 2 PE2 —* R 1 PE1 —* R Port E 0 PE0 —* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF—Port F Register Bit : 7 PF7 Initial value : Read/Write : —* R 6 PF6 —* R 5 PF5 —* R 4 PF4 —* R H'FF5E 3 PF3 —* R 2 PF2 —* R 1 PF1 —* R Port F 0 PF0 —* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. Rev. 4.00 Feb 15, 2006 page 804 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PORTG—Port G Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 PG4 —* R H'FF5F 3 PG3 —* R 2 PG2 —* R 1 PG1 —* R Port G 0 PG0 —* R Initial value : Undefined Undefined Undefined State of port G pins Note: * Determined by the state of pins PG4 to PG0. P1DR—Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 H'FF60 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Port 1 0 P10DR 0 R/W P14DR 0 R/W Stores output data for port 1 pins (P17 to P10) P2DR—Port 2 Data Register Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 H'FF61 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W Port 2 0 P20DR 0 R/W P24DR 0 R/W Stores output data for port 2 pins (P27 to P20) Rev. 4.00 Feb 15, 2006 page 805 of 900 REJ09B0291-0400 Appendix B Internal I/O Register P3DR—Port 3 Data Register Bit : 7 — Read/Write : — 6 — — 5 P35DR 0 R/W 4 H'FF62 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W Port 3 0 P30DR 0 R/W P34DR 0 R/W Initial value : Undefined Undefined Stores output data for port 3 pins (P35 to P30) PADR—Port A Data Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 — — H'FF69 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W Port A 0 PA0DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port A pins (PA3 to PA0) PBDR—Port B Data Register Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 H'FF6A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W Port B 0 PB0DR 0 R/W PB4DR 0 R/W Stores output data for port B pins (PB7 to PB0) Rev. 4.00 Feb 15, 2006 page 806 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PCDR—Port C Data Register Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 H'FF6B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W Port C 0 PC0DR 0 R/W PC4DR 0 R/W Stores output data for port C pins (PC7 to PC0) PDDR—Port D Data Register Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 H'FF6C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W Port D 0 PD0DR 0 R/W PD4DR 0 R/W Stores output data for port D pins (PD7 to PD0) PEDR—Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 H'FF6D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W Port E 0 PE0DR 0 R/W PE4DR 0 R/W Stores output data for port E pins (PE7 to PE0) Rev. 4.00 Feb 15, 2006 page 807 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PFDR—Port F Data Register Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 H'FF6E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W PF4DR 0 R/W Stores output data for port F pins (PF7 to PF0) PGDR—Port G Data Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 0 R/W H'FF6F 3 0 R/W 2 0 R/W 1 0 R/W Port G 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Stores output data for port G pins (PG4 to PG0) PAPCR—Port A MOS Pull-Up Control Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 — — H'FF70 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port A PA3PCR PA2PCR PA1PCR PA0PCR R/W Initial value : Undefined Undefined Undefined Undefined Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis Rev. 4.00 Feb 15, 2006 page 808 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PBPCR—Port B MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF71 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port B PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis PCPCR—Port C MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF72 3 0 R/W 2 0 R/W 1 0 R/W Port C 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR—Port D MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF73 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port D PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Rev. 4.00 Feb 15, 2006 page 809 of 900 REJ09B0291-0400 Appendix B Internal I/O Register PEPCR—Port E MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port E PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis P3ODR—Port 3 Open Drain Control Register Bit : 7 — Read/Write : — 6 — — 5 0 R/W 4 0 R/W H'FF76 3 0 R/W 2 0 R/W 1 0 R/W Port 3 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR—Port A Open Drain Control Register Bit : 7 — Initial value : Read/Write : — 6 — — 5 — — 4 — — H'FF77 3 0 R/W 2 0 R/W 1 0 R/W Port A 0 0 R/W PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined Undefined Undefined Controls the PMOS on/off status for each port A pin (PA3 to PA0) Rev. 4.00 Feb 15, 2006 page 810 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SMR0—Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI0 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev. 4.00 Feb 15, 2006 page 811 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SMR0—Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 0 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Time for transfer of one bit Rev. 4.00 Feb 15, 2006 page 812 of 900 REJ09B0291-0400 Appendix B Internal I/O Register BRR0—Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details. Rev. 4.00 Feb 15, 2006 page 813 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SCR0—Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI0 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev. 4.00 Feb 15, 2006 page 814 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SCR0—Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 0 SCR setting CKE0 SMIF C/A ,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev. 4.00 Feb 15, 2006 page 815 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TDR0—Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev. 4.00 Feb 15, 2006 page 816 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SSR0—Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 817 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SSR0—Serial Status Register 0 Bit : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 0 Initial value : Read/Write : Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is transmitted when GM = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is transmitted when GM = 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR 1 Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 818 of 900 REJ09B0291-0400 Appendix B Internal I/O Register RDR0—Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R SCI0, Smart Card Interface 0 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W H'FF7E 2 SINV 0 R/W SCI0, Smart Card Interface 0 1 — 1 — 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 4.00 Feb 15, 2006 page 819 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SMR1—Serial Mode Register 1 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI1 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev. 4.00 Feb 15, 2006 page 820 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SMR1—Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 1 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Time for transfer of one bit Rev. 4.00 Feb 15, 2006 page 821 of 900 REJ09B0291-0400 Appendix B Internal I/O Register BRR1—Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details. Rev. 4.00 Feb 15, 2006 page 822 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SCR1—Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI1 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev. 4.00 Feb 15, 2006 page 823 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SCR1—Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 1 SCR setting CKE0 SMIF C/A ,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev. 4.00 Feb 15, 2006 page 824 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TDR1—Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev. 4.00 Feb 15, 2006 page 825 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 1 Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 826 of 900 REJ09B0291-0400 Appendix B Internal I/O Register SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 1 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is transmitted when GM = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is transmitted when GM = 1 1 Note: etu: Elementary Time Unit (Time for transfer of one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 827 of 900 REJ09B0291-0400 Appendix B Internal I/O Register RDR1—Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R SCI1, Smart Card Interface 1 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 H'FF86 2 SINV 0 R/W SCI1, Smart Card Interface 1 1 — 1 — 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 4.00 Feb 15, 2006 page 828 of 900 REJ09B0291-0400 Appendix B Internal I/O Register ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : Read/Write : Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 4.00 Feb 15, 2006 page 829 of 900 REJ09B0291-0400 Appendix B Internal I/O Register ADCSR—A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CKS 0 R/W Channel Select Group select CH2 0 Channel select CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 A/D Converter 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Single Mode Scan Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Group Select 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends • Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode Conversion time= 266 states (max.) Conversion time= 134 states (max.) A/D Interrupt Enable 0 A/D End Flag 0 1 A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled [Clearing conditions] • When 0 is written to the ADF flag after reading ADF = 1 • When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When one round of conversion has been performed on all specified channels 1 Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 830 of 900 REJ09B0291-0400 Appendix B Internal I/O Register ADCR—A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — H'FF99 3 — 1 R/W 2 — 1 — 1 — 1 — 0 — 1 — A/D Reserved bit. Write as 1. Timer Trigger Select TRGS1 TRGS0 0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled DADR0—D/A Data Register 0 DADR1—D/A Data Register 1 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA4 H'FFA5 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W D/A D/A Initial value : Read/Write : Stores data for D/A conversion Rev. 4.00 Feb 15, 2006 page 831 of 900 REJ09B0291-0400 Appendix B Internal I/O Register DACR—D/A Control Register Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — H'FFA6 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — D/A D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAOE1 DAOE0 0 0 1 DAE * 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled *: Don’t care Rev. 4.00 Feb 15, 2006 page 832 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 H'FFB0 H'FFB1 1 CKS1 0 R/W 0 CKS0 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 CKS2 0 R/W Initial value : Read/Write : Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of φ/8 Internal clock: counted at falling edge of φ/64 Internal clock: counted at falling edge of φ/8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges 1 1 0 1 Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled Rev. 4.00 Feb 15, 2006 page 833 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : 7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4 H'FFB2 H'FFB3 3 OS3 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 2 OS2 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W ADTE 0 R/W 4 — 1 — Initial value : Read/Write : TCSR1 Bit : Initial value : Read/Write : Output Select 0 0 1 1 0 1 No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) Compare Match Flag A 0 [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORA 1 Compare Match Flag B 0 [Clearing conditions] • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORB 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 4.00 Feb 15, 2006 page 834 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORB1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFB8 H'FFB9 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCNT1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 835 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCSR—Timer Control/Status Register Bit : 7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — H'FFBC (W) H'FFBC (R) 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT Initial value : 0 Read/Write : R/(W)* Clock Select CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow period* (when φ = 20 MHz) 819.2µs 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s φ/2 (initial value) 25.6µs φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Timer Enable 0 1 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows The method for writing to TCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 11.2.4, Notes on Register Access. Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 836 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT—Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFBC (W) H'FFBD (R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W WDT Initial value : Read/Write : The method for writing to TCNT is different from that for general registers to prevent inadvertent overwriting. For details, see section 11.2.4, Notes on Register Access. Rev. 4.00 Feb 15, 2006 page 837 of 900 REJ09B0291-0400 Appendix B Internal I/O Register RSTCSR—Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — H'FFBE (W) H'FFBF (R) 3 — 1 — 2 — 1 — 1 — 1 — 0 WDT — 1 — Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Power-on reset Manual reset Note: * The modules H8S/2345 Group are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 11.2.4, Notes on Register Access. Rev. 4.00 Feb 15, 2006 page 838 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSTR—Timer Start Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 CST5 0 R/W 4 CST4 0 R/W H'FFC0 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W TPU Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR—Timer Synchro Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 SYNC5 0 R/W 4 H'FFC1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 TPU SYNC4 0 R/W SYNC0 0 R/W Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev. 4.00 Feb 15, 2006 page 839 of 900 REJ09B0291-0400 Appendix B Internal I/O Register FLMCR1—Flash Memory Control Register 1 Bit : 7 FWE Initial value : Read/Write : —* R 6 SWE 0 R/W 5 — 0 — 4 — 0 — H'FFC8 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W FLASH 0 P 0 R/W Program 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Software Write Enable 0 1 Writes disabled Writes enabled [Setting condition] When FWE = 1 0 1 Program-Verify 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Erase-Verify Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Flash Write Enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev. 4.00 Feb 15, 2006 page 840 of 900 REJ09B0291-0400 Appendix B Internal I/O Register FLMCR2—Flash Memory Control Register 2 Bit : 7 FLER Initial value : Read/Write : 0 R 6 — 0 — 5 — 0 — 4 — 0 — H'FFC9 3 — 0 — 2 — 0 — 1 ESU 0 R/W FLASH 0 PSU 0 R/W Program Setup 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1, and SWE = 1 Erase Setup 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1, and SWE = 1 Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 17.10.3, Error Protection 1 Rev. 4.00 Feb 15, 2006 page 841 of 900 REJ09B0291-0400 Appendix B Internal I/O Register EBR1—Erase Block Register 1 EBR2—Erase Block Register 2 Bit EBR1 Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : : : 7 — 0 — 7 EB7 0 R/W 6 — 0 — 6 EB6 0 R/W 5 — 0 — 5 EB5 0 R/W 4 — 0 — 4 EB4 0 R/W H'FFCA H'FFCB 3 — 0 — 3 EB3 0 R/W 2 — 0 — 2 EB2 0 R/W 1 EB9 0 R/W 1 EB1 0 R/W FLASH FLASH 0 EB8 0 R/W 0 EB0 0 R/W Flash Memory Erase Blocks Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Rev. 4.00 Feb 15, 2006 page 842 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR0—Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFD0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU0 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 * Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Count at rising edge Count at falling edge Count at both edges *: Don’t care Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 4.00 Feb 15, 2006 page 843 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR0—Timer Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W H'FFD1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU0 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev. 4.00 Feb 15, 2006 page 844 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR0H—Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFD2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU0 TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don’t care TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B Capture input is input source is compare TIOCB0 pin register Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * * Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Rev. 4.00 Feb 15, 2006 page 845 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR0L—Timer I/O Control Register 0L Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W H'FFD3 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is input capture register *1 TGR0C Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don’t care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is input capture register *2 TGR0D Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 4.00 Feb 15, 2006 page 846 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER0—Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 H'FFD4 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU0 TGIED 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 847 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR0—Timer Status Register 0 Bit : 7 — 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* H'FFD5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 848 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT0—Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FFD6 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFD8 H'FFDA H'FFDC H'FFDE 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 849 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR1—Timer Control Register 1 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFE0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU1 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on φ/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 0 1 1 * Count at rising edge Count at falling edge Count at both edges *: Don’t care Note: This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1. Rev. 4.00 Feb 15, 2006 page 850 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR1—Timer Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FFE1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU1 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 1Phase counting mode 4 — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 4.00 Feb 15, 2006 page 851 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR1—Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFE2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is input capture register Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture *: Don’t care TGR1A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0B compare match/input compare match/ capture input capture *: Don’t care TGR1B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 4.00 Feb 15, 2006 page 852 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER1—Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FFE4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGI Interrupt Enable A TPU1 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 853 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR1—Timer Status Register 1 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FFE5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU1 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 854 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT1—Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFE6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFE8 H'FFEA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 855 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCR2—Timer Control Register 2 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 H'FFF0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU2 CKEG0 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 * Count at rising edge Count at falling edge Count at both edges *: Don’t care Note: This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev. 4.00 Feb 15, 2006 page 856 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TMDR2—Timer Mode Register 2 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FFF1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU2 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 4.00 Feb 15, 2006 page 857 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIOR2—Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFF2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU2 TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 4.00 Feb 15, 2006 page 858 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TIER2—Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FFF4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU2 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 4.00 Feb 15, 2006 page 859 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TSR2—Timer Status Register 2 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FFF5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU2 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Count Direction Flag 0 1 TCNT counts down TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 4.00 Feb 15, 2006 page 860 of 900 REJ09B0291-0400 Appendix B Internal I/O Register TCNT2—Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFF6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFF8 H'FFFA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Feb 15, 2006 page 861 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset Internal address bus Internal data bus R Q D P1nDDR C WDDR1 Reset Mode 1/2/3/7 P1n Mode 4/5/6 R Q D P1nDR C WDR1 TPU module Output compare output/PWM output enable Output compare output/PWM output RDR1 RPOR1 Input capture input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 0 or 1 Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev. 4.00 Feb 15, 2006 page 862 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset Internal data bus Internal address bus R Q D P1nDDR C WDDR1 Reset Mode 1/2/3/7 P1n Mode 4/5/6 R Q D P1nDR C WDR1 TPU module Output compare output/PWM output enable Output compare output/PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 2 or 3 Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13) Rev. 4.00 Feb 15, 2006 page 863 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 P1n RPOR1 Input capture input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 4 or 6 Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev. 4.00 Feb 15, 2006 page 864 of 900 REJ09B0291-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 5 or 7 Figure C.1 (d) Port 1 Block Diagram (Pins P15 and P17) Rev. 4.00 Feb 15, 2006 page 865 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams C.2 Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output P2n * RDR2 RPOR2 Input capture input Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Notes: n = 0 or 1 * Priority order: Output compare output/PWM output > DR output Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev. 4.00 Feb 15, 2006 page 866 of 900 REJ09B0291-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output P2n * RDR2 RPOR2 Internal data bus Input capture input 8-bit timer module Counter external reset input Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Notes: n = 2 or 4 * Priority order: Output compare output/PWM output > DR output Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev. 4.00 Feb 15, 2006 page 867 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output P2n * RDR2 RPOR2 Internal data bus Input capture input 8-bit timer module Counter external clock input Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Notes: n = 3 or 5 * Priority order: Output compare output/PWM output > DR output Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev. 4.00 Feb 15, 2006 page 868 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C * WDR2 P2n RDR2 RPOR2 Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Notes: n = 6 or 7 * Priority order: Output compare output/PWM output > compare match output > DR output Figure C.2 (d) Port 2 Block Diagram (Pins P26 and P27) Rev. 4.00 Feb 15, 2006 page 869 of 900 REJ09B0291-0400 Internal data bus 8-bit timer Compare-match output enable Compare-match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Appendix C I/O Port Block Diagrams C.3 Port 3 Block Diagram Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n RPOR3 Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev. 4.00 Feb 15, 2006 page 870 of 900 REJ09B0291-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Internal data bus Serial receive data Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev. 4.00 Feb 15, 2006 page 871 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C WDDR3 *2 Reset R Q D P3nDR C WDR3 *3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable P3n *1 RPOR3 Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: n = 4 or 5 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal Figure C.3 (c) Port 3 Block Diagram (Pins P34 and P35) Rev. 4.00 Feb 15, 2006 page 872 of 900 REJ09B0291-0400 Internal data bus Serial clock input Appendix C I/O Port Block Diagrams C.4 Port 4 Block Diagram Internal data bus A/D converter module Analog input Legend: RPOR4 : Read port 4 Note: n = 0 to 5 RPOR4 P4n Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45) RPOR4 P4n Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4 : Read port 4 Note: n = 6 or 7 Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev. 4.00 Feb 15, 2006 page 873 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams C.5 Port A Block Diagram Reset R Q D PAnPCR C WPCRA RPCRA Mode 4/5*3 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Mode 1/2/3/6/7 Mode 4/5 RDRA RPORA Legend: WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR Notes: n = 0 to 3 1. Output enable signal 2. Open d rain control signal 3. Set priority Figure C.5 Port A Block Diagram (Pins PA0 to PA3) Rev. 4.00 Feb 15, 2006 page 874 of 900 REJ09B0291-0400 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.6 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Mode 1/4/5* Reset S R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn Mode 3/7 Mode 1/2/4/5/6 RDRB RPORB Legend: WDDRB WDRB WPCRB RDRB RPORB RPCRB : Write to PBDDR : Write to PBDR : Write to PBPCR : Read PBDR : Read port B : Read PBPCR Notes: n = 0 to 7 * Set priority Figure C.6 Port B Block Diagram (Pin PBn) Rev. 4.00 Feb 15, 2006 page 875 of 900 REJ09B0291-0400 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.7 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Mode 1/4/5* Reset S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 3/7 Mode 1/2/4/5/6 RDRC RPORC Legend: WDDRC : Write to PCDDR WDRC : Write to PCDR WPCRC : Write to PCPCR RDRC : Read PCDR RPORC : Read port C RPCRC : Read PCPCR Notes: n = 0 to 7 * Set priority Figure C.7 Port C Block Diagram (Pin PCn) Rev. 4.00 Feb 15, 2006 page 876 of 900 REJ09B0291-0400 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.8 Port D Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 3/7 Mode 1/2/4/5/6 External address upper write External address lower write RDRD RPORD Legend: WDDRD WDRD WPCRD RDRD RPORD RPCRD : Write to PDDDR : Write to PDDR : Write to PDPCR : Read PDDR : Read port D : Read PDPCR External address upper read External address lower read Note: n = 0 to 7 Figure C.8 Port D Block Diagram (Pin PDn) Rev. 4.00 Feb 15, 2006 page 877 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams C.9 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Mode 3/7 Mode 1/2/4/5/6 RDRE RPORE Legend: WDDRE WDRE WPCRE RDRE RPORE RPCRE : Write to PEDDR : Write to PEDR : Write to PEPCR : Read PEDR : Read port E : Read PEPCR External address lower read Note: n = 0 to 7 Figure C.9 Port E Block Diagram (Pin PEn) Rev. 4.00 Feb 15, 2006 page 878 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams C.10 Port F Block Diagram Internal data bus Bus controller BRLE bit Bus request input Interrupt controller IRQ interrupt input Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Reset R Q D PF0DDR C Mode 1/2/4/5/6 WDDRF Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Figure C.10 (a) Port F Block Diagram (Pin PF0) Rev. 4.00 Feb 15, 2006 page 879 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Mode 1/2/4/5/6 PF1 RDRF RPORF Interrupt controller IRQ interrupt input Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (b) Port F Block Diagram (Pin PF1) Rev. 4.00 Feb 15, 2006 page 880 of 900 REJ09B0291-0400 Internal data bus Bus controller BRLE output Bus request acknowledge output Appendix C I/O Port Block Diagrams Reset R Q D PF2DDR C WDDRF Reset Mode 1/2/4/5/6 PF2 R Q D PF2DR C WDRF RDRF RPORF Internal data bus Bus controller Wait enable Wait input Interrupt controller Legend: WDDRF WDRF RDRF RPORF IRQ interrupt input : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (c) Port F Block Diagram (Pin PF2) Rev. 4.00 Feb 15, 2006 page 881 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Mode 3/7 PF3 Mode 1/2/4/5/6 Reset R Q D PF3DR C WDRF Mode 1/2/4/5/6 Internal data bus Bus controller LWR output Interrupt controller IRQ interrupt input RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (d) Port F Block Diagram (Pin PF3) Rev. 4.00 Feb 15, 2006 page 882 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF4DDR C WDDRF Mode 3/7 PF4 Mode 1/2/4/5/6 Reset R Q D PF4DR C WDRF Mode 1/2/4/5/6 Internal data bus Bus controller HWR output RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (e) Port F Block Diagram (Pin PF4) Rev. 4.00 Feb 15, 2006 page 883 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF5DDR C WDDRF Mode 3/7 PF5 Mode 1/2/4/5/6 Reset R Q D PF5DR C WDRF Mode 1/2/4/5/6 RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (f) Port F Block Diagram (Pin PF5) Rev. 4.00 Feb 15, 2006 page 884 of 900 REJ09B0291-0400 Internal data bus Bus controller RD output Appendix C I/O Port Block Diagrams Reset R Q D PF6DDR C WDDRF Mode 3/7 PF6 Mode 1/2/4/5/6 Reset R Q D PF6DR C WDRF Mode 1/2/4/5/6 RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (g) Port F Block Diagram (Pin PF6) Rev. 4.00 Feb 15, 2006 page 885 of 900 REJ09B0291-0400 Internal data bus Bus controller AS output Appendix C I/O Port Block Diagrams Mode 1/2/4/5/6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Note: * Set priority Figure C.10 (h) Port F Block Diagram (Pin PF7) Rev. 4.00 Feb 15, 2006 page 886 of 900 REJ09B0291-0400 Internal data bus φ Appendix C I/O Port Block Diagrams C.11 Port G Block Diagram Reset R Q D PG0DDR C WDDRG Reset PG0 R Q D PG0DR C WDRG RDRG RPORG A/D converter A/D converter external trigger input Interrupt controller IRQ interrupt input Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.11 (a) Port G Block Diagram (Pin PG0) Rev. 4.00 Feb 15, 2006 page 887 of 900 REJ09B0291-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PG1DDR C WDDRG Mode 1/2/3/7 PG1 Mode 4/5/6 Reset R Q D PG1DR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Interrupt controller IRQ interrupt input Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.11 (b) Port G Block Diagram (Pin PG1) Rev. 4.00 Feb 15, 2006 page 888 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Reset R Q D PGnDDR C WDDRG Mode 1/2/3/7 PGn Mode 4/5/6 Reset R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Note: n = 2 or 3 Figure C.11 (c) Port G Block Diagram (Pins PG2 and PG3) Rev. 4.00 Feb 15, 2006 page 889 of 900 REJ09B0291-0400 Appendix C I/O Port Block Diagrams Mode Mode 1/4/5 2/3/6/7 Reset WDDRG Reset Mode 3/7 PG4 Mode 1/2/4/5/6 R Q D PG4DR C WDRG RDRG RPORG Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.11 (d) Port G Block Diagram (Pin PG4) Rev. 4.00 Feb 15, 2006 page 890 of 900 REJ09B0291-0400 Internal data bus S R Q D PG4DDR C Bus controller Chip select Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode I/O Port States in Each Processing State MCU Operating Mode 1 to 7 PowerOn Reset T Hardware Software Standby Standby Mode Mode T kept Bus Release State kept Program Execution State Sleep Mode I/O port Table D.1 Port Name Pin Name P17/TIOCB2/ TCLKD P16/TIOCA2 P15/TIOCB1/ TCLKC P14/TIOCA1 P13/TIOCD0/ TCLKB/A23 P12/TIOCC0/ TCLKA/A22 P11/TIOCB0/ A21 P10/TIOCA0/ A20 Port 2 Port 3 P47/DA1 Manual Reset kept 1 to 3, 7 4 to 6 T T kept kept T T kept kept I/O port [DDR = 0] Input port [DDR = 1] Address output [DDR · OPE = 0] T T [DDR · OPE = 1] kept 1 to 7 1 to 7 1 to 7 T T T kept kept T T T T kept kept [DAOE1 = 1] kept [DAOE1 = 0] T kept kept kept I/O port I/O port I/O port P46/DA0 1 to 7 T T T [DAOE0 = 1] kept [DAOE0 = 0] T kept I/O port P45 to P40 1 to 7 T T T T T Input port Rev. 4.00 Feb 15, 2006 page 891 of 900 REJ09B0291-0400 Appendix D Pin States Program Execution State Sleep Mode I/O port Address output Port Name Pin Name Port A MCU Operating Mode 1 to 3, 7 4, 5 PowerOn Reset T L Manual Reset kept kept Hardware Software Standby Standby Mode Mode T T kept [OPE = 0] T [OPE = 1] kept Bus Release State kept T 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept [OPE = 0] T [OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output Address output Port B 1, 4, 5 L kept T 2, 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept [OPE = 0] T [OPE = 1] kept kept T [DDR = 0] Input port [DDR = 1] Address output I/O port Address output 3, 7 Port C 1, 4, 5 T L kept kept T T 2, 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept T kept kept T kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port 3, 7 Port D 1, 2, 4 to 6 3, 7 Port E 1, 2, 8 bit 4 to 6 bus T T T T kept T* kept kept T* kept T T T T T T 16 bit T bus 3, 7 T Rev. 4.00 Feb 15, 2006 page 892 of 900 REJ09B0291-0400 Appendix D Pin States Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS, RD, HWR, LWR Port Name Pin Name PF7/φ MCU Operating Mode 1, 2, 4 to 6 PowerOn Reset Clock output Manual Reset [DDR = 0] T [DDR = 1] Clock output kept Hardware Software Standby Standby Mode Mode T [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H [OPE = 0] T [OPE = 1] H kept [WAITE = 0] kept [WAITE = 1] T kept [BRLE = 0] kept [BRLE = 1] H kept [BRLE = 0] kept [BRLE = 1] T kept Bus Release State [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T 3, 7 T T PF6/AS PF5/RD PF4/HWR PF3/LWR/ IRQ3 PF2/WAIT/ IRQ2 1, 2, 4 to 6 H H* T 3, 7 1, 2, 4 to 6 T T kept T kept [WAITE = 0] kept [WAITE = 1] T kept L I/O port [WAITE = 0] I/O port [WAITE = 1] WAIT I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0 I/O port [WAITE = 0] T kept [WAITE = 1] T kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] BREQ kept [DDR = 0] T [DDR = 1] H* kept T T 3, 7 PF1/BACK/ IRQ1 1, 2, 4 to 6 T T 3, 7 PF0/BREQ/ IRQ0 1, 2, 4 to 6 T T T T kept T 3, 7 PG4/CS0 1, 4, 5 2, 6 T H T T T kept [DDR · OPE = 0] T T [DDR · OPE = 1] H kept kept 3, 7 T T Rev. 4.00 Feb 15, 2006 page 893 of 900 REJ09B0291-0400 Appendix D Pin States Program Execution State Sleep Mode I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 I/O port I/O port Port Name Pin Name PG3/CS1 PG2/CS2 PG1/CS3/ IRQ7 PG0/ADTRG/ IRQ6 MCU Operating Mode 1 to 3, 7 4 to 6 PowerOn Reset T T Manual Reset kept [DDR = 0] T [DDR = 1] H* kept kept Hardware Software Standby Standby Mode Mode T T kept Bus Release State kept [DDR · OPE = 0] T T [DDR · OPE = 1] H kept kept kept T 1 to 3, 7 4 to 6 T T T T Legend: H : L : T : kept : DDR : OPE : WAITE : BRLE : Note: * High level Low level High impedance Input port becomes high-impedance, output port retains state Data direction register Output port enable Wait input enable Bus release enable Indicates the state after completion of the executing bus cycle. Rev. 4.00 Feb 15, 2006 page 894 of 900 REJ09B0291-0400 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t1 ≥ 10tcyc RES t2 ≥ 0ns Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t ≥ 100ns RES tOSC tNMIRH NMI Figure E.2 Timing of Recovery from Hardware Standby Mode Rev. 4.00 Feb 15, 2006 page 895 of 900 REJ09B0291-0400 Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8S/2345 Group Product Code Lineup Product Code HD6432345 Mark Code HD6432345(***)TE HD6432345(***)TF HD6432345(***)F HD6432345(***)FA ZTAT™ HD6472345 HD6472345TE HD6472345TF HD6472345F HD6472345FA F-ZTAT™ HD64F2345 HD64F2345TE HD64F2345TF HD64F2345F HD64F2345FA H8S/2344 Mask ROM HD6432344 HD6432344(***)TE HD6432344(***)TF HD6432344(***)F HD6432344(***)FA H8S/2343 Mask ROM HD6432343 HD6432343(***)TE HD6432343(***)TF HD6432343(***)F HD6432343(***)FA H8S/2341 Mask ROM HD6432341 HD6432341(***)TE HD6432341(***TF HD6432341(***)F HD6432341(***)FA H8S/2340 ROMless HD6412340 HD6412340TE HD6412340TF HD6412340F HD6412340FA Note: (***) indicates the ROM code. Package (Package Code) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) Product Type H8S/2345 Mask ROM Rev. 4.00 Feb 15, 2006 page 896 of 900 REJ09B0291-0400 Appendix G Package Dimensions Appendix G Package Dimensions Figures G.1 to G.4 show the package dimensions of the H8S/2345 Group. JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 51 75 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 A2 1 ZD Index mark 25 A θ F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0 Min Figure G.1 TFP-100B Package Dimensions Rev. 4.00 Feb 15, 2006 page 897 of 900 REJ09B0291-0400 c Appendix G Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code MASS[Typ.] TFP-100G/TFP-100GV 0.4g HD *1 D 75 51 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E b1 Reference Dimension in Millimeters Symbol *2 c1 c 100 26 ZE Terminal cross section 1 ZD Index mark 25 F θ e *3 y bp A1 L L1 x M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0° 8° 0.4 0.07 0.10 1.2 1.2 0.4 0.5 0.6 1.0 Min A2 Figure G.2 TFP-100G Package Dimensions Rev. 4.00 Feb 15, 2006 page 898 of 900 REJ09B0291-0400 A c Appendix G Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JE-B Previous Code FP-100A/FP-100AV MASS[Typ.] 1.7g HD *1 D 51 80 81 50 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 ZE *2 HE E Terminal cross section c 100 31 Reference Dimension in Millimeters Symbol 1 ZD 30 F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 20 14 2.70 24.4 24.8 25.2 18.4 18.8 19.2 3.10 0.00 0.20 0.30 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0° 10° 0.65 0.13 0.15 0.58 0.83 1.0 1.2 1.4 2.4 Min A A2 Figure G.3 FP-100A Package Dimensions Rev. 4.00 Feb 15, 2006 page 899 of 900 REJ09B0291-0400 c Appendix G Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 c1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 1 ZD 25 F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Min A A2 Figure G.4 FP-100B Package Dimensions Rev. 4.00 Feb 15, 2006 page 900 of 900 REJ09B0291-0400 c Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2345 Group, H8S/2345 F-ZTAT™ Publication Date: 1st Edition, September 1997 Rev.4.00, February 15, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.0 H8S/2345 Group, H8S/2345 F-ZTAT™ Hardware Manual