REJ09B0331-0500
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8S/2655 Group
Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series
H8S/2655 H8S/2653 HD6432655 HD6472655 HD6432653
Rev. 5.00 Revision Date: Sep 14, 2006
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 5.00 Sep 14, 2006 page ii of xxviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.
Rev. 5.00 Sep 14, 2006 page iii of xxviii
Rev. 5.00 Sep 14, 2006 page iv of xxviii
Preface
The H8S/2655 Group is a series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT*) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2655 Group enables compact, high-performance systems to be implemented easily. This manual describes the hardware of the H8S/2655 Group. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Note: * ZTAT is a registered trademark of Renesas Technology Corp.
Rev. 5.00 Sep 14, 2006 page v of xxviii
Rev. 5.00 Sep 14, 2006 page vi of xxviii
Main Revisions for This Edition
Item All Page — Revision (See Manual for Details) • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8S/2655 Series → (After) H8S/2655 Group 5.3.1 External Interrupts 102 IRQ7 to IRQ0 Interrupts Description amended • Using ISCR, it is possible ... , at pins IRQ7 to IRQ0. 5.4.6 Interrupt Exception Handling Sequence Figure 5.11 Interrupt Exception Handling 7.2.4 DMA Control Register (CMACR) 9.4.3 Pin Functions Table 9.7 Port 3 Pin Functions 10.2.3 Timer I/O 445 Control Register (TIOR) 227 373 Bit table amended Bit 6 (Before) DTID5 → (After) DTID Table 9.7 amended TxD1 output pin* TxD0 output pin* Bits 7 to 4 I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0) Channel 0 description amended
Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOD3 IOD2 IOD1 IOD0 Description 1 0 0 1 1 * 0 1 * * Capture input TGR0D source is is input TIOCD0 pin capture 2 register* Input capture at rising edge Input capture at falling edge Input capture at both edges
122
Description amended Internal data bus
Capture input Input capture at TCNT1 1 source is channel count-up/count-down* 1/count clock
446
Channel 2 description amended
Bit 7 Bit 6 Bit 5 Bit 4 Channel 2 IOB3 IOB2 IOB1 IOB0 Description 1 0 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges
Rev. 5.00 Sep 14, 2006 page vii of xxviii
Item
Page
Revision (See Manual for Details) Bits 3 to 0 I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0) Channel 0 description amended
Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Capture input TGR0C source is is input TIOCC0 pin capture 1 register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0C Output disabled is output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
10.2.3 Timer I/O 451 Control Register (TIOR)
Capture input Input capture at TCNT1 source is channel count-up/count-down 1/count clock
454
Channel 3 description amended
Bit 3 Bit 2 Bit 1 Bit 0 Channel 3 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Capture input TGR3C source is is input TIOCC3 pin capture 1 register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Output disabled TGR3C is output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock
14.2.6 Serial Control Register (SCR)
598
Bit 5Overrun Error (ORER) Description of setting condition amended When the next serial reception is completed while RDRF = 1*
2
Rev. 5.00 Sep 14, 2006 page viii of xxviii
Item 14.2.8 Bit Rate Register (BRR) Table 14.3 BRR Setting for Various Bit Rates (Asynchronous Mode)
Page 601
Revision (See Manual for Details) Table 14.3 amended
φ = 3 MHz Bit Rate (bit/s) 38400 Error (%) 22.07
n 0
N 1
602
Bit Rate (bit/s) 31250 n 0
φ = 3.6864 MHz N 3 Error (%) –7.84
15.2.3 Serial Mode Register (SMR)
656
Description added Bits 6 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.5, Serial Mode Register (SMR).
657 16.6 Usage Notes 707
Figure of TEND flag generation timing in transmission operation deleted Usage notes deleted (Before) • If conversion is terminated ... 3. After termination, ... 200 A/D reference clock cycles.) → (After) (deleted)
19.1.1 Block Diagram 721 Figure 19.1 Block Diagram of ROM (H8S/2655)
Figure 19.1 amended
H'00FFFE H'010000 H'010002 H'00FFFF H'010001 H'010003 When EAE = 0
H'01FFFE
H'01FFFF
20.1.1 Block Diagram 735 Figure 20.1 Block Diagram of Clock Pulse Generator B.1 Addresses 872
Figure 20.1 amended (Before) SCK1, SCK0 → (After) SCK2 to SCK0
Table amended
Address Register (low) Name H'FF38 H'FF39 H'FF3A H'FF3B H'FF3C H'FF3D SBYCR SYSCR SCKCR MDCR Bit 7 SSBY MACS PSTOP — Bit 6 STS2 — — — Bit 5 STS1 INTM1 — — Bit 4 STS0 INTM0 — — Bit 3 OPE NMIEG — — Bit 2 — — SCK2 MDS2 Bit 1 — — SCK1 MDS1 Bit 0 — RAME SCK0 MDS0 MSTP8 MSTP0 Module Name MCU Data Bus Width 8-bit
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1
Rev. 5.00 Sep 14, 2006 page ix of xxviii
Item B.2 Functions
Page 926
Revision (See Manual for Details) DMABCRH, DMABCRL H'FF06, H'FF07 DMAC Figure amended
Full address mode (cont) Bit :
7 DTME1 0 R/W
6 DTE1 0 R/W
5 DTME0 0 R/W
4 DTE0 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
DMABCRL :
Initial value : Read/Write :
DTIE1B DTIE1A
DTIE0B DTIE0A
Channel 0 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel 1 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
Channel 1 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel 0 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled
Channel 1 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 1 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled
931
DTCERA to DTCERF H'FF30 to H'FF35 DTC Correspondence between Interrupt Sources and DTCER Table amended
Bits Register DTCERD 7 — 6 — 5 TGI5A 4 TGI5B 3 CMIA0 2 CMIB0 1 CMIA1 0 CMIB1
Rev. 5.00 Sep 14, 2006 page x of xxviii
Item B.2 Functions
Page 998
Revision (See Manual for Details) TSR0 H'FFD5 TPU0 Figure amended TGR Input Capture/Output Compare Flag A TGR Input Capture/Output Compare Flag B TGR Input Capture/Output Compare Flag C TGR Input Capture/Output Compare Flag D
1004
TSR1 H'FFE5 TPU1 Figure amended TGR Input Capture/Output Compare Flag A TGR Input Capture/Output Compare Flag B
1010
TSR2 H'FFF5 TPU2 Figure amended TGR Input Capture/Output Compare Flag A TGR Input Capture/Output Compare Flag B
Appendix G Package Dimensions Figure G.1 TFP-120 Package Dimensions Figure G.2 FP-128 Package Dimensions
1058
Figure G.1 replaced
1059
Figure G.2 replaced
Rev. 5.00 Sep 14, 2006 page xi of xxviii
Rev. 5.00 Sep 14, 2006 page xii of xxviii
Contents
Section 1 Overview .............................................................................................................
1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 6 Pin Description.................................................................................................................. 7 1.3.1 Pin Arrangement .................................................................................................. 7 1.3.2 Pin Functions in Each Operating Mode ............................................................... 9 1.3.3 Pin Functions ....................................................................................................... 14
Section 2 CPU ...................................................................................................................... 23
2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function ....................................................... 2.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode................................................................................................. 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State...................................................................................... 2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 23 23 24 25 26 31 32 32 33 34 36 37 37 39 40 40 41 43 52 54 54 57 61 61 62 63 65 66 66
2.2 2.3 2.4
2.5
2.6
2.7
2.8
Rev. 5.00 Sep 14, 2006 page xiii of xxviii
2.9
Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 External Address Space Access Timing ..............................................................
67 67 67 69 70
Section 3 MCU Operating Modes .................................................................................. 71
3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 ................................................................................................................. 3.3.2 Mode 2 ................................................................................................................. 3.3.3 Mode 3 ................................................................................................................. 3.3.4 Mode 4 ................................................................................................................. 3.3.5 Mode 5 ................................................................................................................. 3.3.6 Mode 6 ................................................................................................................. 3.3.7 Mode 7 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ 71 71 72 73 73 73 75 75 75 75 75 76 76 76 77 77
3.2
3.3
3.4 3.5
Section 4 Exception Handling ......................................................................................... 81
4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table ....................................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Types.......................................................................................................... 4.2.3 Reset Sequence .................................................................................................... 4.2.4 Interrupts after Reset............................................................................................ Traces................................................................................................................................ Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack ................................................................................................. 81 81 82 82 84 84 84 85 86 87 88 89 90 91
4.2
4.3 4.4 4.5 4.6 4.7
Rev. 5.00 Sep 14, 2006 page xiv of xxviii
Section 5 Interrupt Controller .......................................................................................... 93
5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 5.2.3 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 5.2.4 IRQ Enable Register (IER) .................................................................................. 5.2.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.6 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0 ..................................................................................... 5.4.3 Interrupt Control Mode 1 ..................................................................................... 5.4.4 Interrupt Control Mode 2 ..................................................................................... 5.4.5 Interrupt Control Mode 3 ..................................................................................... 5.4.6 Interrupt Exception Handling Sequence .............................................................. 5.4.7 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions That Disable Interrupts..................................................................... 5.5.3 Times when Interrupts Are Disabled ................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... DTC and DMAC Activation by Interrupt ......................................................................... 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram ..................................................................................................... 5.6.3 Operation ............................................................................................................. 93 93 94 94 95 96 96 97 97 99 99 100 102 102 104 104 108 108 112 114 117 119 121 123 124 124 125 125 125 126 126 126 127
5.2
5.3
5.4
5.5
5.6
Section 6 Bus Controller ................................................................................................... 129
6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... 129 129 131 132 134
Rev. 5.00 Sep 14, 2006 page xv of xxviii
6.2
6.3
6.4
6.5
6.6
Register Descriptions ........................................................................................................ 6.2.1 Bus Width Control Register (ABWCR)............................................................... 6.2.2 Access State Control Register (ASTCR) ............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 6.2.4 Bus Control Register H (BCRH).......................................................................... 6.2.5 Bus Control Register L (BCRL) .......................................................................... 6.2.6 Memory Control Register (MCR)........................................................................ 6.2.7 DRAM Control Register (DRAMCR) ................................................................. 6.2.8 Refresh Timer/Counter (RTCNT)........................................................................ 6.2.9 Refresh Time Constant Register (RTCOR) ......................................................... Overview of Bus Control .................................................................................................. 6.3.1 Area Partitioning.................................................................................................. 6.3.2 Bus Specifications................................................................................................ 6.3.3 Memory Interfaces ............................................................................................... 6.3.4 Advanced Mode................................................................................................... 6.3.5 Areas in Normal Mode......................................................................................... 6.3.6 Chip Select Signals .............................................................................................. Basic Bus Interface ........................................................................................................... 6.4.1 Overview.............................................................................................................. 6.4.2 Data Size and Data Alignment............................................................................. 6.4.3 Valid Strobes....................................................................................................... 6.4.4 Basic Timing........................................................................................................ 6.4.5 Wait Control ........................................................................................................ DRAM Interface ............................................................................................................... 6.5.1 Overview.............................................................................................................. 6.5.2 Setting DRAM Space........................................................................................... 6.5.3 Address Multiplexing........................................................................................... 6.5.4 Data Bus............................................................................................................... 6.5.5 Pins Used for DRAM Interface............................................................................ 6.5.6 Basic Timing........................................................................................................ 6.5.7 Precharge State Control ....................................................................................... 6.5.8 Wait Control ........................................................................................................ 6.5.9 Byte Access Control ............................................................................................ 6.5.10 Burst Operation.................................................................................................... 6.5.11 Caution Concerning 2-CAS System..................................................................... 6.5.12 Refresh Control.................................................................................................... Pseudo-SRAM Interface ................................................................................................... 6.6.1 Overview.............................................................................................................. 6.6.2 Setting PSRAM Space ......................................................................................... 6.6.3 Data Bus............................................................................................................... 6.6.4 Pins Used for PSRAM Interface ..........................................................................
135 135 136 137 140 143 145 148 151 151 152 152 153 154 155 156 157 158 158 158 160 161 169 171 171 171 172 172 173 174 175 176 178 182 185 186 190 190 190 190 191
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6.7
6.8
6.9
6.10 6.11
6.12
6.13
6.6.5 Basic Timing........................................................................................................ 6.6.6 Precharge State Control ....................................................................................... 6.6.7 Wait Control ........................................................................................................ 6.6.8 Burst Operation.................................................................................................... 6.6.9 Refresh Control.................................................................................................... 6.6.10 Power-On Sequence............................................................................................. DMAC Single Address Mode and DRAM/PSRAM Interface.......................................... 6.7.1 When DDS = 1..................................................................................................... 6.7.2 When DDS = 0..................................................................................................... Burst ROM Interface......................................................................................................... 6.8.1 Overview.............................................................................................................. 6.8.2 Basic Timing........................................................................................................ 6.8.3 Wait Control ........................................................................................................ Idle Cycle .......................................................................................................................... 6.9.1 Operation ............................................................................................................. 6.9.2 Pin States in Idle Cycle ........................................................................................ Write Data Buffer Function .............................................................................................. Bus Release....................................................................................................................... 6.11.1 Overview.............................................................................................................. 6.11.2 Operation ............................................................................................................. 6.11.3 Pin States in External Bus Released State............................................................ 6.11.4 Transition Timing ................................................................................................ Bus Arbitration.................................................................................................................. 6.12.1 Overview.............................................................................................................. 6.12.2 Operation ............................................................................................................. 6.12.3 Bus Transfer Timing ............................................................................................ 6.12.4 External Bus Release Usage Note........................................................................ Resets and the Bus Controller ...........................................................................................
192 193 194 196 199 200 201 201 202 203 203 203 205 206 206 208 209 210 210 210 211 212 213 213 213 214 215 215
Section 7 DMA Controller ................................................................................................ 217
7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Overview of Functions......................................................................................... 7.1.4 Pin Configuration................................................................................................. 7.1.5 Register Configuration......................................................................................... Register Descriptions (1) (Short Address Mode) .............................................................. 7.2.1 Memory Address Registers (MAR) ..................................................................... 7.2.2 I/O Address Register (IOAR) .............................................................................. 7.2.3 Execute Transfer Count Register (ETCR) ........................................................... 7.2.4 DMA Control Register (DMACR)....................................................................... 217 217 218 219 221 222 223 224 225 226 227
7.2
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7.3
7.4
7.5
7.6 7.7
7.2.5 DMA Band Control Register (DMABCR)........................................................... Register Descriptions (2) (Full Address Mode) ................................................................ 7.3.1 Memory Address Register (MAR)....................................................................... 7.3.2 I/O Address Register (IOAR) .............................................................................. 7.3.3 Execute Transfer Count Register (ETCR) ........................................................... 7.3.4 DMA Control Register (DMACR)....................................................................... 7.3.5 DMA Band Control Register (DMABCR)........................................................... Register Descriptions (3) .................................................................................................. 7.4.1 DMA Write Enable Register (DMAWER) .......................................................... 7.4.2 DMA Terminal Control Register (DMATCR)..................................................... 7.4.3 Module Stop Control Register (MSTPCR) .......................................................... Operation .......................................................................................................................... 7.5.1 Transfer Modes .................................................................................................... 7.5.2 Sequential Mode .................................................................................................. 7.5.3 Idle Mode............................................................................................................. 7.5.4 Repeat Mode ........................................................................................................ 7.5.5 Single Address Mode........................................................................................... 7.5.6 Normal Mode....................................................................................................... 7.5.7 Block Transfer Mode ........................................................................................... 7.5.8 DMAC Activation Sources .................................................................................. 7.5.9 Basic DMAC Bus Cycles..................................................................................... 7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 7.5.12 Write Data Buffer Function ................................................................................. 7.5.13 DMAC Multi-Channel Operation ........................................................................ 7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC..................................................................................................... 7.5.15 NMI Interrupts and DMAC.................................................................................. 7.5.16 Forced Termination of DMAC Operation............................................................ 7.5.17 Clearing Full Address Mode ................................................................................ Interrupts ........................................................................................................................... Usage Notes ......................................................................................................................
231 237 237 238 238 240 244 250 250 253 254 255 255 258 261 264 268 271 274 280 283 284 292 298 299 300 301 302 303 304 305
Section 8 Data Transfer Controller................................................................................. 309
8.1 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram ..................................................................................................... 8.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 8.2.1 DTC Mode Register A (MRA) ............................................................................ 8.2.2 DTC Mode Register B (MRB)............................................................................. 309 309 310 311 312 312 314
8.2
Rev. 5.00 Sep 14, 2006 page xviii of xxviii
8.3
8.4 8.5
8.2.3 DTC Source Address Register (SAR).................................................................. 8.2.4 DTC Destination Address Register (DAR).......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 8.2.8 DTC Vector Register (DTVECR)........................................................................ 8.2.9 Module Stop Control Register (MSTPCR) .......................................................... Operation .......................................................................................................................... 8.3.1 Overview.............................................................................................................. 8.3.2 Activation Sources ............................................................................................... 8.3.3 DTC Vector Table................................................................................................ 8.3.4 Location of Register Information in Address Space ............................................ 8.3.5 Normal Mode....................................................................................................... 8.3.6 Repeat Mode ........................................................................................................ 8.3.7 Block Transfer Mode ........................................................................................... 8.3.8 Chain Transfer ..................................................................................................... 8.3.9 Operation Timing................................................................................................. 8.3.10 Number of DTC Execution States........................................................................ 8.3.11 Procedures for Using DTC................................................................................... 8.3.12 Examples of Use of the DTC ............................................................................... Interrupts ........................................................................................................................... Usage Notes ......................................................................................................................
315 315 316 316 317 318 319 319 319 321 323 326 327 328 329 331 332 333 335 336 339 339
Section 9 I/O Ports .............................................................................................................. 341
9.1 9.2 Overview........................................................................................................................... Port 1................................................................................................................................. 9.2.1 Overview.............................................................................................................. 9.2.2 Register Configuration......................................................................................... 9.2.3 Pin Functions ....................................................................................................... Port 2................................................................................................................................. 9.3.1 Overview.............................................................................................................. 9.3.2 Register Configuration......................................................................................... 9.3.3 Pin Functions ....................................................................................................... Port 3................................................................................................................................. 9.4.1 Overview.............................................................................................................. 9.4.2 Register Configuration......................................................................................... 9.4.3 Pin Functions ....................................................................................................... Port 4................................................................................................................................. 9.5.1 Overview.............................................................................................................. 9.5.2 Register Configuration......................................................................................... 9.5.3 Pin Functions ....................................................................................................... 341 347 347 347 350 358 358 358 361 369 369 369 372 374 374 374 375
9.3
9.4
9.5
Rev. 5.00 Sep 14, 2006 page xix of xxviii
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
Port 5................................................................................................................................. 9.6.1 Overview.............................................................................................................. 9.6.2 Register Configuration......................................................................................... 9.6.3 Pin Functions ....................................................................................................... Port 6................................................................................................................................. 9.7.1 Overview.............................................................................................................. 9.7.2 Register Configuration......................................................................................... 9.7.3 Pin Functions ....................................................................................................... Port A................................................................................................................................ 9.8.1 Overview.............................................................................................................. 9.8.2 Register Configuration......................................................................................... 9.8.3 Pin Functions ....................................................................................................... 9.8.4 MOS Input Pull-Up Function............................................................................... Port B ................................................................................................................................ 9.9.1 Overview.............................................................................................................. 9.9.2 Register Configuration......................................................................................... 9.9.3 Pin Functions ....................................................................................................... 9.9.4 MOS Input Pull-Up Function............................................................................... Port C ................................................................................................................................ 9.10.1 Overview.............................................................................................................. 9.10.2 Register Configuration......................................................................................... 9.10.3 Pin Functions ....................................................................................................... 9.10.4 MOS Input Pull-Up Function............................................................................... Port D................................................................................................................................ 9.11.1 Overview.............................................................................................................. 9.11.2 Register Configuration......................................................................................... 9.11.3 Pin Functions ....................................................................................................... 9.11.4 MOS Input Pull-Up Function............................................................................... Port E ................................................................................................................................ 9.12.1 Overview.............................................................................................................. 9.12.2 Register Configuration......................................................................................... 9.12.3 Pin Functions ....................................................................................................... 9.12.4 MOS Input Pull-Up Function............................................................................... Port F................................................................................................................................. 9.13.1 Overview.............................................................................................................. 9.13.2 Register Configuration......................................................................................... 9.13.3 Pin Functions ....................................................................................................... Port G................................................................................................................................ 9.14.1 Overview.............................................................................................................. 9.14.2 Register Configuration......................................................................................... 9.14.3 Pin Functions .......................................................................................................
376 376 376 379 380 380 381 383 385 385 386 389 391 392 392 393 395 397 398 398 399 401 403 404 404 405 407 409 410 410 411 413 415 416 416 417 419 421 421 422 425
Rev. 5.00 Sep 14, 2006 page xx of xxviii
Section 10 16-Bit Timer Pulse Unit (TPU) .................................................................. 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Control Register (TCR) ............................................................................. 10.2.2 Timer Mode Register (TMDR) ............................................................................ 10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.2.5 Timer Status Register (TSR)................................................................................ 10.2.6 Timer Counter (TCNT)........................................................................................ 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR)................................................................................ 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 10.2.10 Module Stop Control Register (MSTPCR) .......................................................... 10.3 Interface to Bus Master ..................................................................................................... 10.3.1 16-Bit Registers ................................................................................................... 10.3.2 8-Bit Registers ..................................................................................................... 10.4 Operation .......................................................................................................................... 10.4.1 Overview.............................................................................................................. 10.4.2 Basic Functions.................................................................................................... 10.4.3 Synchronous Operation........................................................................................ 10.4.4 Buffer Operation .................................................................................................. 10.4.5 Cascaded Operation ............................................................................................. 10.4.6 PWM Modes ........................................................................................................ 10.4.7 Phase Counting Mode .......................................................................................... 10.5 Interrupts ........................................................................................................................... 10.5.1 Interrupt Sources and Priorities............................................................................ 10.5.2 DTC/DMAC Activation....................................................................................... 10.5.3 A/D Converter Activation.................................................................................... 10.6 Operation Timing.............................................................................................................. 10.6.1 Input/Output Timing ............................................................................................ 10.6.2 Interrupt Signal Timing........................................................................................ 10.7 Usage Notes ......................................................................................................................
427 427 427 431 432 434 436 436 441 443 456 459 462 463 464 465 466 467 467 467 469 469 470 476 479 483 485 490 497 497 499 500 501 501 505 509
Section 11 Programmable Pulse Generator (PPG) .................................................... 519
11.1 Overview........................................................................................................................... 519 11.1.1 Features................................................................................................................ 519 11.1.2 Block Diagram ..................................................................................................... 520
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11.1.3 Pin Configuration................................................................................................. 11.1.4 Registers............................................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 11.2.4 Notes on NDR Access.......................................................................................... 11.2.5 PPG Output Control Register (PCR).................................................................... 11.2.6 PPG Output Mode Register (PMR)...................................................................... 11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 11.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 11.2.9 Module Stop Control Register (MSTPCR) .......................................................... 11.3 Operation .......................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing...................................................................................................... 11.3.3 Normal Pulse Output............................................................................................ 11.3.4 Non-Overlapping Pulse Output............................................................................ 11.3.5 Inverted Pulse Output .......................................................................................... 11.3.6 Pulse Output Triggered by Input Capture ............................................................ 11.4 Usage Notes ...................................................................................................................... 11.4.1 Operation of Pulse Output Pins............................................................................ 11.4.2 Note on Non-Overlapping Output........................................................................
521 522 523 523 524 525 525 528 529 532 532 533 534 534 535 536 538 541 542 543 543 543 545 545 545 546 547 547 548 548 548 549 549 552 555 556 556 557 559 559
Section 12 8-Bit Timers ..................................................................................................... 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 12.3 Operation .......................................................................................................................... 12.3.1 TCNT Incrementation Timing ............................................................................. 12.3.2 Compare Match Timing....................................................................................... 12.3.3 Timing of External RESET on TCNT ................................................................. 12.3.4 Timing of Overflow Flag (OVF) Setting .............................................................
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12.3.5 Operation with Cascaded Connection.................................................................. 12.4 Interrupt Sources............................................................................................................... 12.5 Sample Application........................................................................................................... 12.6 Usage Notes ...................................................................................................................... 12.6.1 Contention between TCNT Write and Clear........................................................ 12.6.2 Contention between TCNT Write and Increment ................................................ 12.6.3 Contention between TCOR Write and Compare Match ...................................... 12.6.4 Contention between Compare Matches A and B ................................................. 12.6.5 Switching of Internal Clocks and TCNT Operation............................................
560 561 562 563 563 564 565 566 566 569 569 569 570 571 571 572 572 572 574 576 578 578 579 579 580 581 581 581 582 582 582 582
Section 13 Watchdog Timer ............................................................................................. 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram ..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Timer Counter (TCNT)........................................................................................ 13.2.2 Timer Control/Status Register (TCSR) ................................................................ 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 13.2.4 Notes on Register Access..................................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Watchdog Timer Operation ................................................................................. 13.3.2 Interval Timer Operation ..................................................................................... 13.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 13.4 Interrupts ........................................................................................................................... 13.5 Usage Notes ...................................................................................................................... 13.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 13.5.2 Changing Value of CKS2 to CKS0...................................................................... 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 13.5.4 System Reset by WDTOVF Signal...................................................................... 13.5.5 Internal Reset in Watchdog Timer Mode.............................................................
Section 14 Serial Communication Interface (SCI) .................................................... 583
14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 583 583 585 586 587 588
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14.2.1 Receive Shift Register (RSR) .............................................................................. 14.2.2 Receive Data Register (RDR) .............................................................................. 14.2.3 Transmit Shift Register (TSR) ............................................................................. 14.2.4 Transmit Data Register (TDR)............................................................................. 14.2.5 Serial Mode Register (SMR)................................................................................ 14.2.6 Serial Control Register (SCR).............................................................................. 14.2.7 Serial Status Register (SSR) ................................................................................ 14.2.8 Bit Rate Register (BRR) ...................................................................................... 14.2.9 Smart Card Mode Register (SCMR) .................................................................... 14.2.10 Module Stop Control Register (MSTPCR) .......................................................... 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 14.3.2 Operation in Asynchronous Mode ....................................................................... 14.3.3 Multiprocessor Communication Function............................................................ 14.3.4 Operation in Clocked Synchronous Mode ........................................................... 14.4 SCI Interrupts.................................................................................................................... 14.5 Usage Notes ......................................................................................................................
588 588 589 589 590 593 596 601 610 611 612 612 614 625 633 642 644
Section 15 Smart Card Interface ..................................................................................... 649
15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 Smart Card Mode Register (SCMR) .................................................................... 15.2.2 Serial Status Register (SSR) ................................................................................ 15.2.3 Serial Mode Register (SMR)................................................................................ 15.2.4 Serial Control Register (SCR).............................................................................. 15.3 Operation .......................................................................................................................... 15.3.1 Overview.............................................................................................................. 15.3.2 Pin Connections ................................................................................................... 15.3.3 Data Format ......................................................................................................... 15.3.4 Register Settings .................................................................................................. 15.3.5 Clock.................................................................................................................... 15.3.6 Data Transfer Operations..................................................................................... 15.3.7 Example of Use of Software Standby Mode........................................................ 15.3.8 Powering On ........................................................................................................ 15.4 Usage Notes ...................................................................................................................... 649 649 650 651 652 653 653 654 656 657 658 658 659 660 661 664 666 673 674 674
Rev. 5.00 Sep 14, 2006 page xxiv of xxviii
Section 16 A/D Converter ................................................................................................. 679
16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 16.2.3 A/D Control Register (ADCR) ............................................................................ 16.2.4 Module Stop Control Register (MSTPCR) .......................................................... 16.3 Interface to Bus Master ..................................................................................................... 16.4 Operation .......................................................................................................................... 16.4.1 Select Single Mode .............................................................................................. 16.4.2 Select Scan Mode................................................................................................. 16.4.3 Group Single Mode.............................................................................................. 16.4.4 Group Scan Mode ................................................................................................ 16.4.5 Buffer Operation .................................................................................................. 16.4.6 Simultaneous Sampling Operation....................................................................... 16.4.7 Conversion Start Modes....................................................................................... 16.4.8 Starting Conversion by External Input................................................................. 16.4.9 A/D Conversion Time.......................................................................................... 16.5 Interrupts ........................................................................................................................... 16.6 Usage Notes ...................................................................................................................... 679 679 680 680 681 682 682 683 685 688 688 690 691 692 693 694 695 698 699 702 703 706 707
Section 17 D/A Converter ................................................................................................. 709
17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 17.2.2 D/A Control Register (DACR) ............................................................................ 17.2.3 Module Stop Control Register (MSTPCR) .......................................................... 17.3 Operation .......................................................................................................................... 709 709 710 711 711 712 712 712 714 715
Section 18 RAM .................................................................................................................. 717
18.1 Overview........................................................................................................................... 717 18.1.1 Block Diagram ..................................................................................................... 717 18.1.2 Register Configuration......................................................................................... 718
Rev. 5.00 Sep 14, 2006 page xxv of xxviii
18.2 Register Descriptions ........................................................................................................ 18.2.1 System Control Register (SYSCR) ...................................................................... 18.3 Operation .......................................................................................................................... 18.4 Usage Notes ......................................................................................................................
718 718 719 719
Section 19 ROM .................................................................................................................. 721
19.1 Overview........................................................................................................................... 19.1.1 Block Diagram ..................................................................................................... 19.1.2 Register Configuration......................................................................................... 19.2 Register Descriptions ........................................................................................................ 19.2.1 Bus Control Register L (BCRL) .......................................................................... 19.3 Operation .......................................................................................................................... 19.4 PROM Mode..................................................................................................................... 19.4.1 PROM Mode Setting............................................................................................ 19.4.2 Socket Adapter and Memory Map ....................................................................... 19.5 Programming..................................................................................................................... 19.5.1 Overview.............................................................................................................. 19.5.2 Programming and Verification............................................................................. 19.5.3 Programming Precautions.................................................................................... 19.5.4 Reliability of Programmed Data .......................................................................... 721 721 722 722 722 723 724 724 724 727 727 727 732 733
Section 20 Clock Pulse Generator .................................................................................. 735
20.1 Overview........................................................................................................................... 20.1.1 Block Diagram ..................................................................................................... 20.1.2 Register Configuration......................................................................................... 20.2 Register Descriptions ........................................................................................................ 20.2.1 System Clock Control Register (SCKCR) ........................................................... 20.3 Oscillator........................................................................................................................... 20.3.1 Connecting a Crystal Resonator........................................................................... 20.3.2 External Clock Input ............................................................................................ 20.4 Duty Adjustment Circuit................................................................................................... 20.5 Medium-Speed Clock Divider .......................................................................................... 20.6 Bus Master Clock Selection Circuit .................................................................................. 735 735 736 736 736 737 737 739 741 741 741
Section 21 Power-Down Modes ...................................................................................... 743
21.1 Overview........................................................................................................................... 21.1.1 Register Configuration......................................................................................... 21.2 Register Descriptions ........................................................................................................ 21.2.1 Standby Control Register (SBYCR) .................................................................... 21.2.2 System Clock Control Register (SCKCR) ........................................................... 21.2.3 Module Stop Control Register (MSTPCR) ..........................................................
Rev. 5.00 Sep 14, 2006 page xxvi of xxviii
743 744 745 745 747 748
21.3 Medium-Speed Mode........................................................................................................ 21.4 Sleep Mode ....................................................................................................................... 21.5 Module Stop Mode ........................................................................................................... 21.5.1 Module Stop Mode .............................................................................................. 21.5.2 Usage Notes ......................................................................................................... 21.6 Software Standby Mode.................................................................................................... 21.6.1 Software Standby Mode....................................................................................... 21.6.2 Clearing Software Standby Mode ........................................................................ 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 21.6.4 Software Standby Mode Application Example.................................................... 21.6.5 Usage Notes ......................................................................................................... 21.7 Hardware Standby Mode .................................................................................................. 21.7.1 Hardware Standby Mode ..................................................................................... 21.7.2 Hardware Standby Mode Timing......................................................................... 21.8 φ Clock Output Disabling Function ..................................................................................
748 749 750 750 752 753 753 753 754 755 756 756 756 757 758
Section 22 Electrical Characteristics.............................................................................. 759
22.1 Absolute Maximum Ratings ............................................................................................. 22.2 DC Characteristics ............................................................................................................ 22.3 AC Characteristics ............................................................................................................ 22.3.1 Clock Timing ....................................................................................................... 22.3.2 Control Signal Timing ......................................................................................... 22.3.3 Bus Timing .......................................................................................................... 22.3.4 DMAC Timing..................................................................................................... 22.3.5 Timing of On-Chip Supporting Modules............................................................. 22.4 A/D Conversion Characteristics........................................................................................ 22.5 D/A Convervion Characteristics ....................................................................................... 22.6 Usage Notes ...................................................................................................................... 759 760 765 766 768 770 782 786 791 792 792
Appendix A Instruction Set .............................................................................................. 793
A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .................................................................................................................. 793 Instruction Codes .............................................................................................................. 817 Operation Code Map......................................................................................................... 832 Number of States Required for Instruction Execution ...................................................... 836 Bus States During Instruction Execution .......................................................................... 848 Condition Code Modification ........................................................................................... 862
Appendix B Internal I/O Register ................................................................................... 868
B.1 B.2 Addresses .......................................................................................................................... 868 Functions........................................................................................................................... 878
Rev. 5.00 Sep 14, 2006 page xxvii of xxviii
Appendix C I/O Port Block Diagrams......................................................................... 1012
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 C.13 Port 1 Block Diagram ..................................................................................................... Port 2 Block Diagram ..................................................................................................... Port 3 Block Diagram ..................................................................................................... Port 4 Block Diagram ..................................................................................................... Port 5 Block Diagram ..................................................................................................... Port 6 Block Diagram ..................................................................................................... Port A Block Diagram..................................................................................................... Port B Block Diagram..................................................................................................... Port C Block Diagram..................................................................................................... Port D Block Diagram..................................................................................................... Port E Block Diagram ..................................................................................................... Port F Block Diagram ..................................................................................................... Port G Block Diagram..................................................................................................... 1012 1015 1019 1022 1023 1027 1033 1036 1037 1038 1039 1040 1048
Appendix D Pin States ..................................................................................................... 1051
D.1 Port States in Each Mode ................................................................................................ 1051
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ............................................................................................ 1056 Appendix F Product Code Lineup ............................................................................... 1057
Appendix G Package Dimensions ................................................................................ 1058
Rev. 5.00 Sep 14, 2006 page xxviii of xxviii
Section 1 Overview
Section 1 Overview
1.1 Overview
The H8S/2655 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. The on-chip ROM is either PROM (ZTAT*) or mask ROM, with a capacity of 128 or 64 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and single-chip mode or external expansion mode. The features of the H8S/2655 Group are shown in table 1.1. Note: * ZTAT is a registered trademark of Renesas Technology Corp.
Rev. 5.00 Sep 14, 2006 page 1 of 1060 REJ09B0331-0500
Section 1 Overview
Table 1.1
Item CPU
Overview
Specification • General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 16 × 16-bit register-register multiply: 16 × 16 + 42-bit multiply and accumulate: 32 ÷ 16-bit register-register divide: • Sixty-nine basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Multiply-and accumulate instruction Powerful bit-manipulation instructions • Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space 50 ns 200 ns 200 ns 1000 ns
Instruction set suitable for high-speed operation
Bus controller
• • • • • • • •
Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable Maximum 8-Mbyte DRAM or PSRAM directly connectable (or use of interval timer possible) External bus release function
Rev. 5.00 Sep 14, 2006 page 2 of 1060 REJ09B0331-0500
Section 1 Overview Item DMA controller (DMAC) Specification • • • • • • Data transfer controller (DTC) • • • • 16-bit timer-pulse unit (TPU) • • • Programmable pulse • generator (PPG) • • • 8-bit timer 2 channels • • • Watchdog timer Serial communication interface (SCI) 3 channels A/D converter • • • • • • • • • • Choice of short address mode or full address mode 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible Can be activated by internal interrupt Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels High-speed conversion: 2.2 µs minimum conversion time (at 20-MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger
Rev. 5.00 Sep 14, 2006 page 3 of 1060 REJ09B0331-0500
Section 1 Overview Item D/A converter I/O ports Memory Specification • • • • • Resolution: 8 bits Output: 2 channels 87 I/O pins, 8 input-only pins PROM or mask ROM High-speed static RAM
ROM 128 kbytes 64 kbytes RAM 4 kbytes 4 kbytes
Product Name H8S/2655 H8S/2653
Interrupt controller
• • •
Nine external interrupt pins (NMI, IRQ0 to IRQ7) 52 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode
External Data Bus Description On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode Advanced On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode On-Chip ROM Disabled Enabled Enabled Disabled Disabled Enabled Enabled Initial Value 8 bits 8 bits — 16 bits 8 bits 8 bits — Maximum Value 16 bits 16 bits — 16 bits 16 bits 16 bits —
Power-down state
• • • • •
Operating modes
Seven MCU operating modes
CPU Operating Mode Normal
Mode 1 2 3 4 5 6 7
Rev. 5.00 Sep 14, 2006 page 4 of 1060 REJ09B0331-0500
Section 1 Overview Item Clock pulse generator Packages Product lineup Specification • • • Built-in duty correction circuit 120-pin plastic TQFP (TFP-120) 128-pin plastic QFP (FP-128) Model Name 5 V Version (VCC = 5 V ±10%) HD6472655TE HD6472655F HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F Low-Voltage Version (VCC = 2.7 to 5.5 V) HD6472655VTE HD6472655VF HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F Mask ROM ROM PROM Packages TFP-120 FP-128 TFP-120 FP-128 TFP-120 FP-128
Legend: Marked (***) is ROM code.
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Section 1 Overview
1.2
Block Diagram
Figure 1.1 shows an internal block diagram of the H8S/2655 Group.
PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0
VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS
Port D
Port E
Internal data bus
H8S/2600 CPU
Internal address bus
Bus controller
MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI
Port A
Clock pulse generator
PA7 / A23 / IRQ7 PA6 / A22 / IRQ6 PA5 / A21 / IRQ5 PA4 / A20 / IRQ4 PA3 / A19 PA2 / A18 PA1 / A17 PA0 / A16 PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 P50 /TxD2 P51 /RxD2 P52 /SCK2 P53 / ADTRG
Interrupt controller PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 / LCAS / WAIT / BREQO PF1 / BACK PF0 / BREQ PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS / OE P67 / CS7 / IRQ3 P66 / CS6 / IRQ2 P65 / IRQ1 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 P60 / DREQ0 / CS4
DTC
Port B
Peripheral address bus Peripheral data bus
ROM
Port F
DMAC
Port C
WDT RAM
Port G
8-bit timer
SCI TPU D/A converter
Port 6
Port 3
PPG
A/D converter
Port 5
Port 1
P10 / PO8 /TIOCA0 / DACK0 P11 / PO9 /TIOCB0 / DACK1 P12 / PO10 / TIOCC0 / TCLKA P13 / PO11 / TIOCD0 / TCLKB P14 / PO12 / TIOCA1 P15 / PO13 / TIOCB1 / TCLKC P16 / PO14 / TIOCA2 P17 / PO15 / TIOCB2 / TCLKD
Port 2
Vref AVCC AVSS
Port 4
Figure 1.1 Block Diagram
Rev. 5.00 Sep 14, 2006 page 6 of 1060 REJ09B0331-0500
P20 / PO0 /TIOCA3 P21 / PO1 /TIOCB3 P22 / PO2 /TIOCC3 / TMRI0 P23 / PO3 /TIOCD3 / TMCI0 P24 / PO4 /TIOCA4 / TMRI1 P25 / PO5 /TIOCB4 / TMCI1 P26 / PO6 /TIOCA5 / TMO0 P27 / PO7 /TIOCB5 / TMO1
P47 / AN7 / DA1 P46 / AN6 / DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0
Section 1 Overview
1.3
1.3.1
Pin Description
Pin Arrangement
Figures 1.2 and 1.3 show the pin arrangement of the H8S/2655 Group.
PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS / OE MD2 MD1 MD0 P10 /PO8 /TIOCA0/ DACK0 P11 /PO9 /TIOCB0/ DACK1 P12 /PO10 /TIOCC0/TCLKA P13 /PO11 /TIOCD0/TCLKB P14 /PO12 /TIOCA1 P15 /PO13 /TIOCB1/TCLKC P16 /PO14 /TIOCA2 P17 /PO15 /TIOCB2/TCLKD VSS AVSS P47 /AN7 /DA1 P46 /AN6 /DA0 P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40 /AN0 Vref AVCC P53 / ADTRG P52 /SCK2 P65 / IRQ1 P64 / IRQ0 VCC PE0 /D0 PE1 /D1 PE2 /D2 PE3 /D3 VSS PE4 /D4 PE5 /D5 PE6 /D6 PE7 /D7 PD0 /D8 PD1 /D9 PD2 /D10 PD3 /D11 VSS PD4 /D12 PD5 /D13 PD6 /D14 PD7 /D15 VCC P30 /TxD0 P31 /TxD1 P32 /RxD0 P33 /RxD1 P34 /SCK0 P35 /SCK1 VSS P60 / DREQ0 / CS4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VCC PC0 / A0 PC1 / A1 PC2 / A2 PC3 / A3 VSS PC4 / A4 PC5 / A5 PC6 / A6 PC7 / A7 PB0 / A8 PB1 / A9 PB2 / A10 PB3 / A11 VSS PB4 / A12 PB5 / A13 PB6 / A14 PB7 / A15 PA0 / A16 PA1 /A17 PA2 / A18 PA3 / A19 VSS PA4 / A20 / IRQ4 PA5 / A21 / IRQ5 PA6 / A22 / IRQ6 PA7 / A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P51 / RxD2 P50 / TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 / PO0 / TIOCA3 P21 / PO1 / TIOCB3 P22 / PO2 / TIOCC3 / TMRI0 P23 / PO3 / TIOCD3 / TMCI0 P24 / PO4 / TIOCA4 / TMRI1 P25 / PO5 / TIOCB4 / TMCI1 P26 / PO6 / TIOCA5 / TMO0 P27 / PO7 / TIOCB5 / TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5
Figure 1.2 Pin Arrangement (TFP-120: Top View)
Rev. 5.00 Sep 14, 2006 page 7 of 1060 REJ09B0331-0500
Section 1 Overview
Rev. 5.00 Sep 14, 2006 page 8 of 1060 REJ09B0331-0500
VCC PE0 / D0 PE1 / D1 PE2 / D2 PE3 / D3 VSS PE4 / D4 PE5 / D5 PE6 / D6 PE7 / D7 PD0 / D8 PD1 / D9 PD2 / D10 PD3 / D11 VSS PD4 / D12 PD5 / D13 PD6 / D14 PD7 / D15 VCC P30 / TxD0 P31 / TxD1 P32 / RxD0 P33 / RxD1 P34 / SCK0 P35 / SCK1
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PG3 / CS1 PG4 / CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
PG2 / CS2 PG1 / CS3 PG0 / CAS / OE MD2 MD1 MD0 P10 / PO8 / TIOCA0 / DACK0 P11 / PO9 / TIOCB0 / DACK1 P12 / PO10 / TIOCC0 / TCLKA P13 / PO11 / TIOCD0 / TCLKB P14 / PO12 / TIOCA1 P15 / PO13 / TIOCB1 / TCLKC P16 / PO14 / TIOCA2 P17 / PO15 / TIOCB2 / TCLKD VSS AVSS P47 / AN7 / DA1 P46 / AN6 / DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Vref AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P53 / ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3/TMRI0 P23 /PO3 /TIOCD3/TMCI0 P24 /PO4 /TIOCA4/TMRI1 P25 /PO5 /TIOCB4/TMCI1 P26 /PO6 /TIOCA5/TMO0 P27 /PO7 /TIOCB5/TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 VSS VSS P60 / DREQ0 / CS4 VSS
Figure 1.3 Pin Arrangement (FP-128: Top View)
Section 1 Overview
1.3.2
Pin Functions in Each Operating Mode
Table 1.2 shows the pin functions of the H8S/2655 Group in each of the operating modes. Table 1.2
Pin No. TFP-120 FP-128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 1 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 PA0 PA1 PA2 PA3 VSS PA4/IRQ4 PA5/IRQ5 Mode 2 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0 PA1 PA2 PA3 VSS PA4/IRQ4 PA5/IRQ5 Mode 3 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 VSS PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 VSS PA4/IRQ4 PA5/IRQ5
Pin Functions in Each Operating Mode
Pin Name Mode 4 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA5/A21/ IRQ5 Mode 5 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA5/A21/ IRQ5 Mode 6 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/ IRQ4 PA5/A21/ IRQ5 Mode 7 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 VSS PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 VSS PA4/IRQ4 PA5/IRQ5 PROM Mode VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 OE A10 A11 VSS A12 A13 A14 A15 A16 VCC VCC NC VSS NC NC
Rev. 5.00 Sep 14, 2006 page 9 of 1060 REJ09B0331-0500
Section 1 Overview
Pin No. TFP-120 FP-128 27 28 29 30 — — 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Mode 1 PA6/IRQ6 PA7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 Mode 2 PA6/IRQ6 PA7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 Mode 3 PA6/IRQ6 PA7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0 PE1 PE2 PE3 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 Pin Name Mode 4 PA6/A22/ IRQ6 PA7/A23/ IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 Mode 5 PA6/A22/ IRQ6 PA7/A23/ IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 Mode 6 PA6/A22/ IRQ6 PA7/A23/ IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 Mode 7 PA6/IRQ6 PA7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0 PE1 PE2 PE3 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 PROM Mode NC NC NC NC VSS VSS NC NC VCC NC NC NC NC VSS NC NC NC NC D0 D1 D2 D3 VSS D4 D5 D6 D7 VCC NC NC
Rev. 5.00 Sep 14, 2006 page 10 of 1060 REJ09B0331-0500
Section 1 Overview
Pin No. TFP-120 FP-128 55 56 57 58 59 60 61 62 63 64 65 66 Mode 1 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Mode 2 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND 0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Mode 3 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND 0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Pin Name Mode 4 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND 0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Mode 5 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Mode 6 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 Mode 7 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI1 P24/PO4/ TIOCA4/ TMRI1 P23/PO3/ TIOCD3/ TMCI0 P22/PO2/ TIOCC3/ TMRI1 P21/PO1/ TIOCB3 PROM Mode NC NC NC NC VSS NC
— — 61
67 68 69
VSS VSS NC
62 63 64
70 71 72
NC NC NC
65
73
NC
66
74
NC
67
75
NC
68
76
NC
69
77
NC
70
78
NC
Rev. 5.00 Sep 14, 2006 page 11 of 1060 REJ09B0331-0500
Section 1 Overview
Pin No. TFP-120 FP-128 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Mode 1 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC AS RD HWR LWR Mode 2 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC AS RD HWR LWR Mode 3 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC PF6 PF5 PF4 PF3 Pin Name Mode 4 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC AS RD HWR LWR Mode 5 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC AS RD HWR LWR Mode 6 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC AS RD HWR LWR Mode 7 P20/PO0/ TIOCA3 RES NMI STBY VCC XTAL EXTAL VSS PF7/φ VCC PF6 PF5 PF4 PF3 PROM Mode NC
WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC VPP A9 VSS VCC NC NC VSS NC VCC NC NC NC NC CE
PF2/WAIT/ PF2/WAIT/ PF2 BREQO BREQO PF1/BACK PF1/BACK PF1 PF0/BREQ PF0/BREQ PF0 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4
PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ PF2 WAIT/ WAIT/ WAIT/ BREQO BREQO BREQO PF1/BACK PF1/BACK PF1/BACK PF1 PF0/BREQ PF0/BREQ PF0/BREQ PF0 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4
87 88 89 90 — — 91 92 93 94 95 96 97 98 99
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
PGM NC NC NC VSS VSS NC NC VCC VCC NC NC NC NC NC
Rev. 5.00 Sep 14, 2006 page 12 of 1060 REJ09B0331-0500
Section 1 Overview
Pin No. TFP-120 FP-128 100 101 102 103 104 105 110 111 112 113 114 115 Mode 1 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4/CS0 VSS NC Mode 2 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4/CS0 VSS NC Mode 3 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4 VSS NC Pin Name Mode 4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 Mode 5 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 Mode 6 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 Mode 7 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PROM Mode NC NC NC VSS VSS NC
106 107
116 117
NC NC
108 109
118 119
NC NC
110
120
NC
111
121
NC
112
122
NC
113 114 115 116 117 118 119 120 — —
123 124 125 126 127 128 1 2 3 4
VSS VSS VSS NC NC NC NC NC VSS NC
PG0/CAS/ PG0/CAS/ PG0/CAS/ PG0 OE OE OE PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC PG1 PG2 PG3 PG4 VSS NC
Note: NC pins should be connected to VSS or left open. Rev. 5.00 Sep 14, 2006 page 13 of 1060 REJ09B0331-0500
Section 1 Overview
1.3.3
Pin Functions
Table 1.3 outlines the pin functions of the H8S/2655 Group. Table 1.3 Pin Functions
Pin No. Type Power supply Symbol VCC TFP-120 1, 33, 52, 76, 81 6, 15, 24, 38, 47, 59, 79, 104 FP-128 5, 39, 58, 84, 89 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 85 I/O Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V).
VSS
Input
Clock
XTAL
77
Input
Connects to a crystal oscillator. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input.
EXTAL
78
86
Input
φ
80
88
Output System clock: Supplies the system clock to an external device.
Rev. 5.00 Sep 14, 2006 page 14 of 1060 REJ09B0331-0500
Section 1 Overview Pin No. Type Operating mode control Symbol MD2 to MD0 TFP-120 115 to 113 FP-128 125 to 123 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2655 Group is operating.
MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode — Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
System control
RES
73
81
Input
Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2655 Group.
STBY
75
83
Input
BREQ
88
96
Input
BREQO
86
94
Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master.
BACK
87
95
Rev. 5.00 Sep 14, 2006 page 15 of 1060 REJ09B0331-0500
Section 1 Overview Pin No. Type Interrupts Symbol NMI TFP-120 74 FP-128 82 I/O Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt.
IRQ7 to IRQ0 Address bus A23 to A0
28 to 25, 29 to 32 28 to 25, 23 to 16, 14 to 7, 5 to 2 51 to 48, 46 to 39, 37 to 34
32 to 29, 33, 34, 37, 38 32 to 29, 27 to 20, 18 to 11, 9 to 6 57 to 54, 52 to 45, 43 to 40
Input
Output Address bus: These pins output an address.
Data bus
D15 to D0 CS7 to CS0
I/O
Data bus: These pins constitute a bidirectional data bus.
Bus control
29, 30, 33, 34, Output Chip select: Signals for selecting 61, 60, 69, 66, areas 7 to 0. 117 to 120 127, 128, 1, 2 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write/write enable/upper write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2CAS type DRAM write enable signal. The 2WE type DRAM upper write enable signal.
AS
RD
83
91
HWR
84
92
Rev. 5.00 Sep 14, 2006 page 16 of 1060 REJ09B0331-0500
Section 1 Overview Pin No. Type Bus control Symbol LWR TFP-120 85 FP-128 93 I/O Name and Function
Output Low write/lower column address strobe/lower write enable: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. The 2CAS type (LCASS = 1) DRAM lower column address strobe signal. The 2WE type DRAM lower write enable signal. Output Upper column address strobe/ column address strobe/output enable/refresh: The 2CAS type DRAM upper column address strobe signal. The 2WE type DRAM column address strobe signal. The PSRAM output enable signal. Output Lower column address strobe: The 2-CAS type (LCASS = 0) DRAM lower column address strobe signal Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. DMA request 1 and 0: These pins request DMAC activation.
CAS/ OE
116
126
LCAS
86
94
WAIT
86
94
DMA controller (DMAC)
DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0
62, 60 63, 61
70, 66 71, 69
Input
Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins.
111, 112
121, 122
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Section 1 Overview Pin No. Type 16-bit timerpulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TFP-120 FP-128 I/O Name and Function Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins.
105, 107, 115, 117, Input 109, 110 119, 120 112 to 109 122 to 119 I/O
108, 107
118, 117
I/O
TIOCA2, TIOCB2
106, 105
116, 115
I/O
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
71 to 68
79 to 76
I/O
67, 66
75, 74
I/O
TIOCA5, TIOCB5
65, 64
73, 72
I/O
Programmable PO15 to pulse generator PO0 (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
105 to 112, 64 to 71 65, 64 68, 66
115 to 122, 72 to 79 73, 72 76, 74
Output Pulse output 15 to 0: Pulse output pins. Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins.
69, 67
77, 75
Input
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Section 1 Overview Pin No. Type Watchdog timer (WDT) Serial communication interface (SCI) Smart Card interface Symbol WDTOVF TFP-120 72 FP-128 80 I/O Name and Function
Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. Serial clock (channel 0, 1, 2): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion.
TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1 SCK0
89, 54, 53 90, 56, 55 91, 58 57 102 to 95 92
97, 60, 59 98, 62, 61 101, 64, 63 112 to 105 102
I/O
A/D converter
AN7 to AN0 ADTRG
Input Input
D/A converter A/D converter and D/A converter
DA1, DA0 AVCC
102, 101 93
112, 111 103
Output Analog output: D/A converter analog output pins. Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V).
AVSS
103
113
Input
Vref
94
104
Input
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Section 1 Overview Pin No. Type I/O ports Symbol P17 to P10 TFP-120 105 to 112 FP-128 115 to 122 I/O I/O Name and Function Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR).
P27 to P20
64 to 71
72 to 79
I/O
P35 to P30
58 to 53
64 to 59
I/O
P47 to P40 P53 to P50
102 to 95 92 to 89
112 to 105
Input
102, 101, I/O 98, 97
P67 to P60
29 to 32, 63 to 60
33, 34, 37, 38, 71 to 69, 66 32 to 29, 27 to 24
I/O
PA7 to PA0
28 to 25, 23 to 20
I/O
PB7 to PB0
19 to 16, 14 to 11
23 to 20, 18 to 15
I/O
PC7 to PC0
10 to 7, 5 to 2
14 to 11, 9 to 6
I/O
PD7 to PD0
51 to 48, 46 to 43
57 to 54, 52 to 49
I/O
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Section 1 Overview Pin No. Type I/O ports Symbol PE7 to PE0 TFP-120 42 to 39, 37 to 34 FP-128 48 to 45, 43 to 40 I/O I/O Name and Function Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR).
PF7 to PF0
80, 82 to 88
88, 90 to 96
I/O
PG4 to PG0
120 to 116
2, 1, 128 to 126
I/O
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
2.1 Overview
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features
The H8S/2600 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction • Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] • 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally)
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Section 2 CPU
• High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8 × 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 × 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences from H8/300 CPU 20 MHz 150 ns 600 ns 200 ns 1000 ns 8/16/32-bit register-register add/subtract: 50 ns
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added.
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Section 2 CPU
• Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register One 8-bit and two 32-bit control registers have been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions execute twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Maximum 64 kbytes, program and data areas combined
Normal mode
CPU operating modes
Advanced mode
Maximum 16-Mbytes for program and data areas combined
Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.
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Section 2 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Power-on reset exception vector Manual reset exception vector
(Reserved for system use)
Exception vector table
Exception vector 1 Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.
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Section 2 CPU
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
SP
PC (16 bits)
SP *2 (SP )
EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used.
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Section 2 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling.
H'00000000
Reserved Power-on reset exception vector
H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved for system use)
H'00000010
Reserved Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table.
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Section 2 CPU
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
SP SP Reserved PC (24 bits) *2 (SP )
EXR*1 Reserved*1 *3 CCR PC (24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
Figure 2.5 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be used by the H8S/2655 Group
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.6 Memory Map
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Section 2 CPU
2.4
2.4.1
Register Configuration
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers.
General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: Sign extension MACL 0 41 MACH 32 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit
H: U: N: Z: V: C: MAC:
Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register
Figure 2.7 CPU Registers
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Section 2 CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently.
• Address registers • 32-bit registers
• 16-bit registers E registers (extended registers) (E0 to E7)
• 8-bit registers
ER registers (ER0 to ER7) R registers (R0 to R7)
RH registers (R0H to R7H)
RL registers (R0L to R7L)
Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack.
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.9 Stack 2.4.3 Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller.
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Section 2 CPU
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions.
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Section 2 CPU
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.4 Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.10 shows the data formats in general registers.
Data Type Register Number Data Format
1-bit data
RnH
7 0 76543210
Don’t care
1-bit data
RnL
Don’t care
7 0 76543210
4-bit BCD data
RnH
7 Upper
43 Lower
0 Don’t care
4-bit BCD data
RnL
Don’t care
7 Upper
43 Lower
0
Byte data
RnH
7 MSB
0 Don’t care LSB 7
Don’t care
Byte data
RnL
0 LSB
MSB
Figure 2.10 General Register Data Formats
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Section 2 CPU
Data Type
Register Number
Data Format
Word data
Rn
15 MSB
0 LSB
Word data 15 MSB Longword data 31 MSB
En 0 LSB ERn 16 15 En Rn 0 LSB
Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit
Figure 2.10 General Register Data Formats (cont)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format
Byte data
Address L MSB
LSB
Word data
Address 2M MSB Address 2M + 1 LSB
Longword data
Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB
Figure 2.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.
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Section 2 CPU
2.6
2.6.1
Instruction Set
Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV 1 1 POP* , PUSH* LDM, STM MOVFPE, MOVTPE Size BWL WL L B BWL B BWL L BW WL B — BWL B — — 4 8 14 5 9 1 23 Types 5
Arithmetic operations
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS MAC, LDMAC, STMAC, CLRMAC
Logic operations Shift Bit manipulation Branch System control Block data transfer
AND, OR, XOR, NOT BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS EEPMOV
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions.
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Section 2 CPU
2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn)
@(d:8,PC)
Function
Instruction @ERn
@(d:16,PC)
@@aa:8 — — — — — — — — — — — — — — — — — — — — — —
@aa:16
@aa:24
@aa:32
@aa:8
#xx
Rn
Data transfer
MOV POP, PUSH LDM, STM MOVEPE, MOVTPE
BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — — — — — — — — B — — — — — — B — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
B — — — — — — — — — — — — — — — — — — — — B
BWL — — B — — — — — — — — — — — — — — — — — B
— — — — — — — — — — — — — — — — — — — — — —
BWL — — — — — — — — — — — — — — — — — — — — B
— — — — — — — — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — — — — — — — —
— WL L — — — — — — — — — — — — —
Arithmetic operations
ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS MAC CLRMAC LDMAC, STMAC
BWL BWL WL B — — — — — — — — — — — BWL B L BWL B BW BW BWL WL — — — L
— — — — —
Logic operations
AND, OR, XOR NOT
BWL BWL — — — BWL BWL B
Shift Bit manipulation
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Section 2 CPU
Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn)
@(d:8,PC)
Function
Instruction @ERn #xx
@(d:16,PC)
@@aa:8 — — — — — — — — — —
@aa:16
@aa:24
@aa:32
@aa:8
Rn
Branch
Bcc, BSR JMP, JSR RTS
— — — — — — B — B — —
— — — — — — B B — — —
— — — — — — W W — — —
— — — — — — W W — — —
— — — — — — W W — — —
— — — — — — W W — — —
— — — — — — — — — — —
— — — — — — W W — — —
—
— — — — — — — — — — — — — — — — — — — — — —
— —
— — — — — — — — —
— — — — W W — — —
System control
TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP
— — —
Block data transfer
BW
Legend: B: Byte W: Word L: Longword
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Section 2 CPU
2.6.3
Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Type Data transfer
Instructions Classified by Function
Instruction MOV Size* B/W/L Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2655 Group. Cannot be used in the H8S/2655 Group. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
LDM STM Note: *
L L
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU Type Arithmetic operations Instruction ADD SUB Size* B/W/L Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
ADDX SUBX
B
INC DEC
B/W/L
ADDS SUBS DAA DAS
L
B
MULXU
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU Type Arithmetic operations Instruction DIVXS Size* B/W Function Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two’s complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd – 0, 1 → ( of @Erd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating 0 → MAC Clears the multiply-accumulate register to zero. Rs → MAC, MAC → Rd Transfers data between a general register and a multiply-accumulate register.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS
B
MAC
—
CLRMAC LDMAC STMAC Note: *
— L
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU Type Logic operations Instruction AND Size* B/W/L Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one’s complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU Type Bitmanipulation instructions Instruction BSET Size* B Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BIOR
B
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Section 2 CPU
Type Bitmanipulation instructions
Instruction BXOR
Size* B
Function C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
*
Size refers to the operand size. B: Byte
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Section 2 CPU Type Branch instructions Instruction Bcc Size* — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS — — — — Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z∨(N ⊕ V) = 0 Z∨(N ⊕ V) = 1
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
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Section 2 CPU Type System control instructions Instruction TRAPA RTE SLEEP LDC Size* — — — B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter.
STC
B/W
ANDC
B
ORC
B
XORC
B
NOP Note: *
—
Size refers to the operand size. B: Byte W: Word
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Section 2 CPU Type Block data transfer instruction Instruction EEPMOV.B Size* — Function if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
—
2.6.4
Basic Instruction Formats
The H8S/2655 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. Figure 2.12 shows examples of instruction formats.
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Section 2 CPU
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc.
Figure 2.12 Instruction Formats (Examples)
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Section 2 CPU
2.7
2.7.1
Addressing Modes and Effective Address Calculation
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4
No. 1 2 3 4 5 6 7 8
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
(1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges.
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Section 2 CPU
Table 2.5
Absolute Address Access Ranges
Normal Mode 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
Absolute Address Data address
Program instruction address
24 bits (@aa:24)
(6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
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Section 2 CPU
Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling.
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
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No. Effective Address Calculation 1 op 2 31 31 Don’t care 24 23 General register contents op r 0 Register indirect (@ERn) rm rn Operand is general register contents. Register direct (Rn)
Table 2.6
Section 2 CPU
Addressing Mode and Instruction Format
Effective Address (EA)
0
3 31 General register contents 31 op disp 31 Sign extension disp 0 r 0
Register indirect with displacement @(d:16, ERn) or @(d:32, ERn)
24 23 Don’t care
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0 4 31 General register contents op r 1, 2, or 4 • Register indirect with pre-decrement @–ERn 31 General register contents 31 op r Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 24 23 Don’t care 0 0 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 0 31 24 23 Don’t care 0
Effective Address Calculation
No. Effective Address Calculation 5 @aa:8 31 24 23 H'FFFF abs
Don’t care
Addressing Mode and Instruction Format Absolute address 87
Effective Address (EA)
0
op
@aa:16 31 op abs
Don’t care extension
16 15 24 23 Sign
0
@aa:24 op abs
31
24 23
Don’t care
0
@aa:32 op abs 31 24 23
Don’t care
0
6 op IMM
Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data.
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No. Effective Address Calculation 23 PC contents @(d:8, PC)/@(d:16, PC) 0 7 Program-counter relative
Section 2 CPU
Addressing Mode and Instruction Format
Effective Address (EA)
op 23 Sign extension disp 31 24 23
Don’t care
disp 0
0
8 Memory indirect @@aa:8 • Normal mode op 31 H'000000 87 abs abs 0
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31 24 23
Don’t care
16 15 H'00
0
15 Memory contents • Advanced mode op 31 H'000000 31 Memory contents abs 87 abs
0
0
0
31
24 23
Don’t care
0
Section 2 CPU
2.8
2.8.1
Processing States
Overview
The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions.
Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode
Power-down state CPU operation is stopped to conserve power.*
Software standby mode Hardware standby mode
Note: * The power-down state also includes a medium-speed mode, module stop mode etc.
Figure 2.14 Processing States
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Section 2 CPU
End of bus request
Bus request
Program execution state
End of bus request
Bus request
Bus-released state
End of exception handling
SLEEP instruction with SSBY = 1
SLEEP instruction with SSBY = 0
Request for exception handling
Sleep mode
Interrupt request
Exception-handling state External interrupt RES = high Software standby mode
Reset state*1
STBY = high, RES = low
Hardware standby mode*2 Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.15 State Transitions 2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13, Watchdog Timer.
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2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7
Priority High
Exception Handling Types and Priority
Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 3 executed*
Trace
End of instruction execution or end of exception-handling 1 sequence* End of instruction execution or end of exception-handling 2 sequence* When TRAPA instruction is executed
Interrupt
Trap instruction Low
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state.
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Section 2 CPU
(2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control modes 2 and 3. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control modes 0 and 1, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends.
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Section 2 CPU
Normal mode
SP SP CCR CCR* PC (16 bits)
EXR Reserved* CCR CCR* PC (16 bits)
(a) Interrupt control modes 0 and 1
(b) Interrupt control modes 2 and 3
Advanced mode
SP SP CCR PC (24 bits)
EXR Reserved* CCR PC (24 bits)
(c) Interrupt control modes 0 and 1 Note: * Ignored when returning.
(d) Interrupt control modes 2 and 3
Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
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Section 2 CPU
2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are the direct memory access controller (DMAC) and data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes. (1) Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and onchip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained.
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Section 2 CPU
2.9
2.9.1
Basic Timing
Overview
The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states.
Bus cycle T1 φ Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address
Read access
Figure 2.17 On-Chip Memory Access Cycle
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Section 2 CPU
Bus cycle T1 φ
Address bus AS RD HWR, LWR Data bus
Unchanged High High High High-impedance state
Figure 2.18 Pin States during On-Chip Memory Access
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Section 2 CPU
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Bus cycle T1 T2
φ
Internal address bus
Address
Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data
Read data
Figure 2.19 On-Chip Supporting Module Access Cycle
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Section 2 CPU
Bus cycle T1 T2
φ Unchanged
Address bus
AS RD HWR, LWR
High
High
High
Data bus
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller.
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
3.1.1
Overview
Operating Mode Selection
The H8S/2655 Group has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection
External Data Bus On-Chip ROM — Disabled Initial Width — 8 bits Max. Width — 16 bits
MCU CPU Operating Operating MD2 MD1 MD0 Mode Description Mode 0 1 0 0 0 1 — Normal — On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Advanced On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode
2
1
0
Enabled
8 bits
16 bits
3 4 5 6 1 1 0
1 0 1 0
— Disabled 16 bits 8 bits Enabled 8 bits
— 16 bits 16 bits 16 bits
7
1
—
—
The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2655 Group actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices.
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Section 3 MCU Operating Modes
The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2655 Group can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration
The H8S/2655 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2655 Group. Table 3.2 summarizes these registers. Table 3.2
Name Mode control register System control register Note: *
MCU Registers
Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FF3B H'FF39
Lower 16 bits of the address.
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Section 3 MCU Operating Modes
3.2
3.2.1
Bit
Register Descriptions
Mode Control Register (MDCR)
: 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R
Initial value : R/W :
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2655 Group. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 3.2.2
Bit
System Control Register (SYSCR)
: 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 — 1 — 0 — 0 RAME 1 R/W
Initial value : R/W :
Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction.
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Section 3 MCU Operating Modes Bit 7 MACS 0 1 Description Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction (Initial value)
Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 1 2 3
Description Control of interrupts by I bit (Initial value)
Control of interrupts by I bit, U bit, and ICR Control of interrupts by I2 to I0 bits and IPR Control of interrupts by I, UI, and I2 to I0 bits, and ICR and IPR
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value)
Bits 2 and 1—Reserved: Read-only bits, always read as 0. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
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Section 3 MCU Operating Modes
3.3
3.3.1
Operating Mode Descriptions
Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.2 Mode 2
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set. immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.4 Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.
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Section 3 MCU Operating Modes
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.5 Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. 3.3.7 Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports.
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Section 3 MCU Operating Modes
3.4
Pin Functions in Each Operating Mode
The pin functions of ports A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3
Port Port A Port B Port C Port D Port E Port F PF7 PF6 to PF3 PF2 to PF0 PA7 to PA5 PA4 to PA0 A A D P*/D P*/C* C P*/C P*/A P*/A D P*/D P*/C* C P*/C P P P P P*/C P
Pin Functions in Each Mode
Mode 1 P Mode 2 P Mode 3 P Mode 4 P*/A A A A D P*/D P*/C* C P*/C Mode 5 P*/A A A A D P*/D P*/C* C P*/C P*/A P*/A D P*/D P*/C* C P*/C P P P P P*/C P Mode 6 P*/A Mode 7 P
Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Note: * After reset
3.5
Memory Map in Each Operating Mode
Figure 3.1 shows a memory map for each of the operating modes. The address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 Mbytes in modes 4 to 7 (advanced modes). The on-chip ROM of H8S/2655 contains 128 kbytes, but only 56 kbytes are available in modes 2 and 3 (normal modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller.
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Section 3 MCU Operating Modes
Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000
Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000
Mode 3 (normal single-chip mode)
H'0000
On-chip ROM External address space
On-chip ROM
H'DFFF H'E000 H'EC00 On-chip RAM* H'FBFF H'FC00 External address H'FE3F space Internal I/O registers H'FF08 External address
space
H'DFFF External address space H'EC00 On-chip RAM* On-chip RAM H'FBFF
External address space
H'EC00
H'FBFF H'FC00 H'FE3F H'FF08
Internal I/O registers
External address space
H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
External address space
H'00FFFF H'010000 On-chip ROM/ external address space/reserved area*1
H'00FFFF H'010000 On-chip ROM/ reserved area*2
H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address H'FFFE3F space Internal I/O registers H'FFFF08 External address
space
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address H'FFFE3F space Internal I/O registers H'FFFF08 External address
space
H'01FFFF
H'FFEC00 On-chip RAM H'FFFBFF H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM in the H8S/2655, and a reserved area in the H8S/2653. 2. In the H8S/2655, this area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when the EAE bit is cleared to 0. In the H8S/2653, it is a reserved area. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode (cont)
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Section 3 MCU Operating Modes
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
4.1.1
Overview
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. See appendix D.1, Port States in Each Mode. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset
1 Trace*
Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been 2 issued*
3
Interrupt
Low
Trap instruction (TRAPA)*
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state.
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Section 4 Exception Handling
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses.
Reset Trace Exception sources Interrupts
Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 52 interrupt sources in on-chip supporting modules
Trap instruction
Figure 4.1 Exception Sources In modes 6 and 7 in the H8S/2655, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte area comprising addresses H'000000 to H'01FFFF to be used.
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Section 4 Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
1
Exception Source Power-on reset Manual reset Reserved for system use
Vector Number 0 1 2 3 4
Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00B6 to H'00B7
Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'016C to H'016F
Trace Reserved for system use External interrupt NMI Trap instruction (4 sources)
5 6 7 8 9 10 11
Reserved for system use
12 13 14 15
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
16 17 18 19 20 21 22 23 24 91
2 Internal interrupt*
Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
4.2
4.2.1
Reset
Overview
A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2655 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2655 Group can also be reset by overflow of the watchdog timer. For details see section 13, Watchdog Timer. 4.2.2 Reset Types
A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4.3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4.3 Reset Types
Reset Transition Conditions Type Power-on reset Manual reset NMI High Low RES Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports
A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset.
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Section 4 Exception Handling
4.2.3
Reset Sequence
The H8S/2655 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2655 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2655 Group during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2655 Group starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence.
Vector Internal Prefetch of first program fetch processing instruction
φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) (2) (1) (3)
High
(4)
Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction
Figure 4.2 Reset Sequence (Modes 2 and 3)
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Section 4 Exception Handling
Vector fetch
Internal Prefetch of first processing program instruction * *
φ RES Address bus RD HWR, LWR D15 to D0
*
(1)
(3)
(5)
High (2) (4) (6)
(1) (3) (2) (4) (5) (6)
Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction
Note: * 3 program wait states are inserted.
Figure 4.3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP).
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Section 4 Exception Handling
4.3
Traces
Traces are enabled in interrupt control modes 2 and 3. Trace mode is not activated in interrupt control modes 0 and 1, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.4 Status of CCR and EXR after Trace Exception Handling
CCR I UI I2 to I0 EXR T
Interrupt Control Mode 0 1 2 3 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.
Trace exception handling cannot be used. 1 1 — 1 — — 0 0
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Section 4 Exception Handling
4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt, and is always accepted. Interrupts are controlled by the interrupt controller. The interrupt controller has four interrupt control modes and can assign interrupts other than NMI to either three or eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller.
External interrupts Interrupts
NMI (1) IRQ7 to IRQ0 (8) WDT*1 (1) Refresh timer*2 (1) TPU (26) 8-bit timer (6) SCI (12) DTC (1) DMAC (4) A/D converter (1)
Internal interrupts
Notes:
Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match.
Figure 4.4 Interrupt Sources and Number of Interrupts
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Section 4 Exception Handling
4.5
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling
CCR I 1 1 1 1 UI — 1 — 1 I2 to I0 — — — — EXR T — — 0 0
Interrupt Control Mode 0 1 2 3 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.
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Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
SP SP CCR CCR* PC (16 bits)
EXR Reserved* CCR CCR* PC (16 bits)
(a) Interrupt control modes 0 and 1 Note: * Ignored on return.
(b) Interrupt control modes 2 and 3
Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes)
SP SP CCR PC (24 bits)
EXR Reserved* CCR PC (24 bits)
(a) Interrupt control modes 0 and 1 Note: * Ignored on return.
(b) Interrupt control modes 2 and 3
Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes)
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Section 4 Exception Handling
4.7
Notes on Use of the Stack
When accessing word data or longword data, the H8S/2655 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd.
CCR SP PC
SP
R1L PC
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF
SP
TRAPA instruction executed
MOV.B R1L, @–ER7
SP set to H'FFFEFF
Data saved above SP
Contents of CCR lost
Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.6 Operation when SP Value Is Odd
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Section 4 Exception Handling
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
5.1.1
Overview
Features
The H8S/2655 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Four interrupt control modes Any of four interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI. • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC and DMAC control DTC and DMAC activation is performed by means of interrupts.
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Section 5 Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI I2 to I0 Interrupt request Vector number
CPU
Internal interrupt request WOVI to TEI
CCR EXR
ICR Interrupt controller
IPR
Legend: ISCR : IRQ sense control register : IRQ enable register IER : IRQ status register ISR : Interrupt priority register IPR : Interrupt control register ICR SYSCR : System control register
Figure 5.1 Block Diagram of Interrupt Controller 5.1.3 Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
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Section 5 Interrupt Controller
Table 5.1
Name
Interrupt Controller Pins
Symbol NMI IRQ7 to IRQ0 I/O Input Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
Nonmaskable interrupt External interrupt requests 7 to 0
5.1.4
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller. Table 5.2
Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt control register A Interrupt control register B Interrupt control register C Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K
Interrupt Controller Registers
Abbreviation SYSCR ISCRH ISCRL IER ISR ICRA ICRB ICRC IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2
Initial Value H'01 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77
1 Address*
H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC0 H'FEC1 H'FEC2 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.
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Section 5 Interrupt Controller
5.2
5.2.1
Bit
Register Descriptions
System Control Register (SYSCR)
: 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 — 1 — 0 — 0 RAME 1 R/W
Initial value: R/W :
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four interrupt control modes for the interrupt controller.
Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 1 2 3
Description Interrupts are controlled by I bit (Initial value)
Interrupts are controlled by I and UI bits and ICR Interrupts are controlled by bits I2 to I0, and IPR Interrupts are controlled by bits I, UI, and I2 to I0, ICR, and IPR
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value)
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Section 5 Interrupt Controller
5.2.2
Bit
Interrupt Control Registers A to C (ICRA to ICRC)
: 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W 0 ICR0 0 R/W
Initial value : R/W :
The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 5.3. The ICR registers are initialized to H'00 by a reset and in hardware standby mode. Table 5.3 Correspondence between Interrupt Sources and ICR Settings
Bits Register 7 ICRA ICRB ICRC IRQ0 — 6 IRQ1 5 IRQ2 IRQ3 4 IRQ4 IRQ5 3 IRQ6 IRQ7 2 DTC 1 0
Watchdog Refresh timer timer
A/D TPU TPU TPU TPU TPU TPU converter channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 SCI SCI SCI — channel 0 channel 1 channel 2 —
8-bit timer 8-bit timer DMAC channel 0 channel 1
5.2.3
Bit
Interrupt Priority Registers A to K (IPRA to IPRK)
: 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W
Initial value : R/W :
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.4. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.4 Correspondence between Interrupt Sources and IPR Settings
Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer — TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2
As shown in table 5.4, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU.
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Section 5 Interrupt Controller
5.2.4
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit : 7 IRQ7E Initial value : R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled.
Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (Initial value)
Note: n = 7 to 0
5.2.5
ISCRH
Bit
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
:
15 0 R/W
14 0 R/W
13 0 R/W
12 0 R/W
11 0 R/W
10 0 R/W
9 0 R/W
8 0 R/W
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W :
ISCRL
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W :
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Section 5 Interrupt Controller
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input
5.2.6
Bit
IRQ Status Register (ISR)
: 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
Initial value : R/W :
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests.
Bit n IRQnF 0 Description [Clearing conditions] • • • • 1 (Initial value)
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1)
[Setting conditions] • • • •
Note: n = 7 to 0
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Section 5 Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2655 Group from software standby mode. NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt control level can be set with ICR, and the interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
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Section 5 Interrupt Controller
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n: 7 to 0 S R Q IRQn interrupt request
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF.
φ
IRQn input pin
IRQnF
Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function.
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Section 5 Interrupt Controller
5.3.2
Internal Interrupts
There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. • The interrupt control level can be set by means of ICR, and the interrupt priority level can be set by means of IPR. • The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DMAC or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table
Table 5.5 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the ICR and IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.5.
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Section 5 Interrupt Controller
Table 5.5
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of Interrupt Source External pin Vector Address* Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 DTC 24 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 Advanced Mode ICR H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 Low ICRA7 IPRA 6 to 4 ICRA6 IPRA 2 to 0 ICRA5 IPRB 6 to 4 ICRA4 IPRB 2 to 0 ICRA3 IPRC 6 to 4 ICRA2 IPRC 2 to 0 ICRA1 IPRD 6 to 4 ICRA0 IPRD 2 to 0 ICRB7 IPRE 6 to 4 ICRB6 IPRE 2 to 0 IPR Priority High
Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) Reserved
Watchdog 25 timer Refresh controller — A/D — 26 27 28 29 30 31
TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0)
TPU 32 channel 0 33 34 35 36
ICRB5 IPRF 6 to 4
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Section 5 Interrupt Controller Origin of Interrupt Source — Vector Address* Vector Normal Number Mode 37 38 39 H'004A H'004C H'004E H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 Advanced Mode ICR H'0094 H'0098 H'009C H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC Low ICRB1 IPRH 6 to 4 ICRB2 IPRG 2 to 0 ICRB3 IPRG 6 to 4 ICRB4 IPRF 2 to 0 IPR Priority High
Interrupt Source Reserved
TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 1) Reserved
TPU 40 channel 1 41 42 43 TPU 44 channel 2 45 46 47 TPU 48 channel 3 49 50 51 52 — 53 54 55
TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4)
TPU 56 channel 4 57 58 59
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Section 5 Interrupt Controller Origin of Interrupt Source Vector Address* Vector Normal Number Mode H'0078 H'007A H'007C H'007E H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 Advanced Mode ICR H'00F0 H'00F4 H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C Low ICRC4 IPRJ 2 to 0 ICRC5 IPRJ 6 to 4 ICRC6 IPRI 2 to 0 ICRC7 IPRI 6 to 4 IPR Priority
Interrupt Source TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5)
TPU 60 channel 5 61 62 63
ICRB0 IPRH High 2 to 0
CMIA0 (compare match A0) 8-bit timer 64 CMIB0 (compare match B0) channel 0 65 OVI0 (overflow 0) Reserved — 66 67
CMIA1 (compare match A1) 8-bit timer 68 CMIB1 (compare match B1) channel 1 69 OVI1 (overflow 1) Reserved DEND0A (channel 0/ channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/ channel 1A transfer end) DEND1B (channel 1B transfer end) Reserved — — DMAC 70 71 72 73 74 75 76 77 78 79
ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0)
SCI 80 channel 0 81 82 83
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Section 5 Interrupt Controller Origin of Interrupt Source Vector Address* Vector Normal Number Mode H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 Advanced Mode ICR H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C Low ICRC2 IPRK 2 to 0 IPR Priority
Interrupt Source ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) Note: *
84 SCI channel 1 85 86 87 SCI 88 channel 2 89 90 91
ICRC3 IPRK High 6 to 4
Lower 16 bits of the start address.
5.4
5.4.1
Interrupt Operation
Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2655 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.6 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR and IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
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Section 5 Interrupt Controller
Table 5.6
Interrupt Control Modes
SYSCR Interrupt Priority Setting Interrupt Control Mode INTM1 INTM0 Registers Mask Bits 0 0 0 ICR I
Description Interrupt mask control is performed by the I bit. Priority can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority can be set with ICR. 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Control is performed by a combination of interrupt masking set by the I and UI bits and priority setting by ICR, based on 8-level interrupt mask control performed by bits I2 to I0 and 8-level priority setting by IPR.
1
1
ICR
I, UI
2
1
0
IPR
I2 to I0
3
1
ICR, IPR
I, UI, I2 to I0
Figure 5.4 shows a block diagram of the priority decision circuit.
I ICR UI IPR I2 to I0
Interrupt source
Interrupt acceptance control and 3-level mask control
8-level mask control
Default priority determination
Vector number
Interrupt control modes 0, 1, and 3
Interrupt control modes 2 and 3
Figure 5.4 Block Diagram of Interrupt Control Operation
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Section 5 Interrupt Controller
(1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0, 1, and 3, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.7 shows the interrupts selected in each interrupt control mode. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits Interrupt Control Mode 0 1 I 0 1 0 1 2 3 * 0 1 Legend: *: Don’t care UI * * * 0 1 * * 0 1 Selected Interrupts All interrupts (control level 1 has priority) NMI interrupts All interrupts (control level 1 has priority) NMI and control level 1 interrupts NMI interrupts All interrupts All interrupts NMI and control level 1 interrupts NMI interrupts
(2) 8-Level Control In interrupt control modes 2 and 3, 8-level mask level determination is performed according to the interrupt priority level (IPR) for interrupts selected in interrupt acceptance control and 3-level control. The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.8 Interrupts Selected in Each Interrupt Control Mode (2)
Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0).
Interrupt Control Mode 0 1 2 3
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Section 5 Interrupt Controller
(3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR and ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.9 shows operations and control signal functions in each interrupt control mode. Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control 3-Level Control I UI ICR 8-Level Control I2 to I0 IPR Default Priority Determination T (Trace)
Interrupt Setting Control Mode INTM1 INTM0
0 1 2 3
0 1
0 1 0 1 X
IM IM 1 —* IM
— IM — IM
PR PR — PR
X X
— — IM IM
—* 2 —*
2
— — T T
PR PR
Legend: : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. — : Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting.
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Section 5 Interrupt Controller
5.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.5 is selected. [3] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated? Yes Yes
No
NMI No
Control level 1 interrupt?
Yes No IRQ0 Yes No IRQ1 Yes TEI2 Yes
No
Hold pending
No IRQ0 Yes IRQ1 Yes TEI2 Yes No
I=0 Yes
No
Save PC and CCR I←1 Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.4.3
Interrupt Control Mode 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. • Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00 are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control level 1 and other interrupts to control level 0), the situation is as follows: • When I = 0, all interrupts are enabled • (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 ...) • When I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 interrupts are enabled • When I = 1 and UI = 1, only NMI interrupts are enabled Figure 5.6 shows the state transitions in these cases.
I←0 All interrupts enabled I ← 1, UI ← 0
Only NMI, IRQ2, and IRQ3 interrupts enabled
I←0 Exception handling execution or I ← 1, UI ← 1
UI ← 0 Exception handling execution or UI ← 1
Only NMI interrupts enabled
Figure 5.6 Example of State Transitions in Interrupt Control Mode 1 Figure 5.7 shows a flowchart of the interrupt acceptance operation in this case.
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Section 5 Interrupt Controller
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.5 is selected. [3] The I bit is then referenced. If the I bit is cleared to 0, the UI bit is not affected. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bits is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution status No
Interrupt generated? Yes Yes
NMI No
Control level 1 interrupt? Yes No No IRQ1 Yes TEI2 Yes
No
Hold pending
No IRQ0 Yes IRQ1 Yes TEI2 Yes No
IRQ0 Yes
I=0 Yes
No
I=0 No Yes
No
UI = 0 Yes
Save PC and CCR I ← 1, UI ← 1 Read vector address
Branch to interrupt handling routine
Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1
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Section 5 Interrupt Controller
5.4.4
Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.5 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated? Yes Yes NMI No No
No
Level 7 interrupt? Yes Mask level 6 or below? Yes
Level 6 interrupt? No Yes Mask level 5 or below? Yes
No
Level 1 interrupt? No Yes
No
Mask level 0 Yes
No
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2
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Section 5 Interrupt Controller
5.4.5
Interrupt Control Mode 3
Control of IRQ interrupts and on-chip supporting module interrupts is performed by a combination of interrupt masking set by the I and UI bits and control level setting by ICR, based on 8-level interrupt mask control performed by comparing the interrupt mask level in the CPU’s EXR (bits I2 to I0) and the priority set in IPR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. • Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. • Eight-level priority control is performed when the I bit is cleared to 0. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'00, H'30, and H'10 are set in ICRA, ICRB, and ICRC, respectively, (i.e. TPU channels 0 and 1 and SCI channel 0 are set to control level 1 and other interrupts to control level 0), the situation is as follows: • When I = 0, 8-level mask control is performed for all interrupts. • The interrupt controller enables TPU0, TPU1, and SCI0 interrupts. Bits I2 to I0 are disabled, and the interrupt mask level is regarded as 0. • When I = 1 and UI = 1, only NMI interrupts are enabled. Figure 5.9 shows the state transitions in these cases.
I←0 8-level control of all interrupts I ← 1, UI ← 0
TPU0, TPU1, and SCI0 interrupts enabled
I←0 Exception handling execution or I ← 1, UI ← 1
UI ← 0 Exception handling execution or UI ← 1
Only NMI interrupts enabled
Figure 5.9 Example of State Transitions in Interrupt Control Mode 3 Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case.
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Section 5 Interrupt Controller
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, it performs interrupt acceptance control. If the I bit is cleared to 0, all interrupts are accepted. If the I bit is set to 1 and the UI bit is cleared to 0, control level 1 interrupts are accepted. If both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted. [3] The interrupt request with the highest priority according to the priority levels set in IPR is selected. [4] If the I bit is cleared to 0, the priority level of the selected interrupt request is compared with the interrupt mask level set in bits I2 to I0. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [5] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [6] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [7] Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI. Also, bits I2 to I0 are rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [8] The T bit in EXR is cleared to 0. [9] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. [10]If interrupts are enabled again in the interrupt handling routine, the control level of the interrupt to be enabled is set to 1, and the UI bit in CCR is cleared to 0. At control level 1, the interrupt with the highest priority according to the priority level is selected. Bits I2 to I0 are disabled, and the interrupt mask level is regarded as 0. When the I bit is cleared to 0, the control level is ignored and an interrupt with a priority level higher than the mask level set in bits I2 to I0 is accepted.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes Yes NMI No I=0 Yes UI = 0 Yes Control level? 1 Highest-priority selection Highest-priority selection No Yes Default priority determination Save PC, CCR, and EXR Update mask level (I, UI, I2 to I0) Clear T bit to 0 Read vector address Branch to interrupt handling routine 0 No No Hold pending
Priority level > mask level?
Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 3 5.4.6 Interrupt Exception Handling Sequence
Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
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Interrupt acceptance Interrupt level determination Wait for end of instruction Instruction prefetch Stack Vector fetch Internal operation Internal operation
Interrupt service routine instruction prefetch
Section 5 Interrupt Controller
φ
Interrupt request signal
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Internal address bus (1) (3)
(7)
(5)
(9)
(11)
(13)
Internal read signal Internal write signal Internal data bus (2) (4) (6)
(8) (10) (12) (14)
Figure 5.11 Interrupt Exception Handling
(1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4
(6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine
Section 5 Interrupt Controller
5.4.7
Interrupt Response Times
The H8S/2655 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.10 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.10 are explained in table 5.11. Table 5.10 Interrupt Response Times
Normal Mode No. 1 2 3 4 5 6 Execution Status
1 Interrupt priority determination*
Advanced Mode INTM1 = 0 3 1 to 19 + 2·SI 2·SK 2·SI 2·SI 2 12 to 32 INTM1 = 1 3 1 to 19 + 2·SI 3·SK 2·SI 2·SI 2 13 to 33
INTM1 = 0 3 1 to 19 + 2·SI 2·SK SI 2·SI 2 11 to 31
INTM1 = 1 3 1 to 19 + 2·SI 3·SK SI 2·SI 2 12 to 32
Number of wait states until 2 executing instruction ends* PC, CCR, EXR stack save Vector fetch
3 Instruction fetch* 4 Internal processing*
Total (using on-chip memory) Notes: 1. 2. 3. 4.
Two states in case of internal interrupt. Refers to DIVXS instruction. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.11 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access External Device 8-Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m
Legend: m: Number of wait states in an external device access. Rev. 5.00 Sep 14, 2006 page 123 of 1060 REJ09B0331-0500
Section 5 Interrupt Controller
5.5
5.5.1
Usage Notes
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.12 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0.
TCR write cycle by CPU CMIA exception handling
φ
Internal address bus
TCR address
Internal write signal
CMIEA
CMFA
CMIA interrupt signal
Figure 5.12 Contention between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions That Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or a UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
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Section 5 Interrupt Controller
5.6
5.6.1
DTC and DMAC Activation by Interrupt
Overview
The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Activation request to DMAC • Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC, see section 8, Data Transfer Controller, and section 7, DMA Controller. 5.6.2 Block Diagram
Figure 5.13 shows a block diagram of the DTC and DMAC interrupt controller.
DMAC
Disable signal Clear signal
Interrupt request IRQ interrupt Interrupt source clear signal
Selection circuit Select signal Clear signal DTCER
DTC activation request vector number
Control logic Clear signal
DTC
On-chip supporting module
DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI, I2 to I0
Interrupt controller
Figure 5.13 Interrupt Control for DTC and DMAC
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Section 5 Interrupt Controller
5.6.3
Operation
The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCEA to DTCEF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC, the activation source is input directly to each channel. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities.
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Section 5 Interrupt Controller
Table 5.12 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC. Table 5.12 Interrupt Source Selection and Clearing Control
Settings DMAC DTA 0 DTCE 0 1 1 DTC DISEL * 0 1 * * Interrupt Source Selection/ Clearing Control DMAC DTC CPU
×
× ×
×
Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. × : The relevant bit cannot be used. * : Don’t care
(4) Notes on Use SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit.
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Section 6 Bus Controller
Section 6 Bus Controller
6.1 Overview
The H8S/2655 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.1.1 Features
The features of the bus controller are listed below. • Manages external address space in area units In advanced mode, manages the external space as 8 areas of 128-kbytes/2-Mbytes In normal mode, manages the external space as a single area Bus specifications can be set independently for each area DRAM/PSRAM/burst ROM interfaces can be set • Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area • DRAM interface DRAM interface can be set for areas 2 to 5 (in advanced mode) Row address/column address multiplexed output (8/9/10 bits) Two byte access methods (2-CAS and 2-WE) Burst operation (fast page mode) TP cycle insertion to secure RAS precharging time Choice of CAS-before-RAS refreshing or self-refreshing • Pseudo-SRAM (PSRAM) direct interface PSRAM interface can be set for areas 2 to 5 (in advanced mode) Burst operation (static column mode) TP cycle insertion to secure RAS precharging time
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Section 6 Bus Controller
Choice of auto-refreshing or self-refreshing • Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access • Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions External write cycle and internal access can be executed in parallel DMAC single-address mode and internal access can be executed in parallel • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC • Other features Refresh counter (refresh timer) can be used as an interval timer External bus release function
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Section 6 Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7 Area decoder
Internal address bus
ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal control signals Bus mode signal
WAIT
WCRH WCRL
DRAM/PSRAM controller External DRAM/ PSRAM control signals MCR DRAMCR RTCNT RTCOR
CPU bus request signal DTC bus request signal Bus arbiter DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal
Figure 6.1 Block Diagram of Bus Controller
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Internal data bus
Wait controller
Section 6 Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the pins of the bus controller. Table 6.1
Name Address strobe Read High write/write enable/upper write enable
Bus Controller Pins
Symbol I/O AS RD HWR Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal. 2-WE DRAM upper write enable signal.
Low write/lower column address strobe/lower write enable
LWR
Output
Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. 2-CAS (LCASS = 1) DRAM lower column address strobe signal.* 2-WE DRAM lower write enable signal.
Chip select 0 Chip select 1 Chip select 2/row address strobe 2
CS0 CS1 CS2
Output Output Output
Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space.
Chip select 3/row address strobe 3
CS3
Output
Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space.
Chip select 4/row address strobe 4
CS4
Output
Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space.
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Section 6 Bus Controller Name Chip select 5/row address strobe 5 Symbol I/O CS5 Output Function Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space. Chip select 6 Chip select 7 Upper column address strobe/ column address strobe/output enable/refresh CS6 CS7 CAS/ OE Output Output Output Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. 2-CAS DRAM upper column address strobe signal. 2-WE DRAM column address strobe signal. PSRAM output enable signal when areas 2 to 5 are in PSRAM space. Lower column strobe Wait Bus request Bus request acknowledge Bus request output LCAS WAIT BREQ BACK Output Input Input Output The 2-CAS type (LCASS = 0) DRAM lower column address strobe signal.* Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released.
BREQO Output
Note:
*
Using the LCASS bit in BCRL, it is possible to select use of either the LWR pin or the LCAS pin for the 2-CAS type DRAM lower column strobe signal.
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Section 6 Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers
Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Memory control register DRAM control register Refresh timer/counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL MCR DRAMCR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Power-On Reset
2 H'FF/H'00*
Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9
1
H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF
Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode.
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Section 6 Bus Controller
6.2
6.2.1
Bit
Register Descriptions
Bus Width Control Register (ABWCR)
: 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W
Modes 1 to 3, 5 to 7 Initial value : 1 RW Mode 4 Initial value : RW : 0 R/W : R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1 to 3, and 5 to 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access.
Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access
Note: n = 7 to 0
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Section 6 Bus Controller
6.2.2
Bit
Access State Control Register (ASTCR)
: 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W
Initial value : R/W :
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time.
Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled Note: n = 7 to 0 (Initial value)
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Section 6 Bus Controller
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space. The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH
Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value)
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Section 6 Bus Controller
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value)
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value)
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1.
Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value)
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Section 6 Bus Controller
(2) WCRL
Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value)
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value)
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Section 6 Bus Controller
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1.
Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value)
6.2.4
Bit
Bus Control Register H (BCRH)
: 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 0 R/W 1 RMTS1 0 R/W 0 RMTS0 0 R/W
BRSTRM BRSTS1 BRSTS0 RMTS2
Initial value : R/W :
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.
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Section 6 Bus Controller
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed.
Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Burst ROM interface and PSRAM burst operation cannot be set at the same time.
Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface.
Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value)
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Section 6 Bus Controller
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value)
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface, and when PSRAM space is selected, it is designated as PSRAM interface.
Bit 2 RMTS2 0 Bit 1 RMTS1 0 1 1 0 1 Bit 0 RMTS0 0 1 0 1 0 1 0 1 Normal space PSRAM space Normal space DRAM space Normal space Normal space PSRAM space PSRAM space Area 5 Description Area 4 Normal space Area 3 Area 2 DRAM space DRAM space Normal space
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Section 6 Bus Controller
6.2.5
Bit
Bus Control Register L (BCRL)
: 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W 2 ASS 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W
Initial value : R/W :
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the area partition unit, the LCAS signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) External bus release is enabled.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated.
Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO can be used as I/O port. BREQO output enabled. (Initial value)
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Section 6 Bus Controller
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode.
Bit 5 EAE 0 1 Note: * Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2655) or a reserved area* (in the H8S/2653) Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode) (Initial value) Reserved areas should not be accessed.
Bit 4—LCAS Select (LCASS): Selects use of the LWR pin or the LCAS pin for the 2-CAS type DRAM interface LCAS signal.
Bit 4 LCASS 0 1 Description LCAS pin used for 2-CAS type DRAM interface LCAS signal (BREQO output and WAIT input cannot be used when LCAS signal is used) LWR pin used for 2-CAS type DRAM interface LCAS signal (RAS down mode cannot be used) (Initial value)
Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface or PSRAM interface.
Bit 3 DDS 0 Description When DMAC single address transfer is performed in DRAM/PSRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle 1 Burst access is possible when DMAC single address transfer is performed in DRAM/PSRAM space DACK signal goes low from Tc1 or T2 cycle (Initial value)
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Section 6 Bus Controller
Bit 2—Area Partition Unit Select (ASS): Selects the area partition unit.
Bit 2 ASS 0 1 Description Area partition unit is 128 kbytes (1 Mbit) Area partition unit is 2 Mbytes (16 Mbits) (Initial value)
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle.
Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value)
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value)
6.2.6
Bit
Memory Control Register (MCR)
: 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W
Initial value : R/W :
MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface. When areas 2 to 5 are designated as PSRAM interface, MCR selects the number of precharge cycles and the access mode for PSRAM.
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Section 6 Bus Controller
MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space or PSRAM space are accessed.
Bit 7 TPC 0 1 Description 1-state precharge cycle is inserted 2-state precharge cycle is inserted (Initial value)
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space or PSRAM space. DRAM space burst access is performed in fast page mode, and PSRAM access in static column mode. PSRAM burst operation and burst ROM interface cannot be set at the same time.
Bit 6 BE 0 1 Description Burst disabled (always full access) • • For DRAM space access Access in fast page mode For PSRAM space access Access in static column mode (Initial value)
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). RAS down mode cannot be used with the 2-CAS method (LCASS=1). When selecting RAS down mode, set the BE bit to 1. When areas 2 to 5 are designated as PSRAM space, this bit is invalid.
Bit 5 RCDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value)
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Section 6 Bus Controller
Bit 4—2-CAS Method/2-WE Method Select (CW2): Selects whether the 2-CAS method or 2WE method is used for byte access when areas 2 to 5 are designated as 16-bit DRAM space.
Bit 4 CW2 0 1 Description 2-CAS method selected: CASH, CASL, WE signals enabled 2-WE method selected: CAS, UWE, LWE signals enabled (Initial value)
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM/PSRAM interface, these bits also select the row address to be used for comparison.
Bit 3 MXC1 0 Bit 2 MXC0 0 Description 8-bit shift • • 1 (Initial value)
When 8-bit access space is designated: Row address A23 to A8 used for comparison When 16-bit access space is designated: Row address A23 to A9 used for comparison When 8-bit access space is designated: Row address A23 to A9 used for comparison When 16-bit access space is designated: Row address A23 to A10 used for comparison When 8-bit access space is designated: Row address A23 to A10 used for comparison When 16-bit access space is designated: Row address A23 to A11 used for comparison
9-bit shift • •
1
0
10-bit shift • •
1
—
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Section 6 Bus Controller
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1 RLW1 0 1 Bit 0 RLW0 0 1 0 1 Description No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted (Initial value)
6.2.7
Bit
DRAM Control Register (DRAMCR)
: 7 RFSHE 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value : R/W :
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control is not performed in normal mode.
Bit 7 RFSHE 0 1 Description Refresh control is not performed Refresh control is performed (Initial value)
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Section 6 Bus Controller
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-beforeRAS refreshing. In case of the PSRAM interface, the value of this bit should be kept at 0.
Bit 6 RCW 0 1 Description Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle (Initial value)
Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal refreshing (CAS-before-RAS refreshing for the DRAM interface, autorefreshing for the PSRAM interface) or self-refreshing is performed.
Bit 5 RMODE 0 Description • • 1 DRAM interface CAS-before-RAS refreshing used PSRAM interface Auto-refreshing used Self-refreshing used (Initial value)
Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR.
Bit 4 CMF 0 Description [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) 1 [Setting condition] Set when RTCNT = RTCOR
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Section 6 Bus Controller
Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0.
Bit 3 CMIE 0 1 Description Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled (Initial value)
Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (φ). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.
Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Description Count operation disabled Count uses φ/2 Count uses φ/8 Count uses φ/32 Count uses φ/128 Count uses φ/512 Count uses φ/2048 Count uses φ/4096 (Initial value)
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Section 6 Bus Controller
6.2.8
Bit
Refresh Timer/Counter (RTCNT)
: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Initial value : R/W :
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 6.2.9
Bit
Refresh Time Constant Register (RTCOR)
: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
Initial value : R/W :
RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.
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Section 6 Bus Controller
6.3
6.3.1
Overview of Bus Control
Area Partitioning
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 128-kbyte or 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
H'000000 H'01FFFF H'020000 H'03FFFF H'040000 H'05FFFF H'060000 H'07FFFF H'080000 H'09FFFF H'0A0000 H'0BFFFF H'0C0000 H'0DFFFF H'0E0000 Area 0 (128 kbytes) Area 1 (128 kbytes) Area 2 (128 kbytes) Area 3 (128 kbytes) Area 4 (128 kbytes) Area 5 (128 kbytes) Area 6 (128 kbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF H'FFFFFF H'5FFFFF H'600000 Area 3 (2 Mbytes) H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'0000
H'FFFF
Area 7 (15 Mbytes)
(1) Advanced mode When ASS = 0
(2) Advanced mode When ASS = 1
(3) Normal mode
Figure 6.2 Overview of Area Partitioning
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Section 6 Bus Controller
6.3.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM/PSRAM interface and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area.
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Section 6 Bus Controller
Table 6.3
ABWCR ABWn 0
Bus Specifications for Each Area (Basic Bus Interface)
ASTCR ASTn 0 1 WCRH, WCRL Wn1 — 0 1 Wn0 — 0 1 0 1 — 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3
1
0 1
— 0
6.3.3
Memory Interfaces
The H8S/2655 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a PSRAM interface that allows direct connection of PSRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the PSRAM interface is designated functions as PSRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space.
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Section 6 Bus Controller
6.3.4
Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.5, 6.6, and 6.7) should be referred to for further details. Area 0 Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. The size of area 0 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS bit. Areas 1 and 6 In external expansion mode, all of areas 1 and 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. The size of areas 1 and 6 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS bit. Areas 2 to 5 In external expansion mode, all of areas 2 to 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface, DRAM interface, or PSRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. The size of areas 2 to 5 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS bit.
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Section 6 Bus Controller
Area 7 Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. The size of area 7 is switched between 15 Mbytes and 2 Mbytes according to the state of the ASS bit. 6.3.5 Areas in Normal Mode
In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When external space is accessed, the CS0 signal can be output. The basic bus interface or burst ROM interface can be selected.
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Section 6 Bus Controller
6.3.6
Chip Select Signals
The H8S/2655 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal can be output. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
Bus cycle T1 φ T2 T3
Address bus
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7) CS
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Section 6 Bus Controller
6.4
6.4.1
Basic Bus Interface
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle
Word size
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
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Section 6 Bus Controller
16-Bit Access Space Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address
Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space)
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Section 6 Bus Controller
6.4.3
Valid Strobes
Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4
Area 8-bit access space
Data Buses Used and Valid Strobes
Access Read/ Size Write Byte Read Write Read Write Word Read Write Address — — Even Odd Even Odd — — HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Undefined Valid Upper Data Bus (D15 to D8) Valid Lower Data Bus (D7 to D0) Invalid Undefined Invalid Valid Undefined Valid Valid Valid
16-bit access Byte space
HWR, LWR Valid
Note: Undefined: Undefined data is output. Invalid: Input state; input value is ignored.
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Section 6 Bus Controller
6.4.4
Basic Timing
8-Bit 2-State Access Space Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle T1 φ T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR Write D15 to D8
High
Valid
D7 to D0
Undefined
Note: n = 0 to 7
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space
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Section 6 Bus Controller
8-Bit 3-State Access Space Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted.
Bus cycle T1 φ T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High
LWR Write D15 to D8
Valid
D7 to D0 Note: n = 0 to 7
Undefined
Figure 6.7 Bus Timing for 8-Bit 3-State Access Space
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Section 6 Bus Controller
16-Bit 2-State Access Space Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Bus cycle T1 φ T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR Write D15 to D8
High
Valid
D7 to D0
Undefined
Note: n = 0 to 7
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle T1 φ T2
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR Write D15 to D8 Undefined
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle T1 φ T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
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Section 6 Bus Controller
16-Bit 3-State Access Space Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Bus cycle T1 φ T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High
LWR Write D15 to D8
Valid
D7 to D0 Note: n = 0 to 7
Undefined
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle T1 φ T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR Write D15 to D8 Undefined
D7 to D0 Note: n = 0 to 7
Valid
Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle T1 φ T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0 Note: n = 0 to 7
Valid
Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
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Section 6 Bus Controller
6.4.5
Wait Control
When accessing external space, the H8S/2655 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. • Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of BWCRH and BWCRL. • Pin Wait Insertion Setting the WAITE bit in BCRH to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Figure 6.14 shows an example of wait state insertion timing.
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Section 6 Bus Controller
By program wait T1 φ T2 Tw
By WAIT pin Tw Tw T3
WAIT
Address bus
AS
RD Read Data bus Read data
HWR, LWR Write Data bus Write data
Note:
indicates the timing of WAIT pin sampling.
Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset.
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Section 6 Bus Controller
6.5
6.5.1
DRAM Interface
Overview
When the H8S/2655 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2655 Group. A DRAM space of 2, 4, or 8 Mbytes, or 128, 256, or 512 kbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6.5
RMTS2 0
Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
RMTS1 0 1 RMTS0 1 0 1 Area 5 Area 4 Normal space Normal space DRAM space Area 3 Area 2 DRAM space DRAM space
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Section 6 Bus Controller
6.5.3
Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6.6 Address Multiplexing Settings by Bits MXC1 and MXC0
MCR MXC1 MXC0 Shift Size A23 to A13 Row 0 address 1 0 1 0 1 Column — address — 8 bits 9 bits 10 bits A23 to A13 A23 to A13 A23 to A13 A12 A11 A10 A9 Address Pins A8 A7 A6 A5 A4 A3 A2 A1 A0 A8
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 — — — — — A8 — A7 — A6 — A5 — A4 — A3 — A2 — A1 — A0
Setting — prohibited — A23 to A13
A12 A11 A10 A9
6.5.4
Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment.
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Section 6 Bus Controller
6.5.5
Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7
Pin HWR
DRAM Interface Pins
With DRAM Setting Name WE/UWE Write enable/upper write enable I/O Output Function When 2-CAS system is set, write enable for DRAM space access. When 2-WE system is set, upper write enable for DRAM space access.
LWR
LCAS/LWE
Lower column address strobe/lower write enable
Output
When 2-CAS system (LCASS = 1) is set, lower column address strobe for DRAM space access. When 2-WE system is set, lower write enable for DRAM space access.
LCAS
LCAS
Lower column address strobe Row address strobe 2 Row address strobe 3 Row address strobe 4 Row address strobe 5 Column address strobe/ upper column address strobe Wait Address pins Data pins
Output
Lower column address strobe for access to 2-CAS type (LCASS = 0) DRAM space. Row address strobe when area 2 is designated as DRAM space. Row address strobe when area 3 is designated as DRAM space. Row address strobe when area 4 is designated as DRAM space. Row address strobe when area 5 is designated as DRAM space. When 2-WE system is set, column address strobe. When 2-CAS system is set, upper column address strobe.
CS2 CS3 CS4 CS5 CAS
RAS2 RAS 3 RAS 4 RAS 5 CAS/UCAS
Output Output Output Output Output
WAIT A12 to A0 D15 to D0
WAIT A12 to A0 D15 to D0
Input Output I/O
Wait request signal Row address/column address multiplexed output Data input/output pins
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Section 6 Bus Controller
6.5.6
Basic Timing
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and Tc2.
Tp φ A23 to A0 Row Column Tr Tc1 Tc2
CSn (RAS) CAS HWR, LWR (UWE, LWE) D15 to D0
Read
Write
HWR, LWR (UWE, LWE) D15 to D0
Note: n = 2 to 5
Figure 6.15 Basic Access Timing (2-WE System)
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Section 6 Bus Controller
6.5.7
Precharge State Control
When DRAM is accessed, RAS precharging time must be secured. With the H8S/2655 Group, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the DRAM connected and the operating frequency of the H8S/2655 Group. Figure 6.16 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for refresh cycles.
Tp1 Tp2 Tr Tc1 Tc2
φ
A23 to A0 Row Column
CSn (RAS) CAS HWR, LWR (UWE, LWE) Read D15 to D0 HWR, LWR (UWE, LWE) Write D15 to D0
Note: n = 2 to 5
Figure 6.16 Timing with Two Precharge States (2-WE System)
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Section 6 Bus Controller
6.5.8
Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. • Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. • Pin Wait Insertion When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6.17 shows an example of wait state insertion timing.
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Section 6 Bus Controller
By program wait Tp φ Tr Tc1 Tw
By WAIT pin Tw Tc2
WAIT
Address bus
CSn (RAS)
CAS
Read
Data bus
Read data
HWR, LWR Write Data bus Write data
Notes:
indicates the timing of WAIT pin sampling. n = 2 to 5
Figure 6.17 Example of Wait State Insertion Timing
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Section 6 Bus Controller
6.5.9
Byte Access Control
When DRAM with a ×16 configuration is connected, the control signals needed for byte access differ depending on the kind of DRAM used. Either the 2-CAS system or the 2-WE system can be selected according to the setting of the CW2 bit in MCR. • 2-CAS System When the CW2 bit in MCR is cleared to 0, the 2-CAS system is selected. With this system, UCAS, LCAS, and WE signals are output. Use of the LWR pin or the LCAS pin for the LCAS signal can be selected by means of the LCASS bit. (a) When LCASS = 0 Figure 6.18 (a) shows the control timing in the 2-CAS system (LCASS = 0), and figure 6.19 (a) shows an example of 2-CAS system (LCASS = 0) DRAM connection. (b) When LCASS = 1 Figure 6.18 (b) shows the control timing in the 2-CAS system (LCASS = 1), and figure 6.19 (b) shows an example of 2-CAS system (LCASS = 1) DRAM connection. In this case, since the LWR pin is used for the LCAS signal, RAS down mode cannot be used. Regardless of the ICIS1 and ICIS0 bits, when non-DRAM space is accessed following a DRAM space access, an idle cycle (TDI) is inserted after the DRAM space access. Access to another space is not performed during CBR refreshing; access to another space is performed after insertion of an idle cycle (TRI). • 2-WE System When the CW2 bit in MCR is set to 1, the 2-WE system is selected. With this system, CAS, UWE, and LWE signals are output. Figure 6.20 shows the control timing in the 2-WE system, and figure 6.21 shows an example of DRAM connection using this system.
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Section 6 Bus Controller
Tp φ A23 to A0
Tr
Tc1
Tc2
Row
Column
CSn (RAS) CAS (UCAS) Byte control LCAS (LCAS) HWR (WE) Note: n = 2 to 5
Figure 6.18 (a) 2-CAS System (LCASS = 0) Control Timing (Upper Byte Write Access)
Tp φ A23 to A0
Tr
Tc1
Tc2
Row
Column
CSn (RAS) CAS (UCAS) Byte control LWR (LCAS) HWR (WE) Note: n = 2 to 5
Figure 6.18 (b) 2-CAS System (LCASS = 1) Control Timing (Upper Byte Write Access)
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Section 6 Bus Controller
H8S/2655 (Address shift size set to 9 bits) CS (RAS) CAS (UCAS) LWR (LCAS) HWR (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0
2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Low address input: A8 to A0 Column address input: A8 to A0
Figure 6.19 (a) Example of 2-CAS System (LCASS = 0) DRAM Connection
2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Low address input: A8 to A0 Column address input: A8 to A0
H8S/2655 (Address shift size set to 9 bits) CS (RAS) CAS (UCAS) LWR (LCAS) HWR (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0
Figure 6.19 (b) Example of 2-CAS System (LCASS = 1) DRAM Connection
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Section 6 Bus Controller
Tp φ A23 to A0
Tr
Tc1
Tc2
Row
Column
CSn (RAS) CAS HWR (UWE) Byte control LWR (LWE)
Note: n = 2 to 5
Figure 6.20 2-WE System Control Timing (Upper Byte Access)
2-WE type 4-Mbit DRAM 256-kbyte × 16-bit configuration 8-bit column address RAS CAS UWE LWE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Low address input: A9 to A0 Column address input: A7 to A0
H8S/2655 (Address shift size set to 8 bits) CSn (RAS) CAS HWR (UWE) LWR (LWE) A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0
Note: n = 2 to 5
Figure 6.21 Example of 2-WE Type DRAM Connection
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Section 6 Bus Controller
6.5.10
Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. (1) Burst Access (Fast Page Mode) Operation Timing Figure 6.22 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR.
Tp φ A23 to A0 CSn (RAS) CAS HWR, LWR (UWE, LWE) D15 to D0 HWR, LWR (UWE, LWE) D15 to D0 Row Column 1 Column 2 Tr Tc1 Tc2 Tc1 Tc2
Read
Write
Note: n = 2 to 5
Figure 6.22 Operation Timing in Fast Page Mode (2-WE System) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.
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Section 6 Bus Controller
(2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. RAS down mode cannot be used with the 2-CAS system (when LCASS = 1). RAS down mode: To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.23 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode.
External space access T1 T2
DRAM access Tp Tr Tc1 Tc2
DRAM access Tc1 Tc2
φ
A23 to A0
CSn (RAS)
CAS
D15 to D0
Note: n = 2 to 5
Figure 6.23 Example of Operation Timing in RAS Down Mode
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Section 6 Bus Controller
RAS up mode: To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.24 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level.
External space access T1 T2
DRAM access Tp φ Tr Tc1 Tc2
DRAM access Tc1 Tc2
A23 to A0
CSn (RAS)
CAS
D15 to D0
Note: n = 2 to 5
Figure 6.24 Example of Operation Timing in RAS Up Mode
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Section 6 Bus Controller
6.5.11
Caution Concerning 2-CAS System
When the 2-CAS system (LCASS = 1) is selected, if normal (non-DRAM) space is accessed following a DRAM space access, an idle cycle (TDI) is inserted after the DRAM space access. An idle cycle is not inserted if the DRAM space access is followed by an on-chip memory access or DRAM space access.
Tp φ Tr Tc1 Tc2 TDI
A23 to A0
Row
Column
Normal space address
CSn (RAS)
CAS (RAS) LWR (LCAS) HWR (WE) D15 to D0
Read
HWR (WE) Write D15 to D0
CSm (Non-DRAM space)
Note: n = 2 to 5, m = 0 to 7, m ≠ n
Figure 6.25 Idle Cycle Insertion with 2-CAS System (LCASS = 1)
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Section 6 Bus Controller
6.5.12
Refresh Control
The H8S/2655 Group is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6.26, compare match timing in figure 6.27, and 2-WE and 2CAS system CBR refresh timings in figures 6.28 and 29. An access to another normal space is performed during the 2-WE system or 2-CAS system (LCASS = 0) refresh period. An access to another normal space is not performed during the 2-CAS system (LCASS = 1) refresh period, but following insertion of an idle cycle (TRI) after refreshing is completed. An idle cycle (TRI) is not inserted when an on-chip memory access or DRAM space access follows.
RTCNT RTCOR
H'00 Refresh request
Figure 6.26 RTCNT Operation
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Section 6 Bus Controller
φ RTCNT
N
H'00
RTCOR
N
Refresh request signal and CMF bit setting signal
Figure 6.27 Compare Match Timing
TRp TRr TRc1 TRc2
φ
CS (RAS) CAS, LCAS HWR, LWR (UWE, LWE)
High
Figure 6.28 2-WE System or 2-CAS System (LCASS = 0) CBR Refresh Timing (When RCW = 0 and CW2 = 1; or RCW = 0, CWZ = 0, and LCASS = 0)
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Section 6 Bus Controller
TRp
TRr
TRc1
TRc2
TRI
φ
CSn (RAS)
CAS (UCAS) LWR (LCAS) HWR (UWE)
High
Figure 6.29 2-CAS System (LCASS = 1) CBR Refresh Timing (When RCW = 0 and CW2 = 0, LCASS = 1) When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6.30 shows the timing when the RCW bit is set to 1.
TRp TRr TRc1 TRw TRc2
φ
CS (RAS)
CAS HWR, LWR (UWE, LWE)
High
Figure 6.30 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1, CW2 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
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Section 6 Bus Controller
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figures 6.31 (a) and (b). When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-refresh mode is entered.
Software standby
TRp φ
TRcr
TRc3
CSn (RAS) CAS, LCAS HWR, LWR (UWE, LWE) Note: n = 2 to 5 High
Figure 6.31 (a) Self-Refresh Timing (When CW2 = 1, or CWZ = 1 and LCASS = 0)
Software standby
TRp φ
TRcr
TRc3
TRI
CSn (RAS) CAS, LWR (UCAS, LCAS) HWR (WE) Note: n = 2 to 5 High
Figure 6.31 (b) Self-Refresh Timing (When CW2 = 0, LCASS = 1)
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Section 6 Bus Controller
6.6
6.6.1
Pseudo-SRAM Interface
Overview
When the H8S/2655 Group is in advanced mode, external space areas 2 to 5 can be designated as pseudo-SRAM (PSRAM) space, and PSRAM interfacing performed. With the PSRAM interface, PSRAM can be directly connected to the H8S/2655 Group. A PSRAM space of 2, 4, or 8 Mbytes, or 128, 256, or 512 kbytes can be set by means of bits RMTS3 to RMTS0 in BCRH. In the directly connected PSRAM, the refresh signal (RFSH) and output enable signal (OE) are multiplexed. Burst operation is also possible, using static column mode. 6.6.2 Setting PSRAM Space
Areas 2 to 5 are designated as PSRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and PSRAM space is shown in table 6.8. Possible PSRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6.8
RMTS2 1
Settings of Bits RMTS2 to RMTS0 and Corresponding PSRAM Spaces
RMTS1 0 1 RMTS0 1 0 1 Area 5 Area 4 Normal space Normal space PSRAM space Area 3 Area 2 PSRAM space PSRAM space
6.6.3
Data Bus
If the bit in ABWCR corresponding to an area designated as PSRAM space is set to 1, that area is designated as 8-bit PSRAM space; if the bit is cleared to 0, the area is designated as 16-bit PSRAM space. In 8-bit PSRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit PSRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment.
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Section 6 Bus Controller
6.6.4
Pins Used for PSRAM Interface
Table 6.9 shows the pins used for PSRAM interfacing and their functions. Table 6.9
Pin HWR
PSRAM Interface Pins
With PSRAM Setting Name WE/UWE Write enable/upper write enable I/O Output Function Upper write enable when PSRAM space is designated for 16-bit access, or write enable when designated for 8-bit access. Lower write enable when PSRAM space is designated for 16-bit access. Chip enable signal when area 2 is designated as PSRAM space. Chip enable signal when area 3 is designated as PSRAM space. Chip enable signal when area 4 is designated as PSRAM space. Chip enable signal when area 5 is designated as PSRAM space. Connected to PSRAM output enable/refresh dual-function pin Wait request signal input pin Address output pins Data input/output pins
LWR
LWE
Lower write enable
Output
CS2 CS3 CS4 CS5 CAS WAIT A20 to A0 D15 to D0
CE2 CE3 CE4 CE5 OE/RFSH WAIT A20 to A0 D15 to D0
Chip enable 2 Chip enable 3 Chip enable 4 Chip enable 5 Output enable/refresh Wait Address pins Data pins
Output Output Output Output Output Input Output I/O
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Section 6 Bus Controller
6.6.5
Basic Timing
Figure 6.32 shows the basic access timing for PSRAM space. The basic PSRAM access timing is 4 states, including one TP (precharge cycle) state. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the PSRAM access cycle.
Tp φ A23 to A0 T1 T2 T3
AS CSn (CE) HWR, LWR (UWE, LWE) Read OE
D15 to D0
HWR, LWR (UWE, LWE) Write OE
D15 to D0 Note: n = 2 to 5
Figure 6.32 Basic Access Timing
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Section 6 Bus Controller
6.6.6
Precharge State Control
When PSRAM is accessed, CE precharging time must be secured. With the H8S/2655 Group, one Tp state is always inserted when PSRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the PSRAM connected and the operating frequency of the H8S/2655 Group. Figure 6.33 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for refresh cycles.
Tp1 Tp2 T1 T2 T3
φ A23 to A0 AS
CSn (CE)
HWR, LWR (UWE, LWE)
Read
OE D15 to D0
HWR, LWR (UWE, LWE)
Write
OE
D15 to D0
Note: n = 2 to 5
Figure 6.33 Timing with Two Precharge States
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Section 6 Bus Controller
6.6.7
Wait Control
There are two ways of inserting wait states in a PSRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. (1) Program Wait Insertion When the bit in ASTCR corresponding to an area designated as PSRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the T2 state and T3 state, according to the settings of WCRH and WCRL. (2) Pin Wait Insertion When the WAITE bit in BCRL is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When PSRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6.34 shows an example of wait state insertion timing.
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Section 6 Bus Controller
By program wait Tp φ T1 T2 Tw
By WAIT pin Tw T3
WAIT
Address bus
CSn (CE)
OE Read Data bus Read data
HWR, LWR Write Data bus Write data
Notes:
indicates the timing of WAIT pin sampling. n = 2 to 5
Figure 6.34 Example of Wait State Insertion Timing
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Section 6 Bus Controller
6.6.8
Burst Operation
With PSRAM, a static column mode is provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address while holding the CS signal low. Burst access can be selected by setting the BE bit in MCR to 1. PSRAM burst operation and burst ROM interface cannot be set at the same time. Figure 6.35 shows the operation timing for burst access. When there are consecutive access cycles for PSRAM space, column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR.
Tp φ A23 to A0 AS CSn (CE) HWR, LWR (UWE, LWE) Read OE D15 to D0 High
Only column address changed
T1
T2
T3
T2
T3
HWR, LWR (UWE, LWE) Write OE D15 to D0
Note: n = 2 to 5
Figure 6.35 Operation Timing for Burst Access The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for normal mode. For details, see section 6.6.7, Wait Control.
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Section 6 Bus Controller
Even when burst operation is selected, it may happen that access to PSRAM space is not continuous, but is interrupted by access to another space. If access to PSRAM space is interrupted and on-chip memory or an internal I/O register is accessed, the CE signal is held low during that access, and burst access is performed if the row address of the next PSRAM space address is the same as the row address of the previous PSRAM space access. Figure 6.36 shows an example of the timing in burst access.
Internal I/O access
Tp φ A23 to A0 AS CSn (CE) HWR, LWR (UWE, LWE) Read OE D15 to D0 HWR, LWR (UWE, LWE) Write OE D15 to D0
T1
T2
T3
T2
T3
High
Note: n = 2 to 5
Figure 6.36 Example of Operation Timing in Burst Access
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Section 6 Bus Controller
When access to PSRAM space is interrupted and another space is accessed, the CE signal goes high again. Burst operation is only performed if PSRAM space is continuous. Figure 6.37 shows an example of the timing.
External space access
Tp φ A23 to A0 AS CSn (CE) HWR, LWR (UWE, LWE) OE D15 to D0 HWR, LWR (UWE, LWE) OE D15 to D0
T1
T2
T3
Tp
T1
T2
High
Note: n = 2 to 5
Figure 6.37 Example of Interrupted Operation Timing in Burst Access
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Section 6 Bus Controller
6.6.9
Refresh Control
The H8S/2655 Group is provided with a PSRAM refresh control function. Either of two refreshing methods can be selected: auto-refreshing, or self-refreshing. (1) Auto-Refreshing To select auto-refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With auto-refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the PSRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Auto-refresh timing is shown in figure 6.38.
TRp TR1 TR2 TR3
φ
CSn (CE)
OE/RFSH
HWR, LWR
High
Note: n = 2 to 5
Figure 6.38 Auto-Refresh Timing
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Section 6 Bus Controller
(2) Self-Refreshing PSRAM is placed in self-refresh mode by holding the RFSH signal low for the prescribed time or longer. To select self-refreshing, set the RFSHE bit and RMODE bit to 1. Self-refresh mode is entered when a SLEEP instruction is executed to enter software standby mode. When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. Check the characteristics of the PSRAM used before making settings after self-refreshing is cleared. Figure 6.39 shows self-refresh timing.
Software standby
TRp
TR1
TR3
φ
CSn (CE)
OE/RFSH HWR, LWR (UWE, LWE)
High
Note: n = 2 to 5
Figure 6.39 Self-Refresh Timing 6.6.10 Power-On Sequence
A power-on reset initializes the bus controller. If PSRAM is connected, you should check its characteristics and perform the necessary processing.
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Section 6 Bus Controller
6.7
DMAC Single Address Mode and DRAM/PSRAM Interface
When burst mode is selected with the DRAM or PSRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM or PSRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected. 6.7.1 When DDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the TC1 state in the case of the DRAM interface, and from the T2 state in the case of the PSRAM interface. Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1.
Tp φ A23 to A0 CSn (RAS) CAS, (UCAS) LCAS (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK
Row Column
Tr
Tc1
Tc2
Figure 6.40 DACK Output Timing when DDS = 1 (Example of DRAM Access) DACK
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Section 6 Bus Controller
6.7.2
When DDS = 0
When DRAM or PSRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface, and from the T1 state in the case of the PSRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM or PSRAM space. Figure 6.41 shows the DACK output timing for the DRAM interface when DDS = 0.
Tp φ A23 to A0 CSn (RAS) CAS, (UCAS) LCAS (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK
Row Column
Tr
Tc1
Tc2
Figure 6.41 DACK Output Timing when DDS = 0 (Example of DRAM Access) DACK
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Section 6 Bus Controller
6.8
6.8.1
Burst ROM Interface
Overview
With the H8S/2655 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. Do not select the burst ROM interface and pseudo-SRAM burst operation at the same time. 6.8.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figure 6.42 (a) and (b). The timing shown in figure 6.42 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.42 (b) is for the case where both these bits are cleared to 0.
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Section 6 Bus Controller
Full access T1 φ T2 T3 T1
Burst access T2 T1 T2
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6.42 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
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Section 6 Bus Controller
Full access T1 φ T2
Burst access T1 T1
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 6.42 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.8.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle.
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Section 6 Bus Controller
6.9
6.9.1
Idle Cycle
Operation
When the H8S/2655 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A T1 φ Address bus T2 T3 Bus cycle B T1 T2 φ Address bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
RD Data bus
RD Data bus Data collision
Long output floating time
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.43 Example of Idle Cycle Operation (1) (When ICIS1 = 1)
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Section 6 Bus Controller
(2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal mode. Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A T1 φ Address bus T2 T3 Bus cycle B T1 T2 φ Address bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
RD HWR Data bus
RD HWR Data bus Data collision
Long output floating time
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.44 Example of Idle Cycle Operation (2) (When ICIS0 = 1) (3) Usage Notes When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6.45.
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Section 6 Bus Controller
External read T1 φ Address bus RD Data bus T2 T3 Tp
DRAM space read Tr Tc1 Tc2
Figure 6.45 Example of DRAM Access after External Read 6.9.2 Pin States in Idle Cycle
Table 6.10 shows pin states in an idle cycle. Table 6.10 Pin States in Idle Cycle
Pins A23 to A0 D15 to D0 CSn CAS/OE AS RD HWR LWR DACKn Pin State Contents of next bus cycle High impedance 1 High* High* High High High High High
2
Notes: 1. Remains low in PSRAM space CS down mode. Also remains low in DRAM space RAS down mode or a refresh cycle. 2. Remains low in PSRAM space CS down mode or a refresh cycle.
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Section 6 Bus Controller
6.10
Write Data Buffer Function
The H8S/2655 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6.46 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends.
On-chip memory read Internal I/O register read
External write cycle T1 T2 TW TW T3
Internal address bus Internal memory Internal read signal Internal I/O register address
A23 to A0 CSn
External address
External space write
HWR, LWR
D15 to D0
Figure 6.46 Example of Timing when Write Data Buffer Function is Used
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Section 6 Bus Controller
6.11
6.11.1
Bus Release
Overview
The H8S/2655 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip. 6.11.2 Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2655 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request is generated in the external bus released state, refresh control is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. In the event of simultaneous external bus release request, refresh request, and external access request generation, the order of priority is as follows: (High) Refresh > External bus release > Internal bus master external access (Low)
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Section 6 Bus Controller
6.11.3
Pin States in External Bus Released State
Table 6.11 shows pin states in the external bus released state. Table 6.11 Pin States in Bus Released State
Pins A23 to A0 D15 to D0 CSn CAS AS RD HWR LWR DACKn Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High
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Section 6 Bus Controller
6.11.4
Transition Timing
Figure 6.47 shows the timing for transition to the bus-released state.
CPU cycle
CPU cycle T0 φ T1 T2
External bus released state
High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR
BREQ
BACK
BREQO *
Minimum 1 state [1] [2] [3] [4] [5] [6]
[1] [2] [3] [4] [5] [6]
Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high.
Note: * Output only when BREQOE is set to 1.
Figure 6.47 Bus-Released State Transition Timing
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Section 6 Bus Controller
6.12
6.12.1
Bus Arbitration
Overview
The H8S/2655 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.12.2 Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low)
An internal bus access by an internal bus master, external bus release, and refreshing, can be executed in parallel. In the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh > External bus release > Internal bus master external access (Low)
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Section 6 Bus Controller
6.12.3
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer.
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Section 6 Bus Controller
6.12.4
External Bus Release Usage Note
External bus release can be performed on completion of an external bus cycle. The RD signal, DRAM interface RAS and CAS signals, and PSRAM interface CE and OE signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, CAS, CE, and OE signals may change from the low level to the high-impedance state.
6.13
Resets and the Bus Controller
In a power-on reset, the H8S/2655, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed. Also, since the DMAC is initialized by a manual reset, DACK and TEND output is disabled and these pins become I/O ports controlled by DDR and DR.
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Section 7 DMA Controller
Section 7 DMA Controller
7.1 Overview
The H8S/2655 Group has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features
The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode: Maximum of 4 channels can be used Choice of dual address mode or single address mode In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits In single address mode, transfer source or transfer destination address only is specified as 24 bits In single address mode, transfer can be performed in one bus cycle Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode: Maximum of 2 channels can be used Transfer source and transfer destination address specified as 24 bits Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception complete interrupt A/D converter conversion end interrupt External request Auto-request
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Section 7 DMA Controller
7.1.2
Block Diagram
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B
Address buffer Processor
Channel 1B Channel 1A Channel 0B Channel 0A
MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B
Channel 0
Control logic
DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer
Internal data bus Legend: DMAWER : DMA write enable register DMATCR : DMA terminal control register DMABCR : DMA band control register (for all channels) DMACR : DMA control register MAR : Memory address register IOAR : I/O address register ETCR : Executive transfer counter register
Figure 7.1 Block Diagram of DMAC
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Channel 1
Module data bus
IOAR0A
Section 7 DMA Controller
7.1.3
Overview of Functions
Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7.1 (1) Overview of DMAC Functions (Short Address Mode)
Address Register Bit Length Transfer Mode Dual address mode • Sequential mode 1-byte or 1-word transfer executed for one transfer request Memory address incremented/ decremented by 1 or 2 1 to 65536 transfers • Idle mode 1-byte or 1-word transfer executed for one transfer request Memory address fixed 1 to 65536 transfers • Repeat mode 1-byte or 1-word transfer executed for one transfer request Memory address incremented/ decremented by 1 or 2 After specified number of transfers (1 to 256), initial state is restored and operation continues Single address mode • • • 1-byte or 1-word transfer executed for one transfer request Transfer in 1 bus cycle using DACK pin in place of address specifying I/O Specifiable for modes (1) to (3) • External request 24/DACK DACK/24 • • • • TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request Transfer Source Source 24/16 Destination 16/24
•
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Section 7 DMA Controller
Table 7.1 (2) Overview of DMAC Functions (Full Address Mode)
Address Register Bit Length Transfer Mode • Normal mode Auto-request Transfer request retained internally Transfers continue for the specified number of times (1 to 65536) Choice of burst or cycle steal transfer External request 1-byte or 1-word transfer executed for one transfer request 1 to 65536 transfers • Block transfer mode Specified block size transfer executed for one transfer request 1 to 65536 transfers Either source or destination specifiable as block area Block size: 1 to 256 bytes or words • TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request A/D converter conversion end interrupt 24 24 • External request • Auto-request Transfer Source Source 24 Destination 24
• • • •
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Section 7 DMA Controller
7.1.4
Pin Configuration
Table 7.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7.2
Channel 0
DMAC Pins
Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function DMAC channel 0 external request DMAC channel 0 single address transfer acknowledge DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 single address transfer acknowledge DMAC channel 1 transfer end
1
DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1
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Section 7 DMA Controller
7.1.5
Register Configuration
Table 7.3 summarizes the DMAC registers. Table 7.3 DMAC Registers
Abbreviation R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3FFF
Channel Address* Bus Width Name 0 H'FEE0 H'FEE4 H'FEE6 H'FEE8 H'FEEC H'FEEE 1 H'FEF0 H'FEF4 H'FEF6 H'FEF8 H'FEFC H'FEFE 0, 1 H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF3C Note: * 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits
Memory address register 0A MAR0A I/O address register 0A Transfer count register 0A I/O address register 0B Transfer count register 0B I/O address register 1A Transfer count register 1A I/O address register 1B Transfer count register 1B DMA write enable register DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Module stop control register IOAR0A ETCR0A IOAR0B ETCR0B IOAR1A ETCR1A IOAR1B ETCR1B DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR MSTPCR
Memory address register 0B MAR0B
Memory address register 1A MAR1A
Memory address register 1B MAR1B
DMA terminal control register DMATCR
Lower 16 bits of the address.
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Section 7 DMA Controller
7.2
Register Descriptions (1) (Short Address Mode)
Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.4
FAE0 0
Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0)
Description Short address mode specified (channels A and B operate independently)
Channel 0A
MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc.
Channel 0B
Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc.
1
Full address mode specified (channels A and B operate in combination)
MAR0A MAR0B
Channel 0
Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc.
IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B
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7.2.1
Bit MAR R/W Bit MAR R/W
Memory Address Registers (MAR)
: : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16
Initial value :
Initial value :
Legend: *: Undefined
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.
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Section 7 DMA Controller
7.2.2
Bit IOAR R/W
I/O Address Register (IOAR)
: : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Legend: *: Undefined
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode.
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Section 7 DMA Controller
7.2.3
Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode
Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Legend: *: Undefined
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. (2) Repeat Mode
Transfer Number Storage Bit ETCRH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8
Initial value :
Transfer Counter Bit ETCRL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 7 6 5 4 3 2 1 0
Initial value :
Legend: *: Undefined
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit
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Section 7 DMA Controller
in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. 7.2.4
Bit DMACR R/W
DMA Control Register (DMACR)
: : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W
Initial value :
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value)
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented.
Bit 6 DTID 0 Description MAR is incremented after a data transfer • • 1 • • When DTSZ = 0, MAR is incremented by 1 after a transfer When DTSZ = 1, MAR is incremented by 2 after a transfer When DTSZ = 0, MAR is decremented by 1 after a transfer When DTSZ = 1, MAR is decremented by 2 after a transfer (Initial value)
MAR is decremented after a data transfer
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Section 7 DMA Controller
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
Bit 5 RPE 0 1 DMABCR DTIE 0 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value)
For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode.
DMABCR SAE 0 Bit 4 DTDIR 0 1 1 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address
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Section 7 DMA Controller
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. • Channel A
Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — — — Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — (Initial value)
Activated by A/D converter conversion end interrupt
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Section 7 DMA Controller
• Channel B
Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description — (Initial value)
Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — —
Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.
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Section 7 DMA Controller
7.2.5
Bit
DMA Band Control Register (DMABCR)
: 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W
DMABCRH : Initial value : R/W :
Bit
:
7 DTME1 0 R/W
6 DTE1 0 R/W
5 DTME0 0 R/W
4 DTE0 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
DMABCRL : Initial value : R/W :
DTIE1B DTIE1A
DTIE0B DTIE0A
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels.
Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B are used as independent channels.
Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value)
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Section 7 DMA Controller
Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode.
Bit 13 SAE1 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value)
This bit is invalid in full address mode. Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode.
Bit 12 SAE0 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value)
This bit is invalid in full address mode. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting.
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Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting.
Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting.
Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting.
Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
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Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting.
Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B.
Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
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Section 7 DMA Controller
Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.
Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt.
Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
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Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt.
Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt.
Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt.
Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
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Section 7 DMA Controller
7.3
Register Descriptions (2) (Full Address Mode)
Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7.4. 7.3.1
Bit MAR R/W Bit MAR R/W
Memory Address Register (MAR)
: : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16
Initial value :
Initial value :
Legend: *: Undefined
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.
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Section 7 DMA Controller
7.3.2
I/O Address Register (IOAR)
IOAR is not used in full address transfer. 7.3.3 Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA:
Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Legend: *: Undefined
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB: ETCRB is not used in normal mode.
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Section 7 DMA Controller
(2) Block Transfer Mode ETCRA:
Holds block size Bit ETCRAH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8
Initial value :
Block size counter Bit ETCRAL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 7 6 5 4 3 2 1 0
Initial value :
Legend: *: Undefined
ETCRB:
Block Transfer Counter Bit ETCRB R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000.
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Section 7 DMA Controller
7.3.4
DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. DMACRA:
Bit DMACRA R/W : : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W
Initial value :
DMACRB:
Bit DMACRB R/W : : : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W
Initial value :
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value)
Bit 14—Source Address Increment/Decrement (SAID)
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Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARA is incremented by 1 after a transfer When DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value)
MARA is fixed MARA is decremented after a data transfer • • When DTSZ = 0, MARA is decremented by 1 after a transfer When DTSZ = 1, MARA is decremented by 2 after a transfer
Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
Bit 12 BLKDIR 0 1 Bit 11 BLKE 0 1 0 1 Description Transfer in normal mode Transfer in normal mode Transfer in block transfer mode, source side is block area (Initial value)
Transfer in block transfer mode, destination side is block area
For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Can be read or written to. Bit 6—Destination Address Increment/Decrement (DAID)
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Section 7 DMA Controller
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARB is incremented by 1 after a transfer When DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value)
MARB is fixed MARB is decremented after a data transfer • • When DTSZ = 0, MARB is decremented by 1 after a transfer When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 4—Reserved: Can be read or written to. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode
Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 * * Bit 0 DTF0 0 1 0 1 * 0 1 * Legend: *: Don’t care Description — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — Auto-request (cycle steal) Auto-request (burst) — (Initial value)
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• Block Transfer Mode
Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description — (Initial value)
Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — —
Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.
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Section 7 DMA Controller
7.3.5
Bit
DMA Band Control Register (DMABCR)
: 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W
DMABCRH : Initial value : R/W :
Bit
:
7 DTME1 0 R/W
6 DTE1 0 R/W
5 DTME0 0 R/W
4 DTE0 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
DMABCRL : Initial value : R/W :
DTIE1B DTIE1A
DTIE0B DTIE0A
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value)
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Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting.
Bit 11 DTA1 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting.
Bit 9 DTA0 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled
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Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1.
Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value)
Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0.
Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled
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Section 7 DMA Controller
Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1.
Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value)
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Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt.
Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt.
Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value)
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Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt.
Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt.
Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value)
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Section 7 DMA Controller
7.4
7.4.1
Register Descriptions (3)
DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned, The restrictions applied by DMAWER are valid for the DTC. Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels.
First transfer area
MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A
DTC
IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
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Bit DMAWER R/W : : : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W
Initial value :
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC.
Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
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Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR.
Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR.
Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted.
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Section 7 DMA Controller
7.4.2
Bit
DMA Terminal Control Register (DMATCR)
: : : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 —
DMATCR R/W
Initial value :
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 5 TEE1 0 1 Description TEND1 pin output disabled TEND1 pin output enabled (Initial value)
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
Bit 4 TEE0 0 1 Description TEND0 pin output disabled TEND0 pin output enabled (Initial value)
The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: Read-only bits, always read as 0.
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Section 7 DMA Controller
7.4.3
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15—Module Stop (MSTP15): Specifies the DMAC module stop mode.
Bits 15 MSTP15 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value)
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Section 7 DMA Controller
7.5
7.5.1
Operation
Transfer Modes
Table 7.5 lists the DMAC modes. Table 7.5 DMAC Transfer Modes
Transfer Mode Short address mode Dual (1) Sequential address mode mode (2) Idle mode (3) repeat mode Transfer Source • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmission complete interrupt • SCI reception complete interrupt Remarks • Up to 4 channels can operate independently • External request applies to channel B only • Single address mode applies to channel B only
• A/D converter • Modes (1), (2), and (3) conversion end interrupt can also be specified for single address mode • External request (4) Single address mode Full address mode (5) Normal mode (6) Block transfer mode • External request • Auto-request • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmission complete interrupt • SCI reception complete interrupt • A/D converter conversion end interrupt • External request • Max. 2-channel operation, combining channels A and B • With auto-request, burst mode transfer or cycle steal transfer can be selected
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Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Single address mode In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Modes (1), (2) and (3) can also be specified for single address mode.
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Section 7 DMA Controller
(5) Normal mode Auto-request: By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. • Cycle steal mode: The bus is released to another bus master every byte or word transfer. • Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed. External request: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block transfer mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits.
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Section 7 DMA Controller
7.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in sequential mode. Table 7.6 Register Functions in Sequential Mode
Function Register
23 MAR 23 H'FF 15 ETCR 15 IOAR 0 0 0
DTDIR = 0 Source address register
DTDIR = 1
Initial Setting
Operation
Destination Start address of Incremented/ address transfer destination or decremented register transfer source every transfer Start address of transfer source or transfer destination Number of transfers Fixed
Destination Source address address register register Transfer counter
Decremented every transfer; transfer ends when count reaches H'0000
Legend: MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
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Section 7 DMA Controller
Figure 7.3 illustrates operation in sequential mode.
Address T
Transfer
IOAR
1-byte or -word transfer performed in response to 1 transfer request
Address B
Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR
Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only.
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Figure 7.4 shows an example of the setting procedure for sequential mode.
Sequential mode setting
[1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
Set DMABCRH
Set transfer source and transfer destination addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
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Section 7 DMA Controller
7.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in idle mode. Table 7.7 Register Functions in Idle Mode
Function Register
23 MAR 23 H'FF 15 ETCR 15 IOAR 0 0 0
DTDIR = 0 Source address register
DTDIR = 1
Initial Setting
Operation Fixed
Destination Start address of address transfer destination register or transfer source Start address of transfer source or transfer destination Number of transfers
Destination Source address address register register Transfer counter
Fixed
Decremented every transfer; transfer ends when count reaches H'0000
Legend: MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
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Section 7 DMA Controller
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in response to 1 transfer request
Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set.
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Section 7 DMA Controller
Figure 7.6 shows an example of the setting procedure for idle mode.
Idle mode setting
[1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
Set DMABCRH
Set transfer source and transfer destination addresses
[2]
Set number of transfers
[3]
[4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer.
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
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Section 7 DMA Controller
7.5.4
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in repeat mode. Table 7.8 Register Functions in Repeat Mode
Function Register
23 MAR 0
DTDIR = 0 Source address register
DTDIR = 1
Initial Setting
Operation
Destination Start address of Incremented/ address transfer destination decremented register or transfer source every transfer. Initial setting is restored when value reaches H'0000 Start address of Fixed transfer source or transfer destination Number of transfers Fixed
23 H'FF
15 IOAR
0
Destination Source address address register register Holds number of transfers
7 ETCRH
0
7 ETCRL
0
Transfer counter Number of transfers
Decremented every transfer. Loaded with ETCRH value when count reaches H'00
Legend: MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit
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Section 7 DMA Controller
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)
DTID · 2DTSZ
· ETCRH
The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
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Section 7 DMA Controller
Figure 7.7 illustrates operation in repeat mode.
Address T
Transfer
IOAR
1 byte or word transfer performed in response to 1 transfer request
Address B
Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR
Figure 7.7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only.
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Section 7 DMA Controller
Figure 7.8 shows an example of the setting procedure for repeat mode.
[1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer.
Repeat mode setting
Set DMABCRH
Set transfer source and transfer destination addresses
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
Repeat mode
Figure 7.8 Example of Repeat Mode Setting Procedure
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Section 7 DMA Controller
7.5.5
Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 7.9 summarizes register functions in single address mode. Table 7.9 Register Functions in Single Address Mode
Function Register
23 MAR 0
DTDIR = 0 Source address register Write strobe
0 ETCR
DTDIR = 1
Initial Setting
Operation *
Destination Start address of address transfer destination register or transfer source Read strobe (Set automatically by SAE bit; IOAR is invalid) Number of transfers
DACK pin
Strobe for external device *
15
Transfer counter
Legend: MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit DACK : Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output.
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Section 7 DMA Controller
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
Address T
Transfer
DACK
1 byte or word transfer performed in response to 1 transfer request
Address B
Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)
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Section 7 DMA Controller
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified).
[1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer.
Single address mode setting
Set DMABCRH
[1]
Set transfer source and transfer destination addresses
Set number of transfers
[3]
Set DMACR
[4]
Set DMABCRL
[6]
Single address mode
Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified)
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Section 7 DMA Controller
7.5.6
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.10 summarizes register functions in normal mode. Table 7.10 Register Functions in Normal Mode
Register
23 MARA 23 MARB 15 ETCRA 0 0 0
Function Source address register Destination address register Transfer counter
Initial Setting Start address of transfer source Start address of transfer destination Number of transfers
Operation Incremented/decremented every transfer, or fixed Incremented/decremented every transfer, or fixed Decremented every transfer; transfer ends when count reaches H'0000
Legend: MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
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Section 7 DMA Controller
Figure 7.11 illustrates operation in normal mode.
Address TA
Transfer
Address TB
Address BA Legend: Address Address Address Address Where :
Address BB
TA TB BA BB LA LB N
= LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA
Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends.
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Section 7 DMA Controller
For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7.12 shows an example of the setting procedure for normal mode.
[1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer.
Normal mode setting
Set DMABCRH
Set number of transfers
[3]
Set DMACR
[4]
Set DMABCRL
[6]
Normal mode
Figure 7.12 Example of Normal Mode Setting Procedure
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Section 7 DMA Controller
7.5.7
Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.11 summarizes register functions in block transfer mode. Table 7.11 Register Functions in Block Transfer Mode
Register
23 MARA 23 MARB 0 0
Function Source address register Destination address register Holds block size Block size counter
Initial Setting Start address of transfer source
Operation Incremented/decremented every transfer, or fixed
Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed
7
0 ETCRAH
Block size
7 ETCRAL
15 ETCRB
0
Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000
0
Block transfer counter
Number of block transfers
Legend: MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A ETCRB : Transfer count register B
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Section 7 DMA Controller
MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
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Section 7 DMA Controller
Address TA 1st block Transfer Block area
Address TB
2nd block
Consecutive transfer of M bytes or words is performed in response to one request
Address BB
Nth block Address BA
Legend: Address Address Address Address Where :
TA TB BA BB LA LB N M
= LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (M•N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
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Section 7 DMA Controller
Address TA Block area Address BA
Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block
Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (M•N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC.
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Section 7 DMA Controller
Figure 7.15 shows the operation flow in block transfer mode.
Start (DTE = DTME = 1) No
Transfer request? Yes Acquire bus Read address specified by MARA
MARA = MARA + SAIDE • (–1)SAID • 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE • (–1)DAID • 2DTSZ ETCRAL = ETCRAL – 1 No
ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH
BLKDIR = 0
No
Yes MARB = MARB – DAIDE • (–1)DAID • 2DTSZ • ETCRAH
MARA = MARA – SAIDE • (–1)SAID • 2DTSZ • ETCRAH ETCRB = ETCRB – 1 No
ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer
Figure 7.15 Operation Flow in Block Transfer Mode
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Section 7 DMA Controller
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.16 shows an example of the setting procedure for block transfer mode.
Block transfer mode setting
[1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL.
Set DMABCRH
Set transfer source and transfer destination addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
Block transfer mode
[6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer.
Figure 7.16 Example of Block Transfer Mode Setting Procedure
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Section 7 DMA Controller
7.5.8
DMAC Activation Sources
DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7.12. Table 7.12 DMAC Activation Sources
Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode X X X X X X X X X X X X X X X X Block Transfer Mode
Activation Source Internal Interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External Requests DREQ pin falling edge input DREQ pin low-level input
Auto-request Legend: : Can be specified X : Cannot be specified
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Section 7 DMA Controller
Activation by Internal Interrupt An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by External Request If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
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Section 7 DMA Controller
Activation by Auto-Request Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7.17 shows the data bus in single address mode.
RD HWR, LWR A23 to A0 Address bus (Read) External memory
D15 to D0 (high impedance)
Data bus
H8S/2655
(Write)
External device DACK
Figure 7.17 Data Bus in Single Address Mode
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Section 7 DMA Controller
When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode. 7.5.9 Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
CPU cycle T1 φ Source address Address bus RD HWR LWR Destination address DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle
Figure 7.18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register.
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Section 7 DMA Controller
7.5.10
DMAC Bus Cycles (Dual Address Mode)
Short Address Mode Figure 7.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
DMA read φ Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead
Bus release
Bus release
Bus release
Last transfer cycle
Bus release
Figure 7.19 Example of Short Address Mode Transfer A 1-byte or 1-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0.
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Section 7 DMA Controller
Full Address Mode (Cycle Steal Mode) Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
DMA read φ Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead
Bus release
Bus release
Bus release
Last transfer cycle
Bus release
Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller
Full Address Mode (Burst Mode) Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
DMA read φ Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release DMA write DMA read DMA write DMA read DMA write DMA dead
Figure 7.21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
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Section 7 DMA Controller
Full Address Mode (Block Transfer Mode) Figure 7.22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
DMA read φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead
Figure 7.22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation.
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Section 7 DMA Controller
DREQ Pin Falling Edge Activation Timing Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.23 shows an example of DREQ pin falling edge activated normal mode transfer.
DMA read DMA write Bus release DMA read DMA write Bus release
Bus release
φ
DREQ Address bus DMA control Channel Idle
Request Transfer source Transfer destination Transfer source Transfer destination
Read
Write
Idle
Request
Read
Write
Idle
Request clear period
Request clear period
Minimum of 2 cycles [1] [2] [3]
Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
Figure 7.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
1 block transfer Bus release DMA read DMA write DMA Bus dead release 1 block transfer DMA read DMA write DMA dead Bus release
φ
DREQ Address bus DMA control Channel Idle
Request Transfer source Transfer destination Transfer source Transfer destination
Read
Write
Dead
Idle Read
Request
Write
Dead
Idle
Request clear period
Request clear period
Minimun of 2 cycles [1] [2] [3]
Minimun of 2 cycles [4] [5] [6] [7] Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
DREQ Level Activation Timing (Normal Mode) Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.25 shows an example of DREQ level activated normal mode transfer.
Bus release DMA read DMA write Bus release DMA read DMA write Bus release
φ
DREQ Address bus DMA control Channel Idle
Request Transfer source Transfer destination Transfer source Transfer destination
Read
Write
Idle
Request
Read
Write
Idle
Request clear period
Request clear period
Minimum of 2 cycles [1] [2] [3]
Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Level Activated Normal Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
Figure 7.26 shows an example of DREQ level activated block transfer mode transfer.
1 block transfer Bus release DMA read DMA right DMA Bus dead release 1 block transfer DMA read DMA right DMA dead Bus release
φ
DREQ Address bus DMA control Channel Idle
Request Transfer source Transfer destination Transfer source Transfer destination
Read
Write
Dead
Idle Read
Request
Write
Dead
Idle
Request clear period
Request clear period
Minimum of 2 cycles [1] [2] [3]
Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.26 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
7.5.11
DMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read) Figure 7.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
DMA DMA read dead
DMA read φ Address bus RD DACK TEND
DMA read
DMA read
Bus release
Bus release
Bus release
Bus Last transfer release cycle
Bus release
Figure 7.27 Example of Single Address Mode (Byte Read) Transfer
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Section 7 DMA Controller
Figure 7.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
DMA dead
DMA read φ Address bus RD DACK TEND
DMA read
DMA read
Bus release
Bus release
Bus release
Last transfer cycle
Bus release
Figure 7.28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller
Single Address Mode (Write) Figure 7.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
DMA DMA write dead
DMA write φ Address bus HWR LWR DACK TEND
DMA write
DMA write
Bus release
Bus release
Bus release
Bus Last transfer release cycle
Bus release
Figure 7.29 Example of Single Address Mode (Byte Write) Transfer
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Section 7 DMA Controller
Figure 7.30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
DMA dead
DMA write φ Address bus HWR LWR DACK TEND
DMA write
DMA write
Bus release
Bus release
Bus release
Last transfer cycle
Bus release
Figure 7.30 Example of Single Address Mode (Word Write) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller
DREQ Pin Falling Edge Activation Timing Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer.
Bus release φ DREQ Address bus DACK DMA control
Transfer source/ destination Transfer source/ destination
DMA single
Bus release
DMA single
Bus release
Idle
Single
Idle
Single
Idle
Channel
Request Minimum of 2 cycles
Request clear period
Request Minimum of 2 cycles
Request clear period
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumes [1]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
DREQ Pin Low Level Activation Timing Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.32 shows an example of DREQ pin low level activated single address mode transfer.
Bus release
Bus release φ DREQ Address bus DACK DMA control
DMA single
Bus release
DMA single
Transfer source/ destination
Transfer source/ destination
Idle
Single
Idle
Single
Idle
Channel
Request Minimum of 2 cycles
Request clear period
Request Minimum of 2 cycles
Request clear period
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumes [1]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
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Section 7 DMA Controller
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.12 Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function.
DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead
φ Internal address
Internal read signal
External address HWR, LWR TEND
Figure 7.33 Example of Dual Address Transfer Using Write Data Buffer Function Figure 7.34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory.
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Section 7 DMA Controller
DMA read
DMA single
CPU read
DMA single
CPU read
φ Internal address
Internal read signal
External address RD DACK
Figure 7.34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.13 DMAC Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.13 summarizes the priority order for DMAC channels. Table 7.13 DMAC Channel Priority Order
Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.13.
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Section 7 DMA Controller
During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA DMA write read
DMA read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write
DMA write
DMA read
DMA write
DMA read
Idle
Read
Write
Idle
Read
Write
Read
Request clear Request hold Request hold Selection
Nonselection
Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer
Channel 0A transfer
Channel 0B transfer
Figure 7.35 Example of Multi-Channel Transfer 7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O register, these DMA cycles may be executed at the same time as refresh cycles or external bus release.
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Section 7 DMA Controller
7.5.15
NMI Interrupts and DMAC
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer.
Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL Write 1 to the DTME bit.
DTE = 1 DTME = 0 Yes Set DTME bit to 1
[2]
Transfer continues
Transfer ends
Figure 7.36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt
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Section 7 DMA Controller
7.5.16
Forced Termination of DMAC Operation
If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7.37 shows the procedure for forcibly terminating DMAC operation by software.
[1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time.
Forced termination of DMAC
Clear DTE bit to 0
[1]
Forced termination
Figure 7.37 Example of Procedure for Forcibly Terminating DMAC Operation
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Section 7 DMA Controller
7.5.17
Clearing Full Address Mode
Figure 7.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure.
[1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2]
Clearing full address mode
Stop the channel
[1]
Clear FAE bit to 0
[3]
Initialization; operation halted
Figure 7.38 Example of Procedure for Clearing Full Address Mode
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Section 7 DMA Controller
7.6
Interrupts
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14 shows the interrupt sources and their priority order. Table 7.14 Interrupt Source Priority Order
Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High
Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.13. Figure 7.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0.
DTE/ DTME Transfer end/transfer break interrupt DTIE
Figure 7.39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting.
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Section 7 DMA Controller
7.7
Usage Notes
DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. Module Stop When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/suspend interrupt (DTE = 0 and DTIE = 1) • TEND pin enable (TEE = 1) • DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edgedetected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock.
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Section 7 DMA Controller
Write Data Buffer Function When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. (a) Write Data Buffer Function and DMAC Register Setting If the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. The register that controls external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (c) Write Data Buffer Function and TEND Output TEND A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin.
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Section 7 DMA Controller
Figure 7.40 shows an example in which a low level is not output at the TEND pin.
DMA read φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write
Figure 7.40 Example in Which Low Level Is Not Output at TEND Pin TEND Activation by Falling Edge on DREQ Pin DREQ DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed by detection of a low level.
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Section 7 DMA Controller
Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Internal Interrupt after End of Transfer When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them.
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Section 8 Data Transfer Controller
Section 8 Data Transfer Controller
8.1 Overview
The H8S/2655 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features
The features of the DTC are: • Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible
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Section 8 Data Transfer Controller
8.1.2
Block Diagram
Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed.
Internal address bus Interrupt controller DTC On-chip RAM
CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR
DTC service request
: DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register
Figure 8.1 Block Diagram of DTC
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MRA MRB CRA CRB DAR SAR
Interrupt request
Internal data bus
Register information
Control logic
DTVECR
DTCERA to DTCERF
Section 8 Data Transfer Controller
8.1.3
Register Configuration
Table 8.1 summarizes the DTC registers. Table 8.1
Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register
DTC Registers
Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W —* 2 —*
2 2 —* 2 —* 2 —*
Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF
1 Address* 3 —* 3 —* 3 —* 3 —* 3 —* 3 —*
—*
2
R/W R/W R/W
H'FF30 to H'FF35 H'FF37 H'FF3C
Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Addresses H'F800 to H'FBFF contain register information. When the DTC is used, do not clear the RAME bit in SYSCR to 0.
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Section 8 Data Transfer Controller
8.2
8.2.1
Register Descriptions
DTC Mode Register A (MRA)
MRA is an 8-bit register that controls the DTC operating mode.
Bit : 7 SM1 Initial value : R/W : Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined —
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1)
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Section 8 Data Transfer Controller
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode —
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer
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Section 8 Data Transfer Controller
8.2.2
Bit
DTC Mode Register B (MRB)
: 7 CHNE Undefined — 6 DISEL Undefined — 5 — Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined —
Initial value : R/W :
MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer.
Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2655 Group, and should always be written with 0.
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Section 8 Data Transfer Controller
8.2.3
Bit
DTC Source Address Register (SAR)
: 23 22 21 20 19 4 3 2 1 0
Initial value : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— R/W :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined —————
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4
Bit
DTC Destination Address Register (DAR)
: 23 22 21 20 19 4 3 2 1 0
Initial value : R/W :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined —————
Unde- Unde- Unde- Unde- Undefined fined fined fined fined —————
DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.
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Section 8 Data Transfer Controller
8.2.5
Bit
DTC Transfer Count Register A (CRA)
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRAH CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6
Bit
DTC Transfer Count Register B (CRB)
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ————————————————
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 8 Data Transfer Controller
8.2.7
Bit
DTC Enable Registers (DTCER)
: 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W
Initial value: R/W :
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn)
Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value)
DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrups and write after executing a dummy read on the relevant register.
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Section 8 Data Transfer Controller
8.2.8
Bit
DTC Vector Register (DTVECR)
: 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W :
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1.
Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] • • • When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation (Initial value)
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 4 clocks.
Figure 14.22 Example of Clocked Synchronous Transmission by DTC
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Section 14 Serial Communication Interface (SCI)
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Section 15 Smart Card Interface
Section 15 Smart Card Interface
15.1 Overview
SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.1.1 Features
Features of the Smart Card interface supported by the H8S/2655 Group are as follows. • Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer
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Section 15 Smart Card Interface
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the Smart Card interface.
Bus interface
Module data bus
Internal data bus
RDR
TDR
RxD
RSR
TSR
SCMR SSR SCR SMR
Transmission/ reception control
BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock
TxD
Parity generation Parity check
SCK
Legend: SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register
TXI RXI ERI
Figure 15.1 Block Diagram of Smart Card Interface
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Section 15 Smart Card Interface
15.1.3
Pin Configuration
Table 15.1 shows the Smart Card interface pin configuration. Table 15.1 Smart Card Interface Pins
Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
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Section 15 Smart Card Interface
15.1.4
Register Configuration
Table 15.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI). Table 15.2 Smart Card Interface Registers
Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W
2 R/(W)*
Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF
2
Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C
1
R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W
2 R/(W)*
H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF
R R/W R/W
Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.
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Section 15 Smart Card Interface
15.2
Register Descriptions
Registers added with the Smart Card interface and bits for which the function changes are described here. 15.2.1
Bit
Smart Card Mode Register (SCMR)
: 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W
Initial value : R/W :
SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value)
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Section 15 Smart Card Interface
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 15.3.4, Register Settings.
Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value)
Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function.
Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value)
15.2.2
Bit
Serial Status Register (SSR)
: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Initial value : R/W :
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR).
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Section 15 Smart Card Interface
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode.
Bit 4 ERS 0 Description [Clearing conditions] • • 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value)
[Setting condition] When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below.
Bit 2 TEND 0 Description [Clearing conditions] • • 1 • • • When 0 is written to TDRE after reading TDRE = 1 When data is written to TDR by the DMAC or DTC Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character (Initial value)
[Setting conditions]
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
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Section 15 Smart Card Interface
15.2.3
Bit
Serial Mode Register (SMR)
: 7 GM 0 GM R/W 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/E 0 O/E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W
Initial value : Set value* : R/W :
Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2.
The function of bit 7 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR).
Bit 7 GM 0 Description Normal smart card interface mode operation • • 1 • • TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) (Initial value)
GSM mode smart card interface mode operation
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bits 6 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.5, Serial Mode Register (SMR).
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Section 15 Smart Card Interface
15.2.4
Bit
Serial Control Register (SCR)
: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Initial value : R/W :
In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low.
SCMR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 SMR C/A, GM SCR Setting CKE1 CKE0 See the SCI Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCK Pin Function
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Section 15 Smart Card Interface
Port value SCK pin GM = 0 CKE1 value SCK pin GM = 1
Width undetermined
Width undetermined
Port value
Specified width
Specified width
CKE1 value
Figure 15.2 Clock Output Waveform Control
15.3
15.3.1
Operation
Overview
The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. • If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. • Only asynchronous communication is supported; there is no clocked synchronous communication function.
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Section 15 Smart Card Interface
15.3.2
Pin Connections
Figure 15.3 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground.
VCC TxD I/O RxD H8S/2655 Group Connected equipment
IC card
Figure 15.3 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
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Section 15 Smart Card Interface
15.3.3
Data Format
Figure 15.4 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Transmitting station output Receiving station output
Legend: Ds : Start bit D0 to D7 : Data bits Dp : Parity bit DE : Error signal
Figure 15.4 Smart Card Interface Data Format The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor.
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Section 15 Smart Card Interface
[4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. 15.3.4 Register Settings
Table 15.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15.3 Smart Card Interface Register Settings
Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 — Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — Bit 4 O/E BRR4 RE TDR4 ERS RDR4 — Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF
Legend: —: Unused bit.
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Section 15 Smart Card Interface
SMR Setting The GM bit controls the TEND flag set timing and clock output. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 15.3.5, Clock. BRR Setting BRR is used to set the bit rate. See section 15.3.5, Clock, for the method of calculating the value to be set. SCR Setting The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 14, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
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Section 15 Smart Card Interface
Smart Card Mode Register (SCMR) Setting The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). • Direct convention (SDIR = SINV = O/E = 0)
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. • Inverse convention (SDIR = SINV = O/E = 1)
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2655 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception).
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Section 15 Smart Card Interface
15.3.5
Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 15.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin.
B=
φ
1488 × 22n–1 × (N + 1)
× 106
Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bit/s) φ = Operating frequency (MHz) n = See table 15.4 Table 15.4 Correspondence between n and CKS1, CKS0
n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1
Table 15.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0)
φ (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065
Note: Bit rates are rounded to the nearest whole number.
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Section 15 Smart Card Interface
The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified.
N=
φ
1488 × 22n–1 × B
× 106 – 1
Table 15.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0)
φ (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 10.7136 13.00 14.2848 16.00 18.00 N Error N Error N Error 1 30 1 25 1 8.99 N Error N Error N Error 1 0.00 1 12.01 2 15.99
Table 15.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0
The bit rate error is given by the following formula:
Error (%) =
φ
1488 ×
22n-1
× B × (N + 1)
× 106 – 1
× 100
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Section 15 Smart Card Interface
15.3.6
Data Transfer Operations
Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis.
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Section 15 Smart Card Interface
Serial Data Transmission As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 15.5 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 15.5.
Serial data (1) GM = 0 TEND
Ds
Dp
DE Guard period
12.5 etu (2) GM = 1 TEND 11.0 etu
Figure 15.5 TEND Flag Set Timing
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Section 15 Smart Card Interface
If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC or DTC below.
Start Initialization Start transmission
ERS = 0? Yes
No
Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No
All data transmitted? Yes No ERS = 0? Yes Error processing
No TEND = 1? Yes Clear TE bit to 0
End
Figure 15.6 Example of Transmission Processing Flow
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Section 15 Smart Card Interface
Serial Data Reception Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 15.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0.
Start Initialization Start reception
ORER = 0 and PER = 0 Yes
No
Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0
No
All data received? Yes Clear RE bit to 0
Figure 15.7 Example of Reception Processing Flow
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Section 15 Smart Card Interface
With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DMAC or DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
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Section 15 Smart Card Interface
Specified pulse width
Specified pulse width
SCK
SCR write (CKE0 = 0)
SCR write (CKE0 = 1)
Figure 15.8 Timing for Fixing Clock Output Level Interrupt Operation There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 15.8. Table 15.8 Smart Card Mode Operating States and Interrupt Sources
Operating State Transmit Mode Receive Mode Normal operation Error Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DMAC Activation Possible Not possible Possible Not possible DTC Activation Possible Not possible Possible Not possible
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Section 15 Smart Card Interface
Data Transfer Operation by DMAC or DTC In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying out SCI setting. For details of the DMAC and DTC setting procedures, see section 7, DMA Controller, and section 8, Data Transfer Controller. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. For this reason, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
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Section 15 Smart Card Interface
15.3.7
Example of Use of Software Standby Mode
When using software standby mode in a system that uses smart card interface mode, the following procedure should be followed to maintain the serial clock pulse width. Figure 15.9 shows an example of the use of software standby mode. (1) Transition to software standby mode [1] Set DR and DDR of the I/O port corresponding to the serial clock to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in SCR to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, serial clock output is fixed at the specified level, with the pulse width maintained. [5] Write H'00 to SMR and SCMR. [6] Make the transition to software standby mode. (2) Exiting software standby mode [7] Exit software standby mode by means of an external interrupt. [8] Set the CKE1 bit in SCR to the value for the fixed output state (corresponding I/O port state) in software standby mode. [9] Set smart card interface mode and output the clock. The clock is output with the specified pulse width.
Normal operation Software standby mode Normal operation
Serial clock
[1] [2] [3]
[4] [5] [6]
[7] [8] [9]
Figure 15.9 Entering and Exiting Software Standby Mode
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Section 15 Smart Card Interface
15.3.8
Powering On
The following procedure should be used to secure the serial clock pulse width after powering on. [1] The initial state of the serial clock after powering on is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Specify the output state with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card interface mode. [4] Set the CKE0 bit in SCR to 1 to start the serial clock output.
15.4
Usage Notes
The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 15.10.
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Section 15 Smart Card Interface
372 clocks 186 clocks 0 185 371 0 185 371 0
Internal basic clock
Receive data (RXD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 15.10 Receive Data Sampling Timing in Smart Card Mode Thus the reception margin in asynchronous mode is given by the following formula.
M = (0.5 – 1 2N ) – (L – 0.5) F – D – 0.5 N (1 + F) × 100%
Where M: N: D: L: F:
Reception margin (%) Ratio of bit rate to clock (N = 372) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100% = 49.866%
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Section 15 Smart Card Interface
Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer operation when SCI is in receive mode: Figure 15.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
Transfer frame n+1
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransferred frame
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
[4]
[3]
Figure 15.11 Retransfer Operation in SCI Receive Mode
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Section 15 Smart Card Interface
Retransfer operation when SCI is in transmit mode: Figure 15.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DMAC or DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DMAC or DTC, the TDRE bit is automatically cleared to 0.
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] [8] [9] Transfer to TSR from TDR Transfer to TSR from TDR Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4
Figure 15.12 Retransfer Operation in SCI Transmit Mode
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Section 15 Smart Card Interface
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Section 16 A/D Converter
Section 16 A/D Converter
16.1 Overview
This A/D converter has 10-bit resolution, and allows up to 8 analog input channels to be selected. 16.1.1 Features
A/D converter features are listed below. • 10-bit resolution • Eight input channels • Settable analog conversion voltage range Conversion of analog voltages from 0 V to Vref, with the reference voltage pin (Vref) as the analog reference voltage • High-speed conversion Minimum conversion time: 2.2 µs per channel (at 20-MHz operation) 1.0 µs per channel in continuous conversion • Variety of conversion modes Choice of select mode or group mode Choice of single mode or scan mode Buffer operation possible Simultaneous 2-channel sampling possible • Three kinds of conversion start Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin • Eight data registers Conversion results are held in a 16-bit data register for each channel • Sample and hold function • A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion
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Section 16 A/D Converter
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the A/D converter.
D/A conversion circuit Internal data bus
AVCC Vref S&H A
Bus I/F
ADDRA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AVSS ADTRG ADDRC
Control logic Multiplexer Data bus in module
ADDRB + – CMP ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR
S&H B
8-bit timer or TPU conversion start trigger ADI interrupt
Legend: ADCR : A/D control register ADCSR : A/D control status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D
CMP : Comparator array S&H : Sample and hold circuit ADDRE : A/D data register E ADDRF : A/D data register F ADDRG : A/D data register G ADDRH : A/D data register H
Figure 16.1 Block Diagram of A/D Converter 16.1.3 Pin Configuration
Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin.
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Section 16 A/D Converter
Table 16.1 A/D Converter Pins
Pin Name Analog power supply Analog ground Reference voltage Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 A/D external trigger input Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger for starting A/D conversion
16.1.4
Register Configuration
Table 16.2 summarizes the registers of the A/D converter. Table 16.2 A/D Converter Registers
Name A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register Module stop control register Abbreviation ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR MSTPCR R/W R R R R R R R R
2 R/(W)*
Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'3FFF
1 Address*
H'FF90 H'FF92 H'FF94 H'FF96 H'FF98 H'FF9A H'FF9C H'FF9E H'FFA0 H'FFA1 H'FF3C
R/W R/W
Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev. 5.00 Sep 14, 2006 page 681 of 1060 REJ09B0331-0500
Section 16 A/D Converter
16.2
16.2.1
Bit
Register Descriptions
A/D Data Registers A to H (ADDRA to ADDRH)
: 15 — 0 — 14 — 0 — 13 — 0 — 12 — 0 — 11 — 0 — 10 0 — 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
— AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Initial value : R/W :
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the channel on which conversion was performed, and stored there. The lower 8 bits of the converted data are transferred to the lower byte (bits 7 to 0) of ADDR, and the upper 2 bits are transferred to the upper byte (bits 9 and 8). Bits 15 to 10 are always read as 0. Byte or word length can be selected for data reads. In a byte data read, the upper 8 bits of the converted data are transferred. Buffer operation is also possible by using ADDRA to ADDRD in combination. The correspondence between the analog input channels and ADDR registers is shown in table 16.3. The ADDR registers are initialized to H'0000 by a reset, and in hardware standby mode. Table 16.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Note: * A/D Data Register ADDRA* ADDRB* ADDRC* ADDRD* ADDRE ADDRF ADDRG ADDRH Except when buffer operation is used.
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Section 16 A/D Converter
16.2.2
Bit
A/D Control/Status Register (ADCSR)
: 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 CKS 0 R/W 3 GRP 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Initial value : R/W :
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7 ADF 0 Description [Clearing conditions] • • 1 When 0 is written to the ADF flag after reading ADF = 1 When the DTC or DMAC is activated by an ADI interrupt and the prescribed register is read Single mode: When conversion ends for all specified channels, and A/D conversion ends* Scan mode: When one round of conversion has been performed on all specified channels (Initial value)
[Setting conditions] • •
Note:
*
In buffer operation, the ADF flag is not set until completion of the specified buffer operation.
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Section 16 A/D Converter
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Only set the ADIE bit while conversion is stopped.
Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value)
Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG).
Bit 5 ADST 0 1 Description A/D conversion stopped • • (Initial value)
Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues until ADST is cleared to 0 by software
Bit 4—Clock Select (CKS): Sets the A/D conversion time. Set the CKS bit according to the operating frequency so that the conversion time is at least 2 µs. Only change the conversion time while conversion is stopped.
Bit 4 CKS 0 1 Description Conversion time = 24 states (A/D converter reference clock = φ) Conversion time = 44 states (A/D converter reference clock = φ/2) (Initial value)
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Section 16 A/D Converter
Bit 3—Group Mode (GRP): Selects select mode or group mode for A/D conversion channel operation. Only set the GRP bit while conversion is stopped.
Bit 3 GRP 0 1 Description Select mode Group mode (Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the GRP bit, these bits select the analog input channel(s). Only set the input channel while conversion is stopped.
Bit 2 CH2 0 Bit 1 CH1 0 1 1 0 1 Bit 0 CH0 0 1 0 1 0 1 0 1 Description Select Mode (GRP = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (Initial value) Group Mode (GRP = 1) AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 AN0 to AN4 AN0 to AN5 AN0 to AN6 AN0 to AN7
16.2.3
Bit
A/D Control Register (ADCR)
: 7 — 0 R/W 6 PWR 0 R/W 5 TRGS1 0 R/W 4 TRGS0 0 R/W 3 SCAN 0 R/W 2 DSMP 0 R/W 1 BUFE1 0 R/W 0 BUFE0 0 R/W
Initial value : R/W :
ADCR is an 8-bit readable/writable register that controls A/D conversion operations. ADCR is initialized to H'00 by a reset, and in hardware standby mode.
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Section 16 A/D Converter
Bit 7—Reserved: Always read as 0. When written to, 0 must be written. Bit 6—Power Supply Bit (PWR): Specifies the A/D converter’s conversion start mode. Setting the PWR bit to 1 sets high-speed start mode, while clearing the bit to 0 sets low-power conversion mode. For details of conversion start operations, see section 16.4.7, Conversion Start Modes. Only set the PWR bit while conversion is stopped.
Bit 6 PWR 0 1 Description Low-power conversion mode High-speed start mode (Initial value)
Bits 5 and 4—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of A/D conversion start by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped.
Bit 5 TRGS1 0 1 Bit 4 TRGS0 0 1 0 1 Description A/D conversion start by software is enabled (Initial value)
A/D conversion start by TPU conversion start trigger is enabled A/D conversion start by 8-bit timer conversion start trigger is enabled A/D conversion start by external trigger pin (ADTRG) is enabled
Bit 3—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. For operation in single mode and scan mode, see section 16.4, Operation. Only set the SCAN bit while conversion is stopped.
Bit 3 SCAN 0 1 Description Single mode Scan mode (Initial value)
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Section 16 A/D Converter
Bit 2—Simultaneous Sampling (DSMP): Enables or disables simultaneous sampling of two channels. For details of simultaneous sampling, see section 16.4.6, Simultaneous Sampling Operation. Only set the DSMP bit while conversion is stopped.
Bit 2 DSMP 0 1 Description Normal sampling operation Simultaneous sampling operation (Initial value)
Bits 1 and 0—Buffer Enable 1 and 0 (BUFE1, BUFE0): These bits specify whether or not registers ADDRB to ADDRD are to be used as buffer registers. For setting and clearing of the ADF flag in the case of buffer operation, see section 16.4.5, Buffer Operation. Only set the BUFE1 and BUFE0 bits while conversion is stopped.
Bit 1 BUFE1 0 Bit 0 BUFE0 0 1 Description Normal operation (Initial value)
ADDRA and ADDRB are used for buffer operation (conversion result → ADDRA → ADDRB) (ADDRB is the buffer register) ADDRA and ADDRC, and ADDRB and ADDRD, are used for buffer operation (conversion result 1 → ADDRA → ADDRC; conversion result 2 → ADDRB → ADDRD) (ADDRC and ADDRD are the buffer registers) ADDRA to ADDRD are used for buffer operation (conversion result → ADDRA → ADDRB → ADDRC → ADDRD) (ADDRB to ADDRD are the buffer registers)
1
0
1
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Section 16 A/D Converter
16.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode.
Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value)
16.3
Interface to Bus Master
ADDRA to ADDRH are 16-bit registers, and the data bus to the bus master is 16 bits wide. The bus master can perform either word-size or byte-size reads on ADDRA to ADDRH. In a word-size read of an ADDR register, all 16 bits of the ADDR contents are transferred to the bus master in one go. In a byte-size read of the upper byte only, the contents of the upper 8 bits (AD9 to AD2) of the transferred data (AD9 to AD0) are transferred to the bus master. Figure 16.2 illustrates the operation when reading an ADDR register.
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Section 16 A/D Converter
Word data read Data register 0 0 0 0 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Bus I/F
Internal data bus Upper 8 bits
Lower 8 bits
Byte data read Data register 0 0 0 0 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Bus I/F
Internal data bus Upper 8 bits
Figure 16.2 ADDR Read Operation
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Section 16 A/D Converter
16.4
Operation
The A/D converter has 10-bit resolution. There are four operating modes—select or group, and single or scan—which can be combined with buffer operation or simultaneous sampling operation. A single channel is selected in select mode, and a number of channels in group mode. In select mode, a single activation results in conversion on all the selected channels, while in scan mode, a single activation results in conversion repeated until stopped by software. In buffer operation, when conversion ends for the channel concerned, the previous conversion results are saved in a buffer register. In simultaneous sampling operation, analog input voltages are sampled on two channels simultaneously, and converted sequentially. A software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG input, can be selected as the conversion start condition. Either high-speed start mode or low-power conversion mode can be selected for A/D conversion by means of the PWR bit. The operating mode or input channel can be changed by rewriting ADCSR and ADCR while the ADST bit is cleared to 0. After ADCSR and ADCR have been rewritten, A/D conversion is started again when the ADST bit is set to 1. A change of operating mode or input channel and ADST bit setting can be carried out simultaneously. A/D conversion can be stopped midway by clearing the ADST bit to 0.
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Section 16 A/D Converter
16.4.1
Select Single Mode
Select single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the specified conversion start condition. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. (It can be cleared with the BCLR instruction.) Figure 16.3 shows an example of A/D converter operation when AN1 is selected in select single mode.
ADF ADST Channel 0 Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion result 1
Set to 1 by software Conversion standby
Conversion standby
Cleared automatically
Sampling 1 conversion 1
A/D
Conversion standby
Conversion standby Conversion standby
Figure 16.3 Example of A/D Converter Operation (Select Single Mode)
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Section 16 A/D Converter
16.4.2
Select Scan Mode
Select scan mode is selected when A/D conversion is to be performed repeatedly on a single channel. This mode is suitable for constantly monitoring analog input on a single channel. A/D conversion is started when the ADST bit is set to 1, according to the specified conversion start condition. The ADST bit remains set to 1 until cleared to 0 by software. During this time, A/D conversion is performed repeatedly on the selected input channel. When the first conversion operation ends, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated and A/D conversion is temporarily halted. Clearing the ADF flag to 0 when conversion has been halted by an ADI interrupt request will restart conversion. The ADF flag is cleared by writing 0 after reading ADCSR. (It can be cleared with the BCLR instruction.) Figure 16.4 shows an example of A/D converter operation when AN1 is selected in select scan mode.
ADF ADST Channel 0
Set to 1 by software Conversion standby
Cleared to 0 by software
A/D conversion 5 Channel 1
Conversion standby Sampling 1 A/D conversion 1 Sampling 2 Sampling 3 A/D conversion 2 A/D conversion 3 Sampling 4 Sampling 5 A/D conversion 4
Conversion stops
Conversion standby
Sampling 6 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD
Conversion result 1 Conversion result 2 Conversion result 3 Conversion result 4
Conversion standby Conversion standby
Figure 16.4 Example of A/D Converter Operation (Select Scan Mode)
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Section 16 A/D Converter
16.4.3
Group Single Mode
Group single mode is selected when A/D conversion is to be performed on a number of channels. A/D conversion is started when the ADST bit is set to 1, according to the specified conversion start condition. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends for all the specified input channels. On completion of conversion for all the specified input channels the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. (It can be cleared with the BCLR instruction.) Figure 16.5 shows an example of A/D converter operation when AN0 to AN2 are selected in group single mode.
ADF ADST Channel 0 Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD
Conversion standby
Set to 1 by software
Sampling 1 A/D conversion 1
Cleared automatically
Conversion standby
A/D conversion 2
Conversion standby Conversion standby Conversion standby
Sampling 2
Conversion standby
A/D conversion 3
Sampling 3
Conversion standby
Conversion result 1 Conversion result 2 Conversion result 3
Figure 16.5 Example of A/D Converter Operation (Group Single Mode)
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Section 16 A/D Converter
16.4.4
Group Scan Mode
Group scan mode is selected when A/D conversion is to be performed repeatedly on a number of channels. This mode is suitable for constantly monitoring analog input on a number of channels. A/D conversion is started when the ADST bit is set to 1, according to the specified conversion start condition. The ADST bit remains set to 1 until cleared to 0 by software. During this time, A/D conversion is performed repeatedly on the selected input channels. When the first conversion operation ends for all the selected input channels, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated and A/D conversion is temporarily halted. Clearing the ADF flag to 0 when conversion has been halted by an ADI interrupt will restart conversion. The ADF flag is cleared by writing 0 after reading ADCSR. (It can be cleared with the BCLR instruction.) Figure 16.6 shows an example of A/D converter operation when AN0 to AN2 are selected in group scan mode.
ADF ADST Channel 0 Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD
Conversion standby
Set to 1 by software
Sampling 1 A/D conversion 1 Conversion standby A/D conversion 2 Sampling 4
Cleared to 0 by software
A/D conversion 4 A/D conversion 5
Conversion stops
Conversion standby Conversion standby Conversion standby
Sampling 2
Conversion standby A/D conversion 3
Sampling 5
Sampling 3
Conversion standby
Sampling 6
Conversion result 1 Conversion result 2
Conversion result 4
Conversion result 5
Conversion result 3
Figure 16.6 Example of A/D Converter Operation (Group Scan Mode)
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Section 16 A/D Converter
16.4.5
Buffer Operation
In buffer operation, when conversion ends on the channel concerned, at the same time as the conversion result is stored in an ADDR register, the previously stored conversion result is transferred to another ADDR register. There is a choice of three kinds of buffer operation: a two-stage operation, AN0 → ADDRA → ADDRB; dual two-stage operations, AN0 → ADDRA → ADDRC and AN1 → ADDRB → ADDRD; and a four-stage operation, AN0 → ADDRA → ADDRB → ADDRC → ADDRD. When using buffer operation in combination with simultaneous sampling operation, set GRP=1, BUFE1, BUFE0=B'10, and CH2=0. Figure 16.7 shows buffer operation timing.
ADF ADST Channel 0
Conversion standby
Set to 1 by software
A/D conversion 1 Sampling 2
Cleared to 0 by software
Sampling 3 A/D conversion 2 A/D conversion 3 Sampling 4 Sampling 5 A/D conversion 4
Sampling 1
Conversion standby
Channel 1
Conversion standby
Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD
Conversion standby Conversion standby
Conversion result 1 Conversion result 2 Conversion result 1 Conversion result 3 Conversion result 2 Conversion result 4 Conversion result 3
Figure 16.7 Example of Buffer Operation (Select Scan Mode: Two-Stage Operation, CH2 to CH0 = B'001)
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Section 16 A/D Converter
Using Buffer Operation Only When conversion is performed only on the analog input channels (AN0, AN1) specified by bits BUFE1 and BUFE0, the ADF flag setting condition can be selected by selecting group mode and setting bits CH2 to CH0. Table 16.4 (1) shows the conversion operation and ADF flag setting conditions in buffer operation. The ADF flag is set on completion of the last conversion shown in the table. In single mode, conversion is halted after the ADF flag is set to 1. In scan mode, conversion continues and the conversion data is stored in order in the buffer register specified by the BUFE1 and BUFE0 bits. If the ADIE bit is set to 1 while the ADF flag is set to 1, an ADI interrupt is generated. The ADF flag is cleared to 0 by writing 0 after reading ADCSR. (It can be cleared to 0 with the BCLR instruction.) In select single mode, the conversion wait state is entered on completion of each conversion. When A/D conversion is restarted by software, a timer trigger, or an external trigger, and the number of conversions shown in table 16.4 (1) have been completed, the ADF flag is set to 1. Table 16.4 (1) Conversion Channels and ADF Flag Setting/Clearing Conditions in Buffer Operation
Setting of CH2 to CH0 CH2 0 CH1 0 1 1 — CH0 0 1 0 1 — See table 16.4 (2) BUFE1, 0=B'01 AN0 once (ADDRA) AN0 twice (ADDRB) See table 16.4 (2) Buffer Operation Selection BUFE1, 0=B'10 AN0 and AN1 once each (ADDRB) AN0 and AN1 twice each (ADDRD) BUFE1, 0=B'11 AN0 once (ADDRA) AN0 twice (ADDRB) AN0 three times (ADDRC) AN0 four times (ADDRD)
Combining Group Mode with Buffer Operation Bits CH2 to CH0 can be set to perform continuous conversion on the analog input channels (AN0, AN1) specified by bits BUFE1 and BUFE0, and AN4 to AN7. Table 16.4 (2) shows the conversion operation and ADF flag setting conditions in buffer operation. The ADF flag is set on completion of the last conversion shown in the table. In this case, the analog input corresponding to the ADDR specified in the buffer register is not converted. For example, if BUFE1 and BUFE0 = B'11, and CH2 to CH0 = B'110, the conversion results are
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Section 16 A/D Converter
stored in ADDRA and ADDRE to ADDRG. The contents of ADDRA to ADDRC prior to the start of conversion are stored in ADDRB to ADDRD. In single mode, conversion is halted after the ADF flag is set to 1. In scan mode, conversion continues. Table 16.4 (2) Conversion Channels and ADF Setting/Clearing Conditions in Buffer Operation
Setting of CH2 to CH0 CH2 0 CH1 0 1 CH0 — 0 1 1 0 0 1 1 0 1 BUFE1, 0 = B'01 See table 16.4 (1) AN0, AN2 (ADDRC) AN0, AN2, AN3 (ADDRD) AN0, AN2 to AN4 (ADDRE) AN0, AN2 to AN5 (ADDRF) AN0, AN2 to AN6 (ADDRG) AN0, AN2 to AN7 (ADDRH) AN0, AN1, AN4 (ADDRE) AN0, AN1, AN4, AN5 (ADDRF) AN0, AN1, AN4 to AN6 (ADDRG) AN0, AN1, AN4 to AN7 (ADDRH) AN0, AN4 (ADDRE) AN0, AN4, AN5 (ADDRF) AN0, AN4 to AN6 (ADDRG) AN0, AN4 to AN7 (ADDRH) See table 16.4 (1) Buffer Operation Selection BUFE1, 0 = B'10 BUFE1, 0 = B'11
Clearing the ADF Flag If the DTC or DMAC is activated by an A/D conversion end interrupt, the ADF flag is cleared when the ADDR specified in table 16.4 is read. To Reset the Number of Buffer Operations Suspend the conversion wait state or conversion, and clear the BUFE1 and BUFE0 bits to B'00. The buffer count will be cleared to 0.
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Section 16 A/D Converter
To Change the Buffer Operation Suspend the conversion wait state or conversion, and clear the BUFE1 and BUFE0 bits to B'00. When the BUFE1 and BUFE0 bits are set and conversion is restarted, the buffer operation shown in table 16.4 will be performed. 16.4.6 Simultaneous Sampling Operation
In simultaneous sampling operation, the input voltages of two channels are sampled simultaneously, and continuous conversion is performed. Simultaneous sampling operation is enabled in group mode. The channels involved in simultaneous sampling operation are determined by bits CH2 and CH1. The combinations of these bits are shown in table 16.5. For example, simultaneous sampling will be performed when CH2 and CH1 = B'11, on channel pairs AN0, AN1 → AN2, AN3 → AN4, AN5 → AN6, AN7 in that order if GRP=1. Simultaneous sampling timing is shown in figure 16.8. Table 16.5 Simultaneous Sampling Channels
Channel Setting CH2 0 1 CH1 0 1 0 1 Sampled Channels GRP = 1 AN0, AN1 AN0, AN1 → AN2, AN3 AN0, AN1 → AN2, AN3 → AN4, AN5 AN0, AN1 → AN2, AN3 → AN4, AN5 → AN6, AN7
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Section 16 A/D Converter
ADF ADST Channel 0 Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD
Conversion standby Conversion standby
Set to 1 by software
Sampling 1 A/D conversion 1 Conversion standby
Cleared automatically
Conversion standby A/D conversion 2
Sampling 2
Conversion standby Conversion standby Conversion result 1 Conversion result 2
Figure 16.8 Example of Simultaneous Sampling Operation (Group Single Mode) 16.4.7 Conversion Start Modes
The A/D converter’s conversion start mode is set by means of the PWR bit in ADCSR. When the PWR bit is cleared to 0, low-power conversion mode is set, and the internal analog circuitry is made inactive. When the PWR bit is set to 1, high-speed start mode is set, and the analog circuitry is made active. In low-power conversion mode, the analog circuit power is turned on simultaneously with the start of conversion (ADST setting), and after 200 cycles of the reference clock the analog circuitry changes to the ready state, and the first A/D conversion operation is started. The reference clock is selected by the CKS bit in ADCSR. When conversion is carried out continuously, the second and subsequent A/D conversion operations are performed every 10 cycles. When A/D conversion ends, ADST is cleared to 0 and the analog circuit power is cut automatically. Since the analog circuitry is only active during A/D conversion in this mode, current dissipation can be reduced. In high-speed start mode, even when A/D conversion ends and ADST is cleared to 0, power continues to be supplied to the analog circuitry and conversion can still be carried out. Conversion is started as soon as ADST is set to 1 again. Only in the case of the first conversion after the analog power supply is turned on, conversion does not begin until 200 cycles after ADST is set.
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Section 16 A/D Converter
The analog circuit power supply is turned off by clearing the PWR bit to 0. When conversion is carried out continuously, the second and subsequent A/D conversion operations are performed every 10 cycles. High-speed A/D conversion can be achieved in this mode since the analog circuitry is always active. Figures 16.9 and 16.10 show conversion start operation timing.
ADF Analog circuit power supply ADST Channel 0 Channel 1 Channel 2 Channel 3
Conversion standby Conversion standby Conversion standby
On Set to 1 by software
Sampling 1 A/D conversion 1
Off Cleared to 0 by software
Sampling 3 A/D conversion 3
Sampling 2
A/D conversion 2
Conversion standby 200 cycles
ADDRA ADDRB ADDRC ADDRD
Conversion result 1
Conversion result 3
Conversion result 2
Figure 16.9 Conversion Start Operation (Low-Power Conversion Mode)
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Section 16 A/D Converter
ADF Turned off by software Analog circuit power supply Turned on by software Set to 1 by software ADST Channel 0 Channel 1 Channel 2 Channel 3
Conversion standby Conversion standby Conversion standby
Set to 1 by software
Sampling 1 A/D conversion 1 Sampling 2 A/D conversion 2
Conversion standby 200 cycles
ADDRA ADDRB ADDRC ADDRD
Conversion result 1 Conversion result 2
Figure 16.10 Conversion Start Operation (High-Speed Start Mode)
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Section 16 A/D Converter
16.4.8
Starting Conversion by External Input
A/D conversion can be started by a timer conversion start trigger or a trigger signal generated by ADTRG input. When the trigger signal specified by bits TRGS1 and TRGS0 in ADCR is generated, the ADST bit in ADCSR is set to 1 and A/D conversion is started. Other operations are the same as when the ADST bit is set to 1 by software. Figure 16.11 shows the timing for setting of the ADST bit by external input.
ADTRG (external trigger) ADF ADST Channel 0 Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion result 1 Conversion standby
Conversion standby Sampling 1 A/D conversion 1
Set
Conversion standby
Conversion standby Conversion standby
Figure 16.11 Start of Conversion by ADTRG Conversion Start Trigger ADTRG
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Section 16 A/D Converter
16.4.9
A/D Conversion Time
The A/D converter has a built-in sample and hold circuit. The A/D converter performs input sampling after the elapse of time tD from the point at which the ADCSR write operation or timer compare match that set the ADST bit to 1, and then starts conversion. The A/D conversion time tCONV is the sum of the conversion start delay time tD, the input sampling time tSPL, the operation time tCP, and the ADF flag set delay time tF. A/D conversion timing is shown in figures 16.12 (1) and (2), and A/D conversion times in table 16.6.
φ Address Write signal ADST Sampling timing A/D conversion operation timing ADF tD tSPL tCONV tCP tF
Legend: tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time tCP : A/D conversion operation time tF : ADF flag set delay time
Figure 16.12 (1) A/D Conversion Timing
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Section 16 A/D Converter
φ Compare match signal ADST Sampling timing A/D conversion operation timing ADF tD tSPL tCONV tCP tF
Legend: tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time tCP : A/D conversion operation time tF : ADF flag set delay time
Figure 16.12 (2) A/D Conversion Timing Table 16.6 A/D Conversion Times
Symbol A/D conversion start delay time Input sampling time A/D conversion operation time ADF flag set delay time A/D conversion time tD tSPL tCP tF tCONV CKS = 0 3 10 10 1 24 CKS = 1 3 20 20 1 44
Note: Units: States The figures in the table are for when PWR = 1. If 200 states have not elapsed since setting of the PWR bit, conversion is not performed until 200 states have elapsed. When PWR = 0, 200 states should be added to the first A/D conversion start delay time. When conversion is carried out continuously, the second and subsequent tCONV values are obtained by subtracting tSPL.
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Section 16 A/D Converter
The CKS bit in ADCSR should be set to give the operation time, tCONV. Tables 16.7 (1) and (2) show operating frequencies and CKS bit settings. (1) When AVCC ≥ 4.5 V, tCONV ≥ 2 µs Condition: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AV CC, Vss = AV= 0 V Table 16.7 (1) Operating Frequencies and CKS Bit Settings
Conversion Time (States) 24 44 Minimum Conversion Time (µs) 20 MHz — 2.2 16 MHz — 2.8 10 MHz 2.4 4.4 8 MHz 2.8 5.5 2 MHz 12.0 22.0
CKS 0 1
Legend: —: Cannot be set.
(2) When AVCC < 4.5 V, tCONV ≥ 4 µs Condition: VCC = 2.7 to 5.5 V, AVCC = 2.7 V to 4.5 V, Vref = 2.7 V to AV CC, Vss = AVss = 0 V Table 16.7 (2) Operating Frequencies and CKS Bit Settings
Conversion Time (States) 24 44 Minimum Conversion Time (µs) 10 MHz — 4.4 8 MHz — 5.5 5 MHz 4.8 8.8 4 MHz 6.0 11.0 2 MHz 12.0 22.0
CKS 0 1
Legend: —: Cannot be set.
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Section 16 A/D Converter
16.5
Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16.8. If the ADIE bit is set to 1 in scan mode, setting the ADF flag to 1 will temporarily halt A/D conversion. A/D conversion is restarted when the ADF flag is cleared to 0. When the DTC or DMAC is activated by an ADI interrupt and the last of the specified data registers is read, the ADF flag is cleared to 0. Table 16.8 A/D Converter Interrupt Source
Interrupt Source ADI Description Interrupt due to end of conversion DTC or DMAC Activation Possible
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Section 16 A/D Converter
16.6
Usage Notes
The following points should be noted concerning the A/D converter. • Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ≤ AN0 to AN7 ≤ AVCC. • AVCC and AVSS input voltages The AVCC and AVSS input voltages should be set as follows: AVCC = VCC ±10%, AVSS = VSS. When the A/D converter is not used, set AVCC = VCC, AVSS = VSS. In standby mode, set VRAM ≤ AVCC ≤ 5.5 V, AVSS = VSS (where VRAM is the RAM standby voltage). • Vref input voltage The analog reference voltage Vref should be set as follows: Vref ≤ AVCC. When the A/D converter is not used, set Vref = VCC. In standby mode, set VRAM ≤ Vref ≤ AVCC (where VRAM is the RAM standby voltage). • Input ports When a circuit is connected to an input port, the constant should be set to a value less than the A/D converter sampling time. If the constant is large in the case of a circuit, the input voltage may not be sampled properly. • Conversion start mode There is a difference in the current dissipation between high-speed start mode and low-power conversion mode selected for A/D conversion operation according to the PWR bit setting.
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Section 16 A/D Converter
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Section 17 D/A Converter
Section 17 D/A Converter
17.1 Overview
The H8S/2655 Group includes a two-channel D/A converter. 17.1.1 Features
D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode
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Section 17 D/A Converter
17.1.2
Block Diagram
Figure 17.1 shows a block diagram of the D/A converter.
Module data bus
Bus interface DACR
Internal data bus
Vref AVCC
DADR0
8-bit DA1 D/A DA0 AVSS
Control circuit
Figure 17.1 Block Diagram of D/A Converter
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DADR1
Section 17 D/A Converter
17.1.3
Pin Configuration
Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration
Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage
17.1.4
Register Configuration
Table 17.2 summarizes the registers of the D/A converter. Table 17.2 D/A Converter Registers
Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Note: * Abbreviation DADR0 DADR1 DACR MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C
Lower 16 bits of the address.
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Section 17 D/A Converter
17.2
17.2.1
Register Descriptions
D/A Data Registers 0 and 1 (DADR0, DADR1)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Initial value : R/W :
DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 17.2.2 D/A Control Register (DACR)
Bit : 7 0 R/W 6 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
DAOE1 DAOE0 Initial value : R/W :
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel 1.
Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value)
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Section 17 D/A Converter
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel 0.
Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value)
Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits.
Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 Legend: *: Don’t care * Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled
If the H8S/2655 Group enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: Read-only bits, always read as 1.
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Section 17 D/A Converter
17.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter module stop mode.
Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value)
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Section 17 D/A Converter
17.3
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 17.2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula:
DADR contents × Vref 256
The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin.
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Section 17 D/A Converter
DADR0 write cycle
DACR write cycle
DADR0 write cycle
DACR write cycle
φ
Address
DADR0
Conversion data 1
Conversion data 2
DAOE0
DA0
High-impedance state tDCONV
Conversion result 1 tDCONV
Conversion result 2
Legend: tDCONV: D/A conversion time
Figure 17.2 Example of D/A Converter Operation
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Section 18 RAM
Section 18 RAM
18.1 Overview
The H8S/2655 Group has 4 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 18.1.1 Block Diagram
Figure 18.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFEC00 H'FFEC02 H'FFEC04
H'FFEC01 H'FFEC03 H'FFEC05
H'FFFBFE
H'FFFBFF
Figure 18.1 Block Diagram of RAM
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Section 18 RAM
18.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of SYSCR. Table 18.1 RAM Register
Name System control register Note: * Abbreviation SYSCR Lower 16 bits of the address. R/W R/W Initial Value H'01 Address* H'FF39
18.2
18.2.1
Bit
Register Descriptions
System Control Register (SYSCR)
: 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 — 1 — 0 — 0 RAME 1 R/W
Initial value : R/W :
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
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Section 18 RAM
18.3
Operation
When the RAME bit is set to 1, accesses to addresses H'FFEC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address.
18.4
Usage Notes
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0.
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Section 18 RAM
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Section 19 ROM
Section 19 ROM
19.1 Overview
The H8S/2655 has 128 kbytes of on-chip ROM (PROM or mask ROM), and the H8S/2653 has 64 kbytes. The ROM is connected to the H8S/2600 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. The PROM version of the H8S/2655 Group can be programmed with a general-purpose PROM programmer, by setting PROM mode. 19.1.1 Block Diagram
Figure 19.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000 H'000002
H'000001 H'000003
H'00FFFE H'010000 H'010002
H'00FFFF H'010001 H'010003 When EAE = 0
H'01FFFE
H'01FFFF
Figure 19.1 Block Diagram of ROM (H8S/2655)
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Section 19 ROM
19.1.2
Register Configuration
The H8S/2655’s on-chip ROM is controlled by BCRL. The register configuration is shown in table 19.1. Table 19.1 ROM Register
Initial Value Name Bus control register L Note: * Abbreviation BCRL R/W R/W Power-On Reset H'3C Manual Reset Retained Address* H'FED5
Lower 16 bits of the address.
19.2
19.2.1
Bit
Register Descriptions
Bus Control Register L (BCRL)
: 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W 2 ASS 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W
Initial value : R/W :
Enabling or disabling of part of the H8S/2655’s on-chip ROM area can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see 6.2.5, Bus Control Register L (BCRL). Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode.
Bit 5 EAE 0 1 Note: * Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2655) or a reserved area* (in the H8S/2653). Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode). (Initial value) Reserved areas should not be accessed.
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Section 19 ROM
19.3
Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in table 19.2. In normal mode, a maximum of 56 kbytes of ROM can be used. Table 19.2 Operating Modes and ROM Area
Mode Pin Operating Mode Mode 1 Normal expanded mode with on-chip ROM disabled Mode 2 Normal expanded mode with on-chip ROM enabled Mode 3 Normal single-chip mode Mode 4 Advanced expanded mode with on-chip ROM disabled Mode 5 Advanced expanded mode with on-chip ROM disabled Mode 6 Advanced expanded mode with on-chip ROM enabled Mode 7 Advanced single-chip mode Note: * 1 1 0 MD2 0 MD1 0 1 MD0 1 0 1 0 1 0 1 0 1 0 1 Enabled* Enabled (64 kbytes) Enabled* Enabled (64 kbytes) — Disabled BCRL EAE — — On-Chip ROM Disabled Enabled (56 kbytes)
128 kbytes in the H8S/2655, 64 kbytes in the H8S/2653 In H8/2655 modes 6 and 7, the on-chip ROM available after a power-on reset is the 64kbyte area comprising addresses H'000000 to H'00FFFF.
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Section 19 ROM
19.4
19.4.1
PROM Mode
PROM Mode Setting
The PROM version of the H8S/2655 Group suspends its microcontroller functions when placed in PROM mode, enabling the on-chip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 EPROM (VPP = 12.5 V). Use of a 120-pin/32-pin socket adapter enables programming with a commercial PROM programmer. Note that the PROM programmer should not be set to page mode as the H8S/2655 Group does not support page programming. Table 19.3 shows how PROM mode is selected. Table 19.3 Selecting PROM Mode
Pin Names MD2, MD1, MD0 STBY PA2, PA1 High Setting Low
19.4.2
Socket Adapter and Memory Map
Programs can be written and verified by attaching a 120-pin/32-pin socket adapter to the PROM programmer. Table 19.4 gives ordering information for the socket adapter, and figure 19.2 shows the wiring of the socket adapter. Figure 19.3 shows the memory map in PROM mode.
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Section 19 ROM
H8S/2655 Group
TFP-120 73 43 44 45 46 48 49 50 51 2 3 4 5 7 8 9 10 11 74 13 14 16 17 18 19 20 86 12 87 1, 33, 52, 76, 81 93 94 21 22 6, 15, 24, 38, 47, 59, 79, 104 103 75 113 114 115 FP-128 81 49 50 51 52 54 55 56 57 6 7 8 9 11 12 13 14 15 82 17 18 20 21 22 23 24 94 16 95 1, 39, 58, 84, 89 103 104 25 26 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100,114 113 83 123 124 125 AVSS STBY MD0 MD1 MD2 Legend: VPP Pin RES PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS
EPROM socket
Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27C101 (32 Pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32
VSS
16
Note: Pins not shown in this figure should be left open.
: Programming power supply (12.5 V) EO7 to EO0 : Data input/output EA16 to EA0 : Address input : Output enable OE : Chip enable CE : Program PGM
Figure 19.2 Wiring of 120-Pin/32-Pin Socket Adapter
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Section 19 ROM
Table 19.4 Socket Adapter
Microcontroller H8S/2655 Package 120 pin TQFP (TFP-120) 128 pin QFP (FP-128) Socket Adapter HS2655ESNS1H HS2655ESHS1H
Addresses in MCU mode H'000000
Addresses in PROM mode H'00000
On-chip PROM
H'01FFFF
H'1FFFF
Figure 19.3 Memory Map in PROM Mode
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Section 19 ROM
19.5
19.5.1
Programming
Overview
Table 19.5 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 19.5 Mode Selection in PROM Mode
Pins Mode Program Verify Program-inhibit CE L L L L H H Legend: L : Low voltage level H : High voltage level VPP : VPP voltage level VCC : VCC voltage level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input
Programming and verification should be carried out using the same specifications as for the standard HN27C101 EPROM. However, do not set the PROM programmer to page mode does not support page programming. A PROM programmer that only supports page programming cannot be used. When choosing a PROM programmer, check that it supports high-speed programming in byte units. Always set addresses within the range H'00000 to H'1FFFF. 19.5.2 Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 19.4 shows the basic high-speed programming flowchart. Tables 19.6 and 19.7 list the electrical characteristics of the chip during programming. Figure 19.5 shows a timing chart.
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Section 19 ROM
Start
Set programming/verification mode VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V
Address = 0
n=0
n + 1→ n Yes No n < 25 Program with tPW = 0.2 ms ±5% Address + 1 → address No Verification OK? Yes Program with tOPW = 0.2n ms
No Last address? Yes Set read mode VCC = 5.0 V ±0.25 V VPP = VCC
Fail
No go
All addresses read? Go End
Figure 19.4 High-Speed Programming Flowchart
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Section 19 ROM
Table 19.6 DC Characteristics in PROM Mode (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item Input high voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM EO7 to EO0, EA16 to EA0, OE, CE, PGM EO7 to EO0 EO7 to EO0 EO7 to EO0, EA16 to EA0, OE, CE, PGM Symbol Min VIH 2.4 Typ — Max VCC +0.3 Test Unit Conditions V
Input low voltage
VIL
–0.3 —
0.8
V
Output high voltage Output low voltage Input leakage current VCC current VPP current
VOH VOL | ILI |
2.4 — —
— — —
— 0.45 2
V V µA
IOH = –200 µA IOL = 1.6 mA Vin = 5.25 V/0.5 V
ICC IPP
— —
— —
40 40
mA mA
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Section 19 ROM
Table 19.7 AC Characteristics in PROM Mode (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width VCC setup time CE setup time Data output delay time Symbol tAS tOES tDS tAH tDH 2 t*
DF
Min 2 2 2 0 2 — 2 0.19
Typ — — — — — — — 0.20 — — — —
Max — — — — — 130 — 0.21 5.25 — — 150
Unit µs µs µs µs µs ns µs ms ms µs µs ns
Test Conditions Figure 19.5*
1
tVPS tPW
3
PGM pulse width for overwrite programming tOPW* tVCS tCES tOE
0.19 2 2 0
Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time and fall time ≤ 20 ns Timing reference levels: Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. tOPW is defined by the value shown in the flowchart.
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Section 19 ROM
Program Address tAS Data tDS VPP VCC VPP VCC VCC+1 VCC tVCS tVPS Input data tDH
Verify
tAH Output data tDF
CE tCES PGM tPW OE tOPW* tOES tOE
Note: * tOPW is defined by the value shown in the flowchart.
Figure 19.5 PROM Programming/Verification Timing
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Section 19 ROM
19.5.3
Programming Precautions
• Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas Technology HN27C101 specifications, VPP will be 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU. Be particularly careful about the PROM programmer’s overshoot characteristics. • Before programming, check that the MCU is correctly mounted in the PROM programmer. Overcurrent damage to the MCU can result if the index marks on the PROM programmer, socket adapter, and MCU are not correctly aligned. • Do not touch the socket adapter or MCU while programming. Touching either of these can cause contact faults and programming errors. • The MCU cannot be programmed in page programming mode. Select the programming mode carefully. • The size of the H8S/2655 PROM is 128 kbytes. Always set addresses within the range H'00000 to H'1FFFF. During programming, write H'FF to unused addresses to avoid verification errors.
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Section 19 ROM
19.5.4
Reliability of Programmed Data
An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 19.6 shows the recommended screening procedure.
Program chip and verify data
Bake chip for 24 to 48 hours at 125°C to 150°C with power off
Read and check program
Mount
Figure 19.6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is being used, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
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Section 19 ROM
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Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
20.1 Overview
The H8S/2655 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit. 20.1.1 Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
SCKCR SCK2 to SCK0
Mediumspeed divider EXTAL Oscillator XTAL
Duty adjustment circuit
φ/2 to φ/32 Bus master clock selection circuit
System clock to φ pin
Internal clock to supporting modules
Bus master clock to CPU, DTC, and DMAC
Figure 20.1 Block Diagram of Clock Pulse Generator
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Section 20 Clock Pulse Generator
20.1.2
Register Configuration
The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration. Table 20.1 Clock Pulse Generator Register
Name System clock control register Note: * Abbreviation SCKCR Lower 16 bits of the address. R/W R/W Initial Value H'00 Address* H'FF3A
20.2
20.2.1
Bit
Register Descriptions
System Clock Control Register (SCKCR)
: 7 PSTOP 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W
Initial value : R/W :
SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description Bit 7 PSTOP 0 1 Normal Operation φ output (initial value) Fixed high Sleep Mode φ output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3—Reserved: Read-only bits, always read as 0.
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Section 20 Clock Pulse Generator
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 — Description Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — (Initial value)
20.3
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 Connecting a Crystal Resonator
Circuit Configuration A crystal resonator can be connected as shown in the example in figure 20.2. Select the damping resistance Rd according to table 20.2. An AT-cut parallel-resonance crystal should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 20.2 Connection of Crystal Resonator (Example) Table 20.2 Damping Resistance Value
Frequency (MHz) Rd (Ω ) 2 1k 4 500 8 200 12 0 16 0 20 0
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Section 20 Clock Pulse Generator
Crystal Resonator Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.3 and the same resonance frequency as the system clock (φ).
CL L XTAL Rs EXTAL AT-cut parallel-resonance type
C0
Figure 20.3 Crystal Resonator Equivalent Circuit Table 20.3 Crystal Resonator Parameters
Frequency (MHz) RS max (Ω) C0 max (pF) 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7
Note on Board Design When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins.
Avoid! CL2 Signal A Signal B H8S/2655 XTAL EXTAL CL1
Figure 20.4 Example of Incorrect Board Design
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Section 20 Clock Pulse Generator
20.3.2
External Clock Input
Circuit Configuration An external clock signal can be input as shown in the examples in figure 20.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode.
EXTAL XTAL Open
External clock input
(a) XTAL pin left open
EXTAL XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 20.5 External Clock Input (Examples)
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Section 20 Clock Pulse Generator
External Clock The external clock signal should have the same frequency as the system clock (φ). Table 20.4 and figure 20.6 show the input conditions for the external clock. Table 20.4 External Clock Input Conditions
VCC = 2.7 V to 5.5 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol tEXL tEXH tEXr tEXf tCL tCH Min 40 40 — — 0.4 80 0.4 80 Max — — 10 10 0.6 — 0.6 — VCC = 5.0 V ±10% Min 20 20 — — 0.4 80 0.4 80 Max — — 5 5 0.6 — 0.6 — Unit ns ns ns ns tcyc ns tcyc ns φ ≥ 5 MHz φ < 5 MHz φ ≥ 5 MHz φ < 5 MHz Figure 22.4 Test Conditions Figure 20.6
tEXH
tEXL
EXTAL
VCC × 0.5
tEXr
tEXf
Figure 20.6 External Clock Input Timing
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Section 20 Clock Pulse Generator
20.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ).
20.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
20.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, or φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.
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Section 20 Clock Pulse Generator
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Section 21 Power-Down Modes
Section 21 Power-Down Modes
21.1 Overview
In addition to the normal program execution state, the H8S/2655 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2655 Group operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2655 Group is in high-speed mode. Table 21.1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode.
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Section 21 Power-Down Modes
Table 21.1 Operating Modes
Operating Mode High speed mode Transition Condition Clearing Oscillator Condition Functions High speed Functions Medium speed Functions Halted Functions High/ medium speed Halted Halted CPU Registers Functions Functions High speed High/ medium speed*1 High speed Halted Modules I/O Ports Registers Functions High speed Functions High speed Functions High speed Retained/ reset*2 Retained/ reset*2 Reset Retained
Control register
MediumControl register speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Instruction Interrupt
Retained Functions
Control register
Instruction
External interrupt
Retained
Halted
Retained
Pin
Halted
Halted
Undefined Halted
High impedance
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI is reset, and other on-chip supporting modules retain their state.
21.1.1
Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21.2 summarizes these registers. Table 21.2 Power-Down Mode Registers
Name Standby control register System clock control register Module stop control register H Module stop control register L Note: * Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D
Lower 16 bits of the address.
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Section 21 Power-Down Modes
21.2
21.2.1
Bit
Register Descriptions
Standby Control Register (SBYCR)
: 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 — 0 — 1 — 0 — 0 — 0 —
Initial value : R/W :
SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it.
Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction (Initial value)
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Section 21 Power-Down Modes
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 21.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made.
Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value)
Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS, OE) is retained or set to the highimpedance state in software standby mode.
Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value)
Bits 2 to 0—Reserved: Read-only bits, always read as 0.
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Section 21 Power-Down Modes
21.2.2
Bit
System Clock Control Register (SCKCR)
: 7 PSTOP 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W
Initial value : R/W :
SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description Bit 7 PSTOP 0 1 Normal Operating Mode φ output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance
Sleep Mode φ output Fixed high
Bits 6—Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 — Description Bus master in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — (Initial value)
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Section 21 Power-Down Modes
21.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 21.3 for the method of selecting on-chip supporting modules.
Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set
21.3
Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
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Section 21 Power-Down Modes
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21.1 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
φ, supporting module clock
Bus master clock
Internal address bus
SCKCR
SCKCR
Internal write signal
Figure 21.1 Medium-Speed Mode Transition and Clearance Timing
21.4
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 21 Power-Down Modes
21.5
21.5.1
Module Stop Mode
Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI are retained. After reset clearance, all modules other than DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled.
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Section 21 Power-Down Modes
Table 21.3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module DMA controller Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer Programmable pulse generator (PPG) D/A converter A/D converter — Serial communication interface (SCI) channel 2 Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 — — — — —
Note: Bit 8 and bits 4 to 0 can be read or written to, but do not affect operation.
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Section 21 Power-Down Modes
21.5.2
Usage Notes
DMAC/DTC Module Stop Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupt Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR MSTPCR should only be written to by the CPU.
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Section 21 Power-Down Modes
21.6
21.6.1
Software Standby Mode
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin. Clearing with an interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire H8S/2655 Group chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Clearing with the RES pin RES When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2655 Group chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. Clearing with the STBY pin STBY When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 21 Power-Down Modes
21.6.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21.4 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states —* 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 — 0.8 2.0 4.1 8.2 — 1.0 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 4.1 8.2 Unit ms
8.2 16.4
10.9 16.4 32.8
10.9 13.1 16.4 21.8 32.8 65.5 — 1.3 — 1.6 — 2.0 — 2.7 — 4.0 — 8.0 — µs
13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2
Legend: —: Don’t care : Recommended time setting Note: * Reserved. If set, the standby time will be 16 states.
Using an External Clock Any value can be set. Normally, use of the minimum time is recommended.
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Section 21 Power-Down Modes
21.6.4
Software Standby Mode Application Example
Figure 21.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception handling NMIEG = 1 SSBY = 1
Software standby mode (power-down mode)
Oscillation stabilization time tOSC2
NMI exception handling
SLEEP instruction
Figure 21.2 Software Standby Mode Application Example
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Section 21 Power-Down Modes
21.6.5
Usage Notes
I/O Port Status In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 6.10, Write Data Buffer Function, for details of the write data buffer function.
21.7
21.7.1
Hardware Standby Mode
Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2655 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently
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Section 21 Power-Down Modes
driven high, a transition is made to the program execution state via the reset exception handling state. 21.7.2 Hardware Standby Mode Timing
Figure 21.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation stabilization time
Reset exception handling
Figure 21.3 Hardware Standby Mode Timing (Example)
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Section 21 Power-Down Modes
21.8
φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 21.5 shows the state of the φ pin in each processing state. Table 21.5 φ Pin State in Each Processing State
DDR PSTOP Hardware standby mode Software standby mode Sleep mode Normal operating state 0 — High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high φ output φ output 1 1 High impedance Fixed high Fixed high Fixed high
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Section 22 Electrical Characteristics
Section 22 Electrical Characteristics
22.1 Absolute Maximum Ratings
Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings
Item Power supply voltage Programming voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC VPP Vin Vin Vref AVCC VAN Topr Tstg Value –0.3 to +7.0 –0.3 to +13.5 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 –55 to +125 Unit V V V V V V V °C °C °C
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
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Section 22 Electrical Characteristics
22.2
DC Characteristics
Table 22.2 lists the DC characteristics. Table 22.3 lists the permissible output currents. Table 22.2 DC Characteristics (1) Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* , Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
1
Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P67, PA4 to PA7 RES, STBY, NMI, MD2 to MD0 EXTAL Port 1, 3, 5, B to G, P60 to P63, PA0 to PA3 Port4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Port 1, 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage Input leakage current All output pins
Symbol VT VT
– + + –
Min 1.0 — 0.4 VCC –0.7
Typ — — — —
Max — VCC × 0.7 — VCC +0.3
Unit V V V V
Test Conditions
VT – VT VIH
VCC × 0.7 2.0
— —
VCC +0.3 VCC +0.3
V V
2.0 VIL –0.3 –0.3
— — —
AVCC +0.3 V 0.5 0.8 V V
VOH
VCC –0.5 3.5 — — — — —
— — — — — — —
— — 0.4 1.0 10.0 1.0 1.0
V V V V µA µA µA
I OH = –200 µA I OH = –1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 to VCC –0.5 V Vin = 0.5 to AVCC –0.5 V
All output pins VOL Port 1, A to C RES STBY, NMI, MD2 to MD0 Port 4 | I in |
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Section 22 Electrical Characteristics Item Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G Symbol I TSI Min — Typ — Max 1.0 Unit µA Test Conditions Vin = 0.5 to VCC –0.5 V
MOS input Port A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Normal operation Sleep mode Standby 3 mode* Analog power During A/D supply current and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage
–I P Cin
50 — — —
— — — —
300 80 50 15
µA pF pF pF
Vin = 0 V Vin = 0 V, f = 1 MHz, T a = 25°C
Current 2 dissipation*
4 I CC*
— — — —
80 122 (5.0 V) 60 84 (5.0 V) 0.01 — 5.0 20
mA mA µA mA
f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta
Al CC
—
16 24 (5.0 V) 0.01 2 5.0 3.0
— Al CC —
µA mA
— VRAM 2.0
0.01 —
5.0 —
µA V
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × VCC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × VCC × f [sleep mode]
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Section 22 Electrical Characteristics
Table 22.2 DC Characteristics (2) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V* , Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
1
Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P67, PA4 to PA7 RES, STBY, NMI, MD2 to MD0 EXTAL Port 1, 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Port 1, 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage
Symbol VT VT
– + + –
Min VCC × 0.2 — VCC × 0.9
Typ — — —
Max — VCC × 0.7 — VCC +0.3
Unit V V V V
Test Conditions
VT – VT VIH
VCC × 0.07 —
VCC × 0.7 VCC × 0.7
— —
VCC +0.3 VCC +0.3
V V
VCC × 0.7 VIL –0.3 –0.3
— — —
AVCC +0.3 V VCC × 0.1 VCC × 0.2 0.8 V V VCC < 4.0 V VCC = 4.0 to 5.5 V
All output pins VOH All output pins VOL Port 1, A to C
VCC –0.5 VCC –1.0 — —
— — — —
— — 0.4 1.0
V V V V
I OH = –200 µA I OH = –1 mA I OL = 1.6 mA VCC ≤ 4 V I OL = 5 mA 4.0 < VCC ≤ 5.5 V I OL = 10 mA Vin = 0.5 to VCC –0.5 V Vin = 0.5 to AVCC –0.5 V
Input leakage current
RES STBY, NMI, MD2 to MD0 Port 4
| I in |
— — —
— — —
10.0 1.0 1.0
µA µA µA
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Section 22 Electrical Characteristics Item Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G Symbol I TSI Min — Typ — Max 1.0 Unit µA Test Conditions Vin = 0.5 to VCC –0.5 V
MOS input Port A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current 2 dissipation* Normal operation Sleep mode Standby 3 mode* Analog power During A/D supply current and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage
–I P Cin
10 — — —
— — — —
300 80 50 15
µA pF pF pF
VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25°C
4 I CC*
— — — —
25 62 (3.0 V) 18 42 (3.0 V) 0.01 — 5.0 20
mA mA µA mA
f = 10 MHz f = 10 MHz Ta ≤ 50°C 50°C < Ta
Al CC
—
12 22 (3.0 V) 0.01 5.0
— Al CC —
µA mA
1.5 2.5 (3.0 V) 0.01 — 5.0 —
— VRAM 2.0
µA V
Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × VCC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × VCC × f [sleep mode]
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Section 22 Electrical Characteristics
Table 22.3 Permissible Output Currents Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Port 1, A to C Other output pins Total of 32 pins including port 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –I OH ∑ –I O H ∑ I OL Symbol I OL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA
—
—
120
mA
— —
— —
2.0 40
mA mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.3. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 22.1 and 22.2.
H8S/2655 Group
2 kΩ Port
Darlington Pair
Figure 22.1 Darlington Pair Drive Circuit (Example)
Rev. 5.00 Sep 14, 2006 page 764 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
H8S/2655 Group
600 Ω Port 1, A to C LED
Figure 22.2 LED Drive Circuit (Example)
22.3
AC Characteristics
Figure 22.3 show, the test conditions for the AC characteristics.
5V RL LSI output pin C = 90 pF: Port 1, A to F C = 30 pF: Port 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V
C
RH
Figure 22.3 Output Load Circuit
Rev. 5.00 Sep 14, 2006 page 765 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.3.1
Clock Timing
Table 22.4 lists the clock timing Table 22.4 Clock Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Condition B Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 100 35 35 — — 20 20 500 Max 500 — — 15 15 — — — Min 50 20 20 — — 10 10 500 Max 500 — — 5 5 — — — Unit ns ns ns ns ns ms ms µs Figure 22.5 Figure 21.2 Figure 22.5 Test Conditions Figure 22.4 Figure 22.4
tcyc tCH φ tCL tCr tCf
Figure 22.4 System Clock Timing
Rev. 5.00 Sep 14, 2006 page 766 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
EXTAL tDEXT VCC tDEXT
STBY
NMI tOSC1 RES tOSC1
φ
Figure 22.5 Oscillator Settling Timing
Rev. 5.00 Sep 14, 2006 page 767 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.3.2
Control Signal Timing
Table 22.5 lists the control signal timing. Table 22.5 Control Signal Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Condition B Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIRS t NMIRH t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 250 200 250 10 200 250 10 200 Max — — — — — — — — — — Min 200 20 200 200 150 10 200 150 10 200 Max — — — — — — — — — — ns ns ns ns ns Figure 22.7 Unit ns t cyc ns Test Conditions Figure 22.6
Rev. 5.00 Sep 14, 2006 page 768 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
φ tRESS RES tRESW tNMIRS NMI tNMIRH tRESS
Figure 22.6 Reset Input Timing
φ tNMIS NMI tNMIW tNMIH
IRQi (i = 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input
tIRQW tIRQH
Figure 22.7 Interrupt Input Timing
Rev. 5.00 Sep 14, 2006 page 769 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.3.3
Bus Timing
Table 22.6 lists the bus timing. Table 22.6 Bus Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS pulse width AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time1 Read data access time2 Symbol t AD t AS t AH t PCH t CSD1 t CSD2 t CSW t ASD t RSD1 t RSD2 t CASD t RDS t RDH t ACC1 t ACC2 Min — Max 40 Condition B Min — 0.5 × t cyc –15 0.5 × t cyc –10 1.5 × t cyc –20 — — 2.5 × t cyc –20 — — — — 15 0 — — Max 20 — — — 20 20 — 20 20 20 20 — — 1.0 × t cyc –25 1.5 × t cyc –25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 22.8 to Figure 22.18
— 0.5 × t cyc –30 0.5 × — t cyc –20 — 1.5 × t cyc –40 — — 40 40
— 2.5 × t cyc –40 — — — — 30 0 — — 40 40 40 40 — — 1.0 × t cyc –50 1.5 × t cyc –50
Rev. 5.00 Sep 14, 2006 page 770 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics Condition A Item Read data access time3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WCS t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD Min — — — — — Max 2.0 × t cyc –50 2.5 × t cyc –50 3.0 × t cyc –50 40 40 Condition B Min — — — — — 1.0 × t cyc –20 1.5 × t cyc –20 — 0.5 × t cyc –20 0.5 × t cyc –10 0.5 × t cyc –10 0.5 × t cyc –10 0.5 × t cyc –10 30 5 30 — — — Max 2.0 × t cyc –25 2.5 × t cyc –25 3.0 × t cyc –25 20 20 — — 30 — — — — — — — — 15 50 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 22.20 Figure 22.19 Figure 22.12 Figure 22.10 Test Conditions Figure 22.8 to Figure 22.18
1.0 × — t cyc –40 — 1.5 × t cyc –40 — 60 — 0.5 × t cyc –40 — 0.5 × t cyc –20 0.5 × — t cyc –20 — 0.5 × t cyc –20 — 0.5 × t cyc –20 60 10 60 — — — — — — 30 100 60
Rev. 5.00 Sep 14, 2006 page 771 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tAS
T2
tAH
tASD
tRSD1 RD (read) tAS
tACC2
tRSD2
tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write)
tRDS tRDH
tWRD2
tAS tWDD tWSW1
tAH tWDH
D15 to D0 (write)
Figure 22.8 Basic Bus Timing (Two-State Access)
Rev. 5.00 Sep 14, 2006 page 772 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2
T3
tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tASD tAS tAH
tRSD1 RD (read) tAS
tACC4
tRSD2
tACC5 D15 to D0 (read)
tRDS tRDH
tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2
tWRD2
tAH tWDH
Figure 22.9 Basic Bus Timing (Three-State Access)
Rev. 5.00 Sep 14, 2006 page 773 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2
TW
T3
A23 to A0
CS7 to CS0
AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH
Figure 22.10 Basic Bus Timing (Three-State Access with One Wait State)
Rev. 5.00 Sep 14, 2006 page 774 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
Tp φ
Tr
TC1
TC2
tAD A23 to A0 tAS tPCH CS5 to CS2 (RAS) tCSD2 CAS tAH
tAD
tACC4
tCSD1
tCASD
tACC1
tCASD
tACC3 D15 to D0 (read) tWRD1 HWR, LWR (write) tWCS tWDD tWDS D15 to D0 (write) tWCH
tRDS tRDH
tWRD1
tWDH
Figure 22.11 DRAM Bus Timing
Rev. 5.00 Sep 14, 2006 page 775 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
TRp φ
TRr
TRc1
TRc2
tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS tCASD
Figure 22.12 CAS-Before-RAS Refresh Timing
TRp φ tCSD2 tCSD2 TRr TRc TRc
CS5 to CS2 (RAS) tCASD CAS tCASD
Figure 22.13 Self-Refresh Timing
Rev. 5.00 Sep 14, 2006 page 776 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
Tp φ tAD A23 to A0
T1
T2
T3
tCSD2 tPCH CS5 to CS2 tCASD OE tACC3 D15 to D0 (read) tWRD1 HWR, LWR (write) tWDD D15 to D0 (write) tWDH tWRD1 tRDS tRDH tCSW tCASD tACC4 tCSD1
Figure 22.14 PSRAM Bus Timing
Rev. 5.00 Sep 14, 2006 page 777 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
TRp φ tCASD OE
TR1
TR2
TR3
tCASD
Figure 22.15 Auto Refresh Timing
TRp φ tCASD OE tCASD TR1 TR2 TR3
Figure 22.16 Self-Refresh Timing
Rev. 5.00 Sep 14, 2006 page 778 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2 or T3
T1
T2
tAD A23 to A0 tAS CS7 to CS0 tASD AS tASD tAH
tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH
Figure 22.17 Burst ROM Access Timing (Two-State Access)
Rev. 5.00 Sep 14, 2006 page 779 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2 or T3
T1
tAD A23 to A0
CS7 to CS0
AS
tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH
Figure 22.18 Burst ROM Access Timing (One-State Access)
Rev. 5.00 Sep 14, 2006 page 780 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
φ tBRQS
tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS, OE
tBACD
tBZD
Figure 22.19 External Bus Release Timing
φ tBRQOD tBRQOD
BREQO
Figure 22.20 External Bus Request Output Timing
Rev. 5.00 Sep 14, 2006 page 781 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.3.4
DMAC Timing
Table 22.7 lists the DMAC timing. Table 22.7 DMAC Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol t DRQS t DRQH t TED t DACD1 t DACD2 Min 40 10 — — — Max — — 40 40 40 Condition B Min 30 10 — — — Max — — 20 20 20 ns Figure 22.23 Figure 22.21, Figure 22.22 Unit ns Test Conditions Figure 22.24
Rev. 5.00 Sep 14, 2006 page 782 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2
A23 to A0
CS7 to CS0
AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0 , DACK1 tDACD2
Figure 22.21 DMAC Single Address Transfer Timing (Two-State Access)
Rev. 5.00 Sep 14, 2006 page 783 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2
T3
A23 to A0
CS7 to CS0
AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2
Figure 22.22 DMAC Single Address Transfer Timing (Three-State Access)
Rev. 5.00 Sep 14, 2006 page 784 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ tTED TEND0, TEND1
T2 or T3
tTED
Figure 22.23 DMAC TEND Output Timing TEND
φ tDRQS DREQ0, DREQ1 tDRQH
Figure 22.24 DMAC DREQ Intput Timing DREQ
Rev. 5.00 Sep 14, 2006 page 785 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.3.5
Timing of On-Chip Supporting Modules
Table 22.8 lists the timing of on-chip supporting modules. Table 22.8 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Item I/O PORTS Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Symbol Min t PWD t PRS t PRH t POD t TOCD t TICS t TCKS t TCKWH t TCKWL — 50 50 — — 50 50 1.5 2.5 Max 100 — — 100 100 — — — — Condition B Min — 30 30 — — 30 30 1.5 2.5 Max 50 — — 50 50 — — — — ns t cyc Figure 22.28 ns ns Figure 22.26 Figure 22.27 Unit ns Test Conditions Figure 22.25
Rev. 5.00 Sep 14, 2006 page 786 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics Condition A Item TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width WDT SCI Single edge Both edges Symbol Min t TMOD t TMRS t TMCS t TMCWH t TMCWL t WOVD t Scyc — 50 50 1.5 2.5 — 4 6 t SCKW t SCKr t SCKf t TXD 0.4 — — — 100 100 50 Max 100 — — — — 100 — — 0.6 1.5 1.5 100 — — — Condition B Min — 30 30 1.5 2.5 — 4 6 0.4 — — — 50 50 30 Max 50 — — — — 50 — — 0.6 1.5 1.5 50 — — — ns ns ns ns Figure 22.35 Figure 22.34 t Scyc t cyc ns t cyc Figure 22.32 Figure 22.33 Unit ns ns ns t cyc Test Conditions Figure 22.29 Figure 22.31 Figure 22.30 Figure 22.30
Overflow output delay time Input clock cycle Asynchronous Synchronous
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time
Receive data setup t RXS time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup converter time t RXH t TRGS
Rev. 5.00 Sep 14, 2006 page 787 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
T1 φ
T2
tPRS Port 1 to 6, A to G (read)
tPRH
tPWD Port 1 to 3, 5, 6, A to G (write)
Figure 22.25 I/O Port Input/Output Timing
φ
tPOD PO15 to PO0
Figure 22.26 PPG Output Timing
φ tTOCD Output compare output* tTICS Input capture input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 22.27 TPU Input/Output Timing
Rev. 5.00 Sep 14, 2006 page 788 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
φ tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS
Figure 22.28 TPU Clock Input Timing
φ tTMOD TMO0, TMO1
Figure 22.29 8-Bit Timer Output Timing
φ tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS
Figure 22.30 8-Bit Timer Clock Input Timing
φ
tTMRS TMRI0, TMRI1
Figure 22.31 8-Bit Timer Reset Input Timing
Rev. 5.00 Sep 14, 2006 page 789 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
φ
tWOVD WDTOVF
tWOVD
Figure 22.32 WDT Output Timing
tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf
Figure 22.33 SCK Clock Input Timing
SCK0 to SCK2 tTXD TxD0 to TxD2 transit data tRXS RxD0 to RxD2 receive data tRXH
Figure 22.34 SCI Input/Output Timing (Clock Synchronous Mode)
φ
tTRGS ADTRG
Figure 22.35 A/D Converter External Trigger Input Timing
Rev. 5.00 Sep 14, 2006 page 790 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.4
A/D Conversion Characteristics
Table 22.9 lists the A/D conversion characteristics. Table 22.9 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min 10 — — — — — — — — Typ 10 — — — — — — — — Max 10 44 20 5 ±12.0 ±12.0 ±12.0 ±0.5 ±12.0 Min 10 — — — — — — — — Condition B Typ 10 — — — — — — — — Max 10 44 20 5 ±8.0 ±8.0 ±8.0 ±0.5 ±8.0 Unit bits t cyc pF kΩ LSB LSB LSB LSB LSB
Rev. 5.00 Sep 14, 2006 page 791 of 1060 REJ09B0331-0500
Section 22 Electrical Characteristics
22.5
D/A Convervion Characteristics
Table 22.10 lists the D/A conversion characteristics Table 22.10 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications)
Condition A Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Min 8 — — — Condition B Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Unit bit µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions
22.6
Usage Notes
Although both the ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT version, a similar evaluation should also be performed using the mask ROM version.
Rev. 5.00 Sep 14, 2006 page 792 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ ( ) :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 5.00 Sep 14, 2006 page 793 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Condition Code Notation
Symbol Changes according to the result of instruction * 0 1 — Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction
Rev. 5.00 Sep 14, 2006 page 794 of 1060 REJ09B0331-0500
Table A.1
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic MOV MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd W 2 W 2 W4 B 6 B 4 B 2 B 2 B 8 B 4 B 2 Rs8→@ERd Rs8→@(d:16,ERd) Rs8→@(d:32,ERd) ERd32-1→ERd32,Rs8→@ERd Rs8→@aa:8 Rs8→@aa:16 Rs8→@aa:32 #xx:16→Rd16 Rs16→Rd16 @ERs→Rd16 B 6 @aa:32→Rd8 B 4 @aa:16→Rd8 B 2 @aa:8→Rd8 B 2 @ERs→Rd8,ERs32+1→ERs32 B 8 @(d:32,ERs)→Rd8 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— B 4 @(d:16,ERs)→Rd8 —— B 2 @ERs→Rd8 —— B 2 Rs8→Rd8 —— MOV.B #xx:8,Rd B2 #xx:8→Rd8 —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0—
Operation
I H N Z V C Normal Advanced 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2
Instruction Set
(1) Data Transfer Instructions
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 795 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size #xx
Condition Code
No. of States*1
Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic MOV MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd L L L L 10 4 6 8 L 6 L 4 L 2 L6 W 6 W 4 W 2 W 8 W 4 Rs16→@(d:16,ERd) Rs16→@(d:32,ERd) W 2 Rs16→@ERd W 6 @aa:32→Rd16 W 4 @aa:16→Rd16 W 2 W 8 @(d:32,ERs)→Rd16 —— @ERs→Rd16,ERs32+2→ERs32 — — —— —— —— —— —— MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 ——
Operation
I H N Z V C Normal Advanced 0— 0— 0— 0— 0— 0— 0— 0— 0— —— —— 0— 0— 3 5 3 3 4 2 3 5 3 3 4
Appendix A Instruction Set
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
ERd32-2→ERd32,Rs16→@ERd — — Rs16→@aa:16 Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 @(d:16,ERs)→ERd32 @(d:32,ERs)→ERd32 —— —— —— —— —— @ERs→ERd32,ERs32+4→ERs32 — — @aa:16→ERd32 @aa:32→ERd32 —— ——
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 796 of 1060 REJ09B0331-0500
0— 0— 0— 0— 0— 0— 0— 0— 3 1 4 5 7 5 5 6
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic MOV MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.L ERn PUSH PUSH.L ERn LDM LDM @SP+,(ERm-ERn) L 4 L 4 PUSH.W Rn W 2 L 4 POP.W Rn W 2 L 8 ERs32→@aa:32 @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) Repeated for each register restored STM STM (ERm-ERn),@-SP L 4 (SP-4→SP,ERn32→@SP) Repeated for each register saved MOVFPE MOVTPE MOVTPE Rs,@aa:16 MOVFPE @aa:16,Rd Cannot be used in the H8S/2655 Group Cannot be used in the H8S/2655 Group L 6 ERs32→@aa:16 L 4 10 ERs32→@(d:32,ERd) 6 ERs32→@(d:16,ERd) MOV.L ERs,@ERd L 4 ERs32→@ERd —— —— ——
Operation
I H N Z V C Normal Advanced 0— 0— 0— 0— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— —————— 4 5 7 5 5 6 3 5 3 5 7/9/11 [1]
↔↔↔↔↔↔↔↔↔↔
——————
↔↔↔↔↔↔↔↔↔↔
ERd32-4→ERd32,ERs32→@ERd — —
7/9/11 [1]
[2]
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 797 of 1060 REJ09B0331-0500
[2]
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic ADD ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX Rs,Rd ADDS ADDS #2,ERd ADDS #4,ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA SUB SUB.W #xx:16,Rd W4 SUB.B Rs,Rd B 2 DAA Rd B 2 L 2 L 2 W 2 W 2 INC.B Rd B 2 L 2 L 2 ADDS #1,ERd L 2 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 B 2 Rd8+Rs8+C→Rd8 ADDX #xx:8,Rd B2 Rd8+#xx:8+C→Rd8 L 2 ERd32+ERs32→ERd32 L6 ERd32+#xx:32→ERd32 W 2 Rd16+Rs16→Rd16 W4 Rd16+#xx:16→Rd16 — [3] — [3] B 2 Rd8+Rs8→Rd8 — ADD.B #xx:8,Rd B2 Rd8+#xx:8→Rd8 —
Operation
I H N Z V C Normal Advanced
↔ ↔ ↔ ↔
1 1 2 1
Appendix A Instruction Set
(2) Arithmetic Instructions
— [4]
3 — [4] — — 1 [5] 1 [5] 1 —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —* — * 1 1 1 1 1 1 1 1 1 1 — [3]
↔↔ ↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔↔↔
↔ ↔ ↔ ↔
↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔ ↔ ↔↔↔↔↔ ↔↔
↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 798 of 1060 REJ09B0331-0500
2
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic SUB SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX SUBX Rs,Rd SUBS SUBS #2,ERd SUBS #4,ERd DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS MULXU MULXU.W Rs,ERd W 2 MULXU.B Rs,Rd B 2 DAS Rd B 2 L 2 L 2 W 2 W 2 DEC.B Rd B 2 L 2 Rd8-1→Rd8 Rd16-1→Rd16 Rd16-2→Rd16 ERd32-1→ERd32 ERd32-2→ERd32 Rd8 decimal adjust→Rd8 L 2 ERd32-2→ERd32 ERd32-4→ERd32 SUBS #1,ERd L 2 ERd32-1→ERd32 B 2 Rd8-Rs8-C→Rd8 SUBX #xx:8,Rd B2 Rd8-#xx:8-C→Rd8 L 2 ERd32-ERs32→ERd32 L6 ERd32-#xx:32→ERd32 SUB.W Rs,Rd W 2 Rd16-Rs16→Rd16 — [3] — [4] — [4]
Operation
I H N Z V C Normal Advanced 1 3 1
↔↔↔↔↔ ↔↔↔
— —
↔↔
[5]
↔↔↔↔↔ ↔↔↔↔↔
[5]
1 1 —————— —————— —————— —— —— —— —— —— —* — — — — — *— 1 1 1 1 1 1 1 1 1
↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔
Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — Rd16×Rs16→ERd32 (unsigned multiplication) ——————
3 [6] 4 [6]
MULXS.W Rs,ERd
W
4
Rd16×Rs16→ERd32 (signed multiplication)
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 799 of 1060 REJ09B0331-0500
MULXS MULXS.B Rs,Rd B 4
——
↔↔ ↔↔
——
Rd8×Rs8→Rd16 (signed multiplication)
—— ——
4 [7] 5 [7]
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic DIVXU RdL: quotient) (unsigned division) DIVXU.W Rs,ERd W 2 DIVXU.B Rs,Rd B 2
Operation
I H N Z V C Normal Advanced 12
Appendix A Instruction Set
Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [9] — —
ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [9] — — Rd: quotient) (unsigned division)
20
DIVXS
DIVXS.B Rs,Rd
B
4
Rd16÷Rs8→Rd16 (RdH: remainder, — — [10] [9] — — RdL: quotient) (signed division)
NEG.L ERd EXTU EXTU.L ERd L EXTU.W Rd W 2 2
L
2
0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32)
—
↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔
—— 0
↔↔↔ ↔↔ ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 800 of 1060 REJ09B0331-0500
13 DIVXS.W Rs,ERd Rd8-#xx:8 2 Rd8-Rs8 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 W 4 ERd32÷Rs16→ERd32 (Ed: remainder, — — [10] [9] — — Rd: quotient) (signed division) CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.W Rd W NEG.B Rd B L L6 W W4 B CMP.B #xx:8,Rd B2 — — 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 1 1 1 —— 0 0— 0— 1 1 21
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
—
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa
@–ERn/@ERn+
Mnemonic EXTS ( of Rd16) ( of ERd32)→ ( of ERd32) EXTS.W Rd W 2 ( of Rd16)→ ——
Operation
I H N Z V C Normal Advanced
↔ ↔
0—
1
↔
↔
TAS TAS @ERd ( of @ERd) MAC MAC @ERn+,@ERm+ — 4 B 4
@ERd-0→CCR set, (1)→
@ERn×@ERm+MAC→MAC (signed multiplication) ERn+2→ERn,ERm+2→ERm
— —— — — — [11] [11] [11]
↔
——
↔
EXTS.L ERd
L
2
——
0—
1
0—
4
4
CLRMAC CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd L 2 L 2 L 2 L 2 — 2 LDMAC
0→MACH,MACL ERs→MACH ERs→MACL MACH→ERd MACL→ERd
— —— — — — — —— — — — — —— — — — —— —— — —
2 [12] 2 [12] 2 [12] 1 [12] 1 [12]
↔↔ ↔↔ ↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 801 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd L W 2 2 B 2 L 4 L6 W 2 W4 B 2 B2 L 4 L6 W 2 W4 Rd16∨Rs16→Rd16 ERd32∨#xx:32→ERd32 ERd32∨ERs32→ERd32 Rd8⊕#xx:8→Rd8 Rd8⊕Rs8→Rd8 Rd16⊕#xx:16→Rd16 Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 ERd32⊕ERs32→ERd32 ¬ Rd8→Rd8 ¬ Rd16→Rd16 ¬ ERd32→ERd32 B 2 Rd8∨Rs8→Rd8 Rd16∨#xx:16→Rd16 B2 Rd8∨#xx:8→Rd8 L 4 ERd32∧ERs32→ERd32 L6 ERd32∧#xx:32→ERd32 W 2 Rd16∧Rs16→Rd16 W4 Rd16∧#xx:16→Rd16 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— B 2 Rd8∧Rs8→Rd8 —— B2 Rd8∧#xx:8→Rd8 ——
Operation
I H N Z V C Normal Advanced 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1
(3) Logical Instructions
Appendix A Instruction Set
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 802 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
(4) Shift Instructions
Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd MSB SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L 2 L 2 W 2 W 2 C MSB LSB B 2 0 B 2 L 2 L 2 W 2 W 2 LSB C B 2 B 2 L 2 L 2 W 2 C MSB LSB W 2 0 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— B 2 —— B 2 ——
Operation
I H N Z V C Normal Advanced 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 803 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 — — — — — — MSB — — LSB C W 2 — C W 2 — MSB LSB B 2 — B 2 — L 2 — L 2 — W 2 — MSB LSB C W 2 — 0 B 2 — B 2 — —— 0
Operation
I H N Z V C Normal Advanced 0 0 0 —— 0 0 —— 0 0 —— 0 —— —— —— —— —— —— —— —— —— —— —— —— 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Appendix A Instruction Set
—— 0
↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
—— 0
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 804 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd C MSB ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L 2 L 2 — 1 W 2 W 2 — MSB LSB C B 2 — B 2 — L 2 L 2 W 2 LSB W 2 B 2 B 2 —— —— —— —— —— —— —— —— —— —— —— ——
Operation
I H N Z V C Normal Advanced 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 805 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B B B 4 4 6 B 2 B 8 B 6 B 4 B 4 BCLR #xx:3,Rd B 2 B 8 B 6 B 4 (Rn8 of @aa:8)←1 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 (#xx:3 of @ERd)←0 (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 (#xx:3 of @aa:32)←0 (Rn8 of Rd8)←0 (Rn8 of @ERd)←0 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 B 4 (Rn8 of @ERd)←1 B 2 (Rn8 of Rd8)←1 B 8 (#xx:3 of @aa:32)←1 B 6 (#xx:3 of @aa:16)←1 B 4 (#xx:3 of @aa:8)←1 B 4 (#xx:3 of @ERd)←1 B 2 (#xx:3 of Rd8)←1
Operation
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5
Appendix A Instruction Set
(5) Bit-Manipulation Instructions
Rev. 5.00 Sep 14, 2006 page 806 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
—
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa
Mnemonic BCLR BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd [¬ (#xx:3 of @ERd)] BNOT #xx:3,@aa:8 [¬ (#xx:3 of @aa:8)] BNOT #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)← [¬ (#xx:3 of @aa:16)] BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)← [¬ (#xx:3 of @aa:32)] BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] B 4 (#xx:3 of @aa:8)← B 4 (#xx:3 of @ERd)← B 2 BCLR Rn,@aa:32 B 8 (Rn8 of @aa:32)←0
Operation
I H N Z V C Normal Advanced —————— 6 1 —————— 4
(#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — —
——————
4
——————
5
——————
6
—————— (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← [¬ (Rn8 of @aa:16)] ——————
1 4 4 5
BNOT Rn,@aa:32
B
8
(Rn8 of @aa:32)← [¬ (Rn8 of @aa:32)]
——————
6
BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B B B
BTST #xx:3,Rd
B
2 4 4 6
¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z
——— ——— ——— ———
—— —— —— ——
1 3 3 4
↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 807 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic BTST BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,@ERd BST #xx:3,@aa:8 B B BST #xx:3,Rd B 2 4 4 B B 6 8 B 4 B 4 BILD #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 (#xx:3 of Rd8)→C (#xx:3 of @ERd)→C (#xx:3 of @aa:8)→C (#xx:3 of @aa:16)→C (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C ¬ (#xx:3 of @ERd)→C ¬ (#xx:3 of @aa:8)→C ¬ (#xx:3 of @aa:16)→C ¬ (#xx:3 of @aa:32)→C C→(#xx:3 of Rd8) C→(#xx:3 of @ERd) C→(#xx:3 of @aa:8) B 8 ¬ (Rn8 of @aa:32)→Z B 6 ¬ (Rn8 of @aa:16)→Z B 4 ¬ (Rn8 of @aa:8)→Z B 4 ¬ (Rn8 of @ERd)→Z B 2 ¬ (Rn8 of Rd8)→Z B 8 ¬ (#xx:3 of @aa:32)→Z ——— ——— ——— ——— ——— ———
Operation
I H N Z V C Normal Advanced —— —— —— —— —— —— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 —————— —————— —————— 1 4 4
Appendix A Instruction Set
↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 808 of 1060 REJ09B0331-0500
↔↔↔↔↔↔
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,@ERd B BOR #xx:3,Rd B 2 4 B B B B 4 4 6 8 BIAND #xx:3,Rd B 2 B 8 B 6 B 4 B 4 BAND #xx:3,Rd B 2 B 8 B 6 B 4 ¬ C→(#xx:3 of @aa:8) ¬ C→(#xx:3 of @aa:16) ¬ C→(#xx:3 of @aa:32) C∧(#xx:3 of Rd8)→C C∧(#xx:3 of @ERd)→C C∧(#xx:3 of @aa:8)→C C∧(#xx:3 of @aa:16)→C C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @ERd)]→C C∧[¬ (#xx:3 of @aa:8)]→C C∧[¬ (#xx:3 of @aa:16)]→C C∧[¬ (#xx:3 of @aa:32)]→C C∨(#xx:3 of Rd8)→C C∨(#xx:3 of @ERd)→C B 4 ¬ C→(#xx:3 of @ERd) B 2 ¬ C→(#xx:3 of Rd8) B 8 C→(#xx:3 of @aa:32) B 6 C→(#xx:3 of @aa:16)
Operation
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3
↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 809 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic BOR BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B B B 4 4 6 8 BIXOR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 BXOR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 C∨[¬ (#xx:3 of @ERd)]→C C∨[¬ (#xx:3 of @aa:8)]→C C∨[¬ (#xx:3 of @aa:16)]→C C∨[¬ (#xx:3 of @aa:32)]→C C⊕(#xx:3 of Rd8)→C C⊕(#xx:3 of @ERd)→C C⊕(#xx:3 of @aa:8)→C C⊕(#xx:3 of @aa:16)→C C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C C⊕[¬ (#xx:3 of @ERd)]→C C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C C⊕[¬ (#xx:3 of @aa:32)]→C BIOR #xx:3,Rd B 2 C∨[¬ (#xx:3 of Rd8)]→C B 8 C∨(#xx:3 of @aa:32)→C B 6 C∨(#xx:3 of @aa:16)→C B 4 C∨(#xx:3 of @aa:8)→C
Operation
I H N Z V C Normal Advanced ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5
Appendix A Instruction Set
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Rev. 5.00 Sep 14, 2006 page 810 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operation Condition Code
Branching Condition
Operand Size
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
Mnemonic Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 — — — — 2 4 2 4 V=0 — 4 Z=1 — 2 — 4 Z=0 — 2 — 4 C=1 — 2 — 4 C=0 — 2 — 4 C∨Z=1 — 2 C∨Z=0 — 4 — 2 else next; Never — 4 PC←PC+d — 2 if condition is true then Always
@–ERn/@ERn+
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3
(6) Branch Instructions
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 811 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operation Condition Code
Branching Condition
Operand Size
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic Bcc BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 — 4 — 2 — 4 — 2 — 4 — 2 — 4 N⊕V=1 — 2 — 4 N⊕V=0 — 2 N=1 — 4 — 2 N=0 — 4 BVS d:8 — 2 V=1
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 2 3 2 3 2 3 2 3 2 3
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 812 of 1060 REJ09B0331-0500
Z∨(N⊕V)=0 — — — — — — —————— Z∨(N⊕V)=1 — — — — — — —————— 2 3 2 3
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic JMP JMP @aa:24 JMP @@aa:8 BSR BSR d:16 JSR JSR @aa:24 JSR @@aa:8 RTS RTS — — 2 2 PC←@SP+ — 4 JSR @ERn — 2 PC→@-SP,PC←ERn PC→@-SP,PC←aa:24 PC→@-SP,PC←@aa:8 — 4 PC→@-SP,PC←PC+d:16 BSR d:8 — 2 PC→@-SP,PC←PC+d:8 — 2 PC←@aa:8 — 4 PC←aa:24 JMP @ERn — 2 PC←ERn
Operation
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— —————— —————— 4 3 4 3 4 4 4 2 3 5 4 5 4 5 6 5
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 813 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code Operation PC→@-SP,CCR→@-SP, EXR→@-SP,→PC
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic TRAPA EXR←@SP+,CCR←@SP+, TRAPA #xx:2 —
I H N Z V C Normal Advanced 1 ————— 7 [13] 8 [13]
Appendix A Instruction Set
↔
↔ ↔ ↔ ↔
(7) System Control Instructions
PC←@SP+ SLEEP LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W W W W W 4 6 6 8 8 W 4 W 10 W 10 W 6 W 6 W 4 W 4 @ERs→CCR @ERs→EXR @(d:16,ERs)→CCR @(d:16,ERs)→EXR @(d:32,ERs)→CCR @(d:32,ERs)→EXR @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR @aa:32→EXR B 2 Rs8→EXR B 2 Rs8→CCR B4 #xx:8→EXR LDC #xx:8,CCR B2 #xx:8→CCR SLEEP — Transition to power-down state —————— 2
↔
RTE
RTE
—
5 [13]
↔
↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔
——————
↔
↔
↔ ↔ ↔ ↔
——————
↔
↔ ↔ ↔ ↔ ↔
——————
↔
↔ ↔ ↔ ↔ ↔
——————
↔
↔ ↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔ ↔
↔
Rev. 5.00 Sep 14, 2006 page 814 of 1060 REJ09B0331-0500
——————
↔
1 2 1 1 3 3 4 4 6 6 4 —————— 4 4 —————— 4 5 —————— 5
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@–ERn/@ERn+ @(d,PC) @@aa —
Mnemonic Operation CCR→Rd8 EXR→Rd8 4 4 6 6 10 10 4 4 6 6 8 8 EXR→@(d:32,ERd) EXR→@(d:16,ERd) CCR→@(d:32,ERd) CCR→@(d:16,ERd) EXR→@ERd CCR→@ERd STC STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR NOP NOP B2 B4 — B4 B2 B4 B2 W W W W W W W W W W W W B 2 STC CCR,Rd B 2
I H N Z V C Normal Advanced —————— —————— —————— —————— —————— —————— —————— —————— 1 1 3 3 4 4 6 6 4 —————— —————— 4 4
ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd CCR→@aa:16 EXR→@aa:16 CCR→@aa:32 EXR→@aa:32 CCR∧#xx:8→CCR EXR∧#xx:8→EXR CCR∨#xx:8→CCR EXR∨#xx:8→EXR CCR⊕#xx:8→CCR EXR⊕#xx:8→EXR 2 PC←PC+2
—————— —————— ——————
4 5 5
↔ ↔ ↔
↔ ↔
↔
1 —————— 2
↔ ↔ ↔
↔ ↔
↔
1 —————— 2
↔ ↔ ↔
↔ ↔
↔
1 —————— —————— 2 1
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 815 of 1060 REJ09B0331-0500
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa @(d,PC) @@aa —
@–ERn/@ERn+
Mnemonic EEPMOV EEPMOV.B — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next;
Operation
I H N Z V C Normal Advanced —————— 4+2n*2
Appendix A Instruction Set
(8) Block Transfer Instructions
Rev. 5.00 Sep 14, 2006 page 816 of 1060 REJ09B0331-0500
EEPMOV.W — —————— 4+2n*2 Notes: 1. 2. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. Cannot be used in the H8S/2655 Group. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. One additional state is required for execution immediately after a MULXU, MULXS, or STMAC instruction. Also, a maximum of three additional states are required for execution of a MULXU instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and a MULXU instruction, the MULXU instruction will be two states longer. A maximum of two additional states are required for execution of a MULXS instruction within two states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and a MULXS instruction, the MULXS instruction will be one state longer. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. MAC instruction results are indicated in the flags when the STMAC instruction is executed. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. One additional state is required for execution when EXR is valid.
Appendix A Instruction Set
A.2
Instruction Codes
Table A.2 shows the instruction codes.
Rev. 5.00 Sep 14, 2006 page 817 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 8 IMM rs 1 IMM rs 1 0 erd IMM 1 ers 0 erd 0 0 erd 0 erd 0 erd IMM rs IMM rs 6 IMM rs 6 0 erd 0 0 ers 0 erd IMM 4 IMM 0 IMM 0 erd abs 1 3 disp 0 disp 1 0 disp 0 disp 0 0 abs abs 7 6 0 IMM 0 0 IMM 7 6 rd 0 0 7 6 0 IMM 0 7 6 0 IMM 0 1 0 6 6 6 IMM F rd rd rd rd 8 9 rd rd rd 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L L L L B B B B W W L L B B B B B B B — — — — ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #2,ERd ADDS #4,ERd ADDX ADDX Rs,Rd AND AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,EXR BAND BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BRA d:8 (BT d:8) BAND #xx:3,Rd ANDC #xx:8,CCR AND.B #xx:8,Rd ADDX #xx:8,Rd ADDS #1,ERd ADD
Instruction Format 10th byte
Table A.2 Instruction Codes
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 818 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D 0 disp E disp F 8 0 disp 0 disp disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Bcc
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 819 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 7 7 7 abs 1 abs 0 IMM 7 0 IMM 2 0 abs 3 rn 0 erd abs 1 abs abs 6 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 7 6 0 1 IMM 0 7 6 1 IMM 0 abs 1 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 0 7 7 1 IMM 0 7 7 1 IMM 0 abs 1 3 1 IMM 0 erd abs 1 3 0 0 7 0 7 4 4 rd 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 0 0 7 7 0 7 7 0 rd 0 0 7 6 0 7 6 0 rd 8 8 6 2 rn 0 2 rn 0 6 2 rn 0 0 6 2 rn 0 rd 8 8 7 2 0 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 A A E C 4 A A E C 7 A A E C 6 A A F D 2 A A F 0 IMM 7 2 0 D 0 IMM 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIOR #xx:3,Rd BILD #xx:3,Rd BIAND #xx:3,Rd BCLR
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 820 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 6 1 IMM 0 erd abs 1 abs abs 6 7 1 IMM 1 IMM 3 1 IMM 0 erd abs 1 abs abs 1 IMM 3 0 IMM 0 erd abs 1 abs abs 3 0 IMM 0 erd abs 1 abs abs 3 rn 0 erd abs 1 3 8 8 6 0 6 1 1 abs abs rd rn rn 0 0 6 1 rn 0 6 1 rn 0 8 8 7 0 IMM 1 0 7 1 0 IMM 0 7 1 0 IMM 0 0 0 IMM 7 1 0 rd 0 0 7 7 7 0 IMM 7 0 0 IMM 0 7 7 0 IMM 0 0 0 IMM 7 7 0 rd 0 0 7 5 0 7 5 1 IMM 0 7 1 IMM 5 0 0 1 IMM 7 5 0 rd 8 8 6 7 0 0 6 1 IMM 7 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BNOT #xx:3,Rd BLD #xx:3,Rd BIXOR #xx:3,Rd BIST
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 821 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 7 0 IMM 0 erd abs 1 abs abs 7 0 IMM 4 0 0 IMM 3 0 IMM 0 erd abs 1 abs abs 7 0 IMM 3 rn 0 erd abs 1 abs abs 3 disp 0 disp 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd 0 0 rd 0 C 6 3 rn 0 0 7 7 rd 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 abs abs 6 7 0 IMM 0 0 IMM 6 7 0 0 6 7 0 IMM 0 6 7 0 IMM 0 rd 0 8 8 6 0 6 0 rn 0 rn 0 6 0 rn 0 0 6 0 rn 0 rd 8 8 7 0 0 0 0 IMM 0 7 0 IMM 0 0 0 0 IMM 7 0 0 rd 0 0 7 4 0 7 0 IMM 4 0 0 0 IMM 7 4 0 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 3 A A E C 3 A A F D 7 C 5 A A F D 0 A A F D 0 A A E C 4 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:16 BST BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST #xx:3,Rd BST #xx:3,Rd BSR d:8 BSET #xx:3,Rd BOR
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 822 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 7 6 6 7 7 7 6 6 0 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B B 5 D 3 rs 1 rs rd 0 erd C 4 5 5 9 9 8 8 F F 1 D 0 1 D 0 5 5 B 0 erd 1 3 rs rs rd 0 erd F B 0 erd 7 B D rd B 5 rd A 0 rd F 0 rd F 0 rd F 1 ers 0 erd A 0 erd IMM 2 D rs rd 9 IMM 2 rd C rs rd rd IMM 1 A 0 A 3 abs 0 7 5 A abs 0 IMM 1 0 7 5 0 0 IMM 0 E abs 0 IMM 7 5 0 C 0 IMM 0 erd 0 7 5 0 5 0 IMM rd A 3 abs 0 6 3 rn 0 A abs 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B — B B W W L L B B B W W L L B W B W — — BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.W Rs,ERd DIVXU DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W DIVXU.B Rs,Rd DIVXS.B Rs,Rd DEC.B Rd DAS Rd DAA Rd CMP.B #xx:8,Rd BXOR #xx:3,Rd BTST
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 823 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 4 4 4 4 4 4 4 4 4 1 1 0 1 0 1 0 7 7 6 6 6 6 1 6 0 6 F F 8 8 D D B B 1 6 9 0 6 9 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 rs 0 0 0 0 0 0 0 0 0 0 disp disp 6 6 B B disp disp 2 2 0 0 disp disp rs 1 0 7 0 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 0 ern B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L — — — — — — B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU EXTU.L ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @aa:24 JMP @@aa:8 JSR JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC #xx:8,CCR JSR @ERn JMP @ERn INC.B Rd EXTU.W Rd EXTS
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 824 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 0 0 0 0 ern+1 0 ern+2 0 ern+3 abs 0 0 0 0 0 0 ers 0 ers 0 0 ern 0 erm IMM rs 0 ers 0 ers disp 6 A 2 rd disp 0 ers 0 ers abs 0 abs abs 2 1 erd 1 erd disp 6 A A rs disp 0 erd 1 erd abs 8 A 0 rs 0 ers 0 ers 8 0 ers rd rd rd rd F 0 6 B disp 2 rd disp rs IMM rs abs abs rs 0 rs rs rd rd rd 0 rd rd rd 6 D 0 0 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 9 D 9 A A rs C 8 E 8 A A rd C 8 E 8 C rd 1 6 3 3 3 2 1 3 0 6 D 7 1 2 0 6 D 7 1 1 0 6 D 7 1 4 1 6 B 2 1 abs 4 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L — B B B B B B B B B B B B B B B B W W W W W LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV LDC
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 825 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 6 0 ers 0 abs abs 2 1 erd 1 erd disp 6 disp B A rs 0 erd 1 erd 8 abs abs IMM A 0 0 erd 1 ers 0 erd 0 0 ers 0 erd 0 ers 0 erd disp 6 B 2 0 erd disp 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp abs abs 0 0 0 0 0 0 0 0 0 0 0 0 4 C C C rs rs 2 rs 0 0 rd 0 erd 5 5 0 2 rd 0 6 0 6 B B abs abs rs rs rd 0 erd 0 6 D 0 7 8 0 6 F 0 6 9 0 6 B 0 6 B 0 6 D 0 7 8 0 6 F 0 6 9 rs rs rs 0 rs rs rd rd 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 0 0 5 5 0 1 1 A A 1 1 1 1 1 1 1 1 1 1 1 1 F A B B D 8 F 9 B B D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)* L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.W Rs,ERd MULXU MULXU.W Rs,ERd W MULXU.B Rs,Rd B W MULXS.B Rs,Rd B B B L L L MOV
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 826 of 1060 REJ09B0331-0500
1 erd 0 ers 8 A 0 ers 0 ers abs abs
Instruction Mnemonic Size 1st byte 1 1 1 0 1 1 1 C IMM rs 4 IMM rs 4 0 erd 0 6 4 0 ers 0 erd IMM 4 0 4 IMM 7 0 6 D 7 0 ern F 0 6 D F 8 C 9 D B 0 erd 0 erd F rd rd rd rd 0 rn 0 ern 0 rn 1 IMM F rd rd rd 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 0 erd 3 7 1 rd 7 0 rd 0 0 0 7 0 erd B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L — B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOT.W Rd NOT.L ERd OR OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd POP.W Rn OR.B #xx:8,Rd NOT.B Rd NOP NEG
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 827 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — — B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd RTS SHAL ROTR
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 828 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 6 6 6 6 0 1 4 4 1 1 4 0 1 7 7 6 6 1 0 1 9 9 F F 8 8 D D 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 4 1 4 1 4 1 4 1 4 2 1 2 0 1 8 1 7 1 3 1 5 1 1 1 4 1 0 0 7 0 3 0 5 0 1 0 4 0 0 1 F 1 B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd W W STC SHLR.B Rd SHAR
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 829 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 0 abs abs abs abs 0 0 0 0 0 ern 0 ern 0 ern 0 0 0 0 1 7 IMM 1 7 IMM 1 1 1 1 B IMM rs rd 0 7 B 0 0 erd C E 00 IMM IMM rs 5 rs 5 F rd 0 erd 0 6 5 IMM 0 ers 0 erd rd rd IMM 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B 0 erd 9 B 0 erd 8 B 0 erd 0 A 1 ers 0 erd A 0 erd 3 9 rs rd 9 3 rd 8 rs rd 2 0 ers 3 2 0 ers 2 1 3 0 6 D F 1 2 0 6 D F 1 1 0 6 D F 1 4 1 6 B A 0 1 4 0 6 B A 0 1 4 1 6 B 8 0 1 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B W W L L L L L B B B — B B W W L L STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd TRAPA XOR STC
Instruction Format 10th byte
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 830 of 1060 REJ09B0331-0500
Instruction Mnemonic Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B XORC #xx:8,CCR XORC #xx:8,EXR XORC
Instruction Format 10th byte
Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Note: * Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. The register fields specify general registers as follows. Address Register 32-Bit Register 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 0000 0001 • • • 0111 1000 1001 • • • 1111 General Register Register Field 8-Bit Register General Register R0H R1H • • • R7H R0L R1L • • • R7L Register Field 000 001 • • • 111 ER0 ER1 • • • ER7 General Register
Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.)
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 831 of 1060 REJ09B0331-0500
A.3
Instruction when most significant bit of BH is 0. Instruction code AH AL BH BL Instruction when most significant bit of BH is 1. 1st byte 2nd byte
Appendix A Instruction Set
AL AH 0 NOP ADD SUB Table A.3(2) OR MOV.B 3 4 BRA BVS JMP BPL MULXU MOV MOV Table A.3(2) BSET 7 8 ADD ADDX CMP SUBX OR XOR AND MOV 9 A B C D E F BNOT BCLR BTST DIVXU RTS BSR RTE TRAPA MULXU DIVXU Table A.3(2) BRN BCC BCS BNE BEQ BVC BHI BLS 5 6 BMI BGE BSR BLT XOR AND Table A.3(2) ORC XORC ANDC LDC 1 2 MOV CMP 0 9 C D A B 1 4 5 6 7 8 2 3
E ADDX SUBX
F Table A.3(2) Table A.3(2)
Operation Code Map
Table A.3 Operation Code Map (1)
Table A.3 shows the operation code map.
Rev. 5.00 Sep 14, 2006 page 832 of 1060 REJ09B0331-0500
LDC Table STC A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) BGT JSR MOV Table A.3(3) BLE BST OR XOR AND BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD Table A.3(2) Table A.3(2) EEPMOV
Instruction code AH AL BH BL
1st byte
2nd byte
BH AH AL 01 MOV STM STC SLEEP CLRMAC INC ADDS INC ADDS MOV SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU ROTL ROTR NEG NEG SUB DEC DEC SUBS CMP BRN Table A.3(4) MOV CMP CMP SUB OR SUB OR ADD ADD Table A.3(4) MOVFPE XOR XOR AND AND BHI BLS BCC BCS BNE BEQ BVC MOV BVS BPL MOV BMI SHAR SHAL SHLR ROTXL ROTXR NOT DEC SUBS DAS BRA MOV MOV MOV NOT ROTXR ROTXL SHLR SHLL DAA INC MAC 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 6A 79 7A LDM LDC 0 7 B 8 1 9 A 2 3 4 5 6 C
D Table A.3(3)
E TAS
F Table A.3(3)
Table A.3(3) ADD
Table A.3 Operation Code Map (2)
INC INC SHAL SHAL SHAR ROTL ROTR EXTS SHAR ROTL ROTR EXTS DEC DEC BLE BGE MOVTPE BLT BGT
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 833 of 1060 REJ09B0331-0500
Instruction code AH AL BH BL CH CL DH DL
Appendix A Instruction Set
1st byte
2nd byte
3rd byte
4th byte
Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1.
CL
AH AL BH BL CH
0 MULXS DIVXS OR BTST BTST BSET BSET BTST BTST BSET BSET BNOT BCLR BNOT BCLR BNOT BCLR BNOT BCLR XOR AND DIVXS MULXS
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Table A.3 Operation Code Map (3)
01C05 01D05 01F06 7Cr06*1 7Cr07*1 7Dr06*1 7Dr07*1 7Eaa6*2 7Eaa7*2 7Faa6*2 7Faa7*2 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST
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BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST
Instruction code AH AL BH BL CH CL DH DL EH EL FH FL
1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. EL
AHALBHBLCHCLDHDLEH
0 BTST
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BSET 6A18aaaa7* BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST
Table A.3 Operation Code Map (4)
Instruction code AH AL BH BL CH CL DH DL EH
1st byte
2nd byte
3rd byte
4th byte
5th byte EL
6th byte FH FL
7th byte GH GL
8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1.
GL
AHALBHBL ... FHFLGH
0 1 4 5 BTST 2 3
6
7
8
9
A
B
C
D
E
F
6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET 6A38aaaaaaaa7* Note: * aa is the absolute address specification. BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 835 of 1060 REJ09B0331-0500
Appendix A Instruction Set
A.4
Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Rev. 5.00 Sep 14, 2006 page 836 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Table A.4
Number of States per Cycle
Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus
Cycle Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM SN
On-Chip 8-Bit Memory Bus 1 4
16-Bit Bus 2
2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m
Branch address read SJ 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1
Legend: m: Number of wait states inserted into external device access
Rev. 5.00 Sep 14, 2006 page 837 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Table A.5
Number of Cycles in Instruction Execution
Instruction Branch Stack Fetch Address Read Operation I J K 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 (BHS d:8) (BLO d:8) 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 Byte Data Access L Word Data Access M Internal Operation N
Instruction ADD
Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd
ADDS ADDX
ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd
AND
AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd
ANDC
ANDC #xx:8,CCR ANDC #xx:8,EXR
BAND
BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32
Bcc
BRA d:8 BRN d:8 BHI d:8 BLS d:8 BCC d:8 BCS d:8 BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8
(BT d:8) (BF d:8)
Rev. 5.00 Sep 14, 2006 page 838 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K (BT d:16) (BF d:16) 2 2 2 2 (BHS d:16) (BLO d:16) 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Instruction Bcc
Mnemonic BRA d:16 BRN d:16 BHI d:16 BLS d:16 BCC d:16 BCS d:16 BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16
BCLR
BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32
BIAND
BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32
BILD
BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32
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Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 Byte Data Access L Word Data Access M Internal Operation N
Instruction BIOR
Mnemonic BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32
BIST
BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32
BIXOR
BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32
BLD
BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32
BNOT
BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32
BOR
BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32
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Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 2 2 3 4 1 2 2 3 4 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1*3 1 1 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 1 2 2 2 2 2 2 2 2 Byte Data Access L Word Data Access M Internal Operation N
Instruction BSET
Mnemonic BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32
BSR
BSR d:8
Normal Advanced
BSR d:16
Normal Advanced
BST
BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32
BTST
BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32
BXOR
BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32
CLRMAC
CLRMAC
Rev. 5.00 Sep 14, 2006 page 841 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 2n + 2*1 2n + 2*1 11 19 11 19 Byte Data Access L Word Data Access M Internal Operation N
Instruction CMP
Mnemonic CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd
DAA DAS DEC
DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd
DIVXS
DIVXS.B Rs,Rd DIVXS.W Rs,ERd
DIVXU
DIVXU.B Rs,Rd DIVXU.W Rs,ERd
EEPMOV
EEPMOV.B EEPMOV.W
EXTS
EXTS.W Rd EXTS.L ERd
EXTU
EXTU.W Rd EXTU.L ERd
INC
INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced
JSR
JSR @ERn
Normal Advanced
JSR @aa:24
Normal Advanced
JSR @@aa:8
Normal Advanced
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Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 4 6 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1*3 1*3 2 1 1 Byte Data Access L Word Data Access M Internal Operation N
Instruction LDC
Mnemonic LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR
LDM
LDM.L @SP+, (ERn-ERn+1) 2 LDM.L @SP+, (ERn-ERn+2) 2 LDM.L @SP+, (ERn-ERn+3) 2
LDMAC
LDMAC ERs,MACH LDMAC ERs,MACL
1 1 2 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MAC MOV
MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd
1
1
Rev. 5.00 Sep 14, 2006 page 843 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Can not be used in the H8S/2655 Group. 2*3 3*3 2*3 3*3 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Byte Data Access L Word Data Access M Internal Operation N
Instruction MOV
Mnemonic MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32
MOVFPE MOVTPE MULXS
MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd
2 2 1 1 1 1 1 1
MULXU
MULXU.B Rs,Rd MULXU.W Rs,ERd
NEG
NEG.B Rd NEG.W Rd NEG.L ERd
NOP
NOP
Rev. 5.00 Sep 14, 2006 page 844 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 Byte Data Access L Word Data Access M Internal Operation N
Instruction NOT
Mnemonic NOT.B Rd NOT.W Rd NOT.L ERd
OR
OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd
ORC
ORC #xx:8,CCR ORC #xx:8,EXR
POP
POP.W Rn POP.L ERn
PUSH
PUSH.W Rn PUSH.L ERn
ROTL
ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd
ROTR
ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd
ROTXL
ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd
ROTXR
ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd
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Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 2 Normal Advanced SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 5 5 2 2 1 1 1 1 1 1 1 1 1 1 1
1 2/3*
Instruction RTE RTS
Mnemonic RTE RTS
Byte Data Access L
Word Data Access M
Internal Operation N 1 1 1
1 2
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Appendix A Instruction Set
Instruction Branch Stack Fetch Address Read Operation I J K 3 3 4 4 2 2 2 1 1 1 2 1 3 1 1 1 1 2 Normal Advanced XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR 2 2 1 1 2 1 3 2 1 2 1 2 2/3*1 2/3*1 2 2 2 4 6 8 Byte Data Access L Word Data Access M 1 1 1 1 1 1 1 *3 *3 Internal Operation N
Instruction STC
Mnemonic STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32
STM
STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP
STMAC*3
STMAC MACH,ERd STMAC MACL,ERd
SUB
SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd
SUBS SUBX
SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd
TAS TRAPA
TAS
@ERd
TRAPA #x:2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. 5 for concatenated execution, 4 otherwise. 3. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction.
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Appendix A Instruction Set
A.5
Bus States During Instruction Execution
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table:
Order of execution Instruction
JMP@aa:24
1
R:W 2nd
2
3
4
5
6
7
8
Internal operation R:W EA 1 state
End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read)
Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address
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Appendix A Instruction Set
Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states.
φ Address bus RD HWR, LWR
High level
R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction
Internal operation
R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address
Figure A.1 Address Bus, RD, HWR, and LWR Timing RD HWR LWR (8-Bit Bus, Three-State Access, No Wait States)
Rev. 5.00 Sep 14, 2006 page 849 of 1060 REJ09B0331-0500
2
3
4
5
6
7
8
9
Table A.6
R:W NEXT R:W 3rd R:W NEXT
Appendix A Instruction Set
R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT
Rev. 5.00 Sep 14, 2006 page 850 of 1060 REJ09B0331-0500
Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT
Instruction Execution Cycles
3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA
Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd
1 R:W NEXT R:W 2nd
2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
4
5
6
7
8
9
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 851 of 1060 REJ09B0331-0500
2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Appendix A Instruction Set
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3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT
2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W stack W:W:M stack (H) R:W EA W:W stack (L) W:W stack W:W:M stack (H) W:W stack (L) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Normal BSR d:8 Advanced Normal BSR d:16 Advanced R:W 2nd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA R:W EA Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd
3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th
4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
7
8
9
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 853 of 1060 REJ09B0331-0500
BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd
W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
2 R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd Internal operation, 1 state R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 854 of 1060 REJ09B0331-0500
Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 ← Repeated n times*2 → R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT
Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced R:W NEXT JSR @ERn JSR @aa:24 Advanced R:W 2nd Normal R:W NEXT Advanced R:W NEXT Normal R:W 2nd R:W NEXT R:W EA Internal operation, R:W EA 1 state R:W aa:8 Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W stack R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W stack 1 state Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W aa:8 W:W stack R:W EA R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA R:W NEXT
1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd
2
3
4
5
6
7
8
9
JSR @@aa:8 Normal Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W NEXT R:W NEXT LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state
R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd
R:W EA R:W EA
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 855 of 1060 REJ09B0331-0500
Instruction LDM.L @SP+,(ERn–ERn+2) LDM.L @SP+,(ERn–ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL R:W NEXT R:W NEXT R:W 2nd
Appendix A Instruction Set
1 R:W 2nd
3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Internal operation, ← Repeated n times*3 → 1 state Internal operation, 1 state R:W NEXT R:W EAn R:W EAm
2 R:W NEXT
6
7
8
9
Rev. 5.00 Sep 14, 2006 page 856 of 1060 REJ09B0331-0500
MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:B EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W EA MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA
4 R:W NEXT W:W EA
Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd
1 R:W 2nd R:W 2nd R:W NEXT
3 W:W EA R:E 4th W:W EA
5
6
7
8
9
2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA
MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W EA+2
R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd
R:W EA+2
MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA
R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd
W:W:M EA
W:W EA+2
MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd*4 MOVTPE Rs,@aa:16*4 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd
R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT
R:W:M EA R:W EA+2 R:W NEXT R:W:M EA R:W:M 4th R:W 5th Internal operation, R:W:M EA 1 state R:W:M 3rd R:W NEXT R:W:M EA R:W:M 3rd R:W 4th R:W NEXT R:W:M NEXT W:W:M EA W:W EA+2 R:W:M 3rd R:W NEXT W:W:M EA R:W:M 3rd R:W:M 4th R:W 5th R:W:M NEXT Internal operation, W:W:M EA 1 state R:W:M 3rd R:W NEXT W:W:M EA R:W:M 3rd R:W 4th R:W NEXT R:W NEXT R:B EA R:W NEXT W:B EA R:W NEXT Internal operation, 2 states R:W NEXT Internal operation, 3 states Internal operation, 2 states Internal operation, 3 states W:W EA+2
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 857 of 1060 REJ09B0331-0500
2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT
Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd W:W EA+2 R:W NEXT R:W 2nd R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state R:W EA+2
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 858 of 1060 REJ09B0331-0500
1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT 3 4 5 6 7 8 9
2 R:W stack (EXR) R:W stack (H) R:W stack R:W stack (L) Internal operation, R:W*5 1 state
Instruction ROTXR.L #2,ERd RTE RTS Advanced R:W NEXT Normal R:W NEXT Internal operation, R:W*5 1 state R:W:M stack (H) R:W stack (L) Internal operation, R:W*5 1 state
1 R:W NEXT R:W NEXT
3
4
5
6
7
8
9
SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA
R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 859 of 1060 REJ09B0331-0500
5 R:W NEXT R:W NEXT W:W EA W:W EA
Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn–ERn+1),@–SP STM.L(ERn–ERn+2),@–SP STM.L(ERn–ERn+3),@–SP ←Repeated n times*3→ R:W 2nd W:W:M stack (H)*3 W:W stack (L)*3 R:W 2nd W:W:M stack (H)*3 W:W stack (L)*3 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 R:W 2nd W:W EA
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 860 of 1060 REJ09B0331-0500
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 Normal W:B EA W:W stack (H) W:W stack (H) Advanced R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state Internal operation, W:W stack (L) 1 state R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT W:W stack (EXR) R:W VEC W:W stack (EXR) R:W:M VEC Internal operation, R:W*8 1 state R:W VEC+2 Internal operation, R:W*8 1 state XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd
Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Normal Reset exception handling Advanced R:W VEC W:W stack (EXR) W:W stack (EXR) R:W:M VEC R:W VEC R:W*7 Interrupt exception Normal handling Advanced R:W*7 R:W NEXT Internal operation, R:W*6 1 state R:W VEC+2 Internal operation, R:W*6 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state
1 R:W 2nd R:W NEXT R:W 2nd R:W VEC
2 R:W NEXT
3
4
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9
Internal operation, R:W*8 1 state R:W VEC+2 Internal operation, R:W*8 1 state
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Can not be used in the H8S/2655 Group. 5. Start address after return. 6. Start address of the program. 7. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 8. Start address of the interrupt-handling routine.
Appendix A Instruction Set
Rev. 5.00 Sep 14, 2006 page 861 of 1060 REJ09B0331-0500
Appendix A Instruction Set
A.6
Condition Code Modification
This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m=
31 for longword operands 15 for word operands 7 for byte operands
The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition)
Si Di Ri Dn —
0 1 * Z' C'
Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution
Rev. 5.00 Sep 14, 2006 page 862 of 1060 REJ09B0331-0500
Appendix A Instruction Set
Table A.7
Instruction ADD
Condition Code Modification
H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm
ADDS ADDX
————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm
AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR
—
0
—
N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR.
———— ————— ————— ———— ———— ———— ————— ———— ———— ————— ———— ————— ————— ————— —— ——
C = C' · Dn
C = C' · Dn C = Dn C = C' + Dn C = C' · Dn + C' · Dn C = Dn C = C' + Dn
Z = Dn C = C' · Dn + C' · Dn
————
Rev. 5.00 Sep 14, 2006 page 863 of 1060 REJ09B0331-0500
Appendix A Instruction Set Instruction CLRMAC CMP H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS DIVXU EEPMOV EXTS EXTU INC — — —— —— N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 N = Sm Z = Sm · Sm–1 · ...... · S0 ————— — —0 — 0 0 — — — N = Rm Z = Rm · Rm–1 · ...... · R0 Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm JMP JSR LDC LDM LDMAC ————— ————— ————— ————— Stores the corresponding bits of the result. No flags change when the operand is EXR.
—————
Rev. 5.00 Sep 14, 2006 page 864 of 1060 REJ09B0331-0500
Appendix A Instruction Set Instruction MAC MOV MOVFPE MOVTPE MULXS MULXU NEG — —— N = R2m Z = R2m · R2m–1 · ...... · R0 ————— H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL — — — 0 0 0 — — ————— — — 0 0 — — N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) H N Z V C Definition
————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Can not be used in the H8S/2655 Group.
Rev. 5.00 Sep 14, 2006 page 865 of 1060 REJ09B0331-0500
Appendix A Instruction Set Instruction ROTXL H — N Z V 0 C Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ————— — N = Rm Z = Rm · Rm–1 · ...... · R0
V = Dm · Dm–1 + Dm · Dm−1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm−1 · Dm−2 (2-bit shift)
Stores the corresponding bits of the result.
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR —0 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ————— ————— ————— — — N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow
Rev. 5.00 Sep 14, 2006 page 866 of 1060 REJ09B0331-0500
Appendix A Instruction Set Instruction SUB H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS SUBX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS TRAPA XOR XORC — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 ————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR.
Rev. 5.00 Sep 14, 2006 page 867 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Appendix B Internal I/O Register
B.1 Addresses
Module Name DTC Data Bus Width 16-/ 32*1-bit
Address Register (low) Name H'F800 to H'FBFF MRA SAR
Bit 7 SM1
Bit 6 SM0
Bit 5 DM1
Bit 4 DM0
Bit 3 MD1
Bit 2 MD0
Bit 1 DTS
Bit 0 Sz
MRB DAR
CHNE
DISEL
—
—
—
—
—
—
CRA CRB H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F TGR3D TGR3C TGR3B TGR3A TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 CCLR2 — IOB3 IOD3 TTGE — CCLR1 — IOB2 IOD2 — — CCLR0 BFB IOB1 IOD1 — — CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16-bit
Rev. 5.00 Sep 14, 2006 page 868 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB4 H'FEB5 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF P1DDR P2DDR P3DDR P5DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR TGR5B TGR5A TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 TGR4B TGR4A TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4
Bit 7 — — IOB3 TTGE TCFD
Bit 6 CCLR1 — IOB2 — —
Bit 5 CCLR0 — IOB1 TCIEU TCFU
Bit 4 CKEG1 — IOB0 TCIEV TCFV
Bit 3 CKEG0 MD3 IOA3 — —
Bit 2 TPSC2 MD2 IOA2 — —
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA
Module Name TPU4
— — IOB3 TTGE TCFD
CCLR1 — IOB2 — —
CCLR0 — IOB1 TCIEU TCFU
CKEG1 — IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 — —
TPSC2 MD2 IOA2 — —
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU5
16-bit
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR — — — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR — — P53DDR P52DDR P51DDR P50DDR
8-bit
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Rev. 5.00 Sep 14, 2006 page 869 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 8-bit
Address Register (low) Name H'FEC0 H'FEC1 H'FEC2 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FEE4 H'FEE5 H'FEE6 H'FEE7 H'FEE8 H'FEE9 MAR0BH ETCR0A IOAR0A MAR0AL ICRA ICRB ICRC IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ABWCR ASTCR WCRH WCRL BCRH BCRL MCR DRAMCR RTCNT RTCOR MAR0AH
Bit 7 ICR7 ICR7 ICR7 — — — — — — — — — — — ABW7 AST7 W71 W31 ICIS1 BLE TPC RFSHE
Bit 6 ICR6 ICR6 ICR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0
Bit 5 ICR5 ICR5 ICR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21
Bit 4 ICR4 ICR4 ICR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20
Bit 3 ICR3 ICR3 ICR3 — — — — — — — — — — — ABW3 AST3 W51 W11
Bit 2 ICR2 ICR2 ICR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10
Bit 1 ICR1 ICR1 ICR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 RMTS1 WDBE RLW1 CKS1
Bit 0 ICR0 ICR0 ICR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 RMST0 WAITE RLW0 CKS0
Module Name Interrupt controller
Bus controller
8-bit
BRSTRM BRSTS1 BRSTS0 RMTS2 — CW2 CMF — MXC1 CMIE ASS MXC0 CKS2
BREQOE EAE BE RCW RCDM RMODE
—
—
—
—
—
—
—
—
DMAC
16-bit
—
—
—
—
—
—
—
—
Rev. 5.00 Sep 14, 2006 page 870 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FEFE H'FEFF H'FF00 H'FF01 H'FF02 ETCR1B IOAR1B MAR1BL MAR1BH ETCR1A IOAR1A MAR1AL MAR1AH ETCR0B IOAR0B MAR0BL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name DMAC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMAWER — DMATCR —
— — DTID
— TEE1 RPE
— TEE0 DTDIR
WE1B — DTF3
WE1A — DTF2
WE0B — DTF1
WE0A — DTF0 Short address mode Full address mode Short address mode Full address mode
8-bit
DMACR0A DTSZ
16-bit
DTSZ
SAID
SAIDE
BLKDIR
BLKE
—
—
—
H'FF03
DMACR0B DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
—
DAID
DAIDE
—
DTF3
DTF2
DTF1
DTF0
Rev. 5.00 Sep 14, 2006 page 871 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FF04
Bit 7
Bit 6 DTID
Bit 5 RPE
Bit 4 DTDIR
Bit 3 DTF3
Bit 2 DTF2
Bit 1 DTF1
Bit 0 DTF0
Module Name Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode
DMACR1A DTSZ
DTSZ
SAID
SAIDE
BLKDIR
BLKE
—
—
—
H'FF05
DMACR1B DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
—
DAID
DAIDE
—
DTF3
DTF2
DTF1
DTF0
H'FF06
DMABCRH FAE1
FAE0
SAE1
SAE0
DTA1B
DTA1A
DTA0B
DTA0A
FAE1
FAE0
—
—
DTA1
—
DTA0
—
H'FF07
DMABCRL DTE1B
DTE1A
DTE0B
DTE0A
DTIE1B
DTIE1A
DTIE0B
DTIE0A
DTME1
DTE1
DTME0
DTE0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
H'FF2C H'FF2D H'FF2E H'FF2F
ISCRH ISCRL IER ISR
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt controller IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IRQ7E IRQ7F DTCE7 SWDTE SSBY MACS PSTOP — IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC
8-bit
H'FF30 to DTCER H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF3C H'FF3D DTVECR SBYCR SYSCR SCKCR MDCR
8-bit
DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 STS2 — — — STS1 INTM1 — — STS0 INTM0 — — OPE NMIEG — — — — SCK2 MDS2 — — SCK1 MDS1 — RAME SCK0 MDS0 MSTP8 MSTP0 MCU 8-bit
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1
Rev. 5.00 Sep 14, 2006 page 872 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 8-bit
Address Register (low) Name H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
PCR PMR NDERH NDERL PODRH PODRL
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 P10 P20 P30 P40 P50 P60 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR Port
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 POD15 POD7 NDR15 NDR7 — — P17 P27 — P47 — P67 PA7 PB7 PC7 PD7 PE7 PF7 — P17DR P27DR — — P67DR PA7DR PB7DR PC7DR PD7DR PE7DR PF7DR — NDER6 POD14 POD6 NDR14 NDR6 — — P16 P26 — P46 — P66 PA6 PB6 PC6 PD6 PE6 PF6 — P16DR P26DR — — P66DR PA6DR PB6DR PC6DR PD6DR PE6DR PF6DR — NDER5 POD13 POD5 NDR13 NDR5 — — P15 P25 P35 P45 — P65 PA5 PB5 PC5 PD5 PE5 PF5 — P15DR P25DR P35DR — P65DR PA5DR PB5DR PC5DR PD5DR PE5DR PF5DR — NDER4 POD12 POD4 NDR12 NDR4 — — P14 P24 P34 P44 — P64 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR — P64DR PA4DR PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 P13 P23 P33 P43 P53 P63 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 P12 P22 P32 P42 P52 P62 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P11 P21 P31 P41 P51 P61 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR
H'FF4C* NDRH H'FF4D* NDRL
2
H'FF4E* NDRH
2 2 H'FF4F* NDRL
H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F
PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR PADR PBDR PCDR PDDR PEDR PFDR PGDR
8-bit
Rev. 5.00 Sep 14, 2006 page 873 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 8-bit
Address Register (low) Name H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Port PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR C/A CHR PE O/E STOP MP CKS1 CKS0 8-bit SCI0, Smart card interface 0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ ERS
PER
TEND
MPB
MPBT
— C/A
— CHR
— PE
— O/E
SDIR STOP
SINV MP
— CKS1
SMIF CKS0 8-bit SCI1, Smart card interface 1
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ ERS
PER
TEND
MPB
MPBT
— C/A
— CHR
— PE
— O/E
SDIR STOP
SINV MP
— CKS1
SMIF CKS0 8-bit SCI2, Smart card interface 2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ ERS
PER
TEND
MPB
MPBT
—
—
—
—
SDIR
SINV
—
SMIF
Rev. 5.00 Sep 14, 2006 page 874 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F H'FFA0 H'FFA1 H'FFA4 H'FFA5 H'FFA6 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADDREH ADDREL ADDRFH ADDRFL ADDRGH ADDRGL ADDRHH ADDRHL ADCSR ADCR DADR0 DADR1 DACR TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1
Bit 7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 ADF —
Bit 6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 ADIE PWR
Bit 5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 ADST TRGS1
Bit 4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 CKS TRGS0
Bit 3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 GRP SCAN
Bit 2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 CH2 DSMP
Bit 1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 CH1 BUFE1
Bit 0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 CH0 BUFE0
Module Name A/D converter
D/A converter DAOE1 CMIEB CMIEB CMFB CMFB DAOE0 CMIEA CMIEA CMFA CMFA DAE OVIE OVIE OVF OVF — CCLR1 CCLR1 ADTE — — CCLR0 CCLR0 OS3 OS3 — CKS2 CKS2 OS2 OS2 — CKS1 CKS1 OS1 OS1 — CKS0 CKS0 OS0 OS0
8-bit
8-bit timer 16-bit channel 0, 1
Rev. 5.00 Sep 14, 2006 page 875 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FFBC (read) H'FFBD (read) H'FFBF (read) H'FFC0 H'FFC1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR0D TGR0C TGR0B TGR0A TCSR TCNT RSTCSR TSTR TSYR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0
Bit 7 OVF
Bit 6 WT/IT
Bit 5 TME
Bit 4 —
Bit 3 —
Bit 2 CKS2
Bit 1 CKS1
Bit 0 CKS0
Module Name WDT
WOVF — — CCLR2 — IOB3 IOD3 TTGE —
RSTE — — CCLR1 — IOB2 IOD2 — —
RSTS CST5 SYNC5 CCLR0 BFB IOB1 IOD1 — —
— CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV
— CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD
— CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
— CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
— CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16-bit TPU 16-bit
— — IOB3 TTGE TCFD
CCLR1 — IOB2 — —
CCLR0 — IOB1 TCIEU TCFU
CKEG1 — IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 — —
TPSC2 MD2 IOA2 — —
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU1
16-bit
Rev. 5.00 Sep 14, 2006 page 876 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Data Bus Width 16-bit
Address Register (low) Name H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2
Bit 7 — — IOB3 TTGE TCFD
Bit 6 CCLR1 — IOB2 — —
Bit 5 CCLR0 — IOB1 TCIEU TCFU
Bit 4 CKEG1 — IOB0 TCIEV TCFV
Bit 3 CKEG0 MD3 IOA3 — —
Bit 2 TPSC2 MD2 IOA2 — —
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA
Module Name TPU2
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
Rev. 5.00 Sep 14, 2006 page 877 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
B.2
Functions
H'F800—H'FBFF
5 DM1 — 4 DM0 — 3 MD1 — 2 MD0 — 1 DTS — 0 Sz —
MRA—DTC Mode Register A
Bit : 7 SM1 Initial value : Read/Write : — 6 SM0 —
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer
DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 — 0 1 Source Address Mode 0 1 — 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode — Destination side is repeat area or block area Source side is repeat area or block area
Rev. 5.00 Sep 14, 2006 page 878 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
MRB—DTC Mode Register B
Bit : 7 CHNE Initial value : Read/Write : — 6 DISEL — 5 — — 4 — —
H'F800—H'FBFF
3 — — 2 — — 1 — — 0 — —
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer
SAR—DTC Source Address Register
Bit : 23 22 21 20 19
H'F800—H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
—
—
—
—
—
—
—
—
—
—
Specifies transfer data source address
DAR—DTC Destination Address Register
Bit : 23 22 21 20 19
H'F800—H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
—
—
—
—
—
—
—
—
—
—
Specifies transfer data destination address
Rev. 5.00 Sep 14, 2006 page 879 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
CRA—DTC Transfer Count Register A
Bit : 15 14 13 12 11 10 9 8
H'F800—H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRAH
CRAL
Specifies the number of DTC data transfers
CRB—DTC Transfer Count Register B
Bit : 15 14 13 12 11 10 9 8
H'F800—H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Specifies the number of DTC block data transfers
Rev. 5.00 Sep 14, 2006 page 880 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR3—Timer Control Register 3
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FE80
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU3
CKEG1 CKEG0 R/W
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096
1
0
0 1
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Rev. 5.00 Sep 14, 2006 page 881 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR3—Timer Mode Register 3
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W
H'FE81
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU3
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —
Legend: *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
Buffer Operation A 0
1
TGRA operates normally
TGRA and TGRC used together for buffer operation
Buffer Operation B 0
1
TGRB operates normally
TGRB and TGRD used together for buffer operation
Rev. 5.00 Sep 14, 2006 page 882 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR3H—Timer I/O Control Register 3H
Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FE82
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU3
Initial value :
TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock TGR3A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down TGR3B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur.
Rev. 5.00 Sep 14, 2006 page 883 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR3L—Timer I/O Control Register 3L
Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2
H'FE83
1 IOC1 0 R/W 0 IOC0 0 R/W
TPU3
IOC2 0 R/W
TRG3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C is input 1 capture * register * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock
0 output at compare match 1 output at compare match Toggle output at compare match
1
1 1 *
Legend: *: Don’t care
Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3D Capture input source is is input TIOCD3 pin capture register*2 Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 TGR3D Output disabled is output compare Initial output is 0 0 output at compare match output register 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When GRC or GRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev. 5.00 Sep 14, 2006 page 884 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER3—Timer Interrupt Enable Register 3
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 TGIED 0 R/W
H'FE84
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
TPU3
TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 885 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR3—Timer Status Register 3
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)*
H'FE85
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU3
Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT=TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 886 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT3—Timer Counter 3
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FE86
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU3
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE88 H'FE8A H'FE8C H'FE8E
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU3 TPU3 TPU3 TPU3
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 887 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR4—Timer Control Register 4
Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W
H'FE90
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU4
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges
Counter Clear 0 0 1 1 0 1
Note: This setting is ignored when channel 4 is in phase counting mode.
TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev. 5.00 Sep 14, 2006 page 888 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR4—Timer Mode Register 4
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 —
H'FE91
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU4
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —
Legend: *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev. 5.00 Sep 14, 2006 page 889 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR4—Timer I/O Control Register 4
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FE92
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU4
IOA2 0 R/W
TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture
0 output at compare match 1 output at compare match Toggle output at compare match
1
Legend: *: Don’t care
TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture
0 output at compare match 1 output at compare match Toggle output at compare match
1
Legend: *: Don’t care
Rev. 5.00 Sep 14, 2006 page 890 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER4—Timer Interrupt Enable Register 4
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 —
H'FE94
2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU4
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 891 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR4—Timer Status Register 4
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 —
H'FE95
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU4
Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 892 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT4—Timer Counter 4
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FE96
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU4
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE98 H'FE9A
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU4 TPU4
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 893 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR5—Timer Control Register 5
Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3
H'FEA0
2 TPSC2 0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64
TPU5
1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG0 0 R/W
External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1
Count at rising edge Count at falling edge Count at both edges
—
Note: This setting is ignored when channel 5 is in phase counting mode.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev. 5.00 Sep 14, 2006 page 894 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR5—Timer Mode Register 5
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 —
H'FEA1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU5
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —
Legend: *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev. 5.00 Sep 14, 2006 page 895 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR5—Timer I/O Control Register 5
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FEA2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU5
IOA2 0 R/W
TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Capture input source is TIOCA5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges
0 output at compare match 1 output at compare match Toggle output at compare match
1
1
Legend: *: Don’t care
TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Capture input source is TIOCB5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR5B Output disabled is output compare Initial output is 0 register output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
Rev. 5.00 Sep 14, 2006 page 896 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER5—Timer Interrupt Enable Register 5
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 —
H'FEA4
2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU5
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 897 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR5—Timer Status Register 5
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 —
H'FEA5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU5
Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 898 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT5—Timer Counter 5
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FEA6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU5
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FEA8 H'FEAA
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU5 TPU5
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P1DDR—Port 1 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB0
3 0 W 2 0 W 1 0 W 0 0 W
Port 1
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write :
Specify input or output for individual port 1 pins
Rev. 5.00 Sep 14, 2006 page 899 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
P2DDR—Port 2 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB1
3 0 W 2 0 W 1 0 W 0 0
Port 2
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : W
Specify input or output for individual port 2 pins
P3DDR—Port 3 Data Direction Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 0 W 4 0 W
H'FEB2
3 0 W 2 0 W 1 0 W 0 0
Port 3
P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W
Specify input or output for individual port 3 pins
P5DDR—Port 5 Data Direction Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 —
H'FEB4
3 0 W 2 0 W 1 0 W 0 0 W
Port 5
P53DDR P52DDR P51DDR P50DDR
Specify input or output for individual port 5 pins
Rev. 5.00 Sep 14, 2006 page 900 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
P6DDR—Port 6 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB5
3 0 W 2 0 W 1 0 W
Port 6
0 0 W
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : Read/Write :
Specify input or output for individual port 6 pins
PADDR—Port A Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB9
3 0 W 2 0 W 1 0 W
Port A
0 0 W
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Specify input or output for individual port A pins
PBDDR—Port B Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBA
3 0 W 2 0 W 1 0 W 0 0 W
Port B
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Specify input or output for individual port B pins
Rev. 5.00 Sep 14, 2006 page 901 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PCDDR—Port C Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBB
3 0 W 2 0 W 1 0 W
Port C
0 0 W
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Specify input or output for individual port C pins
PDDDR—Port D Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBC
3 0 W 2 0 W 1 0 W
Port D
0 0 W
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write :
Specify input or output for individual port D pins
PEDDR—Port E Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBD
3 0 W 2 0 W 1 0 W
Port E
0 0 W
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write :
Specify input or output for individual port E pins
Rev. 5.00 Sep 14, 2006 page 902 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PFDDR—Port F Data Direction Register
Bit : 7 6 5 4
H'FEBE
3 2 1 0
Port F
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4 to 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Specify input or output for individual port F pins
PGDDR—Port G Data Direction Register
Bit Modes 1, 4, 5 Initial value Read/Write Initial value Read/Write : : : : 1 — 1 — 1 — 1 — 1 — 1 — 1 W 0 W : 7 — 6 — 5 — 4
H'FEBF
3 2 1
Port G
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Modes 2, 3, 6, 7
Specify input or output for individual port G pins
Rev. 5.00 Sep 14, 2006 page 903 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ICRA—Interrupt Control Register A ICRB—Interrupt Control Register B ICRC—Interrupt Control Register C
Bit : 7 ICR7 Initial value : Read/Write : 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W
H'FEC0 H'FEC1 H'FEC2
3 ICR3 0 R/W 2 ICR2 0 R/W
Interrupt Controller Interrupt Controller Interrupt Controller
1 ICR1 0 R/W 0 ICR0 0 R/W
Sets the interrupt control level for interrupts Correspondence between Interrupt Sources and ICR Settings Bits Register ICRA 7 IRQ0 6 IRQ1 5 IRQ2 IRQ3 4 IRQ4 IRQ5 3 IRQ6 IRQ7 2 DTC 1 0
Watchdog Refresh timer timer
ICRB
—
A/D TPU TPU TPU TPU TPU TPU converter channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 —
ICRC
8-bit 8-bit DMAC SCI SCI SCI — timer timer channel 0 channel 1 channel 2 channel 0 channel 1
Rev. 5.00 Sep 14, 2006 page 904 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Interrupt Priority Register I IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K
Bit : 7 — Initial value : Read/Write : 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W
H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
3 — 0 — 2 IPR2 1 R/W
Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller
1 IPR1 1 R/W 0 IPR0 1 R/W
Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT — TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IRQ1 IRQ4 IRQ5 DTC 2 to 0
Rev. 5.00 Sep 14, 2006 page 905 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ABWCR—Bus Width Control Register
Bit : 7 ABW7 Modes 1, 2, 5, 6 Initial value : R/W : Modes 3, 4, 7 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4
H'FED0
3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1
Bus Controller
0 ABW0 1 R/W 0 R/W
ABW4
ABW1 1 R/W 0 R/W
Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access
Note: n = 7 to 0
ASTCR—Access State Control Register
Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W
H'FED1
3 AST3 1 R/W 2 AST2 1 R/W 1
Bus Controller
0 AST0 1 R/W
AST1 1 R/W
Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled Note: n = 7 to 0
Rev. 5.00 Sep 14, 2006 page 906 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
WCRH—Wait Control Register H
Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3
H'FED2
2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bus Controller
W51 1 R/W
Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
Rev. 5.00 Sep 14, 2006 page 907 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
WCRL—Wait Control Register L
Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3
H'FED3
2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bus Controller
W11 1 R/W
Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
Rev. 5.00 Sep 14, 2006 page 908 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
BCRH—Bus Control Register H
Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W
H'FED4
3 0 R/W 2 0 R/W 1 RMTS1 0 R/W
Bus Controller
0 RMTS0 0 R/W
BRSTRM BRSTS1 BRSTS0 RMTS2
RAM Type Select
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access
Normal space Normal space Normal space DRAM space
DRAM space
DRAM space Normal space Normal space Normal space PSRAM space
PSRAM space
PSRAM space
Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states
Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface
Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles
Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas
Rev. 5.00 Sep 14, 2006 page 909 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
BCRL—Bus Control Register L
Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W
H'FED5
2 ASS 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W
Bus Controller
WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Wait input by WAIT pin enabled
Write Data Buffer Enable 0 1 Write data buffer function not used Write data buffer function used
Area Partition Unit Select 0 1 Area partition unit is 128 kbytes (1 Mbit) Area partition unit is 2 Mbytes (16 Mbits)
DACK Timing Select 0 When DMAC single address transfer is performed in DRAM/PSRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle Burst access is possible when DMAC single address transfer is performed in DRAM/PSRAM space DACK signal goes low from Tc1 or T2 cycle
1
LCAS Pin Select LCAS pin used for 2-CAS type DRAM interface LCAS signal (BREQO output and WAIT input cannot be used when LCAS signal is used) LWR pin used for 2-CAS type DRAM interface LCAS signal (RAS down mode cannot be used)
0
1
External Addresses H'010000 to H'01FFFF Enable 0 1 On-chip ROM (H8S/2655) or reserved area* (H8S/2653) External addresses (in external expansion mode) or reserved area (in single-chip mode)
Notes: * Do not access a reserved area.
BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled
Bus Release Enable 0 1 External bus release is disabled External bus release is enabled
Rev. 5.00 Sep 14, 2006 page 910 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
MCR—Memory Control Register
Bit : 7 TPC Initial value : Read/Write : 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W
H'FED6
2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W
Bus Controller
Refresh Cycle Wait Control 0 0 1 1 0 1 Multiplex Shift Count 0 0 1 1 0 1 8-bit shift 9-bit shift 10-bit shift — No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted
2-CAS Method/2-WE Method Select 0 1 2-CAS method selected: CASH, CASL, WE signals enabled. 2-WE method selected: CAS, UWE, LWE signals enabled.
RAS/CS Down Mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected
Burst Access Enable 0 1 Burst disabled (always full access) • For DRAM space access Access in fast page mode • For PSRAM space access Access in static column mode
TP Cycle Control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted
Rev. 5.00 Sep 14, 2006 page 911 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DRAMCR—DRAM Control Register
Bit : 7 RFSHE Initial value : Read/Write : 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W
H'FED7
3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
Bus Controller
0 CKS0 0 R/W
Refresh Counter Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Count operation disabled Count uses φ/2 Count uses φ/8 Count uses φ/32 Count uses φ/128 Count uses φ/512 Count uses φ/2048 Count uses φ/4096
Compare Match Interrupt Enable 0 1 Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled
Compare Match Flag 0
[Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag [Setting condition] Set when RTCNT = RTCOR
1
Refresh Mode 0 DRAM interface: CAS-before-RAS refreshing used PSRAM interface: Auto-refreshing used 1 RAS-CAS Wait 0 1 Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle Self-refreshing used
Refresh Control 0 1 Refresh control is not performed Refresh control is performed
Rev. 5.00 Sep 14, 2006 page 912 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
RTCNT—Refresh Timer Counter
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FED8
3 0 R/W 2 0 R/W
Bus Controller
1 0 R/W 0 0 R/W
Initial value : Read/Write :
Internal clock count value
RTCOR—Refresh Time Constant Register
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FED9
3 1 R/W 2 1 R/W
Bus Controller
1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the period for compare match operations with RTCNT
MAR0AH—Memory Address Register 0AH MAR0AL—Memory Address Register 0AL
Bit MAR0AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 *
H'FEE0 H'FEE2
24 — 0 * * * * * * * 23 22 21 20 19 18 17
DMAC DMAC
16 *
Initial value : Read/Write : Bit MAR0AL : :
— R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address Legend: *: Undefined
Rev. 5.00 Sep 14, 2006 page 913 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
IOAR0A—I/O Address Register 0A
Bit IOAR0A : : * * * * * * * * 15 14 13 12 11 10 9 8
H'FEE4
7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Legend: *: Undefined
ETCR0A—Transfer Count Register 0A
Bit ETCR0A : : * * * * * * * * 15 14 13 12 11 10 9 8
H'FEE6
7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register Transfer counter Block size counter Transfer counter
Legend: *: Undefined
Rev. 5.00 Sep 14, 2006 page 914 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
MAR0BH—Memory Address Register 0BH MAR0BL—Memory Address Register 0BL
Bit MAR0BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 *
H'FEE8 H'FEEA
24 — 0 * * * * * * * 23 22 21 20 19 18 17
DMAC DMAC
16 *
Initial value : Read/Write : Bit MAR0BL : :
— R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Legend: *: Undefined
IOAR0B—I/O Address Register 0B
Bit IOAR0B : : 15 14 13 12 11 10 9 8
H'FEEC
7 6 5 4 3 2 1
DMAC
0
Initial value :
* * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Legend: *: Undefined
Rev. 5.00 Sep 14, 2006 page 915 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ETCR0B—Transfer Count Register 0B
Bit ETCR0B : : * * * * * * * * 15 14 13 12 11 10 9 8
H'FEEE
7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Repeat mode Transfer number storage register Block transfer mode Block transfer counter Transfer counter
Transfer counter
Legend: *: Undefined Note: Not used in normal mode.
MAR1AH—Memory Address Register 1AH MAR1AL—Memory Address Register 1AL
Bit MAR1AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 *
H'FEF0 H'FEF2
24 — 0 * * * * * * * 23 22 21 20 19 18
DMAC DMAC
17 16 *
Initial value : Read/Write : Bit MAR1AL : :
— R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address Legend: *: Undefined
Rev. 5.00 Sep 14, 2006 page 916 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
IOAR1A—I/O Address Register 1A
Bit IOAR1A : : * * * * * * * * 15 14 13 12 11 10 9 8
H'FEF4
7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Legend: *: Undefined
ETCR1A—Transfer Count Register 1A
Bit ETCR1A : : * * * * * * * 15 14 13 12 11 10 9
H'FEF6
8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register
Legend: *: Undefined
Transfer counter
Transfer counter Block size counter
Rev. 5.00 Sep 14, 2006 page 917 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
MAR1BH—Memory Address Register 1BH MAR1BL—Memory Address Register 1BL
Bit MAR1BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 *
H'FEF8 H'FEFA
24 — 0 * * * * * * * 23 22 21 20 19 18
DMAC DMAC
17 16 *
Initial value : Read/Write : Bit MAR1BL : :
— R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Legend: *: Undefined
IOAR1B—I/O Address Register 1B
Bit IOAR1B : : * * * * * * * * 15 14 13 12 11 10 9 8
H'FEFC
7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Legend: *: Undefined
Rev. 5.00 Sep 14, 2006 page 918 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ETCR1B—Transfer Count Register 1B
Bit ETCR1B : : * * * * * * * 15 14 13 12 11 10 9
H'FEFE
8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 *
DMAC
0 *
Initial value : Read/Write : Sequential mode and idle mode Repeat mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter Transfer number storage register Transfer counter
Block transfer mode Block transfer counter
Legend: *: Undefined
Note: Not used in normal mode.
Rev. 5.00 Sep 14, 2006 page 919 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DMAWER—DMA Write Enable Register
Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W
H'FF00
2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W Write Enable 0A 0
DMAC
DMAWER : Initial value : Read/Write :
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
1
Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled
1
Write Enable 1A 0 1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
Write Enable 1B 0 1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled
Rev. 5.00 Sep 14, 2006 page 920 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DMATCR—DMA Terminal Control Register
Bit DMATCR : : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W
H'FF01
3 — 0 — 2 — 0 — 1 — 0 —
DMAC
0 — 0 —
Initial value : Read/Write :
Transfer End Enable 0 0 1 TEND0 pin output disabled TEND0 pin output enabled
Transfer End Enable 1 0 1 TEND1 pin output disabled TEND1 pin output enabled
Rev. 5.00 Sep 14, 2006 page 921 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DMACR0A—DMA Control Register 0A DMACR0B—DMA Control Register 0B DMACR1A—DMA Control Register 1A DMACR1B—DMA Control Register 1B
Full address mode Bit DMACRA : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W
H'FF02 H'FF03 H'FF04 H'FF05
DMAC DMAC DMAC DMAC
11 BLKE 0 R/W
10 — 0 R/W
9 — 0 R/W
8 — 0 R/W
Initial value : Read/Write :
Block Direction/Block Enable 0 0 1 1 0 1 Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area
Source Address Increment/Decrement 0 0 1 1 0 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer
Rev. 5.00 Sep 14, 2006 page 922 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Full address mode (cont) Bit DMACRB : : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W
Initial value : Read/Write :
Data Transfer Factor
DTF DTF DTF DTF 3 210 0 000 — Block Transfer Mode Normal Mode
— —
1 1 0
Activated by A/D converter conversion end interrupt
Activated by DREQ pin falling edge input Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt Activated by DREQ pin low-level input
1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 *
— —
Auto-request (cycle steal) Auto-request (burst)
— — — — — — —
—
Legend: *: Don’t care
Destination Address Increment/Decrement 0 0 1 1 0 1 MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer
Rev. 5.00 Sep 14, 2006 page 923 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Short address mode Bit DMACR
: : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W
Initial value : Read/Write :
Data Transfer Factor
Channel A Channel B
Data Transfer Direction 0
Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address
0
0
0
0 1
— Activated by A/D converter conversion end interrupt — —
Activated by DREQ pin falling edge input Activated by DREQ pin low-level input
1
0 1
1
1
0
0 1
Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — —
Repeat Enable 0 1 Transfer in sequential mode Transfer in repeat mode or idle mode 1 0
1
0 1
Data Transfer Increment/Decrement 0 1 MAR is incremented after a data transfer MAR is decremented after a data transfer
0
0 1
Data Transfer Size 0 1 Byte-size transfer Word-size transfer 1
1
0 1
0
0 1
1
0 1
Rev. 5.00 Sep 14, 2006 page 924 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DMABCRH—DMA Band Control Register DMABCRL—DMA Band Control Register
Full address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 10 — 0
H'FF06 H'FF07
DMAC DMAC
9 DTA0 0 R/W
8 — 0 R/W
DMABCRH : Initial value : Read/Write :
R/W
Channel 0 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
Channel 1 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
Channel 0 Full Address Enable 0 1 Short address mode Full address mode
Channel 1 Full Address Enable 0 1 Short address mode Full address mode
(Continued on next page)
Rev. 5.00 Sep 14, 2006 page 925 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Full address mode (cont) Bit :
7 DTME1 0 R/W
6 DTE1 0 R/W
5 DTME0 0 R/W
4 DTE0 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
DMABCRL :
Initial value : Read/Write :
DTIE1B DTIE1A
DTIE0B DTIE0A
Channel 0 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel 1 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
Channel 1 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel 0 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled
Channel 1 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 1 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled
(Continued on next page)
Rev. 5.00 Sep 14, 2006 page 926 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Short address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : Read/Write :
Channel 0A Data Transfer Acknowledge 0
Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
1
Channel 0B Data Transfer Acknowledge 0 1
Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
Channel 1A Data Transfer Acknowledge 0 1
Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
Channel 1B Data Transfer Acknowledge 0 1
Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled
Channel 0B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode
Channel 1B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode
Channel 0 Full Address Enable 0 1 Short address mode Full address mode
Channel 1 Full Address Enable 0 1 Short address mode Full address mode
(Continued on next page)
Rev. 5.00 Sep 14, 2006 page 927 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
Short address mode (cont) Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A
Channel 0B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
Channel 1A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
Channel 1B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled
Channel 0A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 0B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 1A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Channel 1B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled
Rev. 5.00 Sep 14, 2006 page 928 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L
ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W
H'FF2C H'FF2D
Interrupt Controller Interrupt Controller
11 0 R/W
10 0 R/W
9 0 R/W
8 0 R/W
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write :
IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write :
IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Note: n = 7 to 0 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input
Rev. 5.00 Sep 14, 2006 page 929 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
IER—IRQ Enable Register
Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4
H'FF2E
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W
Interrupt Controller
1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IRQ4E 0 R/W
IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled
Note: n = 7 to 0
ISR—IRQ Status Register
Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4
H'FF2F
3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)*
Interrupt Controller
1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
IRQ4F 0 R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 930 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DTCERA to DTCERF—DTC Enable Registers
Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W
H'FF30 to H'FF35
3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0
DTC
DTCE0 0 R/W
DTC Activation Enable
0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended
1
Correspondence between Interrupt Sources and DTCER
Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF 7 IRQ0 — TGI2A — DMTEND0A RXI2 6 IRQ1 ADI TGI2B — 5 IRQ2 TGI0A TGI3A TGI5A 4 IRQ3 TGI0B TGI3B TGI5B 3 IRQ4 TGI0C TGI3C CMIA0 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 — 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 — 0 IRQ7 TGI1B TGI4B CMIB1 TXI1 —
DMTEND0B DMTEND1A TXI2 —
DMTEND1B RXI0 — —
Rev. 5.00 Sep 14, 2006 page 931 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DTVECR—DTC Vector Register
Bit : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W
H'FF37
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
DTC
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write :
Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended • During data transfer due to software activation
1
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
Rev. 5.00 Sep 14, 2006 page 932 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SBYCR—Standby Control Register
Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W
H'FF38
2 — 0 — 1 — 0 — 0 — 0 —
Power-Down State
Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state
1
Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states
Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction
Rev. 5.00 Sep 14, 2006 page 933 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SYSCR—System Control Register
Bit : 7 MACS Initial value : Read/Write : 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3
H'FF39
2 — 0 — 1 — 0 — 0 RAME 1 R/W
MCU
NMIEG 0 R/W
RAM Enable 0 1 NMI Input Edge Select 0 1 Falling edge Rising edge On-chip RAM disabled On-chip RAM enabled
Interrupt Control Mode Selection 0 0 1 1 0 1 MAC Saturation 0 1 Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction Interrupt control mode 0 Interrupt control mode 1 Interrupt control mode 2 Interrupt control mode 3
Rev. 5.00 Sep 14, 2006 page 934 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCKCR—System Clock Control Register
Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 —
H'FF3A
2 SCK2 0 R/W 1 SCK1 0 R/W
Clock Pulse Generator
0 SCK0 0 R/W
Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 φ Clock Output Control PSTOP 0 1 Normal Operation φ output Fixed high Sleep Mode φ output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance — Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 —
MDCR—Mode Control Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 0 — 5 — 0 — 4 — 0 —
H'FF3B
3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0
MCU
MDS0 —* R
Current mode pin operating mode Note: * Determined by pins MD2 to MD0
Rev. 5.00 Sep 14, 2006 page 935 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
MSTPCRH—Module Stop Control Register H MSTPCRL—Module Stop Control Register L
MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1
H'FF3C H'FF3D
Power-Down State Power-Down State
MSTPCRL
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set
Rev. 5.00 Sep 14, 2006 page 936 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PCR—PPG Output Control Register
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF46
3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
PPG
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : Read/Write :
Output Trigger for Pulse Output Group 0 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3
Output Trigger for Pulse Output Group 1 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3
Output Trigger for Pulse Output Group 2 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3
Output Trigger for Pulse Output Group 3 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3
Rev. 5.00 Sep 14, 2006 page 937 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PMR—PPG Output Mode Register
Bit : 7 G3INV Initial value : Read/Write : 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4
H'FF47
3 0 R/W 2 0 R/W 1 0 R/W 0 0
PPG
G0INV 1 R/W
G3NOV G2NOV
G1NOV G0NOV R/W
Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the selected TPU channel)
1
Note: n = 3 to 0 Pulse Output Group n Direct/Inverted Output 0 Inverted output for pulse output group n (low-level output at pin for a 1 in PODRH) Direct output for pulse output group n (high-level output at pin for a 1 in PODRH)
1
Note: n = 3 to 0
Rev. 5.00 Sep 14, 2006 page 938 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
NDERH—Next Data Enable Registers H NDERL—Next Data Enable Registers L
NDERH
H'FF48 H'FF49
PPG PPG
Bit
:
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 NDER8 0 R/W
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : Read/Write :
Pulse Output Enable/Disable 0 1 NDERL Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled
Bit
:
7 NDER7 0 R/W
6 NDER6 0 R/W
5 NDER5 0 R/W
4 NDER4 0 R/W
3 NDER3 0 R/W
2 NDER2 0 R/W
1 NDER1 0 R/W
0 NDER0 0 R/W
Initial value : Read/Write :
Pulse Output Enable/Disable 0 1 Pulse outputs PO7 to PO0 are disabled Pulse outputs PO7 to PO0 are enabled
Rev. 5.00 Sep 14, 2006 page 939 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PODRH—Output Data Register H PODRL—Output Data Register L
PODRH
H'FF4A H'FF4B
PPG PPG
Bit
:
7 POD15 0 R/(W)*
6 POD14 0 R/(W)*
5 POD13 0 R/(W)*
4 POD12 0 R/(W)*
3 POD11 0 R/(W)*
2 POD10 0 R/(W)*
1 POD9 0 R/(W)*
0 POD8 0 R/(W)*
Initial value : Read/Write :
Stores output data for use in pulse output PODRL
Bit
:
7 POD7 0 R/(W)*
6 POD6 0 R/(W)*
5 POD5 0 R/(W)*
4 POD4 0 R/(W)*
3 POD3 0 R/(W)*
2 POD2 0 R/(W)*
1 POD1 0 R/(W)*
0 POD0 0 R/(W)*
Initial value : Read/Write :
Stores output data for use in pulse output Note: * A bit that has been set for pulse output by NDER is read-only.
Rev. 5.00 Sep 14, 2006 page 940 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
NDRH—Next Data Register H
H'FF4C (FF4E)
PPG
(1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 NDR15 Initial value : Read/Write : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Stores the next data for pulse output groups 3 and 2
(b) Address: H'FF4E Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
(2) When pulse output group output triggers are different (a) Address: H'FF4C Bit : 7 NDR15 Initial value : Read/Write : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
Stores the next data for pulse output group 3
(b) Address: H'FF4E Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Stores the next data for pulse output group 2
Rev. 5.00 Sep 14, 2006 page 941 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
NDRL—Next Data Register L
H'FF4D (FF4F)
PPG
(1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 NDR7 Initial value : Read/Write : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Stores the next data for pulse output groups 1 and 0
(b) Address: H'FF4F Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
(2) When pulse output group output triggers are different (a) Address: H'FF4D Bit : 7 NDR7 Initial value : Read/Write : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
Stores the next data for pulse output group 1
(b) Address: H'FF4F Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Stores the next data for pulse output group 0
Rev. 5.00 Sep 14, 2006 page 942 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PORT1—Port 1 Register
Bit : 7 P17 Initial value : Read/Write : —* R 6 P16 —* R 5 P15 —* R 4 P14 —* R
H'FF50
3 P13 —* R 2 P12 —* R 1 P11 —* R
Port 1
0 P10 —* R
State of port 1 pins Note: * Determined by the state of pins P17 to P10.
PORT2—Port 2 Register
Bit : 7 P27 Initial value : Read/Write : —* R 6 P26 —* R 5 P25 —* R 4 P24 —* R
H'FF51
3 P23 —* R 2 P22 —* R 1 P21 —* R
Port 2
0 P20 —* R
State of port 2 pins Note: * Determined by the state of pins P27 to P20.
PORT3—Port 3 Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 P35 —* R 4 P34 —* R
H'FF52
3 P33 —* R 2 P32 —* R 1 P31 —* R 0
Port 3
P30 —* R
State of port 3 pins Note: * Determined by the state of pins P35 to P30.
Rev. 5.00 Sep 14, 2006 page 943 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PORT4—Port 4 Register
Bit : 7 P47 Initial value : Read/Write : —* R 6 P46 —* R 5 P45 —* R 4 P44 —* R
H'FF53
3 P43 —* R 2 P42 —* R 1 P41 —* R
Port 4
0 P40 —* R
State of port 4 pins Note: * Determined by the state of pins P47 to P40.
PORT5—Port 5 Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 —
H'FF54
3 P53 —* R 2 P52 —* R 1 P51 —* R
Port 5
0 P50 —* R
State of port 5 pins Note: * Determined by the state of pins P53 to P50.
PORT6—Port 6 Register
Bit : 7 P67 Initial value : Read/Write : —* R 6 P66 —* R 5 P65 —* R 4 P64 —* R
H'FF55
3 P63 —* R 2 P62 —* R 1 P61 —* R
Port 6
0 P60 —* R
State of port 6 pins Note: * Determined by the state of pins P67 to P60.
Rev. 5.00 Sep 14, 2006 page 944 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PORTA—Port A Register
Bit : 7 PA7 Initial value : Read/Write : —* R 6 PA6 —* R 5 PA5 —* R 4 PA4 —* R
H'FF59
3 PA3 —* R 2 PA2 —* R 1 PA1 —* R
Port A
0 PA0 —* R
State of port A pins Note: * Determined by the state of pins PA7 to PA0.
PORTB—Port B Register
Bit : 7 PB7 Initial value : Read/Write : —* R 6 PB6 —* R 5 PB5 —* R 4 PB4 —* R
H'FF5A
3 PB3 —* R 2 PB2 —* R 1 PB1 —* R
Port B
0 PB0 —* R
State of port B pins Note: * Determined by the state of pins PB7 to PB0.
PORTC—Port C Register
Bit : 7 PC7 Initial value : Read/Write : —* R 6 PC6 —* R 5 PC5 —* R 4 PC4 —* R
H'FF5B
3 PC3 —* R 2 PC2 —* R 1 PC1 —* R
Port C
0 PC0 —* R
State of port C pins Note: * Determined by the state of pins PC7 to PC0.
Rev. 5.00 Sep 14, 2006 page 945 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PORTD—Port D Register
Bit : 7 PD7 Initial value : Read/Write : —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R
H'FF5C
3 PD3 —* R 2 PD2 —* R 1 PD1 —* R
Port D
0 PD0 —* R
State of port D pins Note: * Determined by the state of pins PD7 to PD0.
PORTE—Port E Register
Bit : 7 PE7 Initial value : Read/Write : —* R 6 PE6 —* R 5 PE5 —* R 4 PE4 —* R
H'FF5D
3 PE3 —* R 2 PE2 —* R 1 PE1 —* R
Port E
0 PE0 —* R
State of port E pins Note: * Determined by the state of pins PE7 to PE0.
PORTF—Port F Register
Bit : 7 PF7 Initial value : Read/Write : —* R 6 PF6 —* R 5 PF5 —* R 4 PF4 —* R
H'FF5E
3 PF3 —* R 2 PF2 —* R 1 PF1 —* R
Port F
0 PF0 —* R
State of port F pins Note: * Determined by the state of pins PF7 to PF0.
Rev. 5.00 Sep 14, 2006 page 946 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PORTG—Port G Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 PG4 —* R
H'FF5F
3 PG3 —* R 2 PG2 —* R 1 PG1 —* R
Port G
0 PG0 —* R
State of port G pins Note: * Determined by the state of pins PG4 to PG0.
P1DR—Port 1 Data Register
Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4
H'FF60
3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W
Port 1
0 P10DR 0 R/W
P14DR 0 R/W
Stores output data for port 1 pins (P17 to P10)
P2DR—Port 2 Data Register
Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4
H'FF61
3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W
Port 2
0 P20DR 0 R/W
P24DR 0 R/W
Stores output data for port 2 pins (P27 to P20)
Rev. 5.00 Sep 14, 2006 page 947 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
P3DR—Port 3 Data Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 P35DR 0 R/W 4
H'FF62
3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W
Port 3
0 P30DR 0 R/W
P34DR 0 R/W
Stores output data for port 3 pins (P35 to P30)
P5DR—Port 5 Data Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 —
H'FF64
3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0
Port 5
P50DR 0 R/W
Stores output data for port 5 pins (P53 to P50)
P6DR—Port 6 Data Register
Bit : 7 P67DR Initial value : Read/Write : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4
H'FF65
3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W
Port 6
0 P60DR 0 R/W
P64DR 0 R/W
Stores output data for port 6 pins (P67 to P60)
Rev. 5.00 Sep 14, 2006 page 948 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PADR—Port A Data Register
Bit : 7 PA7DR Initial value : Read/Write : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4
H'FF69
3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W
Port A
0 PA0DR 0 R/W
PA4DR 0 R/W
Stores output data for port A pins (PA7 to PA0)
PBDR—Port B Data Register
Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4
H'FF6A
3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W
Port B
0 PB0DR 0 R/W
PB4DR 0 R/W
Stores output data for port B pins (PB7 to PB0)
PCDR—Port C Data Register
Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4
H'FF6B
3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W
Port C
0 PC0DR 0 R/W
PC4DR 0 R/W
Stores output data for port C pins (PC7 to PC0)
Rev. 5.00 Sep 14, 2006 page 949 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PDDR—Port D Data Register
Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4
H'FF6C
3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W
Port D
0 PD0DR 0 R/W
PD4DR 0 R/W
Stores output data for port D pins (PD7 to PD0)
PEDR—Port E Data Register
Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4
H'FF6D
3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W
Port E
0 PE0DR 0 R/W
PE4DR 0 R/W
Stores output data for port E pins (PE7 to PE0)
PFDR—Port F Data Register
Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4
H'FF6E
3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W
Port F
0 PF0DR 0 R/W
PF4DR 0 R/W
Stores output data for port F pins (PF7 to PF0)
Rev. 5.00 Sep 14, 2006 page 950 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PGDR—Port G Data Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 0 R/W
H'FF6F
3 0 R/W 2 0 R/W 1 0 R/W
Port G
0 0 R/W
PG4DR PG3DR PG2DR
PG1DR PG0DR
Stores output data for port G pins (PG4 to PG0)
PAPCR—Port A MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF70
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port A
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis
PBPCR—Port B MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF71
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port B
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis
Rev. 5.00 Sep 14, 2006 page 951 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
PCPCR—Port C MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF72
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port C
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis
PDPCR—Port D MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF73
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port D
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis
PEPCR—Port E MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF74
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port E
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis
Rev. 5.00 Sep 14, 2006 page 952 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
P3ODR—Port 3 Open Drain Control Register
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 0 R/W 4 0 R/W
H'FF76
3 0 R/W 2 0 R/W 1 0 R/W
Port 3
0 0 R/W
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Controls the PMOS on/off status for each port 3 pin (P35 to P30)
PAODR—Port A Open Drain Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF77
3 0 R/W 2 0 R/W 1 0 R/W
Port A
0 0 R/W
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Read/Write :
Controls the PMOS on/off status for each port A pin (PA7 to PA0)
Rev. 5.00 Sep 14, 2006 page 953 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR0—Serial Mode Register 0
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF78
2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI0
STOP 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev. 5.00 Sep 14, 2006 page 954 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR0—Serial Mode Register 0
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF78
3 STOP 0 R/W 2 MP 0 R/W
Smart Card Interface 0
1 CKS1 0 R/W 0 CKS0 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
1
Note: etu (Elementary Time Unit): Interval for transfer of one bit
Rev. 5.00 Sep 14, 2006 page 955 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
BRR0—Bit Rate Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF79
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details.
Rev. 5.00 Sep 14, 2006 page 956 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR0—Serial Control Register 0
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
SCI0
0 CKE0 0 R/W
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1
Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB = 1 data is received
Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0
1
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 957 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR0—Serial Control Register 0
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W Clock Enable 0 CKE0 0 R/W
Smart Card Interface 0
SMCR SMIF 0 1 1 1 1 1 1
SMR C/A, GM
SCR setting CKE1 CKE0
SCK pin function
See SCI specification 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 958 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TDR0—Transmit Data Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF7B
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev. 5.00 Sep 14, 2006 page 959 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR0—Serial Status Register 0
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1
H'FF7C
0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI0
MPB 0 R
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 960 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR0—Serial Status Register 0
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R
H'FF7C
0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1
Smart Card Interface 0
Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 and ERS = 0, 2.5 etu after a 1-byte serial transmit character is sent (normal transmission)
1
Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 961 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
RDR0—Receive Data Register 0
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF7D
3 0 R
SCI0, Smart Card Interface 0
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR0—Smart Card Mode Register 0
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3
H'FF7E
2 SINV 0 R/W
SCI0, Smart Card Interface 0
1 — 1 — 0 SMIF 0 R/W
SDIR 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
1
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev. 5.00 Sep 14, 2006 page 962 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR1—Serial Mode Register 1
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF80
2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI1
STOP 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev. 5.00 Sep 14, 2006 page 963 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR1—Serial Mode Register 1
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF80
2 MP 0 R/W 1
Smart Card Interface 1
0 CKS0 0 R/W
STOP 0 R/W
CKS1 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
1
Note: etu (Elementary Time Unit): Interval for transfer of one bit
Rev. 5.00 Sep 14, 2006 page 964 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
BRR1—Bit Rate Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF81
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details.
Rev. 5.00 Sep 14, 2006 page 965 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR1—Serial Control Register 1
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W
SCI1
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable
0 1
Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 966 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR1—Serial Control Register 1
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W Clock Enable 0 CKE0 0 R/W
Smart Card Interface 1
SMCR
SMIF 0 1 1 1 1 1 1
SMR
C/A, GM
SCR setting CKE1 CKE0
SCK pin function
See SCI specification 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 967 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TDR1—Transmit Data Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF83
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev. 5.00 Sep 14, 2006 page 968 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR1—Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1
H'FF84
0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI1
MPB 0 R
Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 969 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR1—Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R
H'FF84
0 MPBT 0 R/W
Smart Card Interface 1
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 and ERS = 0, 2.5 etu after a 1-byte serial transmit character is sent (normal transmission) [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Note: etu: Elementary Time Unit (the time taken to transmit one bit)
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 970 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
RDR1—Receive Data Register 1
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF85
3 0 R
SCI1, Smart Card Interface 1
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR1—Smart Card Mode Register 1
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 —
H'FF86
3 SDIR 0 R/W 2 SINV 0 R/W
SCI1, Smart Card Interface 1
1 — 1 — 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
1
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev. 5.00 Sep 14, 2006 page 971 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR2—Serial Mode Register 2
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF88
2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI2
STOP 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev. 5.00 Sep 14, 2006 page 972 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SMR2—Serial Mode Register 2
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF88
2 MP 0 R/W 1
Smart Card Interface 2
0 CKS0 0 R/W
STOP 0 R/W
CKS1 0 R/W
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ clock φ/4 clock φ/16 clock φ/64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
1
Note: etu (Elementary Time Unit): Interval for transfer of one bit
Rev. 5.00 Sep 14, 2006 page 973 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
BRR2—Bit Rate Register 2
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF89
3 1 R/W
SCI2, Smart Card Interface 2
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details.
Rev. 5.00 Sep 14, 2006 page 974 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR2—Serial Control Register 2
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF8A
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W
SCI2
Initial value : Read/Write :
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate.
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1
Reception disabled Reception enabled
Transmit Enable 0 1
Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 975 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SCR2—Serial Control Register 2
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF8A
1 CKE1 0 R/W Clock Enable SMCR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SMR C/A, GM 0 CKE0 0 R/W
Smart Card Interface 2
SCR setting CKE1 CKE0 SCK pin function
See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1
Reception disabled Reception enabled
Transmit Enable 0 1
Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev. 5.00 Sep 14, 2006 page 976 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TDR2—Transmit Data Register 2
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF8B
3 1 R/W
SCI2, Smart Card Interface 2
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev. 5.00 Sep 14, 2006 page 977 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR2—Serial Status Register 2
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1
H'FF8C
0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI2
MPB 0 R
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 978 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
SSR2—Serial Status Register 2
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1
H'FF8C
0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 MPB 0 R
Smart Card Interface 2
Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 1
Transmit End
[Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
0
[Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 and ERS = 0, 2.5 etu after a 1-byte serial transmit character is sent (normal transmission)
1
Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error
0 1
[Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception completed while RDRF = 1
Receive Data Register Full
0
[Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty
0
[Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 979 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
RDR2—Receive Data Register 2
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF8D
3 0 R
SCI2, Smart Card Interface 2
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR2—Smart Card Mode Register 2
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W
H'FF8E
2 SINV 0 R/W
SCI2, Smart Card Interface 2
1 — 1 — 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev. 5.00 Sep 14, 2006 page 980 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL ADDREH—A/D Data Register EH ADDREL—A/D Data Register EL ADDRFH—A/D Data Register FH ADDRFL—A/D Data Register FL ADDRGH—A/D Data Register GH ADDRGL—A/D Data Register GL ADDRHH—A/D Data Register HH ADDRHL—A/D Data Register HL
Bit : 15 — Initial value : Read/Write : 0 — 14 — 0 — 13 — 0 — 12 — 0 — 11 — 0 — 10 0 — 9 0 R 8 0 R
H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F
7 0 R 6 0 R 5 0 R 4 0 R 3 0 R
A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter
2 0 R 1 0 R 0 0 R
— AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Stores the results of A/D conversion
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
A/D Data Register ADDRA* ADDRB* ADDRC* ADDRD* ADDRE ADDRF ADDRG ADDRH
Note: * Except when buffer operation is used.
Rev. 5.00 Sep 14, 2006 page 981 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ADCSR—A/D Control/Status Register
Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 CKS 0 R/W
H'FFA0
3 GRP 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W
A/D Converter
0 CH0 0 R/W
Channel Select Select Mode Group Mode
CH2 CH1 CH0
(GRP = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
(GRP = 1) AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 AN0 to AN4 AN0 to AN5 AN0 to AN6 AN0 to AN7
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Group Mode 0 1 Clock Select 0 1 A/D Start 0 1 A/D conversion stopped • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends • Scan mode: A/D conversion is started. Conversion continues until ADST is cleared to 0 by software Conversion time = 20 states (A/D converter reference clock = φ) Conversion time = 40 states (when φ/2 is selected) Select mode Group mode
A/D Interrupt Enable 0 1 A/D End Flag 0 [Clearing conditions] • When 0 is written to the ADF flag after reading ADF = 1 • When the DMAC or DTC is activated by an ADI interrupt, and the relevant register is read 1 [Setting conditions] • Single mode: When conversion ends for all specified channels, and A/D conversion ends* • Scan mode: When one round of conversion has been performed on all specified channels* A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 982 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
ADCR—A/D Control Register
Bit : 7 — Initial value : Read/Write : 0 R/W 6 PWR 0 R/W 5 TRGS1 0 R/W 4 TRGS0 0 R/W 3 SCAN 0 R/W
H'FFA1
2 DSMP 0 R/W 1 BUFE1 0 R/W 0 BUFE0 0 R/W
A/D Converter
Buffer Enable 0 0 1
Normal operation ADDRA and ADDRB are used for buffer operation (Conversion result → ADDRA → ADDRB) ADDRB is buffer register
1
0
ADDRA and ADDRC, and ADDRB and ADDRD, are used for buffer operation (Conversion result 1 → ADDRA → ADDRC; conversion result 2 → ADDRB → ADDRD) ADDRC and ADDRD are buffer registers
1
ADDRA to ADDRD are used for buffer operation (Conversion result → ADDRA → ADDRB → ADDRC → ADDRD) ADDRB to ADDRD are buffer registers
Simultaneous Sampling 0 1 Scan Mode 0 1 Timer Trigger Select 0 0 1 1 0 1 A/D conversion start by software is enabled A/D conversion start by TPU conversion start trigger is enabled A/D conversion start by 8-bit timer conversion start trigger is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Single mode Scan mode Normal sampling operation Simultaneous sampling operation
Specifies conversion start mode 0 1 Low-power conversion mode High-speed start mode
Rev. 5.00 Sep 14, 2006 page 983 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DADR0—D/A Data Register 0 DADR1—D/A Data Register 1
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFA4 H'FFA5
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
D/A D/A
Initial value : Read/Write :
Stores data for D/A conversion
Rev. 5.00 Sep 14, 2006 page 984 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
DACR—D/A Control Register
Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 —
H'FFA6
3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
D/A
D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled
D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled
D/A Conversion Control 0 0 1 * 0 Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled
Legend: *: Don’t care
Rev. 5.00 Sep 14, 2006 page 985 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR0—Time Control Register 0 TCR1—Time Control Register 1
Bit :
7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2
H'FFB0 H'FFB1
1 CKS1 0 R/W 0 CKS0 0 R/W
8-Bit Timer Channel 0 8-Bit Timer Channel 1
CKS2 0 R/W
Initial value : Read/Write :
Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of φ/8 Internal clock: counted at falling edge of φ/64 Internal clock: counted at falling edge of φ/8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges
1 1 0 1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input
Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled
Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled
Rev. 5.00 Sep 14, 2006 page 986 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1
TCSR0 Bit :
7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 4 — 1 — 3
H'FFB2 H'FFB3
2 OS2 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 1 OS1 0 R/W
8-Bit Timer Channel 0 8-Bit Timer Channel 1
0 OS0 0 R/W 0 OS0 0 R/W
OS3 0 R/W 3 OS3 0 R/W
Initial value : Read/Write : TCSR1 Bit :
Initial value : Read/Write :
Output Select 0 0 1 1 0 1 Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output)
A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled
Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00)
Compare Match Flag A 0 [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORA
1
Compare Match Flag B 0 [Clearing conditions] • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORB
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev. 5.00 Sep 14, 2006 page 987 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1
TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB4 H'FFB5
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORA1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1
TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB6 H'FFB7
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORB1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0—Timer Counter 0 TCNT1—Timer Counter 1
TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFB8 H'FFB9
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCNT1
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 988 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCSR—Timer Control/Status Register
Bit :
7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 —
H'FFBC (W) H'FFBC (R)
2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
WDT
Initial value : 0 Read/Write : R/(W)*
Clock Select CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow period* (when φ = 20 MHz) 819.2 µs 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s
φ/2 (initial value) 25.6 µs φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072
Timer Enable 0 1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.
TCNT is initialized to H'00 and halted TCNT counts
Timer Mode Select 0 1 Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
[Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode
Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows
The method for writing to TCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 13.2.4, Notes on Register Access. Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 989 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT—Timer Counter
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFBC (W) H'FFBD (R)
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
WDT
Initial value : Read/Write :
The method for writing to TCNT is different from that for general registers to prevent inadvertent overwriting. For details see section 13.2.4, Notes on Register Access.
Rev. 5.00 Sep 14, 2006 page 990 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
RSTCSR—Reset Control/Status Register
Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 —
H'FFBE (W) H'FFBF (R)
3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 —
WDT
Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Power-on reset Manual reset
Note: * The modules H8S/2655 Series are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation
Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent inadvertent overwriting. For details see section 13.2.4, Notes on Register Access.
Rev. 5.00 Sep 14, 2006 page 991 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSTR—Timer Start Register
Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 CST5 0 R/W 4 CST4 0 R/W
H'FFC0
3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
TPU
Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation
Note: n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.
TSYR—Timer Synchro Register
Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 SYNC5 0 R/W 4 SYNC4 0 R/W
H'FFC1
3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
TPU
Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
Note: n = 5 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing 2. source must also be set by means of bits CCLR2 to CCLR0 in TCR.
Rev. 5.00 Sep 14, 2006 page 992 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR0—Timer Control Register 0
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FFD0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU0
CKEG1 CKEG0
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Rev. 5.00 Sep 14, 2006 page 993 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR0—Timer Mode Register 0
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W
H'FFD1
3 MD3 * 0 R/W
1
TPU0
2 MD2* 0 R/W
2
1 MD1 0 R/W
0 MD0 0 R/W
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —
Legend: *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation
TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation
Rev. 5.00 Sep 14, 2006 page 994 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR0H—Timer I/O Control Register 0H
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFD2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU0
TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock
0 output at compare match 1 output at compare match Toggle output at compare match
1
1 1 *
Legend: *: Don’t care TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is input capture register Capture input source is TIOCB0 pin Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock TGR0B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated.
Rev. 5.00 Sep 14, 2006 page 995 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR0L—Timer I/O Control Register 0L
Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W
H'FFD3
1 IOC1 0 R/W 0 IOC0 0 R/W
TPU0
TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is input capture register Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock TGR0C Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0D Capture input is input source is capture TIOCD0 pin registe*2 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0D Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock
Legend: *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When GRC or GRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev. 5.00 Sep 14, 2006 page 996 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER0—Timer Interrupt Enable Register 0
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3
H'FFD4
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
TPU0
TGIED 0 R/W
TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 997 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR0—Timer Status Register 0
Bit :
7 — 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0
H'FFD5
0 TGFA 0 R/(W)*
TPU0
Initial value : Read/Write :
R/(W)*
TGR Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
TGR Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
TGR Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
TGR Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 998 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT0—Timer Counter 0
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFD6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFD8 H'FFDA H'FFDC H'FFDE
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU0 TPU0 TPU0 TPU0
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 999 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR1—Timer Control Register 1
Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FFE0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU1
CKEG1 CKEG0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on φ/256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
Clock Edge 0 0 1 1 * Count at rising edge Count at falling edge Count at both edges
Legend: *: Don’t care
Note: This setting is ignored when channel 1 is in phase counting mode.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1.
Rev. 5.00 Sep 14, 2006 page 1000 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR1—Timer Mode Register 1
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 —
H'FFE1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU1
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 1Phase counting mode 4 —
Legend: *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev. 5.00 Sep 14, 2006 page 1001 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR1—Timer I/O Control Register 1
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFE2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU1
TGR1A I/O Control
0 0 0
0 1
1
0 1
TGR1A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
1
0
0 1
Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is input capture register Capture input source is TIOCA1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture
1
0 1
1
0
0
0 1
1 1 *
* *
Legend: *: Don’t care TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0B compare match/input compare match/ capture input capture TGR1B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
Rev. 5.00 Sep 14, 2006 page 1002 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER1—Timer Interrupt Enable Register 1
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 —
H'FFE4
2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A
TPU1
0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 1003 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR1—Timer Status Register 1
Bit :
7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 —
H'FFE5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU1
Initial value : Read/Write :
TGR Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
TGR Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 1004 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT1—Timer Counter 1
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFE6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU1
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFE8 H'FFEA
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU1 TPU1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 1005 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCR2—Timer Control Register 2
Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3
H'FFF0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU2
CKEG0 0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1
*
Count at rising edge Count at falling edge Count at both edges
Legend: *: Don’t care Note: This setting is ignored when channel 2 is in phase counting mode.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev. 5.00 Sep 14, 2006 page 1006 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TMDR2—Timer Mode Register 2
Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 —
H'FFF1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU2
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —
Legend: *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev. 5.00 Sep 14, 2006 page 1007 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIOR2—Timer I/O Control Register 2
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFF2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU2
TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
1
1
Legend: *: Don’t care
TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don’t care
Rev. 5.00 Sep 14, 2006 page 1008 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TIER2—Timer Interrupt Enable Register 2
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 —
H'FFF4
2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU2
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev. 5.00 Sep 14, 2006 page 1009 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TSR2—Timer Status Register 2
Bit :
7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 —
H'FFF5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU2
Initial value : Read/Write :
TGR Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
TGR Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Underflow Flag 0 1 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag 0 1 TCNT counts down TCNT counts up
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00 Sep 14, 2006 page 1010 of 1060 REJ09B0331-0500
Appendix B Internal I/O Register
TCNT2—Timer Counter 2
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFF6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU2
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFF8 H'FFFA
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU2 TPU2
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 14, 2006 page 1011 of 1060 REJ09B0331-0500
Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1
P1n
RDR1
RPOR1
Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 0 or 1
Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11)
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Internal data bus
PPG module Pulse output enable Pulse output DMA controller DMA transfer acknowledge enable DMA transfer acknowledge TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Input capture input
Appendix C I/O Port Block Diagrams
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1
P1n
RDR1
RPOR1 Input capture input
External clock input
Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 2, 3, 5, 7
Figure C.1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17)
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Internal data bus
PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Appendix C I/O Port Block Diagrams
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1
P1n
RDR1
RPOR1 Input capture input Legend: WDDR1 WDR1 RDR1 RPOR1 : Write to P1DDR : Write to P1DR : Read P1DR : Read port 1
Note: n = 4 or 6
Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16)
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Internal data bus
PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Appendix C I/O Port Block Diagrams
C.2
Port 2 Block Diagram
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2 Input capture input Legend: WDDR2 WDR2 RDR2 RPOR2
: Write to P2DDR : Write to P2DR : Read P2DR : Read port 2
Note: n = 0 or 1
Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21)
Rev. 5.00 Sep 14, 2006 page 1015 of 1060 REJ09B0331-0500
Internal data bus
PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Appendix C I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2
Internal data bus
PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Input capture input 8-bit timer module Counter external reset input Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2
Note: n = 2 or 4
Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24)
Rev. 5.00 Sep 14, 2006 page 1016 of 1060 REJ09B0331-0500
Appendix C I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2
Internal data bus
PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 8-bit timer module Counter external reset input
Legend: WDDR2 WDR2 RDR2 RPOR2
: Write to P2DDR : Write to P2DR : Read P2DR : Read port 2
Note: n = 3 or 5
Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25)
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Appendix C I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2
Legend: WDDR2 WDR2 RDR2 RPOR2
: Write to P2DDR : Write to P2DR : Read P2DR : Read port 2
Note: n = 6 or 7
Figure C.2 (d) Port 2 Block Diagram (Pins P26 and P27)
Rev. 5.00 Sep 14, 2006 page 1018 of 1060 REJ09B0331-0500
Internal data bus
PPG module Pulse output enable Pulse output 8-bit timer Compare-match output enable Compare-match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Input capture input
Appendix C I/O Port Block Diagrams
C.3
Port 3 Block Diagram
Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3
P3n
RPOR3
Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3
: Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR
Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal
Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31)
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3
RPOR3
Internal data bus
Serial receive data
Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3
: Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR
Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal
Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33)
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Appendix C I/O Port Block Diagrams
Reset R Q D P3nDDR C WDDR3 *2 Reset R Q D P3nDR C WDR3 *3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable
P3n *1
RPOR3
Legend: WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR
Notes: n = 4 or 5 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal
Figure C.3 (c) Port 3 Block Diagram (Pins P34 and P35)
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Internal data bus
Serial clock input
Appendix C I/O Port Block Diagrams
C.4
Port 4 Block Diagram
Internal data bus
A/D converter module Analog input Legennd: RPOR4 : Read port 4 Note: n = 0 to 5
RPOR4 P4n
Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45)
RPOR4 P4n
Internal data bus
A/D converter module Analog input D/A converter module Output enable Analog output
Legend: RPOR4 : Read port 4 Note: n = 6 or 7
Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47)
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Appendix C I/O Port Block Diagrams
C.5
Port 5 Block Diagram
Reset R Q D P50DDR C WDDR0 Reset R Q D P50DR C WDR5 SCI module Serial transmit data output enable Serial transmit data RDR5
P50
RPOR5
Legend: WDDR5 WDR5 RDR5 RPOR5
: Write to P5DDR : Write to P5DR : Read P5DR : Read port 5
Figure C.5 (a) Port 5 Block Diagram (Pin P50)
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P51DDR C WDDR5 Reset P51 R Q D P51DR C WDR5
RDR5
RPOR5
Legend: WDDR5 : Write to P5DDR WDR5 : Write to P5DR RDR5 : Read P5DR RPOR5 : Read port 5
Figure C.5 (b) Port 5 Block Diagram (Pin P51)
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Internal data bus
SCI module Serial receive data enable Serial receive data
Appendix C I/O Port Block Diagrams
Reset R Q D P52DDR C WDDR5 Reset R Q D P52DR C WDR5
P52 *
RDR5
RPOR5
Legend: WDDR5 WDR5 RDR5 RPOR5
: Write to P5DDR : Write to P5DR : Read P5DR : Read port 5
Note: * Priority order: Serial clock input > serial clock output > DR output
Figure C.5 (c) Port 5 Block Diagram (Pin P52)
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Internal data bus
SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input
Appendix C I/O Port Block Diagrams
Reset R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5
RDR5
RPOR5 A/D converter A/D converter external trigger input Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5
Figure C.5 (d) Port 5 Block Diagram (Pin P53)
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Internal data bus
Appendix C I/O Port Block Diagrams
C.6
Port 6 Block Diagram
Reset R Q D P60DDR C WDDR6 Mode 1/2/3/7 P60 Mode 4/5/6 Reset R Q D P60DR C WDR6
Internal data bus
Bus controller Chip select DMA controller DMA request input
RDR6
RPOR6
Legend: WDDR6 WDR6 RDR6 RPOR6
: Write to P6DDR : Write to P6DR : Read P6DR : Read port 6
Figure C.6 (a) Port 6 Block Diagram (Pin P60)
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Appendix C I/O Port Block Diagrams
Reset R Q D P61DDR C WDDR6 Mode 1/2/3/7 P61 Mode 4/5/6 Reset R Q D P61DR C WDR6
RDR6
RPOR6
Legend: WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6
Figure C.6 (b) Port 6 Block Diagram (Pin P61)
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Internal data bus
Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end
Appendix C I/O Port Block Diagrams
Reset R Q D P62DDR C WDDR6 Reset P62 R Q D P62DR C WDR6 RDR6
RPOR6 DMA controller DMA request input Legend: WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6
Figure C.6 (c) Port 6 Block Diagram (Pin P62)
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P63DDR C WDDR6 Reset R Q D P63DR C WDR6 DMA controller DMA transfer end enable DMA transfer end RDR6
P63
RPOR6
Legend: WDDR6 WDR6 RDR6 RPOR6
: Write to P6DDR : Write to P6DR : Read P6DR : Read port 6
Figure C.6 (d) Port 6 Block Diagram (Pin P63)
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6
RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6 WDR6 RDR6 RPOR6
: Write to P6DDR : Write to P6DR : Read P6DR : Read port 6
Note: n = 4 or 5
Figure C.6 (e) Port 6 Block Diagram (Pins P64 and P65)
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P6nDDR C WDDR6 Mode 1/2/3/7 P6n Mode 4/5/6 Reset R Q D P6nDR C WDR6
Internal data bus
Bus controller Chip select
RDR6
RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6 WDR6 RDR6 RPOR6
: Write to P6DDR : Write to P6DR : Read P6DR : Read port 6
Note: n = 6 or 7
Figure C.6 (f) Port 6 Block Diagram (Pins P66 and P67)
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Appendix C I/O Port Block Diagrams
C.7
Port A Block Diagram
Reset R Q D PAnPCR C WPCRA RPCRA
Mode 4/5*3 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA
PAn
Mode 1/2/3/7 Mode 4/5/6
RDRA
RPORA
Legend: WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR
Notes: n = 0 to 3 1. Output enable signal 2. Open drain control signal 3. Set priority
Figure C.7 (a) Port A Block Diagram (Pins PA0 to PA3)
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Internal address bus
Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D PA4PCR C WPCRA RPCRA
Internal data bus
Mode 4/5*3 Reset S R Q D PA4DDR C WDDRA *1 Reset R Q D PA4DR C WDRA *2 Reset R Q D PA4ODR C WODRA RODRA
PA4
Mode 1/2/3/7 Mode 4/5/6
RDRA
RPORA Legend: WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR Interrupt controller
IRQ interrupt input
Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority
Figure C.7 (b) Port A Block Diagram (Pin PA4)
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Internal address bus
Appendix C I/O Port Block Diagrams
Reset R Q D PAnPCR C WPCRA RPCRA
Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA
PAn
Mode 1/2/3/7 Mode 4/5/6
RDRA
RPORA Interrupt controller Legend: WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA : Write to PADDR : Write to PADR : Write to PAODR : Write to PAPCR : Read PADR : Read port A : Read PAODR : Read PAPCR IRQ interrupt input
Notes: n = 5 to 7 1. Output enable signal 2. Open drain control signal
Figure C.7 (c) Port A Block Diagram (Pins PA5 to PA7)
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Internal address bus
Internal data bus
Appendix C I/O Port Block Diagrams
C.8
Port B Block Diagram
Reset R Q D PBnPCR C WPCRB RPCRB
Mode 1/4/5* Reset S R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB
PBn
Mode 3/7 Mode 1/2/4/5/6
RDRB
RPORB
Legend: WDDRB WDRB WPCRB RDRB RPORB RPCRB
: Write to PBDDR : Write to PBDR : Write to PBPCR : Read PBDR : Read port B : Read PBPCR
Notes: n = 0 to 7 * Set priority
Figure C.8 Port B Block Diagram (Pin PBn)
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Internal address bus
Internal data bus
Appendix C I/O Port Block Diagrams
C.9
Port C Block Diagram
Reset R Q D PCnPCR C WPCRC RPCRC
Internal data bus
Mode 1/4/5* Reset S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC
PCn
Mode 3/7 Mode 1/2/4/5/6
RDRC
RPORC
Legend: WDDRC : Write to PCDDR WDRC : Write to PCDR WPCRC : Write to PCPCR RDRC : Read PCDR RPORC : Read port C RPCRC : Read PCPCR
Notes: n = 0 to 7 * Set priority
Figure C.9 Port C Block Diagram (Pin PCn)
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Internal address bus
Appendix C I/O Port Block Diagrams
C.10
Port D Block Diagram
Reset
Internal upper data bus Internal lower data bus
R Q D PDnPCR C WPCRD RPCRD
Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD
Mode 3/7 Mode 1/2/4/5/6 External address write
PDn
Mode 3/7 Mode 1/2/4/5/6
External address upper write External address lower write
RDRD
RPORD Legend: WDDRD WDRD WPCRD RDRD RPORD RPCRD
: Write to PDDDR : Write to PDDR : Write to PDPCR : Read PDDR : Read port D : Read PDPCR
External address upper read
External address lower read
Note: n = 0 to 7
Figure C.10 Port D Block Diagram (Pin PDn)
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Appendix C I/O Port Block Diagrams
C.11
Port E Block Diagram
Reset
Internal upper data bus Internal lower data bus
R Q D PEnPCR C WPCRE RPCRE
Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE
Mode 3/7 8-bit bus mode Mode 1/2/4/5/6 16-bit bus mode External address write
PEn
Mode 3/7 Mode 1/2/4/5/6
RDRE
RPORE Legend: WDDRE WDRE WPCRE RDRE RPORE RPCRE
: Write to PEDDR : Write to PEDR : Write to PEPCR : Read PEDR : Read port E : Read PEPCR
External address lower read
Note: n = 0 to 7
Figure C.11 Port E Block Diagram (Pin PEn)
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Appendix C I/O Port Block Diagrams
C.12
Port F Block Diagram
Internal data bus
Bus controller BRLE bit Bus request input Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F
Reset R Q D PF0DDR C
Mode 1/2/4/5/6
WDDRF Reset
PF0
R Q D PF0DR C WDRF
RDRF
RPORF
Figure C.12 (a) Port F Block Diagram (Pin PF0)
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Appendix C I/O Port Block Diagrams
Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Mode 1/2/4/5/6
PF1
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (b) Port F Block Diagram (Pin PF1)
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Internal data bus
Bus controller BRLE output Bus request acknowledge output
Appendix C I/O Port Block Diagrams
Reset R Q D PF2DDR C WDDRF Reset Mode 1/2/4/5/6 PF2 R Q D PF2DR C WDRF Mode 1/2/4/5/6
Internal data bus
Bus controller Wait enable
Bus request output enable Bus request output RDRF
RPORF
Wait input Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (c) Port F Block Diagram (Pin PF2)
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Appendix C I/O Port Block Diagrams
Reset R Q D PF3DDR C WDDRF Mode 3/7 PF3 Mode 1/2/4/5/6 Reset R Q D PF3DR C WDRF
Mode 1/2/4/5/6
Internal data bus
Bus controller LWR output
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (d) Port F Block Diagram (Pin PF3)
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Appendix C I/O Port Block Diagrams
Reset R Q D PF4DDR C WDDRF Mode 3/7 PF4 Mode 1/2/4/5/6 Reset R Q D PF4DR C WDRF
Mode 1/2/4/5/6
Internal data bus
Bus controller
HWR output
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (e) Port F Block Diagram (Pin PF4)
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Appendix C I/O Port Block Diagrams
Reset R Q D PF5DDR C WDDRF Mode 3/7 PF5 Mode 1/2/4/5/6 Reset R Q D PF5DR C WDRF
Mode 1/2/4/5/6
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (f) Port F Block Diagram (Pin PF5)
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Internal data bus
Bus controller RD output
Appendix C I/O Port Block Diagrams
Reset R Q D PF6DDR C WDDRF Mode 3/7 PF6 Mode 1/2/4/5/6 Reset R Q D PF6DR C WDRF
Mode 1/2/4/5/6
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Figure C.12 (g) Port F Block Diagram (Pin PF6)
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Internal data bus
Bus controller
AS output
Appendix C I/O Port Block Diagrams
Mode 1/2/4/5/6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF
: Write to PFDDR : Write to PFDR : Read PFDR : Read port F
Note: * Set priority
Figure C.12 (h) Port F Block Diagram (Pin PF7)
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Internal data bus
φ
Appendix C I/O Port Block Diagrams
C.13
Port G Block Diagram
Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C WDRG Mode 4/5/6
PG0
RDRG
RPORG
Legend: WDDRG WDRG RDRG RPORG
: Write to PGDDR : Write to PGDR : Read PGDR : Read port G
Figure C.13 (a) Port G Block Diagram (Pin PG0)
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Internal data bus
Bus controller CAS/OE enable CAS/OE output
Appendix C I/O Port Block Diagrams
Reset R Q D PGnDDR C WDDRG Mode 1/2/3/7 PGn Mode 4/5/6 Reset R Q D PGnDR C WDRG
Internal data bus
Bus controller Chip select
RDRG
RPORG
Legend: WDDRG WDRG RDRG RPORG
: Write to PGDDR : Write to PGDR : Read PGDR : Read port G
Note: n = 1, 2, 3
Figure C.13 (b) Port G Block Diagram (Pins PG1 to PG3)
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Appendix C I/O Port Block Diagrams
Mode Mode 1/4/5 2/3/6/7 Reset
WDDRG Reset Mode 3/7 PG4 Mode 1/2/4/5/6 R Q D PG4DR C WDRG
RDRG
RPORG
Legend: WDDRG WDRG RDRG RPORG
: Write to PGDDR : Write to PGDR : Read PGDR : Read port G
Figure C.13 (c) Port G Block Diagram (Pin PG4)
Rev. 5.00 Sep 14, 2006 page 1050 of 1060 REJ09B0331-0500
Internal data bus
S R Q D PG4DDR C
Bus controller Chip select
Appendix D Pin States
Appendix D Pin States
D.1 Port States in Each Mode
Table D.1 I/O Port States in Each Processing State
MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 Port 4 Port 5 P65 to P62 P67/CS7 P66/CS6 P61/CS5 P60/CS4 Port A PA0 to PA3 1 to 3, 7 4, 5 T L kept kept T T kept [OPE = 0] T [OPE = 1] kept kept T I/O port Address output 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 3, 7 4 to 6 PowerOn Manual Reset Reset T T T T T T T T kept kept kept T kept kept kept kept Hardware Software Standby Standby Mode Mode T T T T T T T T kept kept kept T kept kept kept Bus Release State kept kept kept T kept kept kept Program Execution State Sleep Mode I/O port I/O port I/O port Input port I/O port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4
[DDR · OPE = 0] T T [DDR · OPE = 1] H
6
T
kept
T
[DDR · OPE = 0] T T [DDR · OPE = 1] kept
[DDR = 0] Input port [DDR = 1] Address output
Rev. 5.00 Sep 14, 2006 page 1051 of 1060 REJ09B0331-0500
Appendix D Pin States
Program Execution State Sleep Mode I/O port Address output
MCU Port Name Operating Pin Name Mode Port A PA4 1 to 3, 7 4, 5
PowerOn Manual Reset Reset T L kept kept
Hardware Software Standby Standby Mode Mode T T kept [OPE = 0] T [OPE = 1] kept
Bus Release State kept T
6
T
kept
T
[DDR · OPE = 0] T T [DDR · OPE = 1] kept kept kept
[DDR = 0] Input port [DDR = 1] Address output I/O port [DDR = 0] Input port [DDR = 1] Address output [DDR = 0] Input port [DDR = 1] Address output
Port A PA5 to PA7
1 to 3, 7 4, 5
T T
kept kept
T T
[DDR · OPE = 0] T T [DDR · OPE = 1] kept [DDR · OPE = 0] T T [DDR · OPE = 1] kept
6
T
kept
T
Port B
1, 4, 5
L
kept
T
[OPE = 0] T [OPE = 1] kept
T
Address output
2, 6
T
kept
T
[DDR · OPE = 0] T T [DDR · OPE = 1] kept kept kept
[DDR = 0] Input port [DDR = 1] Address output I/O port
3, 7
T
kept
T
Rev. 5.00 Sep 14, 2006 page 1052 of 1060 REJ09B0331-0500
Appendix D Pin States
Program Execution State Sleep Mode Address output
MCU Port Name Operating Pin Name Mode Port C 1, 4, 5
PowerOn Manual Reset Reset L kept
Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept
Bus Release State T
2, 6
T
kept
T
[DDR · OPE = 0] T T [DDR · OPE = 1] kept kept T kept kept T kept T kept kept T
[DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus
3, 7 Port D
T
kept T* kept kept T*
T T T T T
1, 2, 4 to 6 T 3, 7 T
Port E
1, 2, 8-bit T 4 to 6 bus 16- T bit bus 3, 7 T
kept [DDR = 0] T [DDR = 1] Clock output kept
T T
kept [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H [OPE = 0] T [OPE = 1] H kept
kept [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T
I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS, RD, HWR, LWR
PF7/φ
1, 2, 4 to 6 Clock output
3, 7
T
T
PF6/AS PF5/RD PF4/HWR PF3/LWR
1, 2, 4 to 6 H
H*
T
3, 7
T
kept
T
kept
I/O port
Rev. 5.00 Sep 14, 2006 page 1053 of 1060 REJ09B0331-0500
Appendix D Pin States
Program Execution State Sleep Mode [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS
MCU Port Name Operating Pin Name Mode
PowerOn Manual Reset Reset
Hardware Software Standby Standby Mode Mode [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] T kept T [DDR · OPE = 1] H T T T kept kept
Bus Release State [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T
PF2/LCAS/ 1, 2, 4 to 6 T WAIT/ BREQO
T [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H*
3, 7 PF1/BACK
T
kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] BREQ kept [DDR = 0] T [DDR = 1] H* kept kept [DDR = 0] T [DDR = 1] H*
T T
kept L
I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0
1, 2, 4 to 6 T
3, 7
T
T T
kept T
PF0/BREQ 1, 2, 4 to 6 T
3, 7 PG4/CS0 1, 4, 5 2, 6
T H T
T T
kept
[DDR · OPE = 0] T
3, 7 PG3/CS1 PG2/CS2 PG1/CS3 1 to 3, 7 4 to 6
T T T
kept kept
I/O port I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3
[DDR · OPE = 0] T T [DDR · OPE = 1] H
Rev. 5.00 Sep 14, 2006 page 1054 of 1060 REJ09B0331-0500
Appendix D Pin States
Program Execution State Sleep Mode I/O port [DRAME = 0, PSRAME = 0] Input port [DRAME = 1, PSRAME = 0] CAS [DRAME = 0, PSRAME = 1] OE
MCU Port Name Operating Pin Name Mode PG0/CAS OE 1 to 3, 7 4 to 6
PowerOn Manual Reset Reset T T kept
Hardware Software Standby Standby Mode Mode T kept [DRAME = 0, PSRAME = 0] kept [OPE = 0] T [DRAME · OPE= 1] CAS [PSRAME · OPE = 1] OE
Bus Release State kept T
[DRAME = 0, T PSRAME = 0] kept [DRAME = 1] H* [PSRAME = 1] H*
Legend: H L T kept DDR OPE WAITE BRLE BREQOE DRAME LCASE
: High level : Low level : High impedance : Input port becomes high-impedance, output port retains state : Data direction register : Output port enable : Wait input enable : Bus release enable : BREQO pin enable : DRAM space setting : DRAM space setting, CW2 = LCASS = 0
PSRAME : PSRAM space setting Note: * Indicates the state after completion of the executing bus cycle.
Rev. 5.00 Sep 14, 2006 page 1055 of 1060 REJ09B0331-0500
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY t1 ≥ 10tcyc RES t2 ≥ 0ns
Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset.
STBY t ≥ 100ns RES tOSC tNMIRH
NMI
Figure E.2 Timing of Recovery from Hardware Standby Mode
Rev. 5.00 Sep 14, 2006 page 1056 of 1060 REJ09B0331-0500
Appendix F Product Code Lineup
Appendix F Product Code Lineup
Table F.1 H8S/2655 Group Product Code Lineup
Product Code 5 V version (VCC = 5.0 V ±10%) HD6432655 Mark Code HD6432655(***)TE HD6432655(***)F Low-voltage version (VCC = 2.7 to 5.5 V) HD6432655(***)TE HD6432655(***)F ZTAT
TM
Product Type H8S/2655 Mask ROM
Package (Package Code) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128)
5 V version (VCC = 5.0 V ±10%)
HD6472655
HD6472655TE HD6472655F
Low-voltage version (VCC = 2.7 to 5.5 V)
HD6472655VTE HD6472655VF
H8S/2653 Mask ROM
5 V version (VCC = 5.0 V ±10%)
HD6432653
HD6432653(***)TE HD6432653(***)F
Low-voltage version (VCC = 2.7 to 5.5 V)
HD6432653(***)TE HD6432653(***)F
Note: (***) indicates the ROM code.
Rev. 5.00 Sep 14, 2006 page 1057 of 1060 REJ09B0331-0500
Appendix G Package Dimensions
Appendix G Package Dimensions
The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority.
JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g
HD
*1
D
90
61
91
60
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp b1
c1
*2
E
HE
c
Terminal cross section
ZE
Reference Dimension in Millimeters Symbol
120
31
A2
ZD
Index mark F
A1
A
c
1
30
θ
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1
Min Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.12 0.17 0.22 0.15 0.12 0.17 0.22 0.15 0° 8° 0.4 0.07 0.10 1.20 1.20 0.4 0.5 0.6 1.0
Figure G.1 TFP-120 Package Dimensions
Rev. 5.00 Sep 14, 2006 page 1058 of 1060 REJ09B0331-0500
Appendix G Package Dimensions
JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g
HD
*1
D 65 64
102 103
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE E
b1
c1
*2
128 1 ZD Index mark 38
39
ZE
c
Terminal cross section
Reference Dimension in Millimeters Symbol
F
A A2
θ
e
*3
A1
L L1
y
bp
x
M
Detail F
D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1
Nom Max 20 14 2.70 21.8 22.0 22.2 15.8 16.0 16.2 3.15 0.00 0.10 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.10 0.10 0.75 0.75 0.3 0.5 0.7 1.0
Min
Figure G.2 FP-128 Package Dimensions
Rev. 5.00 Sep 14, 2006 page 1059 of 1060 REJ09B0331-0500
c
Appendix G Package Dimensions
Rev. 5.00 Sep 14, 2006 page 1060 of 1060 REJ09B0331-0500
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2655 Group
Publication Date: 1st Edition, November 1995 Rev.5.00, September 14, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
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H8S/2655 Group Hardware Manual
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