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H8SX1544

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H8SX1544 - Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series - Renesas Technology Corp

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H8SX1544 数据手册

REJ09B0381-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 H8SX/1544 Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series H8SX/1544 R5F61544 R5F61543 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.2.00 Revision Date: Oct. 16, 2007 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.2.00 Oct. 16, 2007 Page ii of liv REJ09B0381-0200 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.2.00 Oct. 16, 2007 Page iii of liv REJ09B0381-0200 Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions in this Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev.2.00 Oct. 16, 2007 Page iv of liv REJ09B0381-0200 Preface The H8SX/1544 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs. Target Users: This manual was written for users who will be using the H8SX/1544Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8SX/1544 Group to the target users. Refer to the H8SX Family Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, and peripheral functions. • In order to understand the details of the CPU's functions Read the H8SX Family Software Manual. • In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 25, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. DMA Controller or 16-bit timer pulse unit, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev.2.00 Oct. 16, 2007 Page v of liv REJ09B0381-0200 H8SX/1544 Group manuals: Document Title H8SX/1544 Group Hardware Manual H8SX Family Software Manual Document No. This manual REJ09B0102 Rev.2.00 Oct. 16, 2007 Page vi of liv REJ09B0381-0200 Main Revisions for This Edition Item All Page ⎯ Revision (See Manual for Details) Description of SSU added SSU: Synchronous Serial communication Unit 4.2 Exception Sources 81 and Exception Handling Vector Table Table 4.2 Exception Handling Vector Table 7.1 Features 187 Description amended • DMAC activation methods are … External request: Low level or falling edge detection of DREQ signal can be selected External request is available for all four channels (In block transfer mode only low-level detection can be selected.) 7.3.7 DMA Address Control Register (DACR) 7.5.2 Transfer Modes 207, 208 Bits 15 and 7 description amended (Before) extended area overflow → (After) extended repeat area overflow 216 (1) Normal Transfer Mode DACK signal description deleted … The TEND signal is output only in the last DMA transfer. Figure 7.7 shows an example of signal timing … 217 Repeat Transfer Mode DACK signal description deleted … The timing of the TEND signal are the same as in normal transfer mode. … 7.5.4 Bus Access Modes 223 (2) Burst Access Mode Description amended … However, setting the IBCCS bit in BCR2 of the bus controller makes the DMAC release the bus to pass the bus to another bus master. … 7.5.9 DMA Basic Bus Cycle Figure 7.23 Example of Bus Timing of DMA Transfer 236 Figure 7.23 amended (Before) RD → (After) RD “Reserved for system use” description in vector number 76 to 79 deleted Rev.2.00 Oct. 16, 2007 Page vii of liv REJ09B0381-0200 Item 7.8 Interrupt Sources Figure 7.38 Interrupt and Interrupt Sources 8.2.1 Port 1 Page 256 Revision (See Manual for Details) Figure 7.38 amended (Before) TSIE bit → (After) TSEIE bit 271 (1) P17/SCL0/ IRQ7-A/ADTRG1 Description amended Setting IIC2_0 Module Name IIC2_0 I/O port Pin Function SC L0 I/O P17 output P17 input (initial value) SCL0_OE* 1 0 0 I/O Port P17DDR ⎯ 1 0 8.2.12 Port K Table 8.5 Available Output Signals and Settings in Each Port 295, 296 Table 8.5 amended Output Specification Signal Name 2 Output Signal Name Signal Selection Register Settings Peripheral Module Settings DACR_0.AMS = 1, DMDR_0.DACKE = 1 When SCMR_2.SMIF = 1: SCR_2.TE = 1 or SCR_2.RE = 1 while SMR_2.GM = 0, SCR_2.CKE[1,0] = 01 or while SMR_2.GM = 1 When SCMR_2.SMIF = 0: SCR_2.TE = 1 or SCR_2.RE = 1 while SMR_2.C/A = 0, SCR_2.CKE[1,0] = 01 or while SMR_2.C/A = 1, SCR_2.CKE1 = 0 P2 2 SSCK1_OE TIOCC3_OE TxD0_OE 1 SSI1_OE TIOCA3_OE 0 TIOCB3_OE SCK0_OE SSCK_1 TIOCC3 Tx D0 SSI_1 TIOCA3 TIOCB3 SCK0 SSU.SSCRH_1.MSS1 = 1, SSU.SSCRH_1.SCKS = 1 TPU.TMDR_3.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 SCR_0.TE = 1 SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0, SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 When SCMR_0.SMIF = 1: SCR_0.TE = 1 or SCR_0.RE = 1 while SMR_0.GM = 0, SCR_0.CKE[1,0] = 01 or while SMR_0.GM = 1 When SCMR_0.SMIF = 0: SCR_0.TE = 1 or SCR_0.RE = 1 while SMR_0.C/A = 0, SCR_0.CKE[1,0] = 01 or while SMR_0.C/A = 1, SCR_0.CKE1 = 0 P3 7 SGOUT3_OE SGOUT3 SDG3.SGCR1.SGE = 1 Port P1 DACK0_A_OE DACK0_A SCK2_OE SCK2 299, 300 Output signal names amended Pl1 (Before) SSI_0 → (After) SSI0 Pl0 (Before) SSO_0 → (After) SSO0 Rev.2.00 Oct. 16, 2007 Page viii of liv REJ09B0381-0200 Item Page Revision (See Manual for Details) Figure 9.54 amended TGR write cycle T2 T1 Pφ Address TCNT address 394 9.9.12 Conflict between TCNT Write and Overflow/Underflow Figure 9.54 Conflict between TCNT Write and Overflow Write TCNT write data H'FFFF Prohibited M TCNT TCFV flag 12.9.6 Writing to Registers during SCI Transmit or Receive 13.3.5 I C Bus Status Register (ICSR) 2 486 Newly added 502 Description added Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting condition] • • • • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set to 1 When the start condition has been issued In slave mode, after changing from receive mode to transmit mode 13.4.1 I C Bus Format 507 Figure 13.3 I C Bus Formats 2 2 Figure 13.3 amended (a) I C Bus Format m: Transfer frame count (m ≥1) I C Bus Format (start condition retransmission) m1 and m2: 1: Transfer frame count (m1 and m2 ≥1) 2 2 13.4.4 Slave Transmit 512 Operation 13.4.5 Slave Receive Operation 515 Description amended 1. … ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. … Description amended 1. … ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. … Table 13.3 amended Abbreviation of NACK detection and arbitration lost amended (Before) MAKI → (After) NAKI 13.5 Interrupt Request 521 Table 13.3 Interrupt Requests Rev.2.00 Oct. 16, 2007 Page ix of liv REJ09B0381-0200 Item 14.2.3 Input/Output Pins Table 14.1 Pin Configuration of the RCAN-ET 14.2.4 Memory Map Figure 14.2 RCAN-ET Memory Map Page 527 Revision (See Manual for Details) Table 14.1 amended Channel 0 Name Transmit data pin Receive data pin 1 Transmit data pin Receive data pin Abbreviation CTx_0 CRx_0 CTx_1 CRx_1 I/O Output Input Output Input Function CAN-bus transmit pin CAN-bus receive pin CAN-bus transmit pin CAN-bus receive pin 528 Note added Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed. Addresses shown above are offset addresses. As for actual addresses, see section 25, List of Registers. 14.3.1 Mail Box Structure Table 14.2 Address Map for Each Mailbox 529 Table 14.2 amended Address Control 0 Mailbox 0 (Receive Only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 bytes H'100 to H'103 H'120 to H'123 H'140 to H'143 H'160 to H'163 H'180 to H'183 H'1A0 to H'1A3 H'1C0 to H'1C3 H'1E0 to H'1E3 H'200 to H'203 H'220 to H'223 H'240 to H'243 H'260 to H'263 H'280 to H'283 H'2A0 to H'2A3 H'2C0 to H'2C3 H'2E0 to H'2E3 LAFM 4 bytes H'104 to H' 107 H'124 to H'127 H'144 to H'147 H'164 to H'167 H'184 to H'187 H'1A4 to H'1A7 H'1C4 to H'1C7 H'1E4 to H'1E7 H'204 to H'207 H'224 to H'227 H'244 to H'247 H'264 to H'267 H'284 to H'287 H'2A4 to H'2A7 H'2C4 to H'2C7 H'2E4 to H'2E7 Data 8 bytes H'108 to H'10F H'128 to H'12F H'148 to H'14F H'168 to H'16F H'188 to H'18F H'1A8 to H'1AF H'1C8 to H'1CF H'1E8 to H'1EF H'208 to H'20F H'228 to H'22F H'248 to H'24F H'268 to H'26F H'288 to H'28F H'2A8 to H'2AF H'2C8 to H'2CF H'2E8 to H'2EF Control 1 2 bytes H'110 to H'111 H'130 to H'131 H'150 to H'151 H'170 to H'171 H'190 to H'191 H'1B0 to H'1B1 H'1D0 to H'1D1 H'1F0 to H'1F1 H'210 to H'211 H'230 to H'231 H'250 to H'251 H'270 to H'271 H'290 to H'291 H'2B0 to H'2B1 H'2D0 to H'2D1 H'2F0 to H'2F1 Rev.2.00 Oct. 16, 2007 Page x of liv REJ09B0381-0200 Item 14.3.1 Mail Box Structure Figure 14.3 Mailbox-n Structure Page 530 Revision (See Manual for Details) Figure 14.3 amended MB0 (reception MB) Regiter Name Address MB[0].CONTROL0H MB[0].CONTROL0L MB[0].LAFMH MB[0].LAFML MB[0].MSG_DATA[0][1] MB[0].MSG_DATA[2][3] MB[0].MSG_DATA[4][5] MB[0].MSG_DATA[6][7] MB[0].CONTROL1H, L H'100 H'102 H'104 H'106 H'108 H'10A H'10C H'10E H'110 MB1 to 15 (MB for transmission/reception) Register Name Address MB[n].CONTROL0H MB[n].CONTROL0L MB[n].LAFMH MB[n].LAFML H'100 + n*32 H'102 + n*32 H'104 + n*32 H'106 + n*32 MB[n].MSG_DATA[0][1] H'108 + n*32 MB[n].MSG_DATA[2][3] H'10A + n*32 MB[n].MSG_DATA[4][5] H'10C + n*32 MB[n].MSG_DATA[6][7] H'10E + n*32 MB[n].CONTROL1H, L H'110 + n*32 Note amended Notes: n = 1 to 15 (Mailbox number) 1. All bits shadowed in grey are reserved and the write value should be 0. The value returned by a read may not always be 0 and should not be relied upon. 2 MBC1 bit in mailbox is fixed to 1. 3. ATX and DART are not supported by mailbox-0, and the MBC setting of mailbox-0 is limited. 4. When the MCR15 bit is 1, the order of STDID, RTR, IDE and EXTID of both message control and LAFM differs from HCAN2. 14.4 Local Acceptance 535 Filter Mask (LAFM) Figure 14.4 Acceptance Filter 14.4.1 Master Control 538 Register (MCR) Figure 14.5 ID Reorder Rev.2.00 Oct. 16, 2007 Page xi of liv REJ09B0381-0200 Register names amended MB[N].LAFMH MB[N].LAFML Note added Note: N = 0 to 15 (Mailbox number) Note added Note: N = 0 to 15 (Mailbox number) Item Page Revision (See Manual for Details) Figure 14.9 amended RCAN-ET is in Transmit/Receive Mode (MBC[n] = 0) Mailbox[n] is ready to be updated for next transmission 577 14.6.3 Message Transmission Sequence Figure 14.9 Transmission Request Update Message Data of Mailbox[n] Clear TXACK[n] Yes Write '1' to the TXPR[n] bit at any desired time TXACK[n] set? No Monitor for the next interrupt Internal Arbitration 'n' Highest Priority? Yes No Yes No IRR8 set? Monitor for the next interrupt Transmission Start CAN Bus Arbitration Acknowledge Bit CAN Bus Note added Note: n = 1 to 15 (Mailbox number) Rev.2.00 Oct. 16, 2007 Page xii of liv REJ09B0381-0200 Item 14.6.4 Message Receive Sequence Figure 14.11 Message Receive Sequence Page 579 Revision (See Manual for Details) Figure 14.11 amended Exit Interrupt Service Routine Check and clear UMSR[N]*2 Check and clear UMSR[N]*2 Write 1 to RXPR[N] Write 1 to RFPR[N] Read Mailbox[N] Read Mailbox[N] Read RXPR[N] = 1 Read RFPR[N] = 1 Yes IRR[1] set? No Read IRR CPU received interrupt due to CAN Message Reception Notes: N = 0 to 15 (Mailbox number) 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the message has not been updated. 2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/UMSR[N] when UMSR[N] = 1 and consider the message obsolete. Rev.2.00 Oct. 16, 2007 Page xiii of liv REJ09B0381-0200 Item Page Revision (See Manual for Details) Table 14.10 amended Channel 0 Interrupt ERS_0 Description Error Passive Mode (TEC ≥128 or REC ≥128) Bus Off (TEC ≥256)/Bus Off recovery Error warning (TEC ≥96) Error warning (REC ≥96) OVR_0 Message error detection Reset/halt/CAN sleep transition Overload frame transmission Unread message overwrite (overrun) Detection of CAN bus operation in CAN sleep mode SLE_0 R M1_0* R M0_0* 1 ERS_1 2 2 14.7 Interrupt Sources 583 Table 14.10 RCAN-ET Interrupt Sources Interrupt Flag IRR5 IRR6 IRR3 IRR4 IRR13* IRR0 IRR7 IRR9 IRR12 IRR8 IRR1* IRR2* IRR5 IRR6 IRR3 IRR4 IRR13* IRR0 IRR7 IRR9 IRR12 IRR8 IRR1* IRR2* 3 3 1 3 3 1 DMAC Activation Not possible Message transmission/transmission disabled (slot empty) Data frame reception/ Remote frame reception Error Passive Mode (TEC ≥128 or REC ≥128) Bus Off (TEC ≥256)/Bus Off recovery Error warning (TEC ≥96) Error warning (REC ≥96) Possible Not possible OVR_1 Message error detection Reset/halt/CAN sleep transition Overload frame transmission Unread message overwrite (overrun) Detection of CAN bus operation in CAN sleep mode SLE_1 R M1_1* R M0_1* 2 2 Message transmission/transmission disabled (slot empty) Data frame reception/ Remote frame reception Possible 15.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) 604 Bit figure amended • SSTDR0 Bit Bit Name Initial Value R/W • SSTDR1 Bit Bit Name Initial Value R/W • SSTDR2 Bit Bit Name Initial Value R/W • SSTDR3 Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 Rev.2.00 Oct. 16, 2007 Page xiv of liv REJ09B0381-0200 Item Page Revision (See Manual for Details) Description amended … Be sure not to access to invalid SSRDR. When the SSU has received 1-byte data, … Bit figure amended • SSRDR0 Bit Bit Name Initial Value R/W • SSRDR1 Bit Bit Name Initial Value R/W • SSRDR2 Bit Bit Name Initial Value R/W • SSRDR3 Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 15.3.8 SS Receive 605 Data Registers 0 to 3 (SSRDR0 to SSRDR3) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 15.4.5 SSU Mode Figure 15.6 Flowchart Example of Data Transmission (SSU Mode) 15.4.7 Clock Synchronous Communication Mode Figure 15.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) 18.3.6 PWM Duty Registers A, C, E, G (PWDTRA, PWDTRC, PWDTRE, PWDTRG) 18.4.2 8-Bit Data Registers 615 Figure 15.6 amended [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. … 624 Figure 15.14 amended [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. … 662 Description added …, data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). PWDTR is initialized to H'00 when CST bit is 0. 667 Description amended …; in this case, the lower eight bits are read as H'FF. Rev.2.00 Oct. 16, 2007 Page xv of liv REJ09B0381-0200 Item 22.6.1 Programming/ Erasing Interface Registers Page 717 Revision (See Manual for Details) (5) Flash Transfer Destination Address Register (FTDAR) Bit 7 description amended 1: The value specified by bits TDER and TDA6 to TDA0 is between H'03 and H'FF and download has stopped 22.6.2 Programming/ Erasing Interface Parameters 725 (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) Description amended … The operating frequency available in this LSI ranges from 8 MHz to 40 MHz. 22.11 Standard Serial 766 Communication Interface Specifications for Boot Mode (3) Inquiry and Selection States (h) Erased Block Information Inquiry 24.1 Features Table 24.1 Operating States 25.1 Register Addresses (Address Order) 25.2 Register Bits 843 798 Description amended • Size (two bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. Note 4 amended Notes: 4. Some SCI registers, the motor control PWM, 16-bit PWM, RCAN-ET, SSU*, and SDG are reset. Other peripheral modules retain their states. Note 3 amended Notes: 3. PWM10 is Motor Control PWM. 862 Note 1 amended and note 3 added Notes: 1. SSU: Synchronous Serial communication Unit 2. PWM16 is 16-bit PWM. 3. PWM10 is Motor Control PWM. 25.3 Register States in 862 Each Operating Mode Note 1 amended and note 3 added Notes: 1. SSU: Synchronous Serial communication Unit 2. PWM16 is 16-bit PWM. 3. PWM10 is Motor Control PWM. All trademarks and registered trademarks are the property of their respective owners. Rev.2.00 Oct. 16, 2007 Page xvi of liv REJ09B0381-0200 Contents Section 1 1.1 1.2 1.3 Overview..............................................................................................1 Features.................................................................................................................................. 1 Block Diagram ....................................................................................................................... 2 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 9 Section 2 2.1 2.2 CPU....................................................................................................19 2.3 2.4 2.5 2.6 2.7 2.8 Features................................................................................................................................ 19 CPU Operating Modes ......................................................................................................... 21 2.2.1 Normal Mode.......................................................................................................... 21 2.2.2 Middle Mode........................................................................................................... 23 2.2.3 Advanced Mode...................................................................................................... 24 2.2.4 Maximum Mode ..................................................................................................... 25 Instruction Fetch .................................................................................................................. 27 Address Space...................................................................................................................... 27 Registers............................................................................................................................... 28 2.5.1 General Registers .................................................................................................... 29 2.5.2 Program Counter (PC) ............................................................................................ 30 2.5.3 Condition-Code Register (CCR) ............................................................................. 30 2.5.4 Extended Control Register (EXR) .......................................................................... 32 2.5.5 Vector Base Register (VBR)................................................................................... 32 2.5.6 Short Address Base Register (SBR)........................................................................ 32 2.5.7 Multiply-Accumulate Register (MAC) ................................................................... 33 2.5.8 Initial Values of CPU Registers .............................................................................. 33 2Data Formats...................................................................................................................... 33 2.6.1 General Register Data Formats ............................................................................... 33 2.6.2 Memory Data Formats ............................................................................................ 35 Instruction Set ...................................................................................................................... 36 2.7.1 Instructions and Addressing Modes........................................................................ 38 2.7.2 Table of Instructions Classified by Function .......................................................... 42 2.7.3 Basic Instruction Formats ....................................................................................... 53 Addressing Modes and Effective Address Calculation ........................................................ 54 2.8.1 Register Direct⎯Rn................................................................................................ 55 2.8.2 Register Indirect⎯@ERn ....................................................................................... 55 Rev.2.00 Oct. 16, 2007 Page xvii of liv REJ09B0381-0200 2.9 Register Indirect with Displacement⎯@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) .................................................................................................... 55 2.8.4 Index Register Indirect with Displacement⎯@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement⎯@ERn+, @−ERn, @+ERn, or @ERn− ................................ 56 2.8.6 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58 2.8.7 Immediate⎯#xx ..................................................................................................... 59 2.8.8 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 59 2.8.9 Program-Counter Relative with Index Register⎯ @(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) .................................................................................................... 59 2.8.10 Memory Indirect⎯@@aa:8 ................................................................................... 60 2.8.11 Extended Memory Indirect⎯@@vec:7 ................................................................. 61 2.8.12 Effective Address Calculation ................................................................................ 61 2.8.13 MOVA Instruction.................................................................................................. 63 Processing States.................................................................................................................. 64 2.8.3 Section 3 3.1 3.2 MCU Operating Modes ..................................................................... 67 3.3 3.4 Operating Mode Selection ................................................................................................... 67 Register Descriptions ........................................................................................................... 68 3.2.1 Mode Control Register (MDCR) ............................................................................ 68 3.2.2 System Control Register (SYSCR) ......................................................................... 70 Operating Mode Descriptions .............................................................................................. 72 3.3.1 Mode 2.................................................................................................................... 72 3.3.2 Mode 4.................................................................................................................... 72 3.3.3 Mode 5.................................................................................................................... 72 3.3.4 Mode 6.................................................................................................................... 73 3.3.5 Mode 7.................................................................................................................... 73 3.3.6 Pin Functions .......................................................................................................... 74 Address Map ........................................................................................................................ 75 3.4.1 Address Map........................................................................................................... 75 Section 4 4.1 4.2 4.3 Exception Handling ........................................................................... 79 4.4 Exception Handling Types and Priority............................................................................... 79 Exception Sources and Exception Handling Vector Table .................................................. 80 Reset .................................................................................................................................... 82 4.3.1 Reset Exception Handling ...................................................................................... 82 4.3.2 Interrupts after Reset............................................................................................... 83 4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 83 Traces................................................................................................................................... 85 Rev.2.00 Oct. 16, 2007 Page xviii of liv REJ09B0381-0200 4.5 4.6 4.7 4.8 4.9 Address Error ....................................................................................................................... 86 4.5.1 Address Error Source.............................................................................................. 86 4.5.2 Address Error Exception Handling ......................................................................... 87 Interrupts.............................................................................................................................. 88 4.6.1 Interrupt Sources..................................................................................................... 88 4.6.2 Interrupt Exception Handling.................................................................................. 88 Instruction Exception Handling ........................................................................................... 89 4.7.1 Trap Instruction....................................................................................................... 89 4.7.2 Exception Handling by Illegal Instruction .............................................................. 90 Stack Status after Exception Handling................................................................................. 91 Usage Note........................................................................................................................... 91 Section 5 5.1 5.2 5.3 Interrupt Controller ............................................................................93 5.4 5.5 5.6 5.7 5.8 Features................................................................................................................................ 93 Input/Output Pins ................................................................................................................. 95 Register Descriptions ........................................................................................................... 95 5.3.1 Interrupt Control Register (INTCR) ....................................................................... 96 5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 97 5.3.3 Interrupt Priority Registers A to G, I, K, L, O, Q, and R (IPRA to IPRG, IPRI, IPRK, IPRL, IPRO, IPRQ, and IPRR)................................ 98 5.3.4 IRQ Enable Register (IER) ................................................................................... 101 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 103 5.3.6 IRQ Status Register (ISR)..................................................................................... 108 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 109 Interrupt Sources................................................................................................................ 110 5.4.1 External Interrupts ................................................................................................ 110 5.4.2 Internal Interrupts ................................................................................................. 111 Interrupt Exception Handling Vector Table....................................................................... 112 Interrupt Control Modes and Interrupt Operation .............................................................. 117 5.6.1 Interrupt Control Mode 0 ...................................................................................... 117 5.6.2 Interrupt Control Mode 2 ...................................................................................... 119 5.6.3 Interrupt Exception Handling Sequence ............................................................... 121 5.6.4 Interrupt Response Times ..................................................................................... 122 5.6.5 DMAC Activation by Interrupt............................................................................. 124 CPU Priority Control Function over DMAC ..................................................................... 126 Usage Notes ....................................................................................................................... 128 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 128 5.8.2 Instructions that Disable Interrupts ....................................................................... 129 5.8.3 Times when Interrupts Are Disabled .................................................................... 129 5.8.4 Interrupts during Execution of EEPMOV Instruction........................................... 129 Rev.2.00 Oct. 16, 2007 Page xix of liv REJ09B0381-0200 5.8.5 5.8.6 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 129 Interrupt Flags of Peripheral Modules .................................................................. 130 Section 6 6.1 6.2 Bus Controller (BSC) ......................................................................131 Features.............................................................................................................................. 131 Register Descriptions ......................................................................................................... 133 6.2.1 Bus Width Control Register (ABWCR)................................................................ 134 6.2.2 Access State Control Register (ASTCR) .............................................................. 135 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ......................................... 136 6.2.4 Read Strobe Timing Control Register (RDNCR) ................................................. 141 6.2.5 Idle Control Register (IDLCR) ............................................................................. 142 6.2.6 Bus Control Register 1 (BCR1) ............................................................................ 144 6.2.7 Bus Control Register 2 (BCR2) ............................................................................ 146 6.2.8 Endian Control Register (ENDIANCR) ............................................................... 147 6.3 Bus Configuration.............................................................................................................. 148 6.4 Multi-Clock Function and Number of Access Cycles ....................................................... 149 6.5 External Bus....................................................................................................................... 152 6.5.1 Input/Output Pins.................................................................................................. 152 6.5.2 Area Division........................................................................................................ 154 6.5.3 External Bus Interface .......................................................................................... 155 6.5.4 Area and External Bus Interface ........................................................................... 157 6.5.5 Endian and Data Alignment.................................................................................. 158 6.6 Basic Bus Interface ............................................................................................................ 162 6.6.1 Data Bus ............................................................................................................... 162 6.6.2 I/O Pins Used for Basic Bus Interface .................................................................. 162 6.6.3 Basic Timing......................................................................................................... 163 6.6.4 Wait Control ......................................................................................................... 169 6.6.5 Read Strobe (RD) Timing..................................................................................... 170 6.6.6 DACK Signal Output Timing ............................................................................... 171 6.7 Idle Cycle........................................................................................................................... 172 6.7.1 Operation .............................................................................................................. 172 6.7.2 Pin States in Idle Cycle......................................................................................... 180 6.8 Internal Bus........................................................................................................................ 180 6.8.1 Access to Internal Address Space ......................................................................... 180 6.9 Write Data Buffer Function ............................................................................................... 182 6.9.1 Write Data Buffer Function for External Data Bus .............................................. 182 6.9.2 Write Data Buffer Function for Peripheral Modules ............................................ 183 6.10 Bus Arbitration .................................................................................................................. 184 6.10.1 Operation .............................................................................................................. 184 6.10.2 Bus Handover Timing........................................................................................... 184 Rev.2.00 Oct. 16, 2007 Page xx of liv REJ09B0381-0200 6.11 Bus Controller Operation in Reset ..................................................................................... 186 6.12 Usage Notes ....................................................................................................................... 186 Section 7 7.1 7.2 7.3 DMA Controller (DMAC) ...............................................................187 7.4 7.5 7.6 7.7 7.8 7.9 Features.............................................................................................................................. 187 Input/Output Pins ............................................................................................................... 189 Register Descriptions ......................................................................................................... 190 7.3.1 DMA Source Address Register (DSAR)............................................................... 191 7.3.2 DMA Destination Address Register (DDAR)....................................................... 192 7.3.3 DMA Offset Register (DOFR).............................................................................. 193 7.3.4 DMA Transfer Count Register (DTCR) ............................................................... 194 7.3.5 DMA Block Size Register (DBSR) ...................................................................... 195 7.3.6 DMA Mode Control Register (DMDR)................................................................ 196 7.3.7 DMA Address Control Register (DACR) ............................................................. 205 7.3.8 DMA Module Request Select Register (DMRSR) ............................................... 211 Transfer Modes .................................................................................................................. 211 Operations.......................................................................................................................... 212 7.5.1 Address Modes ..................................................................................................... 212 7.5.2 Transfer Modes ..................................................................................................... 216 7.5.3 Activation Sources................................................................................................ 220 7.5.4 Bus Access Modes ................................................................................................ 222 7.5.5 Extended Repeat Area Function ........................................................................... 224 7.5.6 Address Update Function using Offset ................................................................. 226 7.5.7 Register during DMA Transfer ............................................................................. 230 7.5.8 Priority of Channels .............................................................................................. 235 7.5.9 DMA Basic Bus Cycle.......................................................................................... 236 7.5.10 Bus Cycles in Dual Address Mode ....................................................................... 237 7.5.11 Bus Cycles in Single Address Mode..................................................................... 245 DMA Transfer End ............................................................................................................ 250 Relationship among DMAC and Other Bus Masters ......................................................... 252 7.7.1 CPU Priority Control Function over DMAC ........................................................ 252 7.7.2 Bus Arbitration among DMAC and Other Bus Masters ....................................... 253 Interrupt Sources................................................................................................................ 254 Notes on Usage .................................................................................................................. 257 Section 8 8.1 I/O Ports ...........................................................................................259 Register Descriptions ......................................................................................................... 265 8.1.1 Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A, D, E, F, H, I, J, and K) ....... 266 8.1.2 Data Register (PnDR) (n = 1, 2, 3, 6, A, D, E, F, H, I, J, and K) .......................... 266 8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, E, F, H, I, J, and K) ............................. 267 Rev.2.00 Oct. 16, 2007 Page xxi of liv REJ09B0381-0200 8.2 8.3 8.4 8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, E, F, H, I, J, and K) .... 267 8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, and H to K)...................... 268 8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F).......................................... 270 Output Buffer Control........................................................................................................ 271 8.2.1 Port 1..................................................................................................................... 271 8.2.2 Port 2..................................................................................................................... 274 8.2.3 Port 3..................................................................................................................... 277 8.2.4 Port 5..................................................................................................................... 279 8.2.5 Port 6..................................................................................................................... 280 8.2.6 Port A.................................................................................................................... 282 8.2.7 Port D.................................................................................................................... 286 8.2.8 Port E .................................................................................................................... 286 8.2.9 Port F .................................................................................................................... 287 8.2.10 Port H.................................................................................................................... 291 8.2.11 Port I ..................................................................................................................... 291 8.2.12 Port J ..................................................................................................................... 294 8.2.13 Port K.................................................................................................................... 294 Port Function Controller .................................................................................................... 301 8.3.1 Port Function Control Register 2 (PFCR2)........................................................... 301 8.3.2 Port Function Control Register 4 (PFCR4)........................................................... 302 8.3.3 Port Function Control Register 9 (PFCR9)........................................................... 304 Usage Notes ....................................................................................................................... 306 8.4.1 Notes on Input Buffer Control Register (ICR) Setting ......................................... 306 8.4.2 Notes on Port Function Control Register (PFCR) Settings................................... 306 Section 9 9.1 9.2 9.3 16-Bit Timer Pulse Unit (TPU) .......................................................307 9.4 Features.............................................................................................................................. 307 Input/Output Pins............................................................................................................... 311 Register Descriptions ......................................................................................................... 312 9.3.1 Timer Control Register (TCR).............................................................................. 314 9.3.2 Timer Mode Register (TMDR)............................................................................. 320 9.3.3 Timer I/O Control Register (TIOR) ...................................................................... 321 9.3.4 Timer Interrupt Enable Register (TIER)............................................................... 340 9.3.5 Timer Status Register (TSR)................................................................................. 342 9.3.6 Timer Counter (TCNT)......................................................................................... 346 9.3.7 Timer General Register (TGR) ............................................................................. 346 9.3.8 Timer Start Register (TSTR) ................................................................................ 347 9.3.9 Timer Synchronous Register (TSYR)................................................................... 348 Operation ........................................................................................................................... 349 9.4.1 Basic Functions..................................................................................................... 349 Rev.2.00 Oct. 16, 2007 Page xxii of liv REJ09B0381-0200 9.5 9.6 9.7 9.8 9.9 9.4.2 Synchronous Operation......................................................................................... 355 9.4.3 Buffer Operation ................................................................................................... 357 9.4.4 Cascaded Operation .............................................................................................. 361 9.4.5 PWM Modes ......................................................................................................... 363 9.4.6 Phase Counting Mode........................................................................................... 368 Interrupt Sources................................................................................................................ 376 DMAC Activation.............................................................................................................. 378 A/D Converter Activation.................................................................................................. 378 Operation Timing............................................................................................................... 379 9.8.1 Input/Output Timing ............................................................................................. 379 9.8.2 Interrupt Signal Timing......................................................................................... 382 Usage Notes ....................................................................................................................... 387 9.9.1 Module Stop Mode Setting ................................................................................... 387 9.9.2 Input Clock Restrictions ....................................................................................... 387 9.9.3 Caution on Cycle Setting ...................................................................................... 388 9.9.4 Conflict between TCNT Write and Clear Operations........................................... 388 9.9.5 Conflict between TCNT Write and Increment Operations ................................... 388 9.9.6 Conflict between TGR Write and Compare Match............................................... 389 9.9.7 Conflict between Buffer Register Write and Compare Match .............................. 390 9.9.8 Conflict between TGR Read and Input Capture ................................................... 390 9.9.9 Conflict between TGR Write and Input Capture .................................................. 391 9.9.10 Conflict between Buffer Register Write and Input Capture.................................. 392 9.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................. 393 9.9.12 Conflict between TCNT Write and Overflow/Underflow .................................... 394 9.9.13 Multiplexing of I/O Pins ....................................................................................... 394 9.9.14 Interrupts and Module Stop Mode ........................................................................ 394 Section 10 Watchdog Timer (WDT)..................................................................395 10.1 Features.............................................................................................................................. 395 10.2 Register Descriptions ......................................................................................................... 396 10.2.1 Timer Counter (TCNT)......................................................................................... 396 10.2.2 Timer Control/Status Register (TCSR)................................................................. 396 10.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 399 10.3 Operation ........................................................................................................................... 400 10.3.1 Watchdog Timer Mode ......................................................................................... 400 10.3.2 Interval Timer Mode............................................................................................. 401 10.4 Interrupt Source ................................................................................................................. 401 10.5 Usage Notes ....................................................................................................................... 402 10.5.1 Notes on Register Access...................................................................................... 402 10.5.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 403 Rev.2.00 Oct. 16, 2007 Page xxiii of liv REJ09B0381-0200 10.5.3 Changing Values of Bits CKS2 to CKS0.............................................................. 403 10.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 403 10.5.5 Transition to Watchdog Timer Mode or Software Standby Mode........................ 404 Section 11 Watch Timer (WAT) .......................................................................405 11.1 Features.............................................................................................................................. 405 11.2 Register Descriptions ......................................................................................................... 406 11.2.1 Watch Timer Counter (WTCNT).......................................................................... 406 11.2.2 Watch Timer Control Register (WTCR)............................................................... 407 11.2.3 Watch Timer Status Register (WTSR).................................................................. 408 11.2.4 Watch Timer Constant Register (WTCOR).......................................................... 410 11.3 Operation ........................................................................................................................... 411 11.3.1 Mode Operation in Compare Match Timer........................................................... 411 11.3.2 Operation in Interval Timer Mode........................................................................ 413 11.4 Usage Notes ....................................................................................................................... 415 11.4.1 Precautions for Accessing Registers ..................................................................... 415 11.4.2 Conflict between Write and Increment Processes of WTCNT ............................. 416 11.4.3 Rewriting Bits CKS2 to CKS0 ............................................................................. 416 11.4.4 Switching between Compare Match Timer and Interval Timer Modes................ 416 11.4.5 Rewriting PSS Bit................................................................................................. 416 11.4.6 WTCOR Setting Value and WTCNT Rewrite Value in Compare Match Timer Mode..................................................................................................................... 417 11.4.7 Interrupt Vector Address ...................................................................................... 417 Section 12 Serial Communication Interface (SCI) ............................................419 12.1 Features.............................................................................................................................. 419 12.2 Input/Output Pins............................................................................................................... 421 12.3 Register Descriptions ......................................................................................................... 422 12.3.1 Receive Shift Register (RSR) ............................................................................... 424 12.3.2 Receive Data Register (RDR) ............................................................................... 424 12.3.3 Transmit Data Register (TDR).............................................................................. 424 12.3.4 Transmit Shift Register (TSR) .............................................................................. 425 12.3.5 Serial Mode Register (SMR) ................................................................................ 425 12.3.6 Serial Control Register (SCR) .............................................................................. 428 12.3.7 Serial Status Register (SSR) ................................................................................. 433 12.3.8 Smart Card Mode Register (SCMR)..................................................................... 442 12.3.9 Bit Rate Register (BRR) ....................................................................................... 443 12.4 Operation in Asynchronous Mode ..................................................................................... 448 12.4.1 Data Transfer Format............................................................................................ 449 Rev.2.00 Oct. 16, 2007 Page xxiv of liv REJ09B0381-0200 12.5 12.6 12.7 12.8 12.9 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 450 12.4.3 Clock..................................................................................................................... 451 12.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 452 12.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 453 12.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 455 Multiprocessor Communication Function.......................................................................... 459 12.5.1 Multiprocessor Serial Data Transmission ............................................................. 461 12.5.2 Multiprocessor Serial Data Reception .................................................................. 462 Operation in Clocked Synchronous Mode ......................................................................... 465 12.6.1 Clock..................................................................................................................... 465 12.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................. 466 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 467 12.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 469 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 470 Operation in Smart Card Interface Mode........................................................................... 472 12.7.1 Sample Connection ............................................................................................... 472 12.7.2 Data Format (Except in Block Transfer Mode) .................................................... 473 12.7.3 Block Transfer Mode ............................................................................................ 474 12.7.4 Receive Data Sampling Timing and Reception Margin........................................ 475 12.7.5 Initialization .......................................................................................................... 476 12.7.6 Data Transmission (Except in Block Transfer Mode) .......................................... 477 12.7.7 Serial Data Reception (Except in Block Transfer Mode)...................................... 480 12.7.8 Clock Output Control............................................................................................ 481 Interrupt Sources................................................................................................................ 483 12.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 483 12.8.2 Interrupts in Smart Card Interface Mode .............................................................. 484 Usage Notes ....................................................................................................................... 485 12.9.1 Module Stop Mode Setting ................................................................................... 485 12.9.2 Break Detection and Processing ........................................................................... 485 12.9.3 Mark State and Break Detection ........................................................................... 485 12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 485 12.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 486 12.9.6 Writing to Registers during SCI Transmit or Receive .......................................... 486 12.9.7 Restrictions on Using DMAC ............................................................................... 486 12.9.8 SCI Operations during Mode Transitions ............................................................. 487 Rev.2.00 Oct. 16, 2007 Page xxv of liv REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2)................................................................491 13.1 Features.............................................................................................................................. 491 13.2 Input/Output Pins............................................................................................................... 493 13.3 Register Descriptions ......................................................................................................... 494 2 13.3.1 I C Bus Control Register A (ICCRA) ................................................................... 495 2 13.3.2 I C Bus Control Register B (ICCRB) ................................................................... 497 2 13.3.3 I C Bus Mode Register (ICMR)............................................................................ 498 2 13.3.4 I C Bus Interrupt Enable Register (ICIER) ........................................................... 500 2 13.3.5 I C Bus Status Register (ICSR)............................................................................. 502 13.3.6 Slave Address Register (SAR).............................................................................. 505 2 13.3.7 I C Bus Transmit Data Register (ICDRT) ............................................................ 506 2 13.3.8 I C Bus Receive Data Register (ICDRR).............................................................. 506 2 13.3.9 I C Bus Shift Register (ICDRS)............................................................................ 506 13.4 Operation ........................................................................................................................... 507 2 13.4.1 I C Bus Format...................................................................................................... 507 13.4.2 Master Transmit Operation ................................................................................... 508 13.4.3 Master Receive Operation .................................................................................... 510 13.4.4 Slave Transmit Operation ..................................................................................... 512 13.4.5 Slave Receive Operation....................................................................................... 515 13.4.6 Noise Canceller..................................................................................................... 516 13.4.7 Example of Use..................................................................................................... 517 13.5 Interrupt Request................................................................................................................ 521 13.6 Bit Synchronous Circuit..................................................................................................... 522 Section 14 Controller Area Network (RCAN-ET) ............................................ 523 14.1 Summary............................................................................................................................ 523 14.1.1 Overview .............................................................................................................. 523 14.1.2 Scope .................................................................................................................... 523 14.1.3 Audience............................................................................................................... 523 14.1.4 References............................................................................................................. 524 14.1.5 Features................................................................................................................. 524 14.2 Architecture ....................................................................................................................... 525 14.2.1 Block Diagram...................................................................................................... 525 14.2.2 Important .............................................................................................................. 526 14.2.3 Input/Output Pins.................................................................................................. 527 14.2.4 Memory Map ........................................................................................................ 528 14.3 Mailbox.............................................................................................................................. 529 14.3.1 Mailbox Structure ................................................................................................. 529 14.3.2 Message Control Field .......................................................................................... 531 14.3.3 Local Acceptance Filter Mask (LAFM)................................................................ 535 Rev.2.00 Oct. 16, 2007 Page xxvi of liv REJ09B0381-0200 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.3.4 Message Data Fields ............................................................................................. 536 RCAN-ET Control Registers ............................................................................................. 537 14.4.1 Master Control Register (MCR) ........................................................................... 537 14.4.2 General Status Register (GSR) ............................................................................. 543 14.4.3 Bit Configuration Registers 0 and 1 (BCR0 and BCR1) ...................................... 546 14.4.4 Interrupt Request Register (IRR) .......................................................................... 551 14.4.5 Interrupt Mask Register (IMR) ............................................................................. 557 14.4.6 Transmit Error Counter (TEC) and Receive Error Counter (REC)....................... 558 RCAN-ET Mailbox Registers ............................................................................................ 559 14.5.1 Transmit Pending Registers 0 and 1 (TXPR0 and TXPR1).................................. 560 14.5.2 Transmit Cancel Register 0 (TXCR0) .................................................................. 563 14.5.3 Transmit Acknowledge Register 0 (TXACK0) .................................................... 564 14.5.4 Abort Acknowledge Register 0 (ABACK0) ......................................................... 565 14.5.5 Data Frame Receive Pending Register 0 (RXPR0)............................................... 566 14.5.6 Remote Frame Receive Pending Register 0 (RFPR0) .......................................... 567 14.5.7 Mailbox Interrupt Mask Register 0 (MBIMR0).................................................... 568 14.5.8 Unread Message Status Register 0 (UMSR0) ....................................................... 569 Application Note................................................................................................................ 570 14.6.1 Configuration of RCAN-ET ................................................................................. 570 14.6.2 Test Mode Settings ............................................................................................... 575 14.6.3 Message Transmission Sequence.......................................................................... 577 14.6.4 Message Receive Sequence .................................................................................. 579 14.6.5 Reconfiguration of Mailbox.................................................................................. 581 Interrupt Sources................................................................................................................ 583 PORT Interface .................................................................................................................. 585 14.8.1 RCAN-ET Monitor Register (RCANMON) ......................................................... 585 CAN Bus Interface............................................................................................................. 586 Usage Notes ....................................................................................................................... 587 14.10.1 Module Stop Mode ............................................................................................... 587 14.10.2 Reset ..................................................................................................................... 587 14.10.3 CAN Sleep Mode.................................................................................................. 587 14.10.4 Register Access..................................................................................................... 587 14.10.5 Interrupts............................................................................................................... 588 Section 15 Synchronous Serial Communication Unit (SSU) ............................589 15.1 Features.............................................................................................................................. 589 15.2 Input/Output Pins ............................................................................................................... 591 15.3 Register Descriptions ......................................................................................................... 592 15.3.1 SS Control Register H (SSCRH) .......................................................................... 594 15.3.2 SS Control Register L (SSCRL) ........................................................................... 596 Rev.2.00 Oct. 16, 2007 Page xxvii of liv REJ09B0381-0200 15.3.3 SS Mode Register (SSMR) ................................................................................... 597 15.3.4 SS Enable Register (SSER) .................................................................................. 598 15.3.5 SS Status Register (SSSR) .................................................................................... 599 15.3.6 SS Control Register 2 (SSCR2) ............................................................................ 602 15.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 604 15.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 605 15.3.9 SS Shift Register (SSTRSR)................................................................................. 606 15.4 Operation ........................................................................................................................... 607 15.4.1 Transfer Clock ...................................................................................................... 607 15.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 607 15.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 608 15.4.4 Communication Modes and Pin Functions ........................................................... 609 15.4.5 SSU Mode............................................................................................................. 611 15.4.6 SCS Pin Control and Conflict Error...................................................................... 621 15.4.7 Clock Synchronous Communication Mode .......................................................... 622 15.5 Interrupt Requests .............................................................................................................. 628 Section 16 A/D Converter .................................................................................629 16.1 Features.............................................................................................................................. 629 16.2 Input/Output Pins............................................................................................................... 632 16.3 Register Descriptions ......................................................................................................... 633 16.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 634 16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 635 16.3.3 A/D Control Register (ADCR) ............................................................................. 637 16.4 Operation ........................................................................................................................... 638 16.4.1 Single Mode.......................................................................................................... 638 16.4.2 Scan Mode ............................................................................................................ 639 16.4.3 Input Sampling and A/D Conversion Time .......................................................... 641 16.4.4 External Trigger Input Timing.............................................................................. 642 16.5 Interrupt Sources................................................................................................................ 643 16.6 A/D Conversion Accuracy Definitions .............................................................................. 643 16.7 Usage Notes ....................................................................................................................... 645 16.7.1 Module Stop Mode Setting ................................................................................... 645 16.7.2 Permissible Signal Source Impedance .................................................................. 645 16.7.3 Influences on Absolute Accuracy ......................................................................... 646 16.7.4 Setting Range of Analog Power Supply and Other Pins....................................... 646 16.7.5 Notes on Board Design ......................................................................................... 646 16.7.6 Notes on Noise Countermeasures ......................................................................... 647 16.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 648 Rev.2.00 Oct. 16, 2007 Page xxviii of liv REJ09B0381-0200 Section 17 D/A Converter..................................................................................649 17.1 Features.............................................................................................................................. 649 17.2 Input/Output Pins ............................................................................................................... 650 17.3 Register Descriptions ......................................................................................................... 650 17.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 650 17.3.2 D/A Control Register 01 (DACR01) .................................................................... 651 17.4 Operation ........................................................................................................................... 653 17.5 Usage Notes ....................................................................................................................... 654 17.5.1 Module Stop Mode Setting ................................................................................... 654 17.5.2 D/A Output Hold Function in Software Standby Mode........................................ 654 Section 18 Motor Control PWM Timer (PWM)................................................655 18.1 Features.............................................................................................................................. 655 18.2 Input/Output Pins ............................................................................................................... 657 18.3 Register Descriptions ......................................................................................................... 658 18.3.1 PWM Control Register (PWCR)........................................................................... 659 18.3.2 PWM Output Control Register (PWOCR)............................................................ 660 18.3.3 PWM Polarity Register (PWPR)........................................................................... 661 18.3.4 PWM Counter (PWCNT) ..................................................................................... 661 18.3.5 PWM Cycle Register (PWCYR)........................................................................... 662 18.3.6 PWM Duty Registers A, C, E, G (PWDTRA, PWDTRC, PWDTRE, PWDTRG) ................................................... 662 18.3.7 PWM Buffer Registers A, C, E, G (PWBFRA, PWBFRC, PWBFRE, PWBFRG) ..................................................... 665 18.3.8 PWM Buffer Transfer Control Register (PWBTCR)............................................ 666 18.4 Bus Master Interface .......................................................................................................... 667 18.4.1 16-Bit Data Registers............................................................................................ 667 18.4.2 8-Bit Data Registers.............................................................................................. 667 18.5 Operation ........................................................................................................................... 668 18.5.1 PWM Operation .................................................................................................... 668 18.5.2 Buffer Transfer Control ........................................................................................ 669 18.6 Usage Note......................................................................................................................... 670 18.6.1 Conflict between Buffer Register Write and Compare Match .............................. 670 Section 19 16-Bit PWM.....................................................................................671 19.1 Features.............................................................................................................................. 671 19.2 Input/Output Pins ............................................................................................................... 673 19.3 Register Descriptions ......................................................................................................... 674 19.3.1 PWM Control Register (PWCR)........................................................................... 675 19.3.2 PWM Output Control Register (PWOCR)............................................................ 677 Rev.2.00 Oct. 16, 2007 Page xxix of liv REJ09B0381-0200 19.3.3 PWM Counter (PWCNT) ..................................................................................... 678 19.3.4 PWM Cycle Register (PWCYR) .......................................................................... 678 19.3.5 PWM Duty Registers 0 to 3 (PWDTR0 to PWDTR3) ......................................... 679 19.3.6 PWM Buffer Registers 0 to 3 (PWBFR0 to PWBFR3) ........................................ 681 19.4 Operation ........................................................................................................................... 682 19.4.1 Operation in 16-Bit PWM Mode .......................................................................... 682 19.4.2 Operation in 10-Bit Stepping Motor Mode........................................................... 683 19.5 Usage Notes ....................................................................................................................... 685 19.5.1 Precautions for Accessing Registers ..................................................................... 685 19.5.2 Conflict between Buffer Register Write and Compare Match.............................. 685 19.5.3 Rewriting of CKS2 to CKS0................................................................................. 686 19.5.4 Switching between 16-Bit PWM Mode and 10-Bit Stepping Motor Mode.......... 686 Section 20 Sound Generator (SDG) ..................................................................687 20.1 Features.............................................................................................................................. 687 20.2 Input/Output Pins............................................................................................................... 688 20.3 Register Descriptions ......................................................................................................... 688 20.3.1 Sound Generator Control Register 1 (SGCR1)..................................................... 688 20.3.2 Sound Generator Control Status Register (SGCSR) ............................................. 690 20.3.3 Sound Generator Control Register 2 (SGCR2)..................................................... 691 20.3.4 Sound Generator Loudness Register (SGLR) ....................................................... 691 20.3.5 Sound Generator Tone Frequency Register (SGTFR) .......................................... 692 20.3.6 Sound Generator Reference Frequency Register (SGSFR) .................................. 693 20.4 Operation ........................................................................................................................... 694 20.4.1 SDG Operation ..................................................................................................... 694 20.4.2 Tone Frequency Setting ........................................................................................ 698 20.4.3 Auto Attenuator Function ..................................................................................... 699 20.4.4 Output Waveform ................................................................................................. 700 20.5 Interrupt Source ................................................................................................................. 700 20.6 Usage Note......................................................................................................................... 700 20.6.1 Module Stop Mode Settings ................................................................................. 700 Section 21 RAM ................................................................................................701 Section 22 Flash Memory..................................................................................703 22.1 22.2 22.3 22.4 22.5 Features.............................................................................................................................. 703 Mode Transition Diagram.................................................................................................. 705 Block Structure .................................................................................................................. 707 Programming/Erasing Interface ......................................................................................... 709 Input/Output Pins............................................................................................................... 711 Rev.2.00 Oct. 16, 2007 Page xxx of liv REJ09B0381-0200 22.6 Register Descriptions ......................................................................................................... 711 22.6.1 Programming/Erasing Interface Registers ............................................................ 712 22.6.2 Programming/Erasing Interface Parameters ......................................................... 718 22.6.3 RAM Emulation Register (RAMER).................................................................... 732 22.7 On-Board Programming Mode .......................................................................................... 733 22.7.1 Boot Mode ............................................................................................................ 733 22.7.2 User Program Mode.............................................................................................. 737 22.7.3 On-Chip Program and Storable Area for Program Data ....................................... 747 22.8 Protection ........................................................................................................................... 750 22.8.1 Hardware Protection ............................................................................................. 750 22.8.2 Software Protection............................................................................................... 751 22.8.3 Error Protection..................................................................................................... 751 22.9 Flash Memory Emulation Using RAM .............................................................................. 753 22.10 Programmer Mode ............................................................................................................. 756 22.11 Standard Serial Communication Interface Specifications for Boot Mode ......................... 756 22.12 Usage Notes ....................................................................................................................... 781 Section 23 Clock Pulse Generator .....................................................................785 23.1 Register Description........................................................................................................... 786 23.1.1 System Clock Control Register (SCKCR) ............................................................ 786 23.1.2 Sub-Clock Control Register (SUBCKCR)............................................................ 789 23.2 Oscillator............................................................................................................................ 791 23.2.1 Connecting Crystal Resonator .............................................................................. 791 23.2.2 External Clock Input............................................................................................. 792 23.3 PLL Circuit ........................................................................................................................ 793 23.4 Main Clock Divider ........................................................................................................... 793 23.5 Sub-Clock Waveform Shaping Circuit .............................................................................. 793 23.6 Sub-Clock Divider ............................................................................................................. 793 23.7 Usage Notes ....................................................................................................................... 794 23.7.1 Notes on Clock Pulse Generator ........................................................................... 794 23.7.2 Notes on Resonator ............................................................................................... 795 23.7.3 Notes on Board Design ......................................................................................... 795 23.7.4 Notes on Input Clock Frequency .......................................................................... 796 Section 24 Power-Down Modes ........................................................................797 24.1 Features.............................................................................................................................. 797 24.2 Register Descriptions ......................................................................................................... 800 24.2.1 Standby Control Register (SBYCR) ..................................................................... 800 24.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .............. 803 24.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 806 Rev.2.00 Oct. 16, 2007 Page xxxi of liv REJ09B0381-0200 24.3 Multi-Clock Function of Main Clock ................................................................................ 807 24.4 Sub-Clock .......................................................................................................................... 808 24.5 Sleep Mode ........................................................................................................................ 808 24.5.1 Transition to Sleep Mode...................................................................................... 808 24.5.2 Clearing Sleep Mode ............................................................................................ 809 24.6 Software Standby Mode..................................................................................................... 809 24.6.1 Transition to Software Standby Mode .................................................................. 809 24.6.2 Clearing Software Standby Mode......................................................................... 810 24.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ........... 811 24.6.4 Software Standby Mode Application Example..................................................... 812 24.7 Hardware Standby Mode ................................................................................................... 813 24.7.1 Transition to Hardware Standby Mode................................................................. 813 24.7.2 Clearing Hardware Standby Mode........................................................................ 813 24.7.3 Hardware Standby Mode Timing.......................................................................... 813 24.7.4 Timing Sequence at Power-On ............................................................................. 814 24.8 Module Stop Function........................................................................................................ 815 24.8.1 Module Stop Function .......................................................................................... 815 24.8.2 All-Module-Clock-Stop Mode.............................................................................. 815 24.9 Bφ Clock Output Control................................................................................................... 816 24.10 Usage Notes ....................................................................................................................... 817 24.10.1 I/O Port Status....................................................................................................... 817 24.10.2 Current Consumption during Oscillation Settling Standby Period ....................... 817 24.10.3 Module Stop Mode of DMAC .............................................................................. 817 24.10.4 On-Chip Peripheral Module Interrupts ................................................................. 817 24.10.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC ........................................... 817 Section 25 List of Registers...............................................................................819 25.1 Register Addresses (Address Order).................................................................................. 820 25.2 Register Bits....................................................................................................................... 844 25.3 Register States in Each Operating Mode ........................................................................... 863 Section 26 Electrical Characteristics .................................................................877 26.1 Absolute Maximum Ratings .............................................................................................. 877 26.2 DC Characteristics ............................................................................................................. 878 26.3 AC Characteristics ............................................................................................................. 883 26.3.1 Clock Timing ........................................................................................................ 884 26.3.2 Control Signal Timing .......................................................................................... 886 26.3.3 Bus Timing ........................................................................................................... 888 26.3.4 DMAC Timing...................................................................................................... 892 26.3.5 Timing of On-Chip Peripheral Modules ............................................................... 895 Rev.2.00 Oct. 16, 2007 Page xxxii of liv REJ09B0381-0200 26.3.6 A/D Conversion Characteristics............................................................................ 903 26.3.7 D/A Conversion Characteristics............................................................................ 903 26.3.8 Flash Memory Characteristics .............................................................................. 904 Appendix A. B. C. ..........................................................................................................905 Port States in Each Pin State .............................................................................................. 905 Product Lineup................................................................................................................... 907 Package Dimensions .......................................................................................................... 908 Index ..........................................................................................................909 Rev.2.00 Oct. 16, 2007 Page xxxiii of liv REJ09B0381-0200 Rev.2.00 Oct. 16, 2007 Page xxxiv of liv REJ09B0381-0200 Figures Section 1 Overview Figure 1.1 Block Diagram of H8SX/1544 .................................................................................... 2 Figure 1.2 Pin Assignments of H8SX/1544.................................................................................. 3 Section 2 CPU Figure 2.1 CPU Operating Modes .............................................................................................. 21 Figure 2.2 Exception Vector Table (Normal Mode)................................................................... 22 Figure 2.3 Stack Structure (Normal Mode) ................................................................................ 22 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) .......................................... 24 Figure 2.5 Stack Structure (Middle and Advanced Modes)........................................................ 25 Figure 2.6 Exception Vector Table (Maximum Modes)............................................................. 26 Figure 2.7 Stack Structure (Maximum Mode)............................................................................ 26 Figure 2.8 Memory Map............................................................................................................. 27 Figure 2.9 CPU Registers ........................................................................................................... 28 Figure 2.10 Usage of General Registers ....................................................................................... 29 Figure 2.11 Stack.......................................................................................................................... 30 Figure 2.12 General Register Data Formats ................................................................................. 34 Figure 2.13 Memory Data Formats .............................................................................................. 35 Figure 2.14 Instruction Formats ................................................................................................... 53 Figure 2.15 Branch Address Specification in Memory Indirect Mode......................................... 60 Figure 2.16 State Transitions........................................................................................................ 65 Section 3 MCU Operating Modes Figure 3.1 H8SX/1544 Address Map (1).................................................................................... 75 Figure 3.2 H8SX/1544 Address Map (2).................................................................................... 76 Figure 3.3 H8SX/1543 Address Map (1).................................................................................... 77 Figure 3.4 H8SX/1543 Address Map (2).................................................................................... 78 Section 4 Exception Handling Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)..................................... 83 Figure 4.2 Reset Sequence (16-Bit External Access in On-Chip ROM Disabled Advanced Mode) ................... 84 Figure 4.3 Stack Status after Exception Handling ...................................................................... 91 Figure 4.4 Operation when SP Value Is Odd.............................................................................. 92 Rev.2.00 Oct. 16, 2007 Page xxxv of liv REJ09B0381-0200 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 94 Figure 5.2 Block Diagram of Interrupts IRQn.......................................................................... 111 Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 .................................................................................................................... 118 Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 .................................................................................................................... 120 Figure 5.5 Interrupt Exception Handling.................................................................................. 121 Figure 5.6 Block Diagram of DMAC and Interrupt Controller ................................................ 124 Figure 5.7 Conflict between Interrupt Generation and Disabling............................................. 128 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller ........................................................................... 132 Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)........................ 142 Figure 6.3 Internal Bus Configuration...................................................................................... 148 Figure 6.4 System Clock: External Bus Clock = 4:1, External 2-State Access ........................ 150 Figure 6.5 System Clock: External Bus Clock = 2:1, External 3-State Access ........................ 151 Figure 6.6 Address Space Area Division.................................................................................. 154 Figure 6.7 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian).. 159 Figure 6.8 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian) ......................................................................................................... 159 Figure 6.9 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian). 160 Figure 6.10 Access Sizes and Data Alignment Control for 16-Bit Access Space (Little Endian) ......................................................................................................... 161 Figure 6.11 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) .......... 163 Figure 6.12 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)............ 164 Figure 6.13 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) ......... 165 Figure 6.14 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address) .......... 166 Figure 6.15 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) .......... 167 Figure 6.16 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) ......... 168 Figure 6.17 Example of Wait Cycle Insertion Timing ............................................................... 169 Figure 6.18 Example of Read Strobe Timing ............................................................................. 170 Figure 6.19 DACK Signal Output Timing ................................................................................. 171 Figure 6.20 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 174 Figure 6.21 Example of Idle Cycle Operation (Write after Read).............................................. 175 Figure 6.22 Example of Idle Cycle Operation (Read after Write).............................................. 176 Figure 6.23 Example of Idle Cycle Operation (Write after Single Address Transfer Write) ..... 177 Figure 6.24 Idle Cycle Insertion Example.................................................................................. 178 Figure 6.25 Example of Timing when Write Data Buffer Function Is Used.............................. 182 Rev.2.00 Oct. 16, 2007 Page xxxvi of liv REJ09B0381-0200 Figure 6.26 Example of Timing when Peripheral Module Write Data Buffer Function Is Used ........................................................................................................................ 183 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ....................................................................................... 188 Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................. 213 Figure 7.3 Operations in Dual Address Mode .......................................................................... 213 Figure 7.4 Data Flow in Single Address Mode......................................................................... 214 Figure 7.5 Example of Signal Timing in Single Address Mode............................................... 215 Figure 7.6 Operations in Single Address Mode........................................................................ 215 Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................. 216 Figure 7.8 Operations in Normal Transfer Mode ..................................................................... 216 Figure 7.9 Operations in Repeat Transfer Mode ...................................................................... 217 Figure 7.10 Operations in Block Transfer Mode ........................................................................ 218 Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified)............................................................................................ 219 Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified)..................................................................................... 219 Figure 7.13 Example of Timing in Cycle Stealing Mode........................................................... 223 Figure 7.14 Example of Timing in Burst Mode.......................................................................... 223 Figure 7.15 Example of Extended Repeat Area Operation......................................................... 225 Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 225 Figure 7.17 Address Update Method.......................................................................................... 226 Figure 7.18 Operation of Offset Addition .................................................................................. 227 Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode ......... 228 Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 229 Figure 7.21 Procedure for Changing Register Setting for Channel Being Transferred .............. 233 Figure 7.22 Example of Timing for Channel Priority................................................................. 235 Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 236 Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 237 Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) .............. 238 Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement).............................................................................................................. 238 Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 239 Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 240 Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge ........................................................................................................................ 241 Rev.2.00 Oct. 16, 2007 Page xxxvii of liv REJ09B0381-0200 Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level ....................................................................................................................... 242 Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level .... 243 Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 .......................................................................................................... 244 Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) .................................... 245 Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) ................................... 246 Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge. 247 Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level.... 248 Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 .......................................................................................................... 249 Figure 7.38 Interrupt and Interrupt Sources................................................................................ 256 Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 256 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.1 Block Diagram of TPU ........................................................................................... 310 Figure 9.2 Example of Counter Operation Setting Procedure .................................................. 349 Figure 9.3 Free-Running Counter Operation............................................................................ 350 Figure 9.4 Periodic Counter Operation..................................................................................... 351 Figure 9.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 351 Figure 9.6 Example of 0-Output/1-Output Operation............................................................... 352 Figure 9.7 Example of Toggle Output Operation ..................................................................... 352 Figure 9.8 Example of Setting Procedure for Input Capture Operation ................................... 353 Figure 9.9 Example of Input Capture Operation ...................................................................... 354 Figure 9.10 Example of Synchronous Operation Setting Procedure .......................................... 355 Figure 9.11 Example of Synchronous Operation........................................................................ 356 Figure 9.12 Compare Match Buffer Operation........................................................................... 357 Figure 9.13 Input Capture Buffer Operation .............................................................................. 358 Figure 9.14 Example of Buffer Operation Setting Procedure..................................................... 358 Figure 9.15 Example of Buffer Operation (1) ............................................................................ 359 Figure 9.16 Example of Buffer Operation (2) ............................................................................ 360 Figure 9.17 Example of Cascaded Operation Setting Procedure................................................ 361 Figure 9.18 Example of Cascaded Operation (1) ....................................................................... 362 Figure 9.19 Example of Cascaded Operation (2) ....................................................................... 362 Figure 9.20 Example of PWM Mode Setting Procedure ............................................................ 365 Figure 9.21 Example of PWM Mode Operation (1)................................................................... 366 Figure 9.22 Example of PWM Mode Operation (2)................................................................... 366 Figure 9.23 Example of PWM Mode Operation (3)................................................................... 367 Figure 9.24 Example of Phase Counting Mode Setting Procedure............................................. 369 Figure 9.25 Example of Phase Counting Mode 1 Operation ...................................................... 369 Rev.2.00 Oct. 16, 2007 Page xxxviii of liv REJ09B0381-0200 Figure 9.26 Figure 9.27 Figure 9.28 Figure 9.29 Figure 9.30 Figure 9.31 Figure 9.32 Figure 9.33 Figure 9.34 Figure 9.35 Figure 9.36 Figure 9.37 Figure 9.38 Figure 9.39 Figure 9.40 Figure 9.41 Figure 9.42 Figure 9.43 Figure 9.44 Figure 9.45 Figure 9.46 Figure 9.47 Figure 9.48 Figure 9.49 Figure 9.50 Figure 9.51 Figure 9.52 Figure 9.53 Figure 9.54 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Example of Phase Counting Mode 2 Operation ...................................................... 371 Example of Phase Counting Mode 3 Operation ...................................................... 372 Example of Phase Counting Mode 4 Operation ...................................................... 373 Phase Counting Mode Application Example........................................................... 375 Count Timing in Internal Clock Operation ............................................................. 379 Count Timing in External Clock Operation ............................................................ 379 Output Compare Output Timing ............................................................................. 380 Input Capture Input Signal Timing.......................................................................... 380 Counter Clear Timing (Compare Match) ................................................................ 381 Counter Clear Timing (Input Capture) .................................................................... 381 Buffer Operation Timing (Compare Match) ........................................................... 382 Buffer Operation Timing (Input Capture) ............................................................... 382 TGI Interrupt Timing (Compare Match) ................................................................. 383 TGI Interrupt Timing (Input Capture)..................................................................... 383 TCIV Interrupt Setting Timing................................................................................ 384 TCIU Interrupt Setting Timing................................................................................ 384 Timing for Status Flag Clearing by CPU ................................................................ 385 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 386 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 386 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 387 Conflict between TCNT Write and Clear Operations ............................................. 388 Conflict between TCNT Write and Increment Operations...................................... 389 Conflict between TGR Write and Compare Match ................................................. 389 Conflict between Buffer Register Write and Compare Match ................................ 390 Conflict between TGR Read and Input Capture...................................................... 391 Conflict between TGR Write and Input Capture..................................................... 391 Conflict between Buffer Register Write and Input Capture .................................... 392 Conflict between Overflow and Counter Clearing .................................................. 393 Conflict between TCNT Write and Overflow ......................................................... 394 Watchdog Timer (WDT) Block Diagram of WDT.......................................................................................... 395 Operation in Watchdog Timer Mode ...................................................................... 400 Operation in Interval Timer Mode .......................................................................... 401 Writing to TCNT, TCSR, and RSTCSR ................................................................. 402 Conflict between TCNT Write and Increment ........................................................ 403 Section 11 Watch Timer (WAT) Figure 11.1 Block Diagram of WAT.......................................................................................... 405 Figure 11.2 Operation in Compare Match Timer Mode ............................................................. 412 Rev.2.00 Oct. 16, 2007 Page xxxix of liv REJ09B0381-0200 Figure 11.3 Operation in Interval Timer Mode .......................................................................... 414 Figure 11.4 Conflict between WTCNT Write and Increment .................................................... 416 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI............................................................................................. 420 Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 448 Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 450 Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode)............................................................................................. 451 Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 452 Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 453 Figure 12.7 Sample Serial Transmission Flowchart................................................................... 454 Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 455 Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 457 Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 458 Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ............................................ 460 Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart.......................................... 461 Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 462 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1).......................................... 463 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2).......................................... 464 Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First) ...................... 465 Figure 12.15 Sample SCI Initialization Flowchart ....................................................................... 466 Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode ............... 468 Figure 12.17 Sample Serial Transmission Flowchart................................................................... 468 Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode .................... 469 Figure 12.19 Sample Serial Reception Flowchart ........................................................................ 470 Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ................ 471 Figure 12.21 Pin Connection for Smart Card Interface ................................................................ 472 Figure 12.22 Data Formats in Normal Smart Card Interface Mode ............................................. 473 Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) ........................................................ 473 Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1) ...................................................... 474 Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate)............................................... 475 Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode ........................................ 478 Figure 12.27 TEND Flag Set Timing during Transmission ......................................................... 478 Rev.2.00 Oct. 16, 2007 Page xl of liv REJ09B0381-0200 Figure 12.28 Sample Transmission Flowchart ............................................................................. 479 Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode ............................................. 480 Figure 12.30 Sample Reception Flowchart................................................................................... 481 Figure 12.31 Clock Output Fixing Timing ................................................................................... 481 Figure 12.32 Clock Stop and Restart Procedure........................................................................... 482 Figure 12.33 Sample Transmission Using DMAC in Clocked Synchronous Mode..................... 486 Figure 12.34 Sample Flowchart for Mode Transition during Transmission................................. 488 Figure 12.35 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission)........................................................ 489 Figure 12.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission)............................................ 489 Figure 12.37 Sample Flowchart for Mode Transition during Reception ...................................... 490 Section 13 I C Bus Interface 2 (IIC2) 2 Figure 13.1 Block Diagram of I C Bus Interface 2..................................................................... 492 Figure 13.2 Connections to the External Circuit by the I/O Pins ............................................... 493 2 Figure 13.3 I C Bus Formats ...................................................................................................... 507 2 Figure 13.4 I C Bus Timing........................................................................................................ 507 Figure 13.5 Master Transmit Mode Operation Timing 1............................................................ 509 Figure 13.6 Master Transmit Mode Operation Timing 2............................................................ 509 Figure 13.7 Master Receive Mode Operation Timing 1 ............................................................. 511 Figure 13.8 Master Receive Mode Operation Timing 2 ............................................................. 512 Figure 13.9 Slave Transmit Mode Operation Timing 1.............................................................. 513 Figure 13.10 Slave Transmit Mode Operation Timing 2.............................................................. 514 Figure 13.11 Slave Receive Mode Operation Timing 1 ............................................................... 515 Figure 13.12 Slave Receive Mode Operation Timing 2 ............................................................... 516 Figure 13.13 Block Diagram of Noise Canceller.......................................................................... 516 Figure 13.14 Sample Flowchart of Master Transmit Mode.......................................................... 517 Figure 13.15 Sample Flowchart for Master Receive Mode .......................................................... 518 Figure 13.16 Sample Flowchart for Slave Transmit Mode........................................................... 519 Figure 13.17 Sample Flowchart for Slave Receive Mode ............................................................ 520 Figure 13.18 Timing of the Bit Synchronous Circuit ................................................................... 522 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Controller Area Network (RCAN-ET) RCAN-ET Architecture........................................................................................... 525 RCAN-ET Memory Map ........................................................................................ 528 Mailbox-n Structure ................................................................................................ 530 Acceptance Filter..................................................................................................... 535 ID Reorder............................................................................................................... 538 Reset Sequence........................................................................................................ 571 Rev.2.00 Oct. 16, 2007 Page xli of liv REJ09B0381-0200 2 Figure 14.7 Halt Mode/Sleep Mode ........................................................................................... 573 Figure 14.8 Halt Mode/Sleep Mode ........................................................................................... 574 Figure 14.9 Transmission Request ............................................................................................. 577 Figure 14.10 Internal Arbitration for Transmission...................................................................... 578 Figure 14.11 Message receive sequence....................................................................................... 579 Figure 14.12 Change ID of Receive Box or Change Receive Box to Transmit Box.................... 582 Figure 14.13 Overview of PORT Interface .................................................................................. 586 Figure 14.14 High-Speed Interface Using HA13721 ................................................................... 586 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Synchronous Serial Communication Unit (SSU) Block Diagram of SSU............................................................................................ 590 Relationship of Clock Phase, Polarity, and Data..................................................... 607 Relationship between Data Input/Output Pins and the Shift Register ..................... 608 Example of Initial Settings in SSU Mode ............................................................... 611 Example of Transmission Operation (SSU Mode) (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 .................................... 613 Figure 15.5 Example of Transmission Operation (SSU Mode) (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 ........... 613 Figure 15.5 Example of Transmission Operation (SSU Mode) (3) When 24-bit data length is selected (SSTDR0, SSTDR1, and SSTDR2 are valid) with CPOS = 0 and CPHS = 0.......................................................................................................... 614 Figure 15.5 Example of Transmission Operation (SSU Mode) (4) When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2, and SSTDR3 are valid) with CPOS = 0 and CPHS = 0.......................................................................................................... 614 Figure 15.6 Flowchart Example of Data Transmission (SSU Mode) ......................................... 615 Figure 15.7 Example of Reception Operation (SSU Mode) (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 .................................... 617 Figure 15.7 Example of Reception Operation (SSU Mode) (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0........... 617 Figure 15.7 Example of Reception Operation (SSU Mode) (3) When 24-bit data length is selected (SSRDR0, SSRDR1, and SSRDR2 are valid) with CPOS = 0 and CPHS = 0.......................................................................................................... 618 Figure 15.7 Example of Reception Operation (SSU Mode) (4) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2 and SSRDR3 are valid) with CPOS = 0 and CPHS = 0.......................................................................................................... 618 Figure 15.8 Flowchart Example of Data Reception (SSU Mode) .............................................. 619 Figure 15.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 620 Figure 15.10 Conflict Error Detection Timing (Before Transfer) ................................................ 621 Figure 15.11 Conflict Error Detection Timing (After Transfer End) ........................................... 621 Figure 15.12 Example of Initial Settings in Clock Synchronous Communication Mode............. 622 Rev.2.00 Oct. 16, 2007 Page xlii of liv REJ09B0381-0200 Figure 15.13 Example of Transmission Operation (Clock Synchronous Communication Mode) .......................................................... 623 Figure 15.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) .......................................................... 624 Figure 15.15 Example of Reception Operation (Clock Synchronous Communication Mode)..... 625 Figure 15.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) .......................................................... 626 Figure 15.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode) .......................................................... 627 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 A/D Converter Block Diagram of A/D Converter (Unit 0/AD_0)................................................... 630 Block Diagram of A/D Converter (Unit 1/AD_1)................................................... 631 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 639 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) .......................................... 640 Figure 16.5 A/D Conversion Timing.......................................................................................... 641 Figure 16.6 External Trigger Input Timing ................................................................................ 642 Figure 16.7 A/D Conversion Accuracy Definitions ................................................................... 644 Figure 16.8 A/D Conversion Accuracy Definitions ................................................................... 644 Figure 16.9 Example of Analog Input Circuit ............................................................................ 645 Figure 16.10 Example of Analog Input Protection Circuit........................................................... 647 Figure 16.11 Analog Input Pin Equivalent Circuit ....................................................................... 648 Section 17 D/A Converter Figure 17.1 Block Diagram of D/A Converter ........................................................................... 649 Figure 17.2 Example of D/A Converter Operation..................................................................... 653 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Motor Control PWM Timer (PWM) Block Diagram of PWM ......................................................................................... 656 Cycle Register Compare Match .............................................................................. 662 Duty Register Compare Match (OPS = 0 in PWPR)............................................... 664 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR)................................................................................................. 664 16-Bit Register Access Operation (Bus Master ↔ PWCYR (16 Bits)) .................. 667 8-Bit Register Access Operation (Bus Master ↔ PWCR (Upper Eight Bits)) ....... 667 PWM Operation ...................................................................................................... 668 Disabling Buffer Transfer ....................................................................................... 669 Conflict between Buffer Register Write and Compare Match ................................ 670 Rev.2.00 Oct. 16, 2007 Page xliii of liv REJ09B0381-0200 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 16-Bit PWM Block Diagram of PWM ......................................................................................... 672 Cycle Register Compare Match .............................................................................. 678 Operation in 16-Bit PWM Mode............................................................................. 683 Operation in 10-Bit Stepping Motor Mode ............................................................. 684 Conflict between Buffer Register Write and Compare Match ................................ 685 Sound Generator (SDG) Block Diagram of SDG........................................................................................... 687 Examples of SDG Stopping Operation ................................................................... 696 SDG Operation Flow............................................................................................... 697 Attenuation Characteristics ..................................................................................... 699 Output Waveforms .................................................................................................. 700 Section 22 Flash Memory Figure 22.1 Block Diagram of Flash Memory............................................................................ 704 Figure 22.2 Mode Transition of Flash Memory ......................................................................... 705 Figure 22.3 Block Structure of 512-kbyte User MAT................................................................ 707 Figure 22.4 Block Structure of 384-kbyte User MAT................................................................ 708 Figure 22.5 Procedure for Creating Procedure Program ............................................................ 709 Figure 22.6 System Configuration in Boot Mode....................................................................... 733 Figure 22.7 Automatic-Bit-Rate Adjustment Operation............................................................. 734 Figure 22.8 Boot Mode State Transition Diagram ..................................................................... 735 Figure 22.9 Programming/Erasing Flow .................................................................................... 737 Figure 22.10 RAM Map when Programming/Erasing Is Executed .............................................. 738 Figure 22.11 Programming Procedure in User Program Mode .................................................... 739 Figure 22.12 Erasing Procedure in User Program Mode.............................................................. 744 Figure 22.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode......................................................................................................... 746 Figure 22.14 Transitions to Error Protection State ....................................................................... 752 Figure 22.15 RAM Emulation Flow............................................................................................. 753 Figure 22.16 Address Map of Overlaid RAM Area ..................................................................... 754 Figure 22.17 Programming Tuned Data ....................................................................................... 755 Figure 22.18 Boot Program States................................................................................................ 757 Figure 22.19 Bit-Rate-Adjustment Sequence ............................................................................... 758 Figure 22.20 Communication Protocol Format ............................................................................ 759 Figure 22.21 New Bit-Rate Selection Sequence........................................................................... 770 Figure 22.22 Programming Sequence .......................................................................................... 773 Figure 22.23 Erasure Sequence .................................................................................................... 773 Rev.2.00 Oct. 16, 2007 Page xliv of liv REJ09B0381-0200 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Figure 24.4 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 785 Connection of Crystal Resonator (Example)........................................................... 791 Crystal Resonator Equivalent Circuit...................................................................... 791 External Clock Input (Examples) ............................................................................ 792 Clock Modification Timing..................................................................................... 795 Note on Board Design for Oscillation Circuit ......................................................... 795 Connection Example of Bypass Capacitor .............................................................. 796 Power-Down Modes Mode Transitions..................................................................................................... 799 Software Standby Mode Application Example ....................................................... 812 Hardware Standby Mode Timing ............................................................................ 813 Timing Sequence at Power-On................................................................................ 814 Section 26 Electrical Characteristics Figure 26.1 Output Load Circuit ................................................................................................ 883 Figure 26.2 External Bus Clock Timing..................................................................................... 884 Figure 26.3 Oscillation Settling Timing after Software Standby Mode ..................................... 885 Figure 26.4 Oscillation Settling Timing ..................................................................................... 885 Figure 26.5 External Input Clock Timing................................................................................... 885 Figure 26.6 Reset Input Timing.................................................................................................. 886 Figure 26.7 Interrupt Input Timing............................................................................................. 887 Figure 26.8 Basic Bus Timing: 2-State Access .......................................................................... 890 Figure 26.9 Basic Bus Timing: 3-State Access .......................................................................... 891 Figure 26.10 DMAC (DREQ) Input Timing ................................................................................ 892 Figure 26.11 DMAC (TEND) Output Timing.............................................................................. 892 Figure 26.12 DMAC Single-Address Transfer Timing: 2-State Access....................................... 893 Figure 26.13 DMAC Single-Address Transfer Timing: 3-State Access....................................... 894 Figure 26.14 I/O Port Input/Output Timing.................................................................................. 898 Figure 26.15 TPU Input/Output Timing ....................................................................................... 898 Figure 26.16 TPU Clock Input Timing......................................................................................... 898 Figure 26.17 Motor Control PWM Output Timing ...................................................................... 899 Figure 26.18 16-Bit PWM Output Timing ................................................................................... 899 Figure 26.19 SCK Clock Input/Output Timing ............................................................................ 899 Figure 26.20 SCI Input/Output Timing: Clocked Synchronous Mode......................................... 899 2 Figure 26.21 I C Bus Interface Input/Output Timing ................................................................... 900 Figure 26.22 A/D Converter External Trigger Input Timing........................................................ 900 Figure 26.23 RCAN-ET Input/Output Timing ............................................................................. 900 Figure 26.24 SSU Timing (Master, CPHS = 1)............................................................................ 901 Rev.2.00 Oct. 16, 2007 Page xlv of liv REJ09B0381-0200 Figure 26.25 SSU Timing (Master, CPHS = 0)............................................................................ 901 Figure 26.26 SSU Timing (Slave, CPHS = 1) .............................................................................. 902 Figure 26.27 SSU Timing (Slave, CPHS = 0) .............................................................................. 902 Appendix Figure C.1 Package Dimensions (FP-144L).............................................................................. 908 Rev.2.00 Oct. 16, 2007 Page xlvi of liv REJ09B0381-0200 Tables Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode................................................................ 4 Table 1.2 Pin Functions............................................................................................................... 9 Section 2 CPU Instruction Classification........................................................................................... 36 Table 2.1 Table 2.2 Combinations of Instructions and Addressing Modes (1) ......................................... 38 Table 2.2 Combinations of Instructions and Addressing Modes (2) ......................................... 41 Table 2.3 Operation Notation.................................................................................................... 42 Table 2.4 Data Transfer Instructions ......................................................................................... 43 Table 2.5 Block Transfer Instructions ....................................................................................... 44 Table 2.6 Arithmetic Operation Instructions............................................................................. 45 Table 2.7 Logic Operation Instructions..................................................................................... 47 Table 2.8 Shift Operation Instructions ...................................................................................... 48 Table 2.9 Bit Manipulation Instructions.................................................................................... 49 Table 2.10 Branch Instructions ................................................................................................... 51 Table 2.11 System Control Instructions ...................................................................................... 52 Table 2.12 Addressing Modes..................................................................................................... 54 Table 2.13 Absolute Address Access Ranges ............................................................................. 58 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions ................... 62 Table 2.15 Effective Address Calculation for Branch Instructions ............................................. 63 Section 3 MCU Operating Modes MCU Operating Mode Settings................................................................................. 67 Table 3.1 Table 3.2 Settings of Bits MDS3 to MDS0 ............................................................................... 69 Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode)....................................... 74 Section 4 Exception Handling Exception Types and Priority .................................................................................... 79 Table 4.1 Table 4.2 Exception Handling Vector Table ............................................................................. 80 Table 4.3 Calculation Method of Exception Handling Vector Table Address .......................... 81 Table 4.4 Status of CCR and EXR after Trace Exception Handling......................................... 85 Table 4.5 Bus Cycle and Address Error .................................................................................... 86 Table 4.6 Status of CCR and EXR after Address Error Exception Handling............................ 87 Table 4.7 Interrupt Sources ....................................................................................................... 88 Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling ........................ 89 Rev.2.00 Oct. 16, 2007 Page xlvii of liv REJ09B0381-0200 Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling...................... 90 Section 5 Interrupt Controller Pin Configuration ...................................................................................................... 95 Table 5.1 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority .......................... 112 Table 5.3 Interrupt Control Modes.......................................................................................... 117 Table 5.4 Interrupt Response Times........................................................................................ 122 Table 5.5 Number of Execution States in Interrupt Handling Routine ................................... 123 Table 5.6 Interrupt Source Selection and Clear Control ......................................................... 125 Table 5.7 CPU Priority Control............................................................................................... 127 Table 5.8 Example of Priority Control Function Setting and Control State............................ 127 Section 6 Bus Controller (BSC) Synchronization Clocks and Corresponding Functions........................................... 149 Table 6.1 Table 6.2 Pin Configuration .................................................................................................... 152 Table 6.3 Pin Functions in Each Interface .............................................................................. 153 Table 6.4 Interface Names and Area Names ........................................................................... 155 Table 6.5 Areas Specifiable for Each Interface....................................................................... 155 Table 6.6 Number of Access Cycles ....................................................................................... 156 Table 6.7 I/O Pins for Basic Bus Interface.............................................................................. 162 Table 6.8 Number of Idle Cycle Insertion Selection in Each Area ......................................... 173 Table 6.9 Number of Idle Cycle Insertions ............................................................................. 173 Table 6.10 Idle Cycles in Mixed Accesses to Normal Space.................................................... 179 Table 6.11 Pin States in Idle Cycle ........................................................................................... 180 Table 6.12 Number of Access Cycles for On-Chip Memory Spaces ........................................ 180 Table 6.13 Number of Access Cycles for Registers of On-Chip Peripheral Modules .............. 181 Section 7 DMA Controller (DMAC) Pin Configuration .................................................................................................... 189 Table 7.1 Table 7.2 Data Access Size, Valid Bits, and Settable Size ..................................................... 196 Table 7.3 Settings and Areas of Extended Repeat Area.......................................................... 210 Table 7.4 Transfer Modes ....................................................................................................... 211 Table 7.5 List of On-Chip Module Interrupts to DMAC ........................................................ 221 Table 7.6 Priority among DMAC Channels ............................................................................ 235 Table 7.7 Interrupt Sources and Priority ................................................................................. 254 Section 8 I/O Ports Port Functions ......................................................................................................... 259 Table 8.1 Table 8.2 Register Configuration in Each Port ....................................................................... 265 Table 8.3 Startup Mode and Initial Value ............................................................................... 266 Rev.2.00 Oct. 16, 2007 Page xlviii of liv REJ09B0381-0200 Table 8.4 Table 8.5 Input Pull-Up MOS State ........................................................................................ 269 Available Output Signals and Settings in Each Port ............................................... 295 Section 9 16-Bit Timer Pulse Unit (TPU) TPU Functions ........................................................................................................ 308 Table 9.1 Table 9.2 Pin Configuration .................................................................................................... 311 Table 9.3 CCLR2 to CCLR0 (Channels 0 and 3).................................................................... 315 Table 9.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)........................................................... 316 Table 9.5 Input Clock Edge Selection..................................................................................... 316 Table 9.6 TPSC2 to TPSC0 (Channel 0)................................................................................. 317 Table 9.7 TPSC2 to TPSC0 (Channel 1)................................................................................. 317 Table 9.8 TPSC2 to TPSC0 (Channel 2)................................................................................. 318 Table 9.9 TPSC2 to TPSC0 (Channel 3)................................................................................. 318 Table 9.10 TPSC2 to TPSC0 (Channel 4)................................................................................. 319 Table 9.11 TPSC2 to TPSC0 (Channel 5)................................................................................. 319 Table 9.12 MD3 to MD0........................................................................................................... 321 Table 9.13 TIORH_0................................................................................................................. 324 Table 9.14 TIORL_0 ................................................................................................................. 325 Table 9.15 TIOR_1 ................................................................................................................... 326 Table 9.16 TIOR_2 ................................................................................................................... 327 Table 9.17 TIORH_3................................................................................................................. 328 Table 9.18 TIORL_3 ................................................................................................................. 329 Table 9.19 TIOR_4 ................................................................................................................... 330 Table 9.20 TIOR_5 ................................................................................................................... 331 Table 9.21 TIORH_0................................................................................................................. 332 Table 9.22 TIORL_0 ................................................................................................................. 333 Table 9.23 TIOR_1 ................................................................................................................... 334 Table 9.24 TIOR_2 ................................................................................................................... 335 Table 9.25 TIORH_3................................................................................................................. 336 Table 9.26 TIORL_3 ................................................................................................................. 337 Table 9.27 TIOR_4 ................................................................................................................... 338 Table 9.28 TIOR_5 ................................................................................................................... 339 Table 9.29 Register Combinations in Buffer Operation............................................................ 357 Table 9.30 Cascaded Combinations .......................................................................................... 361 Table 9.31 PWM Output Registers and Output Pins................................................................. 364 Table 9.32 Clock Input Pins in Phase Counting Mode.............................................................. 368 Table 9.33 Up-/Down-Count Conditions in Phase Counting Mode 1....................................... 370 Table 9.34 Up-/Down-Count Conditions in Phase Counting Mode 2....................................... 371 Table 9.35 Up-/Down-Count Conditions in Phase Counting Mode 3....................................... 372 Table 9.36 Up-/Down-Count Conditions in Phase Counting Mode 4....................................... 373 Rev.2.00 Oct. 16, 2007 Page xlix of liv REJ09B0381-0200 Table 9.37 TPU Interrupts......................................................................................................... 376 Section 10 Watchdog Timer (WDT) Table 10.1 WDT Interrupt Source............................................................................................. 401 Section 12 Serial Communication Interface (SCI) Table 12.1 Pin Configuration .................................................................................................... 421 Table 12.2 Relationships between N Setting in BRR and Bit Rate B ....................................... 443 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)......... 444 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)......... 445 Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)............ 445 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 446 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 446 Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 447 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) 447 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) .................................................................... 447 Table 12.10 Serial Transfer Formats (Asynchronous Mode) ...................................................... 449 Table 12.11 SSR Status Flags and Receive Data Handling ........................................................ 456 Table 12.12 SCI Interrupt Sources.............................................................................................. 483 Table 12.13 SCI Interrupt Sources.............................................................................................. 484 Section 13 I C Bus Interface 2 (IIC2) 2 Table 13.1 Pin configuration of the I C bus interface 2 ............................................................ 493 Table 13.2 Transfer Rate........................................................................................................... 496 Table 13.3 Interrupt Requests ................................................................................................... 521 Table 13.4 Time for Monitoring SCL ....................................................................................... 522 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Controller Area Network (RCAN-ET) Pin Configuration of the RCAN-ET........................................................................ 527 Address Map for Each Meailbox............................................................................. 529 Roles of Mailboxes ................................................................................................. 530 Mailbox Function Setting........................................................................................ 534 RCAN-ET Control Registers Configuration ........................................................... 537 TSG and TSEG Setting ........................................................................................... 550 RCAN-ET Mailbox Registers ................................................................................. 559 Conditions to Access Registers ............................................................................... 575 Test Mode Settings.................................................................................................. 575 RCAN-ET Interrupt Sources................................................................................... 583 2 Rev.2.00 Oct. 16, 2007 Page l of liv REJ09B0381-0200 Section 15 Synchronous Serial Communication Unit (SSU) Table 15.1 Pin Configuration .................................................................................................... 591 Table 15.2 Communication Modes and Pin States of SSI and SSO Pins .................................. 609 Table 15.3 Communication Modes and Pin States of SSCK Pin .............................................. 610 Table 15.4 Communication Modes and Pin States of SCS Pin ................................................. 610 Table 15.5 SSU Interrupt Sources............................................................................................. 628 Section 16 A/D Converter Table 16.1 Pin Configuration .................................................................................................... 632 Table 16.2 Analog Input Channels and Corresponding ADDR Registers................................. 634 Table 16.3 A/D Conversion Characteristics (Single Mode)...................................................... 642 Table 16.4 A/D Conversion Characteristics (Scan Mode) ........................................................ 642 Table 16.5 A/D Converter Interrupt Sources............................................................................. 643 Table 16.6 Analog Pin Specifications ....................................................................................... 647 Section 17 D/A Converter Table 17.1 Pin Configuration .................................................................................................... 650 Table 17.2 Control of D/A Conversion ..................................................................................... 652 Section 18 Motor Control PWM Timer (PWM) Table 18.1 Pin Configuration .................................................................................................... 657 Table 18.2 Output Selection by OTS Bit................................................................................... 663 Section 19 16-Bit PWM Table 19.1 Pin Configuration .................................................................................................... 673 Table 19.2 Selection for PWM0 and PWM1 Outputs ............................................................... 680 Table 19.3 Selection for PWM2 and PWM3 Outputs ............................................................... 681 Section 20 Sound Generator (SDG) Table 20.1 Pin Configuration .................................................................................................... 688 Table 20.2 SDG Stop Conditions .............................................................................................. 695 Table 20.3 Relationship between Tone Frequency and Output Error ....................................... 698 Table 20.4 SDG Interrupt Source.............................................................................................. 700 Section 22 Flash Memory Table 22.1 Differences between Boot Mode, User Program Mode, and Programmer Mode.... 706 Table 22.2 Pin Configuration .................................................................................................... 711 Table 22.3 Registers/Parameters and Target Modes ................................................................. 712 Table 22.4 Parameters and Target Modes ................................................................................. 718 Table 22.5 On-Board Programming Mode Setting ................................................................... 733 Rev.2.00 Oct. 16, 2007 Page li of liv REJ09B0381-0200 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 Table 22.15 Table 22.16 Table 22.17 System Clock Frequency for Automatic-Bit-Rate Adjustment ............................... 734 Executable Memory MAT ...................................................................................... 748 Usable Area for Programming in User Program Mode........................................... 748 Usable Area for Erasure in User Program Mode..................................................... 749 Hardware Protection................................................................................................ 750 Software Protection................................................................................................. 751 Device Types Supported in Programmer Mode ...................................................... 756 Inquiry and Selection Commands ........................................................................... 760 Programming/Erasing Commands .......................................................................... 772 Status Codes ............................................................................................................ 779 Error Codes ............................................................................................................. 780 Initiation Intervals of User Branch Processing........................................................ 782 Section 23 Clock Pulse Generator Table 23.1 Damping Resistance Value ..................................................................................... 791 Table 23.2 Crystal Resonator Characteristics ........................................................................... 792 Section 24 Power-Down Modes Table 24.1 Operating States ...................................................................................................... 798 Table 24.2 Oscillation Settling Time Settings........................................................................... 811 Table 24.3 Bφ Pin (PA7) State in Each Processing State.......................................................... 816 Section 26 Table 26.1 Table 26.2 Table 26.2 Table 26.2 Table 26.3 Table 26.3 Table 26.4 Table 26.5 Table 26.6 Table 26.6 Table 26.7 Table 26.8 Table 26.8 Table 26.9 Table 26.10 Table 26.11 Electrical Characteristics Absolute Maximum Ratings.................................................................................... 877 DC Characteristics (1)............................................................................................. 878 DC Characteristics (2)............................................................................................. 879 DC Characteristics (3)............................................................................................. 880 Permissible Output Currents (1).............................................................................. 881 Permissible Output Currents (2).............................................................................. 882 Clock Timing .......................................................................................................... 884 Control Signal Timing............................................................................................. 886 Bus Timing (1) ........................................................................................................ 888 Bus Timing (2) ........................................................................................................ 889 DMAC Timing ........................................................................................................ 892 Timing of On-Chip Peripheral Modules (1)............................................................ 895 Timing of On-Chip Peripheral Modules (2)............................................................ 897 A/D Conversion Characteristics.............................................................................. 903 D/A Conversion Characteristics.............................................................................. 903 Flash Memory Characteristics................................................................................. 904 Rev.2.00 Oct. 16, 2007 Page lii of liv REJ09B0381-0200 Appendix Table A.1 Port States in Each Pin State ................................................................................... 905 Rev.2.00 Oct. 16, 2007 Page liii of liv REJ09B0381-0200 Rev.2.00 Oct. 16, 2007 Page liv of liv REJ09B0381-0200 Section 1 Overview Section 1 Overview 1.1 Features • 32-bit high-speed H8SX CPU Upward compatible at object level with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions DMA controller (DMAC) 16-bit timer pulse unit (TPU) Watchdog timer (WDT) Watch timer (WAT) Motor control PWM timer 16-bit PWM timer Sound generator (SDG) Asynchronous or clocked-synchronous serial communication interface (SCI) I C bus interface 2 (IIC2) Controller area network (RCAN-ET) Synchronous serial communication unit (SSU) 10-bit A/D converter 8-bit D/A converter Clock pulse generator • On-chip memory Product Classification Flash memory version H8SX/1544 H8SX/1543 Part No. R5F61544 R5F61543 ROM 512 kbytes 384 kbytes RAM 24 kbytes 16 kbytes 2 • General I/O port 95 input/output ports 17 input ports • Supports a variety of power-down modes Rev.2.00 Oct. 16, 2007 Page 1 of 916 REJ09B0381-0200 Section 1 Overview • Small package Package LQFP-144 Code FP-144L Body Size 20.0 × 20.0 mm Pin Pitch 0.50 mm 1.2 Block Diagram WDT Port 1 WAT Port 2 RAM TPU × 6 channels SCI × 4 channels ROM SSU × 2 channels IIC2 × 2 channels H8SX CPU Peripheral bus Internal bus Port 3 Port 4 Port 5 Port 6 Port A Port D RCAN-ET × 2 channels Motor control PWM Clock pulse generator Interrupt controller 16-bit PWM Port E SDG × 4 channels Port F A/D converter unit 0 × 8 channels A/D converter unit 1 × 8 channels D/A converter × 2 channels Port H Port I Port J Port K BSC DMAC × 4 channels Legend: CPU: DMAC: BSC: WDT: WAT: TPU: Central processing unit DMA controller Bus controller Watchdog timer Watch timer 16-bit timer pulse unit Serial communication interface SCI: Synchronous serial communication unit SSU: I2C bus interface 2 IIC2: RCAN-ET: Controller area network SDG: Sound generator Figure 1.1 Block Diagram of H8SX/1544 Rev.2.00 Oct. 16, 2007 Page 2 of 916 REJ09B0381-0200 Section 1 Overview 1.3 1.3.1 Pin Assignments Pin Assignments MD2 P30/TIOCA0 P31/TIOCB0 P32/TIOCC0/TCLKA-A P33/TIOCD0/TCLKB-A P34/TIOCA1/SGOUT_0 P35/TIOCB1/TCLKC-A/SGOUT_1 P36/TIOCA2/SGOUT_2 P37/TIOCB2/TCLKD-A/SGOUT_3 RES Vcc Vss EXTAL XTAL Vss VCL EMLE* NMI P27/TIOCB5 P26/TIOCA5 P25/TIOCA4 P24/TIOCB4 P23/TIOCD3/SCS_1 P22/TIOCC3/TxD0/SSCK_1 P21/TIOCA3/RxD0/SSI_1 P20/TIOCB3/SCK0/SSO_1 PA7/Bφ PA6/AS PA5/RD PA4/LHWR PA3/LLWR STBY P62/SCK4/IRQ10-B/TRST/DACK2_B P61/RxD4/IRQ9-B/TEND2_B P60/TxD4/IRQ8-B/DREQ2_B NC 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Note: * Emulator enable pin. This pin should be low in normal operating modes. When the EMLE pin is driven high, the emulation function is enabled and the TDO, TDI, TCK, TMS, and TRST pins are only used specific for the on-chip emulator E10A. PI4/D12 PI5/D13 PI6/D14 PI7/D15 Vcc Vss PD0/A0 PD1/A1 PD2/A2 PD3/A3 PD4/A4 PD5/A5 PD6/A6 PD7/A7 Vcc Vss PE0/A8 PE1/A9 PE2/A10 PE3/A11 PE4/A12 PE5/A13 PE6/A14 PE7/A15 PF0/A16/PWM0_0 PF1/A17/PWM1_0 PF2/A18/PWM2_0 PF3/A19/PWM3_0 PWMVcc PWMVss PF4/A20/PWM0_1 PF5/A21/TxD5/PWM1_1 PF6/A22/RxD5/PWM2_1 PF7/A23/SCK5/PWM3_1 PJ0/PWM1A PJ1/PWM1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 P47/AN11 AVcc1 Vref AVcc0 AVss P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6/DA0 P57/AN7/DA1 MD1 MD0 PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PH7/D7 Vcc Vss PI0/D8/SSO_0 PI1/D9/SSI_0 PI2/D10/SSCK_0 PI3/D11/SCS_0 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 FP-144L (Top view) Index 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Vss Vcc P67/IRQ15-B/CTx_1 P66/IRQ14-B/CRx_1 P65/IRQ13-B/CTx_0/DACK3_B P64/IRQ12-B/CRx_0/TEND3_B P63/IRQ11-B/PWM3_2/TMS/DREQ3_B PA2/TCK/PWM2_2 PA1/TDI/PWM1_2 PA0/TDO/PWM0_2 P17/SCL0/IRQ7-A/ADTRG1 P16/SDA0/IRQ6-A/DACK1_A P15/SCL1/IRQ5-A/TEND1_A P14/SDA1/IRQ4-A/DREQ1_A P13/IRQ3-A/ADTRG0 P12/SCK2/IRQ2-A/DACK0_A P11/RxD2/IRQ1-A/TEND0_A P10/TxD2/IRQ0-A/DREQ0_A PK7/PWM2H PK6/PWM2G PK5/PWM2F PK4/PWM2E PWMVss PWMVcc PK3/PWM2D PK2/PWM2C PK1/PWM2B PK0/PWM2A PJ7/PWM1H PJ6/PWM1G PJ5/PWM1F PJ4/PWM1E PWMVss PWMVcc PJ3/PWM1D PJ2/PWM1C Figure 1.2 Pin Assignments of H8SX/1544 Rev.2.00 Oct. 16, 2007 Page 3 of 916 REJ09B0381-0200 Section 1 Overview 1.3.2 Table 1.1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Configuration in Each Operating Mode Pin Configuration in Each Operating Mode Abbreviation in Mode 2, Mode 6, and Mode 7 PI4/D12 PI5/D13 PI6/D14 PI7/D15 Vcc Vss PD0/A0 PD1/A1 PD2/A2 PD3/A3 PD4/A4 PD5/A5 PD6/A6 PD7/A7 Vcc Vss PE0/A8 PE1/A9 PE2/A10 PE3/A11 PE4/A12 PE5/A13 PE6/A14 PE7/A15 PF0/A16/PWM0_0 PF1/A17/PWM1_0 PF2/A18/PWM2_0 PF3/A19/PWM3_0 Abbreviation in Mode 4 and Mode 5 PI4/D12 PI5/D13 PI6/D14 PI7/D15 Vcc Vss A0 A1 A2 A3 A4 A5 A6 A7 Vcc Vss A8 A9 A10 A11 A12 A13 A14 A15 PF0/A16/PWM0_0 PF1/A17/PWM1_0 PF2/A18/PWM2_0 PF3/A19/PWM3_0 Rev.2.00 Oct. 16, 2007 Page 4 of 916 REJ09B0381-0200 Section 1 Overview Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Abbreviation in Mode 2, Mode 6, and Mode 7 PWMVcc PWMVss PF4/A20/PWM0_1 PF5/A21/TxD5/PWM1_1 PF6/A22/RxD5/PWM2_1 PF7/A23/SCK5/PWM3_1 PJ0/PWM1A PJ1/PWM1B PJ2/PWM1C PJ3/PWM1D PWMVcc PWMVss PJ4/PWM1E PJ5/PWM1F PJ6/PWM1G PJ7/PWM1H PK0/PWM2A PK1/PWM2B PK2/PWM2C PK3/PWM2D PWMVcc PWMVss PK4/PWM2E PK5/PWM2F PK6/PWM2G PK7/PWM2H P10/TxD2/IRQ0-A/DREQ0_A P11/RxD2/IRQ1-A/TEND0_A P12/SCK2/IRQ2-A/DACK0_A P13/IRQ3-A/ADTRG0 Abbreviation in Mode 4 and Mode 5 PWMVcc PWMVss PF4/A20/PWM0_1 PF5/A21/TxD5/PWM1_1 PF6/A22/RxD5/PWM2_1 PF7/A23/SCK5/PWM3_1 PJ0/PWM1A PJ1/PWM1B PJ2/PWM1C PJ3/PWM1D PWMVcc PWMVss PJ4/PWM1E PJ5/PWM1F PJ6/PWM1G PJ7/PWM1H PK0/PWM2A PK1/PWM2B PK2/PWM2C PK3/PWM2D PWMVcc PWMVss PK4/PWM2E PK5/PWM2F PK6/PWM2G PK7/PWM2H P10/TxD2/IRQ0-A/DREQ0_A P11/RxD2/IRQ1-A/TEND0_A P12/SCK2/IRQ2-A/DACK0_A P13/IRQ3-A/ADTRG0 Rev.2.00 Oct. 16, 2007 Page 5 of 916 REJ09B0381-0200 Section 1 Overview Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Abbreviation in Mode 2, Mode 6, and Mode 7 P14/SDA1/IRQ4-A/DREQ1_A P15/SCL1/IRQ5-A/TEND1_A P16/SDA0/IRQ6-A/DACK1_A P17/SCL0/IRQ7-A/ADTRG1 PA0/TDO/PWM0_2 PA1/TDI/PWM1_2 PA2/TCK/PWM2_2 P63/IRQ11-B/PWM3_2/TMS/DREQ3_B P64/IRQ12-B/CRx_0/TEND3_B P65/IRQ13-B/CTx_0/DACK3_B P66/IRQ14-B/CRx_1 P67/IRQ15-B/CTx_1 Vcc Vss NC P60/TxD4/IRQ8-B/DREQ2_B P61/RxD4/IRQ9-B/TEND2_B P62/SCK4/IRQ10-B/TRST/DACK2_B STBY PA3/LLWR PA4/LHWR PA5/RD PA6/AS PA7/Bφ P20/TIOCB3/SCK0/SSO_1 P21/TIOCA3/RxD0/SSI_1 P22/TIOCC3/TxD0/SSCK_1 P23/TIOCD3/SCS_1 P24/TIOCB4 P25/TIOCA4 Abbreviation in Mode 4 and Mode 5 P14/SDA1/IRQ4-A/DREQ1_A P15/SCL1/IRQ5-A/TEND1_A P16/SDA0/IRQ6-A/DACK1_A P17/SCL0/IRQ7-A/ADTRG1 PA0/TDO/PWM0_2 PA1/TDI/PWM1_2 PA2/TCK/PWM2_2 P63/IRQ11-B/PWM3_2/TMS/DREQ3_B P64/IRQ12-B/CRx_0/TEND3_B P65/IRQ13-B/CTx_0/DACK3_B P66/IRQ14-B/CRx_1 P67/IRQ15-B/CTx_1 Vcc Vss NC P60/TxD4/IRQ8-B/DREQ2_B P61/RxD4/IRQ9-B/TEND2_B P62/SCK4/IRQ10-B/TRST/DACK2_B STBY PA3/LLWR PA4/LHWR PA5/RD PA6/AS PA7/Bφ P20/TIOCB3/SCK0/SSO_1 P21/TIOCA3/RxD0/SSI_1 P22/TIOCC3/TxD0/SSCK_1 P23/TIOCD3/SCS_1 P24/TIOCB4 P25/TIOCA4 Rev.2.00 Oct. 16, 2007 Page 6 of 916 REJ09B0381-0200 Section 1 Overview Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Abbreviation in Mode 2, Mode 6, and Mode 7 P26/TIOCA5 P27/TIOCB5 NMI EMLE* VCL Vss XTAL EXTAL Vss Vcc RES P37/TIOCB2/TCLKD_A/SGOUT_3 P36/TIOCA2/SGOUT_2 P35/TIOCB1/TCLKC_A/SGOUT_1 P34/TIOCA1/SGOUT_0 P33/TIOCD0/TCLKB-A P32/TIOCC0/TCLKA-A P31/TIOCB0 P30/TIOCA0 MD2 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 P47/AN11 AVcc1 Vref Abbreviation in Mode 4 and Mode 5 P26/TIOCA5 P27/TIOCB5 NMI EMLE* VCL Vss XTAL EXTAL Vss Vcc RES P37/TIOCB2/TCLKD_A/SGOUT_3 P36/TIOCA2/SGOUT_2 P35/TIOCB1/TCLKC_A/SGOUT_1 P34/TIOCA1/SGOUT_0 P33/TIOCD0/TCLKB-A P32/TIOCC0/TCLKA-A P31/TIOCB0 P30/TIOCA0 MD2 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 P47/AN11 AVcc1 Vref Rev.2.00 Oct. 16, 2007 Page 7 of 916 REJ09B0381-0200 Section 1 Overview Pin No. 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Note: * Abbreviation in Mode 2, Mode 6, and Mode 7 AVcc0 AVss P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6/DA0 P57/AN7/DA1 MD1 MD0 PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PH7/D7 Vcc Vss PI0/D8/SSO_0 PI1/D9/SSI_0 PI2/D10/SSCK_0 PI3/D11/SCS_0 Abbreviation in Mode 4 and Mode 5 AVcc0 AVss P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6/DA0 P57/AN7/DA1 MD1 MD0 D0 D1 D2 D3 D4 D5 D6 D7 Vcc Vss PI0/D8/SSO_0 PI1/D9/SSI_0 PI2/D10/SSCK_0 PI3/D11/SCS_0 The EMLE (emulator enable) pin enables/disables the on-chip emulation function. This pin should be low in the normal operating modes. When the pin is driven high, the emulation function is enabled and the TDO, TDI, TCK, TMS, and TRST pins are only used for the on-chip emulator E10A. Rev.2.00 Oct. 16, 2007 Page 8 of 916 REJ09B0381-0200 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin Number 5, 15, 71, 98, 139 93 6, 16, 72 94, 97, 140 95 96 I/O Input Description Power supply pins Connect to the system power supply. Input Input Connect to Vss via a 0.1 μF capacitor, which should be placed close to this pin. Ground pins Connect to the system power supply (0 V). Input Input These pins connect to crystal resonator. EXTAL pin can be used to input external clock. For a connection example, see section 23, Clock Pulse Generator. Supplies the system clock to external devices. These pins set the operating mode. The signal levels of the pins must not be changed during operation. Reset signal input pin This LSI enters a reset state when the level on this pin goes low. STBY EMLE 77 92 34 to 31 28 to 17 14 to 7 4 to 1, 144 to 141 D7 to D0 138 to 131 I/O Bidirectional data bus Input Input Output This LSI enters hardware standby mode when the level on this pin goes low. Enables the on-chip emulator. Usually, the signal level should be fixed low. Address output pins Classification Abbreviation Power supply VCC VCL VSS Clock XTAL EXTAL Bφ Operating mode control MD2 MD1 MD0 System control RES 82 108 129 130 99 Output Input Input Address bus A23 to A20 A19 to A8 A7 to A0 Data bus D15 to D8 Rev.2.00 Oct. 16, 2007 Page 9 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation Bus control RD AS LHWR Pin Number 80 81 79 I/O Output Output Output Description External address space is being read when the level on this pin is low. Address outputs on the address bus are valid when the level on this pin is low. External address space is being written to when the level on this pin is low. The upper half of the data bus is valid. External address space is being written to when the level on this pin is low. The lower half of the data bus is valid. Non-maskable interrupt request pin When this pin is not used, this signal must be fixed high. IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B IRQ10-B IRQ9-B IRQ8-B IRQ7-A IRQ6-A IRQ5-A IRQ4-A IRQ3-A IRQ2-A IRQ1-A IRQ0-A On-chip emulator TRST TMS TDO TDI TCK 70 69 68 67 66 76 75 74 62 61 60 59 58 57 56 55 76 66 63 64 65 Input Input Output Input Input Interface pins for debugging with the on-chip emulator Input Maskable interrupt request pins LLWR 78 Output Interrupts NMI 91 Input Rev.2.00 Oct. 16, 2007 Page 10 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation DMA controller DREQ0_A (DMAC) DREQ1_A DREQ2_B DREQ3_B DACK0_A DACK1_A DACK2_B DACK3_B TEND0_A TEND1_A TEND2_B TEND3_B 16-bit timer pulse unit (TPU) (unit 0) TCLKA-A TCLKB-A TCLKC-A TCLKD-A TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Pin Number 55 59 74 66 57 61 76 68 56 60 75 67 105 104 102 100 107 106 105 104 103 102 101 100 84 83 85 86 88 87 89 90 I/O I/O These pins are used for TGRA_4 and TGRB_4 input-capture inputs, output-compare outputs, and PWM outputs. These pins are used for TGRA_5 and TGRB_5 input-capture inputs, output-compare outputs, and PWM outputs. I/O I/O I/O These pins are used for TGRA_1 and TGRB_1 input-capture inputs, output-compare outputs, and PWM outputs. These pins are used for TGRA_2 and TGRB_2 input-capture inputs, output-compare outputs, and PWM outputs. These pins are used for TGRA_3 toTGRD_3 input-capture inputs, output-compare outputs, and PWM outputs. I/O These pins are used for TGRA_0 to TGRD_0 input-capture inputs, output-compare outputs, and PWM outputs. Input These pins supply the external clocks. Output These pins indicate the transfer completion of DMAC data. Output Single address transfer acknowledge pins for DMAC I/O Input Description Pins for requesting DMAC to activate Rev.2.00 Oct. 16, 2007 Page 11 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation Motor control PWM timer PWM1A to PWM1H PWM2A to PWM2H 16-bit PWM PWM0_0 to PWM3_0 PWM0_1 to PWM3_1 PWM0_2 to PWM3_2 PWM power supply PWMVcc PWMVss Pin Number 35 to 38, 41 to 44 45 to 48, 51 to 54 25 to 28 31 to 34 63 to 66 29, 39, 49 30, 40, 50 85 55 74 32 84 56 75 33 83 57 76 34 62 60 61 59 68 70 67 69 Input RCAN-ET bus reception Output RCAN-ET bus transmission I/O IIC2 data input/output pins I/O IIC2 clock signals input/output pins I/O Clock signals input/output pins Input Receive data input pins I/O Output Output Output Output Output Input Input Output Description Output pins for the motor control PWM timer channels 1A to 1H. Output pins for the motor control PWM timer channels 2A to 2H. Output pins for the 16-bit PWM timer channels 0_0 to 3_0. Output pins for the 16-bit PWM timer channels 0_1 to 3_1. Output pins for the 16-bit PWM timer channels 0_2 to 3_2 Power supply pins for the PWM timer outputs. Power supply pins for the PWM timer outputs. Connect to the system power supply (0 V). Transmit data output pins Serial TxD0 communication TxD2 interface (SCI) TxD4 TxD5 RxD0 RxD2 RxD4 RxD5 SCK0 SCK2 SCK4 SCK5 I C bus interface 2 (IIC2) 2 SCL0 SCL1 SDA0 SDA1 Controller area CTx_0 network CTx_1 (RCAN-ET) CRx_0 CRx_1 Rev.2.00 Oct. 16, 2007 Page 12 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation Synchronous SSO_1 serial SSO_0 communication SSI_1 unit (SSU) SSI_0 SSCK_1 SSCK_0 SCS_1 SCS_0 Sound generator (SDG) A/D converter SGOUT3 to SGOUT0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG1 ADTRG0 Pin Number 83 141 84 142 85 143 86 144 100 to 103 Output Sound generator output pin I/O Chip select input/output pins. I/O Clock input/output pins. I/O Data input/output pins. I/O I/O Description Data input/output pins. 112 111 110 109 116 115 114 113 128 127 126 125 124 123 122 121 62 58 Input Inputs analog signals for the A/D converter. Input Inputs the external trigger signal to start A/D conversion. Rev.2.00 Oct. 16, 2007 Page 13 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation A/D converter AVCC1 AVCC0 Pin Number 117 119 I/O Input Description Analog power supply pins for the A/D converter and D/A converter. When neither the A/D converter nor the D/A converter is used, connect to the system power supply. Ground pin for the A/D converter and the D/A converter. Connect to the system power supply (0 V). Reference voltage input pin for the A/D converter and the D/A converter. When neither the A/D converter nor the D/A converter is used, connect to the system power supply. Analog signal output pins AVSS 120 Input Vref 118 Input D/A converter DA1 DA0 128 127 62 61 60 59 58 57 56 55 90 89 88 87 86 85 84 83 Output I/O port P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 I/O 8-bit input/output pins I/O 8-bit input/output pins Rev.2.00 Oct. 16, 2007 Page 14 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation I/O port P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 Pin Number 100 101 102 103 104 105 106 107 116 115 114 113 112 111 110 109 128 127 126 125 124 123 122 121 70 69 68 67 66 76 75 74 I/O 8-bit input/output pins Input 8-bit input pins Input 8-bit input pins I/O I/O Description 8-bit input/output pins Rev.2.00 Oct. 16, 2007 Page 15 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation I/O port PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Pin Number 82 81 80 79 78 65 64 63 14 13 12 11 10 9 8 7 24 23 22 21 20 19 18 17 34 33 32 31 28 27 26 25 I/O 8-bit input/output pins I/O 8-bit input/output pins I/O 8-bit input/output pins I/O Input I/O Description 1-bit input pin 7-bit input/output pins Rev.2.00 Oct. 16, 2007 Page 16 of 916 REJ09B0381-0200 Section 1 Overview Classification Abbreviation I/O port PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Pin Number 138 137 136 135 134 133 132 131 4 3 2 1 144 143 142 141 44 43 42 41 38 37 36 35 54 53 52 51 48 47 46 45 I/O 8-bit input/output pins I/O 8-bit input/output pins I/O 8-bit input/output pins I/O I/O Description 8-bit input/output pins Rev.2.00 Oct. 16, 2007 Page 17 of 916 REJ09B0381-0200 Section 1 Overview Rev.2.00 Oct. 16, 2007 Page 18 of 916 REJ09B0381-0200 Section 2 CPU Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upwardcompatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system. 2.1 Features • Upward-compatible with H8/300, H8/300H, and H8S CPUs ⎯ Can execute H8/300, H8/300H, and H8S/2000 object programs • Sixteen 16-bit general registers ⎯ Also usable as sixteen 8-bit registers or eight 32-bit registers • 87 basic instructions ⎯ 8/16/32-bit arithmetic and logic instructions ⎯ Multiply and divide instructions ⎯ Bit field transfer instructions ⎯ Powerful bit-manipulation instructions ⎯ Bit condition branch instructions ⎯ Multiply-and-accumulate instruction • Eleven addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@ERn] ⎯ Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)] ⎯ Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)] ⎯ Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @ERn+, @−ERn, or @ERn−] ⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ⎯ Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] ⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)] ⎯ Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)] ⎯ Memory indirect [@@aa:8] ⎯ Extended memory indirect [@@vec:7] Rev.2.00 Oct. 16, 2007 Page 19 of 916 REJ09B0381-0200 Section 2 CPU • Two base registers ⎯ Vector base register ⎯ Short address base register • 4-Gbyte address space ⎯ Program: 4 Gbytes ⎯ Data: 4 Gbytes • High-speed operation ⎯ All frequently-used instructions executed in one or two states ⎯ 8/16/32-bit register-register add/subtract: 1 state ⎯ 8 × 8-bit register-register multiply: ⎯ 16 ÷ 8-bit register-register divide: ⎯ 16 × 16-bit register-register multiply: ⎯ 32 ÷ 16-bit register-register divide: ⎯ 32 × 32-bit register-register multiply: ⎯ 32 ÷ 32-bit register-register divide: • Four CPU operating modes ⎯ Normal mode ⎯ Middle mode ⎯ Advanced mode ⎯ Maximum mode • Power-down modes ⎯ Transition is made by execution of SLEEP instruction ⎯ Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1544 Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1544 Group. 3. In the H8SX/1544 Group, an instruction is fetched in 32-bit mode. 1 state 10 states 1 state 18 states 5 states 18 states Rev.2.00 Oct. 16, 2007 Page 20 of 916 REJ09B0381-0200 Section 2 CPU 2.2 CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced, and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. Normal mode* Maximum 64 kbytes for program and data areas combined Maximum 16-Mbyte program area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Maximum 4 Gbytes for program and data areas combined Middle mode* CPU operating modes Advanced mode Maximum mode* Note: * Not supported in this LSI. Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Note: Normal mode is not supported in this LSI. • Address Space The maximum address space of 64 kbytes can be accessed. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) • Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev.2.00 Oct. 16, 2007 Page 21 of 916 REJ09B0381-0200 Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2. H'0000 H'0001 H'0002 H'0003 Reset exception vector Reset exception vector Exception vector table Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.3 Stack Structure (Normal Mode) Rev.2.00 Oct. 16, 2007 Page 22 of 916 REJ09B0381-0200 Section 2 CPU 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. Note: Middle mode is not supported in this LSI. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) • Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended. • Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. Rev.2.00 Oct. 16, 2007 Page 23 of 916 REJ09B0381-0200 Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Reserved Exception vector table Reset exception vector Reserved Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. Rev.2.00 Oct. 16, 2007 Page 24 of 916 REJ09B0381-0200 Section 2 CPU • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.5 Stack Structure (Middle and Advanced Modes) 2.2.4 Maximum Mode The program area is extended to 4 Gbytes as compared with that in advanced mode. Note: Maximum mode is not supported in this LSI. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6. Rev.2.00 Oct. 16, 2007 Page 25 of 916 REJ09B0381-0200 Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Exception vector table Reset exception vector Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The EXR contents are saved or restored regardless of whether or not EXR is in use. SP PC (32 bits) SP EXR CCR PC (32 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.7 Stack Structure (Maximum Mode) Rev.2.00 Oct. 16, 2007 Page 26 of 916 REJ09B0381-0200 Section 2 CPU 2.3 Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Note: In the H8SX/1544 Group, an instruction is fetched in 32-bit mode. 2.4 Address Space Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. Normal mode H'0000 H'000000 H'007FFF Program area Data area (64 kbytes) Middle mode H'00000000 Advanced mode H'00000000 Maximum mode H'FFFF Program area (16 Mbytes) Program area (16 Mbytes) Data area (64 kbytes) H'FF8000 H'FFFFFF H'00FFFFFF Program area Data area (4 Gbytes) Data area (4 Gbytes) H'FFFFFFFF H'FFFFFFFF Figure 2.8 Memory Map Rev.2.00 Oct. 16, 2007 Page 27 of 916 REJ09B0381-0200 Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). General Registers and Extended Registers 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers 31 PC 76543210 CCR I UI H U N Z V C 76543210 T — — — — I2 I1 I0 0 (Reserved) 31 SBR 63 MAC Legend: SP: PC: CCR: I: UI: H: U: N: 31 Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag User bit Negative flag Z: V: C: EXR: T: I2 to I0: VBR: SBR: MAC: Zero flag Overflow flag Carry flag Extended control register Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register Sign extension MACL 0 41 MACH 8 (Reserved) 32 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 0 EXR 31 VBR 12 Figure 2.9 CPU Registers Rev.2.00 Oct. 16, 2007 Page 28 of 916 REJ09B0381-0200 Section 2 CPU 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. • 16-bit registers • Address registers • 32-bit registers • 32-bit index registers General registers ER (ER0 to ER7) General registers E (E0 to E7) • 8-bit registers • 16-bit registers • 16-bit index registers General registers R (R0 to R7) General registers RH (R0H to R7H) • 8-bit registers • 8-bit index registers General registers RL (R0L to R7L) Figure 2.10 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. Rev.2.00 Oct. 16, 2007 Page 29 of 916 REJ09B0381-0200 Section 2 CPU Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0. 2.5.3 Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. Rev.2.00 Oct. 16, 2007 Page 30 of 916 REJ09B0381-0200 Section 2 CPU Bit 5 Bit Name H Initial Value R/W Description Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Undefined R/W 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit (regarded as sign bit) of data. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types: • • • Carry from the result of addition Borrow from the result of subtraction Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev.2.00 Oct. 16, 2007 Page 31 of 916 REJ09B0381-0200 Section 2 CPU 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see section 4, Exception Handling. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 ⎯ I2 I1 I0 All 1 1 1 1 R/W R/W R/W R/W Reserved These bits are always read as 1. Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7). 2.5.5 Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions. 2.5.6 Short Address Base Register (SBR) SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions. Rev.2.00 Oct. 16, 2007 Page 32 of 916 REJ09B0381-0200 Section 2 CPU 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 2.5.8 Initial Values of CPU Registers Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset. 2.6 2Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.6.1 General Register Data Formats Figure 2.12 shows the data formats in general registers. Rev.2.00 Oct. 16, 2007 Page 33 of 916 REJ09B0381-0200 Section 2 CPU 1-bit data RnH 7 0 76543210 Don’t care 7 0 76543210 1-bit data RnL Don’t care 7 Upper 43 0 Lower 4-bit BCD data RnH Don’t care 7 43 0 Lower 4-bit BCD data RnL Don’t care Upper 0 Byte data RnH 7 Don’t care MSB LSB 7 Don’t care MSB 15 0 LSB 0 LSB Byte data RnL Word data Rn Word data En Longword data ERn MSB 0 LSB 16 15 En Rn RnL: General register RL MSB: Most significant bit LSB: Least significant bit 15 MSB 31 MSB 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH Figure 2.12 General Register Data Formats Rev.2.00 Oct. 16, 2007 Page 34 of 916 REJ09B0381-0200 Section 2 CPU 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.13 Memory Data Formats Rev.2.00 Oct. 16, 2007 Page 35 of 916 REJ09B0381-0200 Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Function Data transfer Instruction Classification Instructions MOV MOVFPE* , MOVTPE* POP, PUSH* LDM, STM MOVA 1 6 6 Size B/W/L B W/L L B/W* B B/W/L B B/W/L B L B/W W/L L W/L B ⎯ ⎯ ⎯ B/W/L B/W/L B B B 2 Types 6 Block transfer EEPMOV MOVMD MOVSD 3 Arithmetic operations ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC DAA, DAS ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS MULU, DIVU, MULS, DIVS MULU/U, MULS/U EXTU, EXTS TAS MAC LDMAC, STMAC CLRMAC 27 Logic operations Shift Bit manipulation AND, OR, XOR, NOT SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ BFLD, BFST 4 8 20 Rev.2.00 Oct. 16, 2007 Page 36 of 916 REJ09B0381-0200 Section 2 CPU Function Branch Instructions BRA/BS, BRA/BC, BSR/BS, BSR/BC Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S 5 Size B* ⎯ L* ⎯ ⎯ L* 5 5 3 Types 9 System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC 10 B/W/L Total 87 Legend: B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @−SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @−SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Not available in this LSI. Rev.2.00 Oct. 16, 2007 Page 37 of 916 REJ09B0381-0200 Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) SD SD @−ERn/ @ERn+/ @ERn−/ @+ERn SD S/D S/D*1 S/D*2 S/D*2 S S S S S SD*3 SD*3 SD*3 S D S D D D S SD S S S D SD SD D D S SD S S S S D D D SD SD SD SD* 5 Classification Instruction Size B/W/L B #xx S Rn SD S/D S/D S/D S/D S @ERn SD @aa:8 @aa:16/ @aa:32 SD ⎯ Data transfer MOV MOVFPE, 12 MOVTPE* POP, PUSH LDM, STM MOVA* Block transfer 4 B W/L L B/W B B/W/L B B B B B W/L EEPMOV MOVMD MOVSD Arithmetic operations ADD, CMP D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S D D S SD SD SUB B B B B W/L D D S D D S SD SD SD ADDX, SUBX B/W/L B/W/L B/W/L INC, DEC ADDS, SUBS DAA, DAS B/W/L L B Rev.2.00 Oct. 16, 2007 Page 38 of 916 REJ09B0381-0200 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) @−ERn/ @ERn+/ @ERn−/ @+ERn Classification Arithmetic operations Instruction MULXU, DIVXU MULU, DIVU MULXS, DIVXS MULS, DIVS NEG Size B/W W/L B/W W/L B W/L #xx S:4 S:4 S:4 S:4 Rn SD SD SD SD D D D @ERn @aa:8 @aa:16/ @aa:32 ⎯ D D D D D D D D D D D D D D D D D EXTU, EXTS TAS MAC CLRMAC LDMAC STMAC Logic operations AND, OR, XOR W/L B ⎯ ⎯ ⎯ ⎯ B B B W/L S O S D S D D S SD SD D D D 6 D S SD SD D D D D D S SD SD D D D D D S SD SD D D D D D S D S SD SD SD D D D D NOT B W/L D D D Shift SHLL, SHLR B B/W/L* D D D D D D D D B/W/L*7 SHAL, SHAR B ROTL, ROTR W/L ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc B D D D D D D D D D D D D D D B BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ D D D D Rev.2.00 Oct. 16, 2007 Page 39 of 916 REJ09B0381-0200 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) @−ERn/ @ERn+/ @ERn−/ @+ERn Classification Bit manipulation Branch Instruction BFLD BFST BRA/BS, BRA/BC*8 BSR/BS, BSR/BC*8 Size B B B B B/W*9 L B/W*9 L B ⎯ ⎯ #xx Rn D S @ERn S D S S @aa:8 S D S S @aa:16/ @aa:32 S D S S S ⎯ System control LDC (CCR, EXR) LDC (VBR, SBR) STC (CCR, EXR) STC (VBR, SBR) ANDC, ORC, XORC SLEEP NOP S S S D D S S S*10 D D D*11 D S O O Legend: d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a source or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn+ as a source operand and @−ERn as a destination operand 3. Specified by ER5 as a source address and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn− is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or register direct, otherwise, word 10. Only @ERn+ is available 11. Only @−ERn is available 12. Not available in this LSI. Rev.2.00 Oct. 16, 2007 Page 40 of 916 REJ09B0381-0200 Section 2 CPU Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode @(RnL. B/Rn.W/ Classification Instruction Size @ERn ERn.L, @(d,PC) PC) @aa:24 @ aa:32 @@ aa:8 @@vec:7 ⎯ Branch BRA/BS, BRA/BC BSR/BS, BSR/BC Bcc BRA BRA/S JMP BSR JSR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O O O O O O O* O O O O O O O O O O O O O RTS, RTS/L ⎯ System control TRAPA ⎯ RTE, RTE/L ⎯ Legend: d: d:8 or d:16 Note: * Only @(d:8, PC) is available. Rev.2.00 Oct. 16, 2007 Page 41 of 916 REJ09B0381-0200 Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register Vector base register Short address base register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) 8-, 16-, 24-, or 32-bit length Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR VBR SBR N Z V C PC SP #IMM disp + − × ÷ ∧ ∨ ⊕ → ∼ :8/:16/:24/:32 Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.2.00 Oct. 16, 2007 Page 42 of 916 REJ09B0381-0200 Section 2 CPU Table 2.4 Instruction MOV MOVFPE* MOVTPE* POP PUSH LDM Data Transfer Instructions Size B/W/L B B W/L W/L L Function #IMM → (EAd), (EAs) → (EAd) Transfers data between immediate data, general registers, and memory. (EAs) → Rd Rs → (EAs) @SP+ → Rn Restores the data from the stack to a general register. Rn → @−SP Saves general register contents on the stack. @SP+ → Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) → @−SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA → Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register. Note: * Not available in this LSI. Rev.2.00 Oct. 16, 2007 Page 43 of 916 REJ09B0381-0200 Section 2 CPU Table 2.5 Instruction EEPMOV.B EEPMOV.W Block Transfer Instructions Size B Function Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.B MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address. Rev.2.00 Oct. 16, 2007 Page 44 of 916 REJ09B0381-0200 Section 2 CPU Table 2.6 Instruction ADD SUB Arithmetic Operation Instructions Size B/W/L Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. (EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits). Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 16 bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits). ADDX SUBX B/W/L INC DEC ADDS SUBS DAA DAS MULXU B/W/L L B B/W MULU W/L MULU/U L MULXS B/W MULS W/L MULS/U L Rev.2.00 Oct. 16, 2007 Page 45 of 916 REJ09B0381-0200 Section 2 CPU Instruction DIVXU Size B/W Function Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. (EAd) − #IMM, (EAd) − (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. 0 − (EAd) → (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. (EAd) (zero extension) → (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. (EAd) (sign extension) → (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. @ERd − 0, 1 → ( of @EAd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to MAC. 0 → MAC Clears MAC to zero. DIVU W/L DIVXS B/W DIVS W/L CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS MAC B ⎯ CLRMAC ⎯ Rev.2.00 Oct. 16, 2007 Page 46 of 916 REJ09B0381-0200 Section 2 CPU Instruction LDMAC STMAC Size ⎯ ⎯ Function Rs → MAC Loads data from a general register to MAC. MAC → Rd Stores data from MAC to a general register. Table 2.7 Instruction AND Logic Operation Instructions Size B/W/L Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L ∼ (EAd) → (EAd) Takes the one's complement of the contents of a general register or a memory location. Rev.2.00 Oct. 16, 2007 Page 47 of 916 REJ09B0381-0200 Section 2 CPU Table 2.8 Instruction SHLL SHLR Shift Operation Instructions Size B/W/L Function (EAd) (shift) → (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL SHAR B/W/L (EAd) (shift) → (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL ROTR ROTXL ROTXR B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. Rev.2.00 Oct. 16, 2007 Page 48 of 916 REJ09B0381-0200 Section 2 CPU Table 2.9 Instruction BSET Bit Manipulation Instructions Size B Function 1 → ( of ) Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. if cc, 1 → ( of ) If the specified condition is satisfied, this instruction sets a specified bit in a memory location to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. 0 → ( of ) Clears a specified bit in the contents of a general register or a memory location to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. if cc, 0 → ( of ) If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. ∼ ( of ) → ( of ) Inverts a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ∼ ( of ) → Z Tests a specified bit in the contents of a general register or a memory location and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∧ [∼ ( of )] → C ANDs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BSET/cc B BCLR B BCLR/cc B BNOT B BTST B BAND B BIAND B BOR B Rev.2.00 Oct. 16, 2007 Page 49 of 916 REJ09B0381-0200 Section 2 CPU Instruction BIOR Size B Function C ∨ [~ ( of )] → C ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ⊕ [~ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. ~ ( of ) → C Transfers the inverse of a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. C → ( of ) Transfers the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. Z → ( of ) Transfers the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. ∼ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. BXOR B BIXOR B BLD B BILD B BST B BSTZ B BIST B Rev.2.00 Oct. 16, 2007 Page 50 of 916 REJ09B0381-0200 Section 2 CPU Instruction BISTZ Size B Function ∼ Z → ( of ) Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BFLD B (EAs) (bit field) → Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs → (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction BRA/BS BRA/BC BSR/BS BSR/BC Bcc BRA/S ⎯ ⎯ B Size B Function Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Branches to a specified address if the specified condition is satisfied. Branches unconditionally to a specified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Returns from a subroutine, restoring data from the stack to multiple general registers. JMP BSR JSR RTS RTS/L ⎯ ⎯ ⎯ ⎯ ⎯ Rev.2.00 Oct. 16, 2007 Page 51 of 916 REJ09B0381-0200 Section 2 CPU Table 2.11 System Control Instructions Instruction TRAPA RTE RTE/L SLEEP LDC Size ⎯ ⎯ ⎯ ⎯ B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Returns from an exception-handling routine, restoring data from the stack to multiple general registers. Causes a transition to a power-down state. #IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L STC B/W Rs → VBR, Rs → SBR Transfers the general register contents to VBR or SBR. CCR → (EAd), EXR → (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L ANDC ORC XORC NOP B B B ⎯ VBR → Rd, SBR → Rd Transfers the contents of VBR or SBR to a general register. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. Rev.2.00 Oct. 16, 2007 Page 52 of 916 REJ09B0381-0200 Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.14 Instruction Formats • Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. • Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. • Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. • Condition Field Specifies the branch condition of Bcc instructions. Rev.2.00 Oct. 16, 2007 Page 53 of 916 REJ09B0381-0200 Section 2 CPU 2.8 Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode 1 2 3 4 5 Register direct Register indirect Register indirect with displacement Index register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Register indirect with pre-increment Register indirect with post-decrement 6 7 8 9 10 11 Absolute address Immediate Program-counter relative Program-counter relative with index register Memory indirect Extended memory indirect Symbol Rn @ERn @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L) @ERn+ @−ERn @+ERn @ERn− @aa:8/@aa:16/@aa:24/@aa:32 #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC) @@aa:8 @@vec:7 Rev.2.00 Oct. 16, 2007 Page 54 of 916 REJ09B0381-0200 Section 2 CPU 2.8.1 Register Direct⎯Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.8.2 Register Indirect⎯@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.8.3 Register Indirect with Displacement⎯@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. Rev.2.00 Oct. 16, 2007 Page 55 of 916 REJ09B0381-0200 Section 2 CPU 2.8.4 Index Register Indirect with Displacement⎯@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively. 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement⎯@ERn+, @−ERn, @+ERn, or @ERn− (1) Register indirect with post-increment⎯@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. (2) Register indirect with pre-decrement⎯@−ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. (3) Register indirect with pre-increment⎯@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. Rev.2.00 Oct. 16, 2007 Page 56 of 916 REJ09B0381-0200 Section 2 CPU (4) Register indirect with post-decrement⎯@ERn− The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. If the contents of a general register which is also used as an address register is written to memory using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0+ When the value of ER0 before execution is H'12345678, H'567A is written to the address H'12345678. Example 2: MOV.B @ER0+, @ER0+ When the value of ER0 before execution is H'00001000, the address H'00001000 is read and the contents are written to the address H'00001001. The value of ER0 after execution is H'00001002. Rev.2.00 Oct. 16, 2007 Page 57 of 916 REJ09B0381-0200 Section 2 CPU 2.8.6 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Data area 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program area 24 bits (@aa:24) 32 bits (@aa:32) Normal Mode Middle Mode Advanced Mode Maximum Mode A consecutive 256-byte area (the upper address is set in SBR) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF H'00000000 to H'FFFFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF Rev.2.00 Oct. 16, 2007 Page 58 of 916 REJ09B0381-0200 Section 2 CPU 2.8.7 Immediate⎯#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. 2.8.8 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register⎯ @(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added are the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). Rev.2.00 Oct. 16, 2007 Page 59 of 916 REJ09B0381-0200 Section 2 CPU 2.8.10 Memory Indirect⎯@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the content of a memory location pointed to by an 8-bit absolute address in the instruction codes. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.15 Branch Address Specification in Memory Indirect Mode Rev.2.00 Oct. 16, 2007 Page 60 of 916 REJ09B0381-0200 Section 2 CPU 2.8.11 Extended Memory Indirect⎯@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). 2.8.12 Effective Address Calculation Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows: • The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. • The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. Rev.2.00 Oct. 16, 2007 Page 61 of 916 REJ09B0381-0200 Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. 1 Addressing Mode and Instruction Format Immediate op 2 Register direct op 3 Register indirect op 4 r 31 31 General register contents 15 disp Sign extension 0 31 0 + 0 rm rn 31 General register contents 0 31 0 IMM Effective Address Calculation Effective Address (EA) Register indirect with 16-bit displacement op r disp Register indirect with 32-bit displacement op r disp 31 General register contents 0 + disp 31 0 5 Index register indirect with 16-bit displacement 31 Zero extension Contents of general register (RL, R, or ER) 31 15 Sign extension 31 Zero extension Contents of general register (RL, R, or ER) 31 disp 0 1, 2, or 4 × 0 disp 0 1, 2, or 4 × 0 + + 31 0 op r disp Index register indirect with 32-bit displacement 31 0 op r disp 6 Register indirect with post-increment or post-decrement op r 31 General register contents 0 ± 31 0 Register indirect with pre-increment or pre-decrement op r 31 General register contents 1, 2, or 4 0 ± 1, 2, or 4 31 0 7 8-bit absolute address 31 op aa SBR 7 aa 0 31 0 16-bit absolute address op aa 31 Sign extension 15 aa 0 31 0 32-bit absolute address op aa 31 aa 0 31 0 Rev.2.00 Oct. 16, 2007 Page 62 of 916 REJ09B0381-0200 Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions No. 1 Addressing Mode and Instruction Format Register indirect op 2 r Effective Address Calculation 31 General register contents 0 Effective Address (EA) 31 0 Program-counter relative with 8-bit displacement 31 PC contents 31 op disp Sign extension 7 disp 0 + 0 31 0 Program-counter relative with 16-bit displacement 31 op disp 31 PC contents 15 Sign extension 0 31 0 disp + 0 3 Program-counter relative with index register 31 op r 0 Zero extension Contents of general register (RL, R, or ER) × 2 + 0 31 PC contents Zero 31extension23 31 0 4 24-bit absolute address op aa 0 aa 31 0 32-bit absolute address op aa 31 aa 0 31 0 5 Memory indirect 31 op aa 31 Memory contents Zero extension 7 aa 0 31 0 0 6 Extended memory indirect 31 op vec Zero extension 7 1 0 vec 2 or 4 × 0 0 Memory contents 31 0 31 31 2.8.13 MOVA Instruction The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual. Rev.2.00 Oct. 16, 2007 Page 63 of 916 REJ09B0381-0200 Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 4, Exception Handling. • Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, refer to section 4, Exception Handling. • Program execution state In this state the CPU executes program instructions in sequence. • Bus-released state In this state, the bus has been released in response to a bus request from the DMA controller (DMAC). While the bus is released, the CPU halts operations. • Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For details, refer to section 24, Power-Down Modes. Rev.2.00 Oct. 16, 2007 Page 64 of 916 REJ09B0381-0200 Section 2 CPU Reset state* RES = high RES = low Bus-released state Exception-handling state Request for exception handling Interrupt Bus request request End of exception handling End of bus request Bus request End of bus request Program execution state Note: * Program stop state SLEEP instruction A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Figure 2.16 State Transitions Rev.2.00 Oct. 16, 2007 Page 65 of 916 REJ09B0381-0200 Section 2 CPU Rev.2.00 Oct. 16, 2007 Page 66 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has five operating modes (modes 2, 4, 5, 6, and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Table 3.1 lists MCU operating mode settings. Table 3.1 MCU Operating Mode Settings CPU Operating Mode Advanced Address Space LSI Initiation Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode On-Chip ROM Enabled Disabled Disabled Enabled External Data Bus Width Default Max. 8 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits MCU Operating Mode MD2 2 4 5 6 0 1 1 1 MD1 1 0 0 1 MD0 0 0 1 0 16 Mbytes Boot mode 7 1 1 1 Enabled 8 bits 16 bits In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are available. The initial external bus widths are eight or 16 bits. As the LSI initiation mode, the external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be selected. Mode 2 is the boot mode in which the flash memory can be programmed and erased. For details on the boot mode, see section 22, Flash Memory. Mode 7 is a single-chip mode. In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables to use the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. Modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address space for each area by the bus controller after starting program execution. Rev.2.00 Oct. 16, 2007 Page 67 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read from, the states of signals MD2 to MD0 are latched. This latch is canceled by a reset. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 0 R 7 ⎯ 0 R 14 ⎯ 1 R 6 ⎯ 1 R 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 1 R 4 ⎯ 1 R 11 MDS3 Undefined* R 3 ⎯ Undefined* R 10 MDS2 Undefined* R 2 ⎯ Undefined* R 9 MDS1 Undefined* R 1 ⎯ Undefined* R 8 MDS0 Undefined* R 0 ⎯ Undefined* R Note: * Determined by pins MD2 to MD0. Bit 15 14 13 12 11 10 9 8 Bit Name ⎯ ⎯ ⎯ ⎯ MDS3 MDS2 MDS1 MDS0 Initial Value R/W 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R Descriptions Reserved These are read-only bits and cannot be modified. Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD2 to MD0) (see table 3.2). When MDCR is read, the signal levels input on pins MD2 to MD0 are latched into these bits. These latches are released by a reset. Rev.2.00 Oct. 16, 2007 Page 68 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Bit 7 6 5 4 3 2 1 0 Note: * Bit Name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial Value R/W 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R Descriptions Reserved These are read-only bits and cannot be modified. Determined by pins MD2 to MD0. Table 3.2 Settings of Bits MDS3 to MDS0 Mode Pins MD2 0 1 1 1 1 MD1 1 0 0 1 1 MD0 0 0 1 0 1 MDS3 1 0 0 0 0 MDS2 1 0 0 1 1 MDCR MDS1 0 1 0 0 0 MDS0 0 0 1 1 0 MCU Operating Mode 2 4 5 6 7 Rev.2.00 Oct. 16, 2007 Page 69 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, and enables or disables the on-chip RAM. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 1 R/W 7 ⎯ 0 R/W 14 ⎯ 1 R/W 6 ⎯ 0 R/W 13 MACS 0 R/W 5 ⎯ 0 R/W 12 ⎯ 1 R/W 4 ⎯ 0 R/W 11 FETCHMD 0 R/W 3 ⎯ 0 R/W 10 ⎯ 0 R/W 2 ⎯ 0 R/W 9 EXPE Undefined* R/W 1 ⎯ 1 R/W 8 RAME 1 R/W 0 ⎯ 1 R/W Note: * The initial value depends on the startup mode. Bit 15, 14 Bit Name ⎯ Initial Value All 1 R/W R/W Descriptions Reserved These bits are always read as 1. The write value should always be 1. 13 MACS 0 R/W MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12 ⎯ 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 11 FETCHMD 0 R/W Instruction Fetch Mode Select This LSI can prefetch an instruction in units of 16 bits or 32 bits. Select the bus width for instruction fetch depending on the used memory for the storage of 1 programs* . 0: 32-bit mode 1: 16-bit mode Rev.2.00 Oct. 16, 2007 Page 70 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Bit 10 Bit Name ⎯ Initial Value 0 R/W R/W Descriptions Reserved This bit is always read as 0. The write value should always be 0. 9 EXPE Undefined* 2 R/W External Bus Mode Enable Selects external bus mode. In external extended mode, this bit is fixed 1 and cannot be changed. In single-chip mode, the initial value of this bit is 0, and can be read from or written to. When writing 0 to this bit after reading EXPE = 1, an external bus cycle should not be executed. The external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer function. 0: External bus disabled 1: External bus enabled 8 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled 7 to 2 ⎯ All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1, 0 ⎯ All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. The initial value depends on the LSI initiation mode. Rev.2.00 Oct. 16, 2007 Page 71 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 2 This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 22, Flash Memory. 3.3.2 Mode 4 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of port A function as bus control signals. However, if any area is designated as an 8-bit access space by the bus controller, the bus mode switches to eight bits, and only port H functions as a data bus. 3.3.3 Mode 5 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of port A function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. Rev.2.00 Oct. 16, 2007 Page 72 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.3.4 Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the data direction register (DDR) for each port. For details, see section 8, I/O Ports. Port H functions as a data bus, and parts of port A function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. 3.3.5 Mode 7 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. For details, see section 8, I/O Ports. Rev.2.00 Oct. 16, 2007 Page 73 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) Port A MCU Operating Mode PA7 PA6 to PA2 to PA3 PA0 Port D Port E Port F PF3 to PF7 to PF0 PF4 Port H Port I 2 4 5 6 7 Boot mode ROM disabled extended ROM disabled extended ROM enabled extended Single chip mode P*/C C C C P*/C P*/C C C C P*/C P P P P P P*/A A A P*/A P*/A P*/A A A P*/A P*/A P*/A A A P*/A P*/A P*/A A A P*/A P*/A P*/D D D D P*/D P*/D P/D* P*/D P*/D P*/D Legend: P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Rev.2.00 Oct. 16, 2007 Page 74 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes 3.4 3.4.1 Address Map Address Map Figures 3.1 and 3.2 are the address maps of the H8SX/1544. Mode 2 Boot mode (Advanced mode) H'000000 H'000000 Mode 4*5 On-chip ROM disabled extended mode (Advanced mode) On-chip ROM (FLASH) 512 kbytes External address space H'080000 External address space/ reserved area*1*3 H'FD9000 H'FD9000 Reserved area*3 H'FDC000 H'FDC000 Reserved area*3 External address space/ reserved area*1*3 H'FF6000 H'FF6000 External address space On-chip RAM 24 kbytes/ On-chip RAM*2 24 kbytes H'FFC000 H'FFC000 external address space*4 External address space/ reserved area*1*3 H'FFEA00 H'FFEA00 External address space On-chip I/O registers H'FFFF00 H'FFFF20 On-chip I/O registers H'FFFF00 External address space/ reserved area*1*3 On-chip I/O registers External address space H'FFFF20 On-chip I/O registers H'FFFFFF H'FFFFFF Notes: 1. 2. 3. 4. 5. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Initial external bus width: 16 bits, Maximum external bus width: 16 bits Figure 3.1 H8SX/1544 Address Map (1) Rev.2.00 Oct. 16, 2007 Page 75 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Mode 5*5 On-chip ROM disabled extended mode (Advanced mode) H'000000 H'000000 Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 Mode 7 Shingle-chip mode (Advanced mode) On-chip ROM (FLASH) 512 kbytes On-chip ROM (FLASH) 512 kbytes External address space H'080000 H'080000 External address space H'FD9000 H'FD9000 H'FD9000 External address space/ reserved area*1*3 Reserved area*3 H'FDC000 H'FDC000 Reserved area*3 H'FDC000 Reserved area*3 External address space H'FF6000 H'FF6000 External address space H'FF6000 External address space/ reserved area*1*3 On-chip RAM 24 kbytes/ On-chip RAM 24 kbytes/ On-chip RAM 24 kbytes/ external address space*4 H'FFC000 H'FFC000 external address space*4 H'FFC000 external address space*4 External address space H'FFEA00 H'FFEA00 External address space H'FFEA00 External address space/ reserved area*1*3 On-chip I/O registers H'FFFF00 On-chip I/O registers H'FFFF00 H'FFFF20 On-chip I/O registers H'FFFF00 H'FFFF20 External address space H'FFFF20 External address space On-chip I/O registers External address space/ reserved area*1*3 On-chip I/O registers On-chip I/O registers H'FFFFFF H'FFFFFF H'FFFFFF Notes: 1. 2. 3. 4. 5. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Initial external bus width: 8 bits, Maximum external bus width: 16 bits Figure 3.2 H8SX/1544 Address Map (2) Rev.2.00 Oct. 16, 2007 Page 76 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Figures 3.3 and 3.4 are the address maps of the H8SX/1543. Mode 2 Boot mode (Advanced mode) H'000000 H'000000 Mode 4*5 On-chip ROM disabled extended mode (Advanced mode) On-chip ROM (FLASH) 384 kbytes External address space H'060000 External address space/ reserved area*1*3 H'FD9000 H'FD9000 Reserved area*3 H'FDC000 H'FDC000 Reserved area*3 External address space/ reserved area*1*3 H'FF8000 H'FF8000 External address space On-chip RAM 16 kbytes/ On-chip RAM*2 16 kbytes H'FFC000 H'FFC000 external address space*4 External address space/ reserved area*1*3 H'FFEA00 H'FFEA00 External address space On-chip I/O registers H'FFFF00 H'FFFF20 On-chip I/O registers H'FFFF00 External address space/ reserved area*1*3 On-chip I/O registers External address space H'FFFF20 On-chip I/O registers H'FFFFFF H'FFFFFF Notes: 1. 2. 3. 4. 5. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Initial external bus width: 16 bits, Maximum external bus width: 16 bits Figure 3.3 H8SX/1543 Address Map (1) Rev.2.00 Oct. 16, 2007 Page 77 of 916 REJ09B0381-0200 Section 3 MCU Operating Modes Mode 5*5 On-chip ROM disabled extended mode (Advanced mode) H'000000 H'000000 Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 Mode 7 Shingle-chip mode (Advanced mode) On-chip ROM (FLASH) 384 kbytes On-chip ROM (FLASH) 384 kbytes External address space H'060000 H'060000 External address space H'FD9000 H'FD9000 H'FD9000 External address space/ reserved area*1*3 Reserved area*3 H'FDC000 H'FDC000 Reserved area*3 H'FDC000 Reserved area*3 External address space H'FF8000 H'FF8000 External address space H'FF8000 External address space/ reserved area*1*3 On-chip RAM 16 kbytes/ On-chip RAM 16 kbytes/ On-chip RAM 16 kbytes/ external address space*4 H'FFC000 H'FFC000 external address space*4 H'FFC000 external address space*4 External address space H'FFEA00 H'FFEA00 External address space H'FFEA00 External address space/ reserved area*1*3 On-chip I/O registers H'FFFF00 On-chip I/O registers H'FFFF00 H'FFFF20 On-chip I/O registers H'FFFF00 H'FFFF20 External address space H'FFFF20 External address space On-chip I/O registers External address space/ reserved area*1*3 On-chip I/O registers On-chip I/O registers H'FFFFFF H'FFFFFF H'FFFFFF Notes: 1. 2. 3. 4. 5. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Initial external bus width: 8 bits, Maximum external bus width: 16 bits Figure 3.4 H8SX/1543 Address Map (2) Rev.2.00 Oct. 16, 2007 Page 78 of 916 REJ09B0381-0200 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Exception Handling Start Timing Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Exception handling starts when an undefined code is executed. Exception handling starts after execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. After an address error has occurred, exception handling starts on completion of instruction execution. Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has 2 occurred.* 3 Illegal instruction Trace* 1 Address error Interrupt Trap instruction* Low Exception handling starts by execution of a trap instruction (TRAPA). Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev.2.00 Oct. 16, 2007 Page 79 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 4.2 shows the correspondence between the exception sources and vector table address offsets. Table 4.3 shows the calculation method of exception handling vector table addresses. Table 4.2 Exception Handling Vector Table Vector Table Address Offset* Exception Source Reset Reserved for system use Vector Number 0 1 2 3 Illegal instruction Trace Reserved for system use Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) CPU address error DMA address error* 3 1 Normal Mode* 2 Advanced, Middle* , 2 Maximum* Modes H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B ⏐ H'005C to H'005F H'0060 to H'0063 ⏐ H'00FC to H'00FF 2 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D ⏐ H'002E to H'002F H'0030 to H'0031 ⏐ H'007E to H'007F 4 5 6 7 8 9 10 11 12 13 14 ⏐ 23 24 ⏐ 63 Reserved for system use User area (not used) Rev.2.00 Oct. 16, 2007 Page 80 of 916 REJ09B0381-0200 Section 4 Exception Handling Vector Table Address Offset* Exception Source External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt* 4 1 Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ⎜ 255 Normal Mode* 2 Advanced, Middle* , 2 Maximum* Modes H'0100 to H'0103 H'0104 to H'0107 H'0108 to H'010B H'010C to H'010F H'0110 to H'0113 H'0114 to H'0117 H'0118 to H'011B H'011C to H'011F H'0120 to H'0123 H'0124 to H'0127 H'0128 to H'012B H'012C to H'012F H'0130 to H'0133 H'0134 to H'0137 H'0138 to H'013B H'013C to H'013F H'0140 to H'0143 ⎜ H'03FC to H'03FF 2 H'0080 to H'0081 H'0082 to H'0083 H'0084 to H'0085 H'0086 to H'0087 H'0088 to H'0089 H'008A to H'008B H'008C to H'008D H'008E to H'008F H'0090 to H'0091 H'0092 to H'0093 H'0094 to H'0095 H'0096 to H'0097 H'0098 to H'0099 H'009A to H'009B H'009C to H'009D H'009E to H'009F H'00A0 to H'00A1 ⎜ H'01FE to H'01FF Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. A DMA address error is generated by the DMAC. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. Table 4.3 Calculation Method of Exception Handling Vector Table Address Calculation Method of Vector Table Address Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset) Exception Source Reset, CPU address error Other than above Legend: VBR: Vector base register Note: Vector table address offset: See table 4.2. Rev.2.00 Oct. 16, 2007 Page 81 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms with the STBY pin driven high when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by overflow of the watchdog timer. For details, see section 10, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev.2.00 Oct. 16, 2007 Page 82 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA is initialized to H'0FFF, MSTPCRB is initialized to H'FFFF, and MSTPCRC is initialized to H'FF00, and all modules except the DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is canceled. First instruction prefetch Vector fetch Internal operation Iφ RES Internal address bus (1) (3) Internal read signal Internal write signal Internal data bus (2) High (4) (1): Reset exception handling vector address (when reset, (1) = H'000000) (2): Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First instruction in the exception handling routine Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode) Rev.2.00 Oct. 16, 2007 Page 83 of 916 REJ09B0381-0200 Section 4 Exception Handling Vector fetch Internal First instruction operation prefetch * Bφ * * RES Address bus (1) (3) (5) RD LHWR, LLWR High D15 to D0 (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) (6) First instruction in the exception handling routine Note: * Seven program wait cycles are inserted. Figure 4.2 Reset Sequence (16-Bit External Access in On-Chip ROM Disabled Advanced Mode) Rev.2.00 Oct. 16, 2007 Page 84 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 I UI ⎯ I2 to I0 ⎯ EXR T Trace exception handling cannot be used. 1 0 Legend: 1: Set to 1 0: Cleared to 0 ⎯: Retains the previous value. Rev.2.00 Oct. 16, 2007 Page 85 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.5 4.5.1 Address Error Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Instruction fetch Bus Master Description CPU Fetches instructions from even addresses Fetches instructions from odd addresses Fetches instructions from areas other than on-chip 1 peripheral module space* Fetches instructions from on-chip peripheral module 1 space* Fetches instructions from external memory space in single-chip mode 2 Fetches instructions from access prohibited area* Accesses stack when the stack pointer value is even address Accesses stack when the stack pointer value is odd Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode 2 Accesses to access prohibited area* Data read/write DMAC Accesses word data from even addresses Accesses word data from odd addresses Address Error No (normal) Occurs No (normal) Occurs Occurs Occurs No (normal) Occurs No (normal) No (normal) Occurs Occurs No (normal) No (normal) Stack operation Data read/write CPU CPU Single address transfer DMAC Accesses external memory space in single-chip Occurs mode 2 Accesses to access prohibited area* Occurs Address access space is the external memory space No (normal) for single address transfer Address access space is not the external memory space for single address transfer Occurs Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC). 2. For the access-prohibited area, refer to figure 3.1, Address Map (Advanced Mode) in section 3.4, Address Map. Rev.2.00 Oct. 16, 2007 Page 86 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DMAC. • The ERRF bit of DMDR_0 in the DMAC is set to 1. • The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate transfer. Table 4.6 shows the state of CCR and EXR after execution of the address error exception handling. Table 4.6 Status of CCR and EXR after Address Error Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI ⎯ ⎯ T ⎯ 0 EXR I2 to I0 ⎯ 7 Legend: 1: Set to 1 0: Cleared to 0 ⎯: Retains the previous value. Rev.2.00 Oct. 16, 2007 Page 87 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.6 4.6.1 Interrupts Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Type NMI IRQ0 to IRQ15 On-chip peripheral module Interrupt Sources Source NMI pin (external input) Pins IRQ0 to IRQ15 (external input) DMA controller (DMAC) Watchdog timer (WDT) A/D converter 16-bit timer pulse unit (TPU) Serial communications interface (SCI) I2C bus interface 2 (IIC2) Synchronous serial communication unit (SSU) Motor control PWM timer Controller area network (RCAN-ET) 16-bit PWM timer Sound generator (SDG) Watch timer (WAT) Number of Sources 1 16 8 1 1 26 12 2 2 2 4 3 4 2 Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 5.2, Interrupt Sources, Vector Address Offsets, and Interrupt Priority in section 5, Interrupt Controller. 4.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. Rev.2.00 Oct. 16, 2007 Page 88 of 916 REJ09B0381-0200 Section 4 Exception Handling The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. 4.7 Instruction Exception Handling There are two instructions that cause exception handling: trap instruction and illegal instruction. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI ⎯ ⎯ T ⎯ 0 EXR I2 to I0 ⎯ ⎯ Legend: 1: Set to 1 0: Cleared to 0 ⎯: Retains the previous value. Rev.2.00 Oct. 16, 2007 Page 89 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.7.2 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the PC contents) at a delay slot (immediately after a delayed branch instruction) is executed. The exception handling by the general illegal instruction and slot illegal instruction is always executable in the program execution state. The exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 4.9 shows the state of CCR and EXR after execution of illegal instruction exception handling. Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI ⎯ ⎯ T ⎯ 0 EXR I2 to I0 ⎯ ⎯ Legend: 1: Set to 1 0: Cleared to 0 ⎯: Retains the previous value. Rev.2.00 Oct. 16, 2007 Page 90 of 916 REJ09B0381-0200 Section 4 Exception Handling 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of exception handling. Advanced mode SP EXR Reserved* SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Note: * Ignored on return. Interrupt control mode 2 Figure 4.3 Stack Status after Exception Handling 4.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: • PUSH.W Rn (or MOV.W Rn, @-SP) • PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: • POP.W • POP.L Rn (or MOV.W @SP+, Rn) ERn (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.4 shows an example of operation when the SP value is odd. Rev.2.00 Oct. 16, 2007 Page 91 of 916 REJ09B0381-0200 Section 4 Exception Handling Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP (Address error occurred) Legend: CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev.2.00 Oct. 16, 2007 Page 92 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following five interrupt requests are given priority of 8, therefore they are accepted at all times. ⎯ NMI ⎯ Illegal instructions ⎯ Trace ⎯ Trap instructions ⎯ CPU address error ⎯ DMA address error (occurred in the DMAC) • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Seventeen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ15 to IRQ0. • DMAC control DMAC can be activated by means of interrupts. • CPU priority control function The priority levels can be assigned to the CPU and DMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DMAC transfer. Rev.2.00 Oct. 16, 2007 Page 93 of 916 REJ09B0381-0200 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG IPR I I2 to I0 CPU CCR EXR NMI input IRQ input NMI input unit IRQ input unit ISR Priority determination CPU interrupt request CPU vector DMAC DMAC activation permission DMAC priority control DMDR ISCR IER SSIER Internal interrupt sources WOVI to WCMI Source selector CPUPCR Interrupt controller Legend: INTCR: Interrupt control register CPUPCR: CPU priority control register IRQ sense control register ISCR: IRQ enable register IER: ISR: SSIER: IPR: IRQ status register Software standby release IRQ enable register Interrupt priority register Figure 5.1 Block Diagram of Interrupt Controller Rev.2.00 Oct. 16, 2007 Page 94 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Name NMI IRQ15 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable External Interrupt Rising or falling edge can be selected. Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • CPU priority control register (CPUPCR) • Interrupt priority registers A to G, I, K, L, O, Q, and R (IPRA to IPRG, IPRI, IPRK, IPRL, IPRO, IPRQ, and IPRR) • IRQ enable register (IER) • IRQ sense control registers H and L (ISCRH, ISCRL) • IRQ status register (ISR) • Software standby release IRQ enable register (SSIER) Rev.2.00 Oct. 16, 2007 Page 95 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W 7 ⎯ 0 R 6 ⎯ 0 R 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 ⎯ 0 R 1 ⎯ 0 R 0 ⎯ 0 R Bit 7, 6 5 4 Bit Name ⎯ INTM1 INTM0 Initial Value All 0 0 0 R/W R R/W R/W Description Reserved These are read-only bits and cannot be modified. Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 96 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.2 CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception handling by the CPU can be given priority over that of the DMAC transfer. The priority level of the DMAC is set by the DMAC control register for each channel. Bit Bit Name Initial Value R/W 7 CPUPCE 0 R/W 6 — 0 R/W 5 — 0 R/W 4 — 0 R/W 3 IPSETE 0 R/W 2 CPUP2 0 R/(W)* 1 CPUP1 0 R/(W)* 0 CPUP0 0 R/(W)* Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Bit 7 Bit Name CPUPCE Initial Value 0 R/W R/W Description CPU Priority Control Enable Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled 6 to 4 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 IPSETE 0 R/W Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0 Rev.2.00 Oct. 16, 2007 Page 97 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 2 1 0 Bit Name CPUP2 CPUP1 CPUP0 Initial Value 0 0 0 R/W R/(W)* R/(W)* R/(W)* Description CPU Priority Level 2 to 0 These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function over the DMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. 5.3.3 Interrupt Priority Registers A to G, I, K, L, O, Q, and R (IPRA to IPRG, IPRI, IPRK, IPRL, IPRO, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 5.2. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 0 R 7 ⎯ 0 R 14 IPR14 1 R/W 6 IPR6 1 R/W 13 IPR13 1 R/W 5 IPR5 1 R/W 12 IPR12 1 R/W 4 IPR4 1 R/W 11 ⎯ 0 R 3 ⎯ 0 R 10 IPR10 1 R/W 2 IPR2 1 R/W 9 IPR9 1 R/W 1 IPR1 1 R/W 8 IPR8 1 R/W 0 IPR0 1 R/W Rev.2.00 Oct. 16, 2007 Page 98 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 15 14 13 12 Bit Name ⎯ IPR14 IPR13 IPR12 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 11 10 9 8 ⎯ IPR10 IPR9 IPR8 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 7 ⎯ 0 R Reserved This is a read-only bit and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 99 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 6 5 4 Bit Name IPR6 IPR5 IPR4 Initial Value 1 1 1 R/W R/W R/W R/W Description Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 3 2 1 0 ⎯ IPR2 IPR1 IPR0 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Rev.2.00 Oct. 16, 2007 Page 100 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.4 IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15E 0 R/W 7 IRQ7E 0 R/W 14 IRQ14E 0 R/W 6 IRQ6E 0 R/W 13 IRQ13E 0 R/W 5 IRQ5E 0 R/W 12 IRQ12E 0 R/W 4 IRQ4E 0 R/W 11 IRQ11E 0 R/W 3 IRQ3E 0 R/W 10 IRQ10E 0 R/W 2 IRQ2E 0 R/W 9 IRQ9E 0 R/W 1 IRQ1E 0 R/W 8 IRQ8E 0 R/W 0 IRQ0E 0 R/W Bit 15 Bit Name IRQ15E Initial Value 0 R/W R/W Description IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. Rev.2.00 Oct. 16, 2007 Page 101 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 8 7 6 5 4 3 2 1 0 Bit Name IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev.2.00 Oct. 16, 2007 Page 102 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ15 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 0 to 15) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0. • ISCRH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15SR 0 R/W 7 IRQ11SR 0 R/W 14 IRQ15SF 0 R/W 6 IRQ11SF 0 R/W 13 IRQ14SR 0 R/W 5 IRQ10SR 0 R/W 12 IRQ14SF 0 R/W 4 IRQ10SF 0 R/W 11 IRQ13SR 0 R/W 3 IRQ9SR 0 R/W 10 IRQ13SF 0 R/W 2 IRQ9SF 0 R/W 9 IRQ12SR 0 R/W 1 IRQ8SR 0 R/W 8 IRQ12SF 0 R/W 0 IRQ8SF 0 R/W • ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ7SR 0 R/W 7 IRQ3SR 0 R/W 14 IRQ7SF 0 R/W 6 IRQ3SF 0 R/W 13 IRQ6SR 0 R/W 5 IRQ2SR 0 R/W 12 IRQ6SF 0 R/W 4 IRQ2SF 0 R/W 11 IRQ5SR 0 R/W 3 IRQ1SR 0 R/W 10 IRQ5SF 0 R/W 2 IRQ1SF 0 R/W 9 IRQ4SR 0 R/W 1 IRQ0SR 0 R/W 8 IRQ4SF 0 R/W 0 IRQ0SF 0 R/W Rev.2.00 Oct. 16, 2007 Page 103 of 916 REJ09B0381-0200 Section 5 Interrupt Controller • ISCRH Bit 15 14 Bit Name IRQ15SR IRQ15SF Initial Value 0 0 R/W R/W R/W Description IRQ15 Sense Control Rise IRQ15 Sense Control Fall 00: Interrupt request generated by low level of IRQ15 01: Interrupt request generated at falling edge of IRQ15 10: Interrupt request generated at rising edge of IRQ15 11: Interrupt request generated at both falling and rising edges of IRQ15 13 12 IRQ14SR IRQ14SF 0 0 R/W R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14 10: Interrupt request generated at rising edge of IRQ14 11: Interrupt request generated at both falling and rising edges of IRQ14 11 10 IRQ13SR IRQ13SF 0 0 R/W R/W IRQ13 Sense Control Rise IRQ13 Sense Control Fall 00: Interrupt request generated by low level of IRQ13 01: Interrupt request generated at falling edge of IRQ13 10: Interrupt request generated at rising edge of IRQ13 11: Interrupt request generated at both falling and rising edges of IRQ13 9 8 IRQ12SR IRQ12SF 0 0 R/W R/W IRQ12 Sense Control Rise IRQ12 Sense Control Fall 00: Interrupt request generated by low level of IRQ12 01: Interrupt request generated at falling edge of IRQ12 10: Interrupt request generated at rising edge of IRQ12 11: Interrupt request generated at both falling and rising edges of IRQ12 Rev.2.00 Oct. 16, 2007 Page 104 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 7 6 Bit Name IRQ11SR IRQ11SF Initial Value 0 0 R/W R/W R/W Description IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 5 4 IRQ10SR IRQ10SF 0 0 R/W R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 3 2 IRQ9SR IRQ9SF 0 0 R/W R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 1 0 IRQ8SR IRQ8SF 0 0 R/W R/W IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8 Rev.2.00 Oct. 16, 2007 Page 105 of 916 REJ09B0381-0200 Section 5 Interrupt Controller • ISCRL Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 13 12 IRQ6SR IRQ6SF 0 0 R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 9 8 IRQ4SR IRQ4SF 0 0 R/W R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 Rev.2.00 Oct. 16, 2007 Page 106 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Bit 7 6 Bit Name IRQ3SR IRQ3SF Initial Value 0 0 R/W R/W R/W Description IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 5 4 IRQ2SR IRQ2SF 0 0 R/W R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2 3 2 IRQ1SR IRQ1SF 0 0 R/W R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 1 0 IRQ0SR IRQ0SF 0 0 R/W R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0 Rev.2.00 Oct. 16, 2007 Page 107 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request register. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 IRQ15F 0 R/(W)* 7 IRQ7F 0 R/(W)* 14 IRQ14F 0 R/(W)* 6 IRQ6F 0 R/(W)* 13 IRQ13F 0 R/(W)* 5 IRQ5F 0 R/(W)* 12 IRQ12F 0 R/(W)* 4 IRQ4F 0 R/(W)* 11 IRQ11F 0 R/(W)* 3 IRQ3F 0 R/(W)* 10 IRQ10F 0 R/(W)* 2 IRQ2F 0 R/(W)* 9 IRQ9F 0 R/(W)* 1 IRQ1F 0 R/(W)* 8 IRQ8F 0 R/(W)* 0 IRQ0F 0 R/(W)* Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: * Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] • • • • When the interrupt selected by ISCR occurs Writing 0 after reading IRQnF = 1 When interrupt exception handling is executed when low-level sensing is selected and IRQn input is high When IRQn interrupt exception handling is executed when falling-, rising-, or both-edge sensing is selected [Clearing conditions] Only 0 can be written, to clear the flag. The flag should be cleared by a bit manipulation instruction or memory operation instruction. Rev.2.00 Oct. 16, 2007 Page 108 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSI15 0 R/W 7 SSI7 0 R/W 14 SSI14 0 R/W 6 SSI6 0 R/W 13 SSI13 0 R/W 5 SSI5 0 R/W 12 SSI12 0 R/W 4 SSI4 0 R/W 11 SSI11 0 R/W 3 SSI3 0 R/W 10 SSI10 0 R/W 2 SSI2 0 R/W 9 SSI9 0 R/W 1 SSI1 0 R/W 8 SSI8 0 R/W 0 SSI0 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Software Standby Release IRQ Setting These bits select the IRQn pins used to leave software standby mode (n = 15 to 0). 0: IRQn requests are not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed Rev.2.00 Oct. 16, 2007 Page 109 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. • Sets the ERRF bit of DMDR_0 in the DMAC to 1 • Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate transfer (2) IRQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQn (n = 15 to 0). IRQn have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn. • IRQn interrupt requests can be selected by IER. • The interrupt priority can be set by IPR. • The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions and memory operation instructions should be used to clear the flag. Detection of IRQn interrupts is enabled through the P1ICR and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. Rev.2.00 Oct. 16, 2007 Page 110 of 916 REJ09B0381-0200 Section 5 Interrupt Controller A block diagram of interrupts IRQn is shown in figure 5.2. IRQnE Corresponding bit in ICR IRQnSF, IRQnSR IRQnF Input buffer IRQn input Edge/level detection circuit IRQn interrupt request S R Q Clear signal Note: n = 15 to 0 Figure 5.2 Block Diagram of Interrupts IRQn When ISCR is set so that an IRQn interrupt request is generated at IRQn low-level input, IRQn input should be held low until interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins. 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. • The interrupt priority can be set by means of IPR. • The DMAC can be activated by a TPU, SCI, or other interrupt request. • The priority level of DMAC activation can be controlled by the DMAC priority control functions. Rev.2.00 Oct. 16, 2007 Page 111 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Interrupt Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Reserved WDT Reserved for system use WOVI Vector Number 7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Vector Address H'001C H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 IPR ⎯ IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 IPRD14 to IPRD12 IPRD10 to IPRD8 IPRD6 to IPRD4 IPRD2 to IPRD0 ⎯ IPRE10 to IPRE8 DMAC Activation ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Interrupt Source External pin Rev.2.00 Oct. 16, 2007 Page 112 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Vector Number 82 83 84 85 A/D_0 A/D_1 TPU_0 ADI0 ADI1 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V TPU_4 TGI4A TGI4B TCI4V TCI4U 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Vector Address H'0148 H'014C H'015C H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 IPRG6 to IPRG4 IPRG10 to IPRG8 IPRG14 to IPRG12 IPRF2 to IPRF0 IPRF6 to IPRF4 IPRF10 to IPRF8 DMAC Activation ⎯ ⎯ ⎯ ⎯ O O O ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ Interrupt Source Reserved Interrupt Name Reserved for system use IPR ⎯ Rev.2.00 Oct. 16, 2007 Page 113 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Vector Number 110 111 112 113 114 | 127 128 129 130 131 132 133 134 135 DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 Reserved Reserved for system use 136 137 138 139 140 141 142 143 SCI_0 ERI_0 RXI_0 TXI_0 TEI_0 144 145 146 147 Vector Address H'01B8 H'01BC H'01C0 H'01C4 H'01C8 | H'01FC H'0200 H'0204 H'0208 H'020C H'0210 H'0214 H'0218 H'021C H'0220 H'0224 H'0228 H'022C H'0230 H'0234 H'0238 H'023C H'0240 H'0244 H'0248 H'024C IPRK6 to IPRK4 ⎯ IPRK14 to IPRK12 ⎯ DMAC Activation O ⎯ ⎯ ⎯ ⎯ Interrupt Source TPU_5 Interrupt Name TGI5A TGI5B TCI5V TCI5U IPR IPRG2 to IPRG0 Reserved Reserved for system use DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 IPRI2 to IPRI0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O O ⎯ Reserved Reserved for system use Rev.2.00 Oct. 16, 2007 Page 114 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Vector Number 148 149 150 151 SCI_2 ERI_2 RXI_2 TXI_2 TEI_2 Reserved Reserved for system use 152 153 154 155 156 | 159 160 161 162 163 164 | 191 192 193 194 195 196 | 215 216 217 218 219 Vector Address H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C H'0270 | H'027C H'0280 H'0284 H'0288 H'028C H'0290 | H'02FC H'0300 H'0304 H'0308 H'030C H'0310 | H'035C H'0360 H'0364 H'0368 H'036C ⎯ ⎯ ⎯ IPRL14 to IPRL12 DMAC Activation ⎯ ⎯ ⎯ ⎯ ⎯ O O ⎯ ⎯ Interrupt Source Reserved Interrupt Name Reserved for system use IPR ⎯ SCI_4 ERI_4 RXI_4 TXI_4 TEI_4 IPRL6 to IPRL4 ⎯ O O ⎯ ⎯ Reserved Reserved for system use SCI_5 ERI_5 RXI_5 TXI_5 TEI_5 IPRO2 to IPRO0 ⎯ O O ⎯ ⎯ Reserved Reserved for system use IIC2 IICI0 Reserved for system use IICI1 Reserved for system use IPRQ6 to IPRQ4 ⎯ ⎯ ⎯ ⎯ Rev.2.00 Oct. 16, 2007 Page 115 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Vector Number 220 221 Vector Address H'0370 H'0374 H'0378 H'037C H'0380 H'0384 H'0388 H'038C H'0390 H'0394 H'0398 H'039C H'03A0 H'03A4 H'03A8 H'03AC H'03B0 H'03B4 H'03B8 H'03BC IPRR2 to IPRR0 IPRR6 to IPRR4 IPRR10 to IPRR8 IPRR14 to IPRR12 DMAC Activation O O ⎯ ⎯ O O ⎯ ⎯ O O ⎯ ⎯ O O ⎯ ⎯ O O ⎯ ⎯ Interrupt Source RCAN-ET_0 RCAN-ET_1 RCAN-ET_0 RCAN-ET_1 Motor control PWM_0 Motor control PWM_1 Interrupt Name RM0_0 RM0_1 IPR IPRQ2 to IPRQ0 ERS0_0/OVR0_0/RM1_0/ 222 SLE0_0 ERS0_1/OVR0_1/RM1_1/ 223 SLE0_1 CMI0_0 CMI1_0 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 Watch timer (WAT) WCMI Reserved 16-bit PWM_0 16-bit PWM_1 16-bit PWM_2 Reserved SDG_0 SDG_1 SSU*1_0 SSU*1_1 SDG_2 SDG_3 Watch timer (WAT)*2 Reserved Reserved for system use CMI0_1 CMI1_1 CMI2_1 Reserved for system use SGI_0 SGI_1 SSERI_0/SSRXI_0/ SSTXI_0 SSERI_1/SSRXI_1/ SSTXI_1 SGI_2 SGI_3 WCMI Reserved for system use Notes: 1. SSU: Synchronous Serial communication Unit 2. Software standby mode is cancelled when this interrupt is generated. Rev.2.00 Oct. 16, 2007 Page 116 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Mask Bit I Interrupt Priority Setting Control Mode Register 0 Default Description The priority levels of the interrupt sources are fixed default settings. The interrupts except for NMI is masked by the I bit. Eight priority levels can be set for interrupt sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 2 IPR I2 to I0 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack are the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. Rev.2.00 Oct. 16, 2007 Page 117 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Yes Yes No NMI No I=0 Yes No Pending No IRQ0 Yes No IRQ1 Yes WCMI Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.2.00 Oct. 16, 2007 Page 118 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests have the same priority, an interrupt request is selected according to the default setting shown in table 5.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev.2.00 Oct. 16, 2007 Page 119 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Program execution state Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes No Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.2.00 Oct. 16, 2007 Page 120 of 916 REJ09B0381-0200 5.6.3 Interrupt acceptance Interrupt level determination Wait for end of instruction Internal operation Stack Vector fetch Instruction prefetch Instruction prefetch Internal in interrupt handling operation routine Iφ Interrupt request signal Internal address bus (1) (3) (5) (7) (9) Internal read signal Internal write signal Internal data bus (2) (4) (6) (8) (10) Interrupt Exception Handling Sequence (11) Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in onchip memory. Figure 5.5 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP − 2 (7) SP − 4 (6) (8) (9) (10) (11) (12) (12) Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine Section 5 Interrupt Controller Rev.2.00 Oct. 16, 2007 Page 121 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times⎯the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 Interrupt Control Mode 0 Interrupt Control Mode 2 Advanced Mode Interrupt Control Mode 0 3 1 to 19 + 2·SI SK to 2·SK*6 2·SK SK to 2·SK*6 2·SK Sh 2·SI 4 Maximum Mode*5 Interrupt Control Mode 0 Interrupt Control Mode 2 Execution State Interrupt priority determination*1 Number of states until executing instruction ends*2 PC, CCR, EXR stacking Vector fetch Instruction fetch*3 Internal processing* Interrupt Control Mode 2 2·SK 2·SK 2 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. 6. Two states for an internal interrupt. In the case of the MULXS or DIVXS instruction Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. Internal operation after interrupt acceptance or after vector fetch Not available in this LSI. When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n + 2, the interrupt response time is 2·SK. Rev.2.00 Oct. 16, 2007 Page 122 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 4 2 4 3-State Access 6 + 2m 3+m 6 + 2m Symbol Vector fetch Sh Instruction fetch SI Stack manipulation SK On-Chip Memory 1 1 1 2-State Access 8 4 8 3-State Access 12 + 4m 6 + 2m 12 + 4m Legend: m: Number of wait cycles in an external device access. Rev.2.00 Oct. 16, 2007 Page 123 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.6.5 DMAC Activation by Interrupt The DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to the CPU • Activation request to the DMAC • Combination of the above For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and section 7, DMA Controller (DMAC). Figure 5.6 shows a block diagram of the DMAC and interrupt controller. Select signal DMRSR_0 to DMRSR_3 Control signal Interrupt request On-chip peripheral module Interrupt request clear signal DMAC select circuit DMAC activation request signal Clear signal DMAC Interrupt request Clear signal CPU Interrupt request IRQ interrupt Interrupt request clear signal select circuit Priority determination I, I2 to I0 CPU interrupt request vector number CPU Interrupt controller Figure 5.6 Block Diagram of DMAC and Interrupt Controller Rev.2.00 Oct. 16, 2007 Page 124 of 916 REJ09B0381-0200 Section 5 Interrupt Controller (1) Selection of Interrupt Sources A DMAC activation request source for each channel is specified by DMRSR. The request is passed to the DMAC via a selector. When the DTA bit in DMDR is set to 1, the specified request source cannot be used as a CPU interrupt source. Other interrupt sources, meaning that interrupt sources are not controlled by the DMAC, are used as CPU interrupt sources. When the same interrupt source is set as both the DMAC activation source and CPU interrupt source, the DMAC must be given priority over the CPU. Otherwise, DMAC transfer may not be performed or the DMAC may malfunction. (2) Operation Order If the same interrupt is selected as both the DMAC activation source and CPU interrupt source, the respective operations are performed independently. Table 5.6 lists the selection of interrupt sources and interrupt source clear control by means of the setting of the DTA bit in DMDR of the DMAC. Table 5.6 Setting DMAC DTA 0 1 DMAC O √ Interrupt Source Selection/Clear Control CPU √ X Interrupt Source Selection and Clear Control Legend: √: The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. (3) Usage Note The interrupt sources of the SCI and A/D converter are cleared according to the setting shown in table 5.6, when the DMAC reads/writes the prescribed register. To initiate multiple channels for the DMAC with the same interrupt, the same priority should be assigned. Rev.2.00 Oct. 16, 2007 Page 125 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.7 CPU Priority Control Function over DMAC The interrupt controller has a function to control the priority among the DMAC and the CPU by assigning priority levels to the DMAC and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DMAC is assigned to each channel by bits DMAP2 to DMAP0 in the DMA mode control registers 0 to 3 (DMDR_0 to DMDR_3). The priority control function over the DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DMAC activation source is controlled according to the respective priority level. The priority level of the DMAC can be specified for each channel. The DMAC activation source is controlled according to the priority level of the CPU and the priority level of the DMAC indicated by bits DMAP2 to DMAP0. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). When the different priority levels of the DMAC are assigned for the channels, the channel having higher priority continues to transfer while the channel having lower priority than the CPU is held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Rev.2.00 Oct. 16, 2007 Page 126 of 916 REJ09B0381-0200 Section 5 Interrupt Controller Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Control Status Interrupt Mask Bit I = any I=0 I=1 2 IPR setting I2 to I0 0 1 IPSETE in CPUPCR CPUP2 to CPUP0 0 1 B'111 to B'000 B'000 B'100 B'111 to B'000 I2 to I0 Enabled Disabled Updating of CPUP2 to CPUP0 Enabled Disabled Interrupt Control Interrupt Mode Priority 0 Default Table 5.8 shows a setting example of the priority control function over the DMAC and the transfer request control state. Although the DMAC priority levels can be assigned for each channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be performed independently by assigning the different priority levels. Table 5.8 Example of Priority Control Function Setting and Control State CPUP2 to CPUP0 DMAP2 to DMAP0 Transfer Request Control State DMAC Interrupt Control CPUPCE in Mode CPUPCR 0 0 1 Any B'000 B'100 B'100 B'100 Any B'000 B'000 B'011 B'101 B'101 Any B'000 B'101 B'101 B'101 B'101 B'101 B'101 Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked 2 0 1 B'000 Any B'000 B'000 B'011 B'100 B'101 B'110 B'111 Rev.2.00 Oct. 16, 2007 Page 127 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling Iφ Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.7 Conflict between Interrupt Generation and Disabling Rev.2.00 Oct. 16, 2007 Page 128 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller. 5.8.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions With the MOVMD and MOVSD instructions, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine. Rev.2.00 Oct. 16, 2007 Page 129 of 916 REJ09B0381-0200 Section 5 Interrupt Controller 5.8.6 Interrupt Flags of Peripheral Modules To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared in the interrupt service routine if a peripheral module interrupt request is used. This makes the request signal synchronized with the system clock. Rev.2.00 Oct. 16, 2007 Page 130 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; CPU and DMAC. 6.1 Features • Manages external address space in area units Manages the external address space divided into eight areas Bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area An endian conversion function is provided to connect a device of little endian • Basic bus interface This interface can be connected to the SRAM and ROM 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area The negation timing of the read strobe signal (RD) can be modified • Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be inserted before the external read access after an external write access Idle cycles can be inserted before the external access after a DMAC single address transfer (write access) • Write buffer function External write cycles and internal accesses can be executed in parallel Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU and DMAC Rev.2.00 Oct. 16, 2007 Page 131 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) • Multi-clock function The on-chip peripheral functions can be operated in synchronization with the peripheral module clock (Pφ). Accesses to the external address space can be operated in synchronization with the external bus clock (Bφ). A block diagram of the bus controller is shown in figure 6.1. Internal bus control signals Internal bus control unit External bus control unit External bus control signals CPU bus mastership acknowledge signal DMAC bus mastership acknowledge signal CPU bus mastership request signal DMAC bus mastership request signal Internal bus arbiter Control register Internal data bus ABWCR ASTCR WTCRA WTCRB RDNCR Legend: ABWCR: ASTCR: WTCRA: WTCRB: RDNCR: IDLCR BCR1 BCR2 ENDIANCR Bus width control register Access state control register Wait control register A Wait control register B Read strobe timing control register IDLCR: BCR1: BCR2: ENDIANCR: Idle control register Bus control register 1 Bus control register 2 Endian control register Figure 6.1 Block Diagram of Bus Controller Rev.2.00 Oct. 16, 2007 Page 132 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • Read strobe timing control register (RDNCR) • Idle control register (IDLCR) • Bus control register 1 (BCR1) • Bus control register 2 (BCR2) • Endian control register (ENDIANCR) Rev.2.00 Oct. 16, 2007 Page 133 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.1 Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ABWH7 1 R/W 7 ABWL7 1 R/W 14 ABWH6 1 R/W 6 ABWL6 1 R/W 13 ABWH5 1 R/W 5 ABWL5 1 R/W 12 ABWH4 1 R/W 4 ABWL4 1 R/W 11 ABWH3 1 R/W 3 ABWL3 1 R/W 10 ABWH2 1 R/W 2 ABWL2 1 R/W 9 ABWH1 1 R/W 1 ABWL1 1 R/W 8 ABWH0 1/0 R/W 0 ABWL0 1 R/W Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ABWH7 ABWH6 ABWH5 ABWH4 ABWH3 ABWH2 ABWH1 ABWL0 ABWL7 ABWL6 ABWL5 ABWL4 ABWL3 ABWL2 ABWL1 ABWL0 Initial Value* 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. ABWHn × 0 1 ABWLn (n = 7 to 0) 0: 1: 1: Setting prohibited Area n is designated as 16-bit access space Area n is designated as 8-bit access space Legend: ×: Don't care Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. Rev.2.00 Oct. 16, 2007 Page 134 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 AST7 1 R/W 7 ⎯ 0 R 14 AST6 1 R/W 6 ⎯ 0 R 13 AST5 1 R/W 5 ⎯ 0 R 12 AST4 1 R/W 4 ⎯ 0 R 11 AST3 1 R/W 3 ⎯ 0 R 10 AST2 1 R/W 2 ⎯ 0 R 9 AST1 1 R/W 1 ⎯ 0 R 8 AST0 1 R/W 0 ⎯ 0 R Bit 15 14 13 12 11 10 9 8 Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 ⎯ Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait cycle insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait cycle insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait cycle insertion in area n access is enabled (n = 7 to 0) Reserved These are read-only bits and cannot be modified. 7 to 0 All 0 R Rev.2.00 Oct. 16, 2007 Page 135 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 0 R 7 ⎯ 0 R 14 W72 1 R/W 6 W52 1 R/W 13 W71 1 R/W 5 W51 1 R/W 12 W70 1 R/W 4 W50 1 R/W 11 ⎯ 0 R 3 ⎯ 0 R 10 W62 1 R/W 2 W42 1 R/W 9 W61 1 R/W 1 W41 1 R/W 8 W60 1 R/W 0 W40 1 R/W • WTCRB Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 0 R 7 ⎯ 0 R 14 W32 1 R/W 6 W12 1 R/W 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 ⎯ 0 R 3 ⎯ 0 R 10 W22 1 R/W 2 W02 1 R/W 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W Rev.2.00 Oct. 16, 2007 Page 136 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) • WTCRA Bit 15 14 13 12 Bit Name ⎯ W72 W71 W70 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 7 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 7 while bit AST7 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 ⎯ W62 W61 W60 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 6 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 6 while bit AST6 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ⎯ 0 R Reserved This is a read-only bit and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 137 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bit 6 5 4 Bit Name W52 W51 W50 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 5 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 5 while bit AST5 in ASTCR is 1. 000: Program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 2 1 0 ⎯ W42 W41 W40 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 4 while bit AST4 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Rev.2.00 Oct. 16, 2007 Page 138 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) • WTCRB Bit 15 14 13 12 Bit Name ⎯ W32 W31 W30 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 3 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 3 while bit AST3 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 ⎯ W22 W21 W20 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 2 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 2 while bit AST2 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ⎯ 0 R Reserved This is a read-only bit and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 139 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bit 6 5 4 Bit Name W12 W11 W10 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 1 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 1 while bit AST1 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 2 1 0 ⎯ W02 W01 W00 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 0 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 0 while bit AST0 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Rev.2.00 Oct. 16, 2007 Page 140 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 RDN7 0 R/W 7 ⎯ 0 R 14 RDN6 0 R/W 6 ⎯ 0 R 13 RDN5 0 R/W 5 ⎯ 0 R 12 RDN4 0 R/W 4 ⎯ 0 R 11 RDN3 0 R/W 3 ⎯ 0 R 10 RDN2 0 R/W 2 ⎯ 0 R 9 RDN1 0 R/W 1 ⎯ 0 R 8 RDN0 0 R/W 0 ⎯ 0 R Bit 15 14 13 12 11 10 9 8 Bit Name RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Read Strobe Timing Control These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-cycle earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time are also given one half-cycle earlier. 0: In an area n read access, the RD signal is negated at the end of the read cycle 1: In an area n read access, the RD signal is negated one half-cycle before the end of the read cycle (n = 7 to 0) 7 to 0 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 141 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bus cycle T1 Bφ T2 T3 RD RDNn = 0 Data RD RDNn = 1 Data (n = 7 to 0) Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) 6.2.5 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IDLS3 1 R/W 7 IDLSEL7 0 R/W 14 IDLS2 1 R/W 6 IDLSEL6 0 R/W 13 IDLS1 1 R/W 5 IDLSEL5 0 R/W 12 IDLS0 1 R/W 4 IDLSEL4 0 R/W 11 IDLCB1 1 R/W 3 IDLSEL3 0 R/W 10 IDLCB0 1 R/W 2 IDLSEL2 0 R/W 9 IDLCA1 1 R/W 1 IDLSEL1 0 R/W 8 IDLCA0 1 R/W 0 IDLSEL0 0 R/W Rev.2.00 Oct. 16, 2007 Page 142 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bit 15 Bit Name IDLS3 Initial Value 1 R/W R/W Description Idle Cycle Insertion 3 Inserts an idle cycle between the bus cycles when the DMAC single address transfer (write cycle) is followed by external access. 0: No idle cycle is inserted 1: An idle cycle is inserted 14 IDLS2 1 R/W Idle Cycle Insertion 2 Inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted 13 IDLS1 1 R/W Idle Cycle Insertion 1 Inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: No idle cycle is inserted 1: An idle cycle is inserted 12 IDLS0 1 R/W Idle Cycle Insertion 0 Inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted 11 10 IDLCB1 IDLCB0 1 1 R/W R/W Idle Cycle State Number Select B Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS1 and IDLS0. 00: No idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted Rev.2.00 Oct. 16, 2007 Page 143 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bit 9 8 Bit Name IDLCA1 IDLCA0 Initial Value 1 1 R/W R/W R/W Description Idle Cycle State Number Select A Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS3 to IDLS0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted 7 6 5 4 3 2 1 0 IDLSEL7 IDLSEL6 IDLSEL5 IDLSEL4 IDLSEL3 IDLSEL2 IDLSEL1 IDLSEL0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Idle Cycle Number Select Specifies the number of idle cycles to be inserted for each area for the idle insertion condition specified by IDLS1 and IDLS0. 0: Number of idle cycles to be inserted for area n is specified by IDLCA1 and IDLCA0. 1: Number of idle cycles to be inserted for area n is specified by IDLCB1 and IDLCB0. (n = 7 to 0) 6.2.6 Bus Control Register 1 (BCR1) BCR1 is used for enabling/disabling of the write data buffer function. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ⎯ 0 R/W 7 DKC 0 R/W 14 ⎯ 0 R/W 6 ⎯ 0 R/W 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R/W 3 ⎯ 0 R 10 ⎯ 0 R/W 2 ⎯ 0 R 9 WDBE 0 R/W 1 ⎯ 0 R 8 ⎯ 0 R/W 0 ⎯ 0 R Rev.2.00 Oct. 16, 2007 Page 144 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bit 15, 14 Bit Name ⎯ Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 11, 10 ⎯ ⎯ All 0 All 0 R R/W Reserved These are read-only bits and cannot be modified. Reserved These bits are always read as 0. The write value should always be 0. 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle and a DMAC single address transfer cycle. The changed setting may not affect an external access immediately after the change. 0: Write data buffer function not used 1: Write data buffer function used 8 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 7 DKC 0 R/W DACK Control Selects the timing of DMAC transfer acknowledge signal assertion. 0: DACK signal is asserted at the Bφ falling edge 1: DACK signal is asserted at the Bφ rising edge 6 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 to 0 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 145 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.7 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the write data buffer function to the peripheral modules. Bit Bit Name Initial Value R/W 7 ⎯ 0 R 6 ⎯ 0 R 5 ⎯ 0 R/W 4 IBCCS 0 R/W 3 ⎯ 0 R 2 ⎯ 0 R 1 ⎯ 1 R/W 0 PWDBE 0 R/W Bit 7, 6 5 Bit Name ⎯ ⎯ Initial Value All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 4 IBCCS 0 R/W Internal Bus Cycle Control Select Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC bus mastership request 3, 2 1 ⎯ ⎯ All 0 1 R R/W Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 1. The write value should always be 1. 0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used Rev.2.00 Oct. 16, 2007 Page 146 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.2.8 Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address space access. Note that the data format for the areas used as a program area or a stack area should be big endian. Bit Bit Name Initial Value R/W 7 LE7 0 R/W 6 LE6 0 R/W 5 LE5 0 R/W 4 LE4 0 R/W 3 LE3 0 R/W 2 LE2 0 R/W 1 ⎯ 0 R 0 ⎯ 0 R Bit 7 6 5 4 3 2 1, 0 Bit Name LE7 LE6 LE5 LE4 LE3 LE2 ⎯ Initial Value 0 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R/W R/W R Description Little Endian Select Selects the endian for the corresponding area. 0: Data format of area n is specified as big endian 1: Data format of area n is specified as little endian (n = 7 to 2) Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 147 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.3 Bus Configuration Figure 6.3 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, DMAC, on-chip RAM, on-chip ROM, internal peripheral bus, and external access bus. • Internal peripheral bus A bus that accesses registers in the bus controller, interrupt controller, and DMAC, and registers of peripheral modules such as SCI and timer. • External access cycle A bus that accesses external devices via the external bus interface. Iφ synchronization CPU On-chip RAM On-chip ROM Internal system bus Write data buffer Bus controller, interrupt controller, power-down controller DMAC Write data buffer External access bus Internal peripheral bus Pφ synchronization Peripheral functions Bφ synchronization External bus interface Figure 6.3 Internal Bus Configuration Rev.2.00 Oct. 16, 2007 Page 148 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.4 Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral module clock (Pφ), or the external bus clock (Bφ). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Corresponding Functions Function Name MCU operating mode Interrupt controller Bus controller CPU DMAC Internal memory Clock pulse generator Power down control I/O ports TPU PPG TMR WDT SCI IIC2 A/D D/A SSU* RCAN-ET WAT SDG Motor control PWM 16-bit PWM External bus interface * SSU: Synchronous Serial communication Unit Synchronization Clock Iφ Pφ Bφ Note: The frequency of each synchronization clock (Iφ, Pφ, and Bφ) is specified by the system clock control register (SCKCR) independently. For further details, see section 23, Clock Pulse Generator. There will be cases when Pφ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ according to the SCKCR specifications. In any case, access cycles for internal peripheral functions and external space is performed synchronously with Pφ and Bφ, respectively. Rev.2.00 Oct. 16, 2007 Page 149 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) For example, in an external address space access where the frequency rate of Iφ and Bφ is n : 1, the operation is performed in synchronization with Bφ. In this case, external 2-state access space is 2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number of access cycles is counted based on Iφ. If the frequencies of Iφ, Pφ and Bφ are different, the start of bus cycle may not synchronize with Pφ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle (Tsy) is inserted at the beginning of each bus cycle. For example, if an external address space access occurs when the frequency rate of Iφ and Bφ is n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when the frequency rate of Iφ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted. Figure 6.4 shows the external 2-state access timing when the frequency rate of Iφ and Bφ is 4 : 1. Figure 6.5 shows the external 3-state access timing when the frequency rate of Iφ and Bφ is 2 : 1. Divided clock synchronization cycle Tsy Iφ Bφ Address AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 T1 T2 Figure 6.4 System Clock: External Bus Clock = 4:1, External 2-State Access Rev.2.00 Oct. 16, 2007 Page 150 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Divided clock synchronization cycle Tsy Iφ Bφ Address AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 T1 T2 T3 Figure 6.5 System Clock: External Bus Clock = 2:1, External 3-State Access Rev.2.00 Oct. 16, 2007 Page 151 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.5 6.5.1 External Bus Input/Output Pins Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions on each interface. Table 6.2 Name Address strobe Pin Configuration Symbol AS I/O Output Function Strobe signal indicating that the basic bus space is being accessed and address output on address bus is valid Strobe signal indicating that the basic bus space is being read Strobe signal indicating that the basic bus space is being written to, and the upper byte (D15 to D8) of data bus is valid Strobe signal indicating that the basic bus space is being written to, and the lower byte (D7 to D0) of data bus is valid Data transfer acknowledge signal for DMAC_3 single address transfer Data transfer acknowledge signal for DMAC_2 single address transfer Data transfer acknowledge signal for DMAC_1 single address transfer Data transfer acknowledge signal for DMAC_0 single address transfer External bus clock Read strobe Low-high write RD LHWR Output Output Low-low write LLWR Output Data transfer acknowledge 3 (DMAC_3) Data transfer acknowledge 2 (DMAC_2) Data transfer acknowledge 1 (DMAC_1) Data transfer acknowledge 0 (DMAC_0) External bus clock DACK3 DACK2 DACK1 DACK0 Bφ Output Output Output Output Output Rev.2.00 Oct. 16, 2007 Page 152 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Table 6.3 Pin Functions in Each Interface Initial State Basic Bus Single-Chip Pin Name Bφ AS RD LHWR LLWR 16 Output Output Output Output Output 8 Output Output Output Output Output 16 O O O O O 8 O O O ⎯ O Remarks ⎯ ⎯ ⎯ ⎯ ⎯ Legend: O: Used as a bus control signal ⎯: Not used as a bus control signal (used as a port input when initialized) Rev.2.00 Oct. 16, 2007 Page 153 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.5.2 Area Division The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Figure 6.6 shows an area division of the 16-Mbyte address space. For details on address map, see section 3, MCU Operating Modes. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (8 Mbytes) H'BFFFFF H'C00000 Area 3 (2 Mbytes) H'DFFFFF H'E00000 Area 4 (1 Mbyte) H'EFFFFF H'F00000 Area 5 (1 Mbyte − 8 kbytes) H'FFDFFF H'FFE000 H'FFFEFF H'FFFF00 H'FFFFFF Area 6 (8 kbytes − 256 bytes) Area 7 (256 bytes) 16-Mbyte space Figure 6.6 Address Space Area Division Rev.2.00 Oct. 16, 2007 Page 154 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.5.3 External Bus Interface The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. The bus width and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and are not affected by the external bus settings. (1) Type of External Bus Interface One type of external bus interfaces is provided and can be selected in area units. Table 6.4 shows each interface name, description, area name to be set for each interface. Table 6.5 shows the areas that can be specified for each interface. The initial state of each area is a basic bus interface. Table 6.4 Interface Basic bus interface Interface Names and Area Names Description Directly connected to ROM and SRAM Area Name Basic bus space Table 6.5 Areas Specifiable for Each Interface Related Registers ⎯ Areas 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 O Interface Basic bus interface (2) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions as a 16-bit access space. The initial state of the bus width is specified by the operating mode. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. Rev.2.00 Oct. 16, 2007 Page 155 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (3) Endian Format Though the endian format of this LSI is big endian, data can be converted into little endian format when reading or writing to the external address space. Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in ENDIANCR. The initial state of each area is the big endian format. Note that the data format for the areas used as a program area or a stack area should be big endian. (4) Number of Access Cycles 1. Basic Bus Interface The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area specified as 3-state access is specified as 3-state access space. For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a program wait (0 to 7 cycles) specified by WTCRA and WTCRB can be inserted. Number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) Table 6.6 lists the number of access cycles for each interface. Table 6.6 Number of Access Cycles = = Th [0,1] Th [0,1] +T1 [1] +T1 [1] +T2 [1] +T2 [1] +Tt [0,1] +Tt [0,1] Basic bus interface [2 to 4] [3 to 12] +Tpw [0 to 7] +T3 [1] Legend: Numbers: Number of access cycles Rev.2.00 Oct. 16, 2007 Page 156 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (5) Strobe Assert/Negate Timings The assert and negate timings of the strobe signals can be modified as well as number of access cycles. • Read strobe (RD) in the basic bus interface • Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers 6.5.4 (1) Area and External Bus Interface Area 0 Area 0 includes on-chip ROM*. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space in onchip ROM enabled extended mode. Note: Applied to the LSI version that incorporates the ROM. (2) Area 1 In externally extended mode, all of area 1 is external address space. In on-chip ROM enabled extended mode, the space excluding on-chip ROM* is external address space. Note: Applied to the LSI version that incorporates the ROM. (3) Area 2 In externally extended mode, all of area 2 is external address space. (4) Area 3 In externally extended mode, all of area 3 is external address space. (5) Area 4 In externally extended mode, all of area 4 is external address space. Rev.2.00 Oct. 16, 2007 Page 157 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (6) Area 5 Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an external address space. For details, see section 3, MCU Operating Modes. (7) Area 6 Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O register area is external address space. (8) Area 7 Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register area is external address space. 6.5.5 Endian and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space. (1) 8-Bit Access Space With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Figures 6.7 and 6.8 illustrate data alignment control for the 8-bit access space. Figure 6.7 shows the data alignment when the data endian format is specified as big endian. Figure 6.8 shows the data alignment when the data endian format is specified as little endian. Rev.2.00 Oct. 16, 2007 Page 158 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Strobe signal LHWR RD LLWR Data Size Byte Word Access Address n Access Count 1 Bus Cycle 1st 1st Data Size Byte Byte Byte Byte Byte Byte Byte D15 Data bus D8 D7 7 15 7 31 23 15 7 D0 0 8 0 24 16 8 0 n n 2 2nd 1st 2nd 3rd 4th Longword 4 Figure 6.7 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian) Strobe signal LHWR RD LLWR Data Size Byte Word Access Address n n n Access Count 1 2 Bus Cycle 1st 1st 2nd Data Size Byte Byte Byte Byte Byte Byte Byte D15 Data bus D8 D7 7 7 15 7 15 23 31 D0 0 0 8 0 8 16 24 Longword 4 1st 2nd 3rd 4th Figure 6.8 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian) Rev.2.00 Oct. 16, 2007 Page 159 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (2) 16-Bit Access Space With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word. Figures 6.9 and 6.10 illustrate data alignment control for the 16-bit access space. Figure 6.9 shows the data alignment when the data endian format is specified as big endian. Figure 6.10 shows the data alignment when the data endian format is specified as little endian. In big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performed by using the lower byte data bus. In little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performed by using the third byte data bus. Strobe signal LHWR LLWR RD Access Size Byte Word Access Address Even (2n) Odd (2n+1) Even (2n) Odd (2n+1) Access Count 1 1 1 2 Bus Cycle 1st 1st 1st 1st 2nd Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte D15 7 Data bus D8 D7 0 7 D0 0 0 8 15 87 15 7 31 15 0 24 23 87 31 16 0 24 8 Longword Even (2n) Odd (2n+1) 2 1st 2nd 3 1st 2nd 3rd 23 7 16 15 0 Figure 6.9 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian) Rev.2.00 Oct. 16, 2007 Page 160 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Strobe signal LHWR RD LLWR Access Size Byte Word Access Address Even (2n) Odd (2n+1) Even (2n) Odd (2n+1) Access Count 1 1 1 2 Bus Cycle 1st 1st 1st 1st 2nd Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte D15 Data bus D8 D7 7 D0 0 7 15 7 0 87 0 15 8 0 16 0 Longword Even (2n) Odd (2n+1) 2 1st 2nd 15 31 7 23 87 24 23 0 16 15 31 3 1st 2nd 3rd 8 24 Figure 6.10 Access Sizes and Data Alignment Control for 16-Bit Access Space (Little Endian) Rev.2.00 Oct. 16, 2007 Page 161 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.6 Basic Bus Interface The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and ENDINCR. 6.6.1 Data Bus Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space,. For details, see section 6.5.5, Endian and Data Alignment. 6.6.2 I/O Pins Used for Basic Bus Interface Table 6.7 shows the pins used for basic bus interface. Table 6.7 Name Address strobe Read strobe Low-high write Low-low write I/O Pins for Basic Bus Interface Symbol AS RD LHWR LLWR I/O Output Output Output Output Function Strobe signal indicating that an address output on the address bus is valid during access Strobe signal indicating the read access Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Rev.2.00 Oct. 16, 2007 Page 162 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.6.3 Basic Timing This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space Figures 6.11 to 6.13 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted. Bus cycle T1 Bφ Address T2 AS RD Read D15 to D8 D7 to D0 LHWR LLWR Valid Invalid Write High level Valid D15 to D8 D7 to D0 High-Z DACK Notes: 1. When RDNn = 0 2. When DKC = 0 Figure 6.11 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) Rev.2.00 Oct. 16, 2007 Page 163 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bus cycle T1 Bφ Address AS RD Read D15 to D8 D7 to D0 Invalid T2 Valid LHWR LLWR D15 to D8 D7 to D0 DACK High level Write High-Z Valid Notes: 1. When RDNn = 0 2. When DKC = 0 Figure 6.12 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) Rev.2.00 Oct. 16, 2007 Page 164 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bus cycle T1 Bφ Address AS RD Read D15 to D8 D7 to D0 Valid T2 Valid LHWR LLWR Write D15 to D8 D7 to D0 Valid Valid DACK Notes: 1. When RDNn = 0 2. When DKC = 0 Figure 6.13 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) Rev.2.00 Oct. 16, 2007 Page 165 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (2) 16-Bit 3-State Access Space Figures 6.14 to 6.16 show the bus timing of 16-bit 3-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be inserted. Bus cycle T1 Bφ Address AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 DACK Notes: 1. When RDNn = 0 2. When DKC = 0 High-Z High level Valid Valid Invalid T2 T3 Figure 6.14 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address) Rev.2.00 Oct. 16, 2007 Page 166 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bus cycle T1 Bφ Address AS RD Read D15 to D8 D7 to D0 LHWR High level Write LLWR Invalid Valid T2 T3 D15 to D8 D7 to D0 DACK Notes: 1. When RDNn = 0 2. When DKC = 0 High-Z Valid Figure 6.15 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) Rev.2.00 Oct. 16, 2007 Page 167 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Bus cycle T1 Bφ Address AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 DACK Valid Valid Valid Valid T2 T3 Notes: 1. When RDNn = 0 2. When DKC = 0 Figure 6.16 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) Rev.2.00 Oct. 16, 2007 Page 168 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.6.4 Wait Control This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is accessed. There is one way of inserting wait cycle: program wait (Tpw) insertion. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between the T2 state and T3 state for 3-state access space, according to the settings in WTCRA and WTCRB. Figure 6.17 shows an example of wait cycle insertion timing. After a reset, the 3-state access is specified and the program wait is inserted for seven cycles. Wait by program wait Tpw T1 Bφ T2 T3 Address AS RD Read Data bus Read data LHWR, LLWR Write Data bus Write data Note: When RDNn = 0 Figure 6.17 Example of Wait Cycle Insertion Timing Rev.2.00 Oct. 16, 2007 Page 169 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.6.5 Read Strobe (RD) Timing The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to 1. Note that the RD timing with respect to the DACK rising edge will change if the read strobe timing is modified by setting RDNn to 1 when the DMAC is used in the single address mode. Figure 6.18 shows an example of timing when the read strobe timing is changed in the basic bus 3state access space. Bus cycle T1 Bφ T2 T3 Address bus AS RD RDNn = 0 Data bus RD RDNn = 0 Data bus DACK Note: When DKC = 0 Figure 6.18 Example of Read Strobe Timing Rev.2.00 Oct. 16, 2007 Page 170 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.6.6 DACK Signal Output Timing For DMAC single address transfers, the DACK signal assert timing can be modified by using the DKC bit in BCR1. Figure 6.19 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK signal a half cycle earlier. Bus cycle T1 Bφ Address bus AS RD Read Data bus LHWR, LLWR Write Data bus DKC = 0 DACK DKC = 1 Note: RDNn = 0 Write data Read data T2 Figure 6.19 DACK Signal Output Timing Rev.2.00 Oct. 16, 2007 Page 171 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.7 Idle Cycle In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the idle cycle, data conflicts between ROM read cycle whose output floating time is long and an access cycle from/to high-speed memory or I/O interface can be prevented. 6.7.1 Operation When this LSI consecutively accesses external address space, it can insert an idle cycle between bus cycles in the following four cases. These conditions are determined by the sequence of read and write and previously accessed area. 1. When read cycles of different areas in the external address space occur consecutively 2. When an external write cycle occurs immediately after an external read cycle 3. When an external read cycle occurs immediately after an external write cycle 4. When an external access occurs immediately after a DMAC single address transfer (write cycle) Up to four idle cycles can be inserted under the conditions shown above. The number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7 to IDLSEL0 correspond to the previously accessed area of the consecutive accesses. The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determined by setting A as described above. After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. Table 6.8 shows the correspondence between conditions 1 to 4 and number of idle cycles to be inserted for each area. Table 6.9 shows the correspondence between the number of idle cycles to be inserted specified by settings A and B, and number of cycles to be inserted. Rev.2.00 Oct. 16, 2007 Page 172 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Table 6.8 Number of Idle Cycle Insertion Selection in Each Area Bit Settings IDLSn IDLSELn n = 0 to 7 ⎯ 0 1 ⎯ 0 1 ⎯ A ⎯ A A A A A A B A B A B A B A B A B 0 Area for Previous Access 1 2 3 4 5 6 7 Insertion Condition n Setting 0 1 Consecutive reads in different areas 1 Invalid A B A B A B A B A B Write after read 0 0 1 Invalid A B A B A B A B A B Read after write 2 0 1 Invalid A A A A A External access after single address 3 transfer 0 1 Invalid A A A A A Legend: A: Number of idle cycle insertion A is selected. B: Number of idle cycle insertion B is selected. Invalid: No idle cycle is inserted for the corresponding condition. Table 6.9 Number of Idle Cycle Insertions Bit Settings A B IDLCB1 0 ⎯ 0 1 1 IDLCB0 0 ⎯ 1 0 1 Number of Cycles 0 1 2 3 4 IDLCA1 ⎯ 0 0 1 1 IDLCA0 ⎯ 0 1 0 1 Rev.2.00 Oct. 16, 2007 Page 173 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). Figure 6.20 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 Bφ Address bus RD T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Data bus Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 6.20 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev.2.00 Oct. 16, 2007 Page 174 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (2) Write after Read If an external write occurs after an external read while bit IDLS0 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0 when IDLSELn = 0, or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of the write cycle (n = 0 to 7). Figure 6.21 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 Bφ Address bus RD LLWR T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Data bus Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS0 = 0) (b) Idle cycle inserted (IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA1 = 0) Figure 6.21 Example of Idle Cycle Operation (Write after Read) Rev.2.00 Oct. 16, 2007 Page 175 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7). Figure 6.22 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM device. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 Bφ Address bus RD LLWR Data bus T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS2 = 0) (b) Idle cycle inserted (IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0) Figure 6.22 Example of Idle Cycle Operation (Read after Write) Rev.2.00 Oct. 16, 2007 Page 176 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (4) External Access after Single Address Transfer Write If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external access (n = 0 to 7). Figure 6.23 shows an example of the operation in this case. In this example, bus cycle A is a single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the external device write data and this LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 Bφ T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus LLWR DACK Data bus Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS3 = 0) (b) Idle cycle inserted (IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0) Figure 6.23 Example of Idle Cycle Operation (Write after Single Address Transfer Write) Rev.2.00 Oct. 16, 2007 Page 177 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) (5) External NOP Cycles and Idle Cycles A cycle in which an external space is not accessed due to internal operations is called an external NOP cycle. Even when an external NOP cycle occurs between consecutive external bus cycles, an idle cycle can be inserted. In this case, the number of external NOP cycles is included in the number of idle cycles to be inserted. Figure 6.24 shows an example of external NOP and idle cycle insertion. No external access Idle cycle (NOP) (remaining) Ti Ti T1 Preceding bus cycle T1 Bφ T2 Tpw T3 Following bus cycle T2 Tpw T3 Address bus RD Data bus Specified number of idle cycles or more including no external access cycles (NOP) (Condition: Number of idle cycles to be inserted when different reads continue: 4 cycles) Figure 6.24 Idle Cycle Insertion Example Rev.2.00 Oct. 16, 2007 Page 178 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Table 6.10 Idle Cycles in Mixed Accesses to Normal Space Previous Access Normal space read Next Access Normal space read IDLS 3 ⎯ ⎯ 2 ⎯ ⎯ 1 0 1 0 ⎯ ⎯ IDLSEL 7 to 0 ⎯ 0 1 ⎯ 0 0 1 1 1 ⎯ IDLCA 0 ⎯ 0 1 0 1 ⎯ 0 0 1 1 Normal space read Normal space write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 ⎯ 0 ⎯ 0 0 1 1 1 ⎯ ⎯ 0 1 0 1 ⎯ 0 0 1 1 Normal space write Normal space read ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 1 1 Normal Single space read address transfer write 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 1 1 ⎯ 0 1 0 1 ⎯ 0 1 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 0 1 ⎯ ⎯ ⎯ ⎯ 0 1 0 1 ⎯ ⎯ 1 ⎯ ⎯ IDLCB 0 ⎯ ⎯ Idle Cycle Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted 0 cycle inserted 2 cycle inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted 0 cycle inserted 2 cycle inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Rev.2.00 Oct. 16, 2007 Page 179 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.7.2 Pin States in Idle Cycle Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins A23 to A0 D15 to D0 AS RD LHWR, LLWR DACKn (n = 3 to 0) Pin State Contents of following bus cycle High impedance High High High High 6.8 6.8.1 Internal Bus Access to Internal Address Space The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.12 shows the number of access cycles for each on-chip memory space. Table 6.12 Number of Access Cycles for On-Chip Memory Spaces Access Space On-chip ROM space Access Read Write On-chip RAM space Read Write Number of Access Cycles One Iφ cycle Six Iφ cycles One Iφ cycle Two Iφ cycle Rev.2.00 Oct. 16, 2007 Page 180 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. Table 6.13 lists the number of access cycles for registers of on-chip peripheral modules. Table 6.13 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed DMAC registers MCU operating mode, clock pulse generator, power-down control registers, interrupt controller, and bus controller registers I/O port PFCR registers and WDT registers I/O port registers other than PFCR, TPU, IIC2, SCI, A/D, and D/A registers RCANMON registers in RCAN-ET, SSU*, WAT, SDG, motor control PWM, and 16-bit PWM registers Registers other than RCANMON in RCAN-ET Note: * SSU: Synchronous Serial communication Unit 2Iφ Read Write 2Iφ 3I φ Write Data Buffer Function Disabled Disabled 2Pφ 3P φ 2Pφ 3Pφ Disabled Enabled Enabled 4Pφ Enabled Rev.2.00 Oct. 16, 2007 Page 181 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.9 6.9.1 Write Data Buffer Function Write Data Buffer Function for External Data Bus This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables internal accesses in parallel with external writes or DMAC single address transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1. Figure 6.25 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or a DMAC single address transfer continues for two cycles or longer, and there is an internal access next, an external write only is executed in the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or internal I/O register read/write) and the external address space write rather than waiting until it ends are executed in parallel. On-chip memory read External write cycle Iφ Peripheral module read Internal address bus On-chip memory 1 On-chip memory 2 Peripheral module address T1 Bφ T2 T3 A23 to A0 External space write LHWR, LLWR External address D15 to D0 Figure 6.25 Example of Timing when Write Data Buffer Function Is Used Rev.2.00 Oct. 16, 2007 Page 182 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.9.2 Write Data Buffer Function for Peripheral Modules This LSI has a write data buffer function for the peripheral module access. Using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. For details on the on-chip peripheral module registers, see table 6.13, Number of Access Cycles for Registers of On-Chip Peripheral Modules in section 6.8, Internal Bus. Figure 6.26 shows an example of the timing when the write data buffer function is used. When this function is used, if an internal I/O register write continues for two cycles or longer and then there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only is performed in the first two cycles. However, from the next cycle onward an internal memory or an external access and internal I/O register write are executed in parallel rather than waiting until it ends. On-chip memory read Peripheral module write Iφ Internal address bus Pφ Internal I/O address bus Internal I/O data bus Peripheral module address Figure 6.26 Example of Timing when Peripheral Module Write Data Buffer Function Is Used Rev.2.00 Oct. 16, 2007 Page 183 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.10 Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI incorporates internal access and external access bus arbiters that can be used and controlled independently. The internal bus arbiter handles the CPU and DMAC accesses. The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. 6.10.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: (High) DMAC > CPU (Low) If the DMAC access continue, the CPU can be given priority over the DMAC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this case, the priority of the DMAC does not change. 6.10.2 Bus Handover Timing Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily handed over immediately. There are specific timings at which each bus master can release the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC, the bus arbiter grants the bus to the bus master that issued the request. The timing of bus handover is at the end of the bus cycle. In sleep mode, the bus is handed over synchronously with the clock. Rev.2.00 Oct. 16, 2007 Page 184 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) Note, however, that bus handover is prohibited in the following cases. • The word or longword access is performed in some divisions. • Stack handling is performed in multiple bus cycles. • Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be handed over between the write cycle and the following transfer data read cycle.) • From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) (2) DMAC The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DMAC accesses an external bus space, the DMAC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. After the DMAC takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bus cycle depending on the conditions. The DMAC continues transfers without releasing the bus in the following case: • Between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle If no bus master of a higher priority than the DMAC requests the bus and the IBCSS bit in BCR2 is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases: • During transfer of one block in the block transfer mode In other cases, the DMAC releases the bus at the end of the bus cycle. Rev.2.00 Oct. 16, 2007 Page 185 of 916 REJ09B0381-0200 Section 6 Bus Controller (BSC) 6.11 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.12 (1) Usage Notes Setting Registers The BSC registers must be specified before accessing the external address space. In on-chip ROM disabled mode, the BSC registers must be specified before accessing the external address space for other than an instruction fetch access. Rev.2.00 Oct. 16, 2007 Page 186 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC). 7.1 Features • Maximum of 4-G byte address space can be accessed • Byte, word, or longword can be set as data transfer unit • Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed • DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request: Low level or falling edge detection of the DREQ signal can be selected External request is available for all four channels (In block transfer mode only low-level detection can be selected.) • Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode: Either source or destination is specified by the DREQ signal and the other is specified by address • Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 65,536 bytes/words/longwords can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size • Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas Rev.2.00 Oct. 16, 2007 Page 187 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) • Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously • Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred • Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. A block diagram of the DMAC is shown in figure 7.1. Internal address bus External pins DREQn DACKn TENDn Interrupt signals requested to the CPU by each channel Internal activation sources ... Controller Address buffer Operation unit Operation unit DOFR_n DSAR_n Internal activation source detector DMRSR_n DMDR_n DACR_n DDAR_n DTCR_n DBSR_n Internal data bus Data buffer Module data bus Legend: DSAR_n: DDAR_n: DOFR_n: DTCR_n: DBSR_n: DMDR_n: DACR_n: DMRSR_n: DMA source address register DMA destination address register DMA offset register DMA transfer count register DMA block size register DMA mode control register DMA address control register DMA module request select register DREQn: DACKn: TENDn: DMA transfer request DMA transfer acknowledge DMA transfer end Note: n = 0 to 3 Figure 7.1 Block Diagram of DMAC Rev.2.00 Oct. 16, 2007 Page 188 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the DMAC. Table 7.1 Pin Configuration Abbreviation I/O DREQ0_A Input Function Channel 0 external request Channel Name 0 DMA transfer request 0 DMA transfer acknowledge 0 DACK0_A DMA transfer end 0 1 DMA transfer request 1 TEND0_A DREQ1_A Output Channel 0 single address transfer acknowledge Output Channel 0 transfer end Input Channel 1 external request DMA transfer acknowledge 1 DACK1_A DMA transfer end 1 2 DMA transfer request 2 TEND1_A DREQ2_A Output Channel 1 single address transfer acknowledge Output Channel 1 transfer end Input Channel 2 external request DMA transfer acknowledge 2 DACK2_A DMA transfer end 2 3 DMA transfer request 3 TEND2_A DREQ3_A Output Channel 2 single address transfer acknowledge Output Channel 2 transfer end Input Channel 3 external request DMA transfer acknowledge 3 DACK3_A DMA transfer end 3 TEND3_A Output Channel 3 single address transfer acknowledge Output Channel 3 transfer end Rev.2.00 Oct. 16, 2007 Page 189 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3 Register Descriptions The DMAC has the following registers. Channel 0 • DMA source address register_0 (DSAR_0) • DMA destination address register_0 (DDAR_0) • DMA offset register_0 (DOFR_0) • DMA transfer count register_0 (DTCR_0) • DMA block size register_0 (DBSR_0) • DMA mode control register_0 (DMDR_0) • DMA address control register_0 (DACR_0) • DMA module request select register_0 (DMRSR_0) Channel 1 • DMA source address register_1 (DSAR_1) • DMA destination address register_1 (DDAR_1) • DMA offset register_1 (DOFR_1) • DMA transfer count register_1 (DTCR_1) • DMA block size register_1 (DBSR_1) • DMA mode control register_1 (DMDR_1) • DMA address control register_1 (DACR_1) • DMA module request select register_1 (DMRSR_1) Channel 2 • DMA source address register_2 (DSAR_2) • DMA destination address register_2 (DDAR_2) • DMA offset register_2 (DOFR_2) • DMA transfer count register_2 (DTCR_2) • DMA block size register_2 (DBSR_2) • DMA mode control register_2 (DMDR_2) • DMA address control register_2 (DACR_2) • DMA module request select register_2 (DMRSR_2) Rev.2.00 Oct. 16, 2007 Page 190 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Channel 3 • DMA source address register_3 (DSAR_3) • DMA destination address register_3 (DDAR_3) • DMA offset register_3 (DOFR_3) • DMA transfer count register_3 (DTCR_3) • DMA block size register_3 (DBSR_3) • DMA mode control register_3 (DMDR_3) • DMA address control register_3 (DACR_3) • DMA module request select register_3 (DMRSR_3) 7.3.1 DMA Source Address Register (DSAR) DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.2.00 Oct. 16, 2007 Page 191 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.2.00 Oct. 16, 2007 Page 192 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.2.00 Oct. 16, 2007 Page 193 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.4 DMA Transfer Count Register (DTCR) DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: −1, word: −2, and longword: −4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.2.00 Oct. 16, 2007 Page 194 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.5 DMA Block Size Register (DBSR) DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 BKSZH31 0 R/W 23 BKSZH23 0 R/W 15 BKSZ15 0 R/W 7 BKSZ7 0 R/W 30 BKSZH30 0 R/W 22 BKSZH22 0 R/W 14 BKSZ14 0 R/W 6 BKSZ6 0 R/W 29 BKSZH29 0 R/W 21 BKSZH21 0 R/W 13 BKSZ13 0 R/W 5 BKSZ5 0 R/W 28 BKSZH28 0 R/W 20 BKSZH20 0 R/W 12 BKSZ12 0 R/W 4 BKSZ4 0 R/W 27 BKSZH27 0 R/W 19 BKSZH19 0 R/W 11 BKSZ11 0 R/W 3 BKSZ3 0 R/W 26 BKSZH26 0 R/W 18 BKSZH18 0 R/W 10 BKSZ10 0 R/W 2 BKSZ2 0 R/W 25 BKSZH25 0 R/W 17 BKSZH17 0 R/W 9 BKSZ9 0 R/W 1 BKSZ1 0 R/W 24 BKSZH24 0 R/W 16 BKSZH16 0 R/W 8 BKSZ8 0 R/W 0 BKSZ0 0 R/W Bit Bit Name Initial Value R/W Description Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 7.2). While the DMA is in operation, the setting is fixed. Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits. 31 to 16 BKSZH31 to Undefined R/W BKSZH16 15 to 0 BKSZ15 to BKSZ0 Undefined R/W Rev.2.00 Oct. 16, 2007 Page 195 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Table 7.2 Mode Data Access Size, Valid Bits, and Settable Size Data Access Size BKSZH Valid Bits BKSZ Valid Bits 31 to 16 15 to 0 Settable Size (Byte) 1 to 65,536 2 to 131,072 4 to 262,144 Byte Repeat transfer and block transfer Word Longword 7.3.6 DMA Mode Control Register (DMDR) DMDR controls the DMAC operation. • DMDR_0 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 — 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 — 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 — 0 R/W 20 — 0 R 12 MDS0 0 R/W 4 — 0 R 27 DREQS 0 R/W 19 ERRF 0 R/(W)* 11 TSEIE 0 R/W 3 — 0 R 26 NRD 0 R/W 18 — 0 R 10 — 0 R 2 DMAP2 0 R/W 25 — 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 — 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 196 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) • DMDR_1 to DMDR_3 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 — 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 — 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 — 0 R/W 20 — 0 R 12 MDS0 0 R/W 4 — 0 R 27 DREQS 0 R/W 19 — 0 R 11 TSEIE 0 R/W 3 — 0 R 26 NRD 0 R/W 18 — 0 R 10 — 0 R 2 DMAP2 0 R/W 25 — 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 — 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 197 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 31 Initial Bit Name Value DTE 0 R/W R/W Description Data Transfer Enable Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions] • • • • • When the specified total transfer size of transfers is completed When a transfer is stopped by an overflow interrupt by a repeat size end When a transfer is stopped by an overflow interrupt by an extended repeat size end When a transfer is stopped by a transfer size error interrupt When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer. • • When an address error or an NMI interrupt is requested In the reset state or hardware standby mode Rev.2.00 Oct. 16, 2007 Page 198 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 30 Initial Bit Name Value DACKE 0 R/W R/W Description DACK Signal Output Enable Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output 29 TENDE 0 R/W TEND Signal Output Enable Enables/disables the TEND signal output. 0: Enables TEND signal output 1: Disables TEND signal output 28 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 27 DREQS 0 R/W DREQ Select Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. When a block transfer is performed in external request mode, clear this bit to 0 to select the low level detection. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 NRD 0 R/W Next Request Delay Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle after completion of the current transfer 25, 24 23 ⎯ ACT All 0 0 R R Reserved These are read-only bits and cannot be modified. Active State Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 199 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 19 Initial Bit Name Value ERRF 0 R/W R/(W)* Description System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition] • • When clearing to 0 after reading ERRF = 1 When an address error or an NMI interrupt has been generated [Setting condition] However, when an address error or an NMI interrupt has been generated in module stop mode, this bit is not set. 18 17 ⎯ ESIF 0 0 R R/(W)* Reserved This is a read-only bit and cannot be modified. Transfer Escape Interrupt Flag Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions] • • • • • When setting the DTE bit to 1 When clearing to 0 before reading ESIF = 1 When a transfer size error interrupt is requested When a repeat size end interrupt is requested When a transfer end interrupt by an extended repeat area overflow is requested [Setting conditions] Rev.2.00 Oct. 16, 2007 Page 200 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 16 Initial Bit Name Value DTIF 0 R/W R/(W)* Description Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions] • • • When setting the DTE bit to 1 When clearing to 0 after reading DTIF = 1 When DTCR reaches 0 and the transfer is completed [Setting condition] 15 14 DTSZ1 DTSZ0 0 0 R/W R/W Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited 13 12 MDS1 MDS0 0 0 R/W R/W Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited Rev.2.00 Oct. 16, 2007 Page 201 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 11 Initial Bit Name Value TSEIE 0 R/W R/W Description Transfer Size Error Interrupt Enable Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows: • • In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10 9 ⎯ ESIE 0 0 R R/W Reserved This is a read-only bit and cannot be modified. Transfer Escape Interrupt Enable Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt 8 DTIE 0 R/W Data Transfer End Interrupt Enable Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt Rev.2.00 Oct. 16, 2007 Page 202 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 7 6 Initial Bit Name Value DTF1 DTF0 0 0 R/W R/W R/W Description Data Transfer Factor 1 and 0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request 5 DTA 0 R/W Data Transfer Acknowledge This bit is valid in DMA transfer by the on-chip module interrupt source. This bit enables or disables the clearing of the source flag selected by DMRSR. 0: Disables the clearing of the source in DMA transfer. Since the on-chip module interrupt source is not cleared in DMA transfer, it should be cleared by the CPU. 1: Enables the clearing of the source in DMA transfer. Since the on-chip module interrupt source is cleared in DMA transfer, it does not require an interrupt by the CPU. 4, 3 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 203 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 2 1 0 Initial Bit Name Value DMAP2 DMAP1 DMAP0 0 0 0 R/W R/W R/W R/W Description DMA Priority Level 2 to 0 Select the priority level of the DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 204 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.7 DMA Address Control Register (DACR) DACR specifies the operating mode and transfer method. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 AMS 0 R/W 23 — 0 R 15 SARIE 0 R/W 7 DARIE 0 R/W 30 DIRS 0 R/W 22 — 0 R 14 — 0 R 6 — 0 R 29 — 0 R 21 SAT1 0 R/W 13 — 0 R 5 — 0 R 28 — 0 R 20 SAT0 0 R/W 12 SARA4 0 R/W 4 DARA4 0 R/W 27 — 0 R 19 — 0 R 11 SARA3 0 R/W 3 DARA3 0 R/W 26 RPTIE 0 R/W 18 — 0 R 10 SARA2 0 R/W 2 DARA2 0 R/W 25 ARS1 0 R/W 17 DAT1 0 R/W 9 SARA1 0 R/W 1 DARA1 0 R/W 24 ARS0 0 R/W 16 DAT0 0 R/W 8 SARA0 0 R/W 0 DARA0 0 R/W Bit 31 Initial Bit Name Value AMS 0 R/W R/W Description Address Mode Select Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode 30 DIRS 0 R/W Single Address Direction Select Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27 ⎯ All 0 R/W Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 205 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 26 Initial Bit Name Value RPTIE 0 R/W R/W Description Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt 25 24 ARS1 ARS0 0 0 R/W R/W Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22 21 20 ⎯ SAT1 SAT0 All 0 0 0 R R/W R/W Reserved These are read-only bits and cannot be modified. Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size Rev.2.00 Oct. 16, 2007 Page 206 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 19, 18 17 16 Initial Bit Name Value ⎯ DAT1 DAT0 All 0 0 0 R/W R R/W R/W Description Reserved These are read-only bits and cannot be modified. Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size 15 SARIE 0 R/W Interrupt Enable for Source Address Extended Repeat Area Overflow Enables/disables an interrupt request for an extended repeat area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended repeat area overflow on the source address 1: Enables an interrupt request for an extended repeat area overflow on the source address 14, 13 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 207 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 12 11 10 9 8 Initial Bit Name Value SARA4 SARA3 SARA2 SARA1 SARA0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 7.3 shows the settings and areas of the extended repeat area. 7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow Interrupt Enable Enables/disables an interrupt request for an extended repeat area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended repeat area overflow on the destination address 1: Enables an interrupt request for an extended repeat area overflow on the destination address 6, 5 ⎯ All 0 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 208 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Bit 4 3 2 1 0 Initial Bit Name Value DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.3 shows the settings and areas of the extended repeat area. Rev.2.00 Oct. 16, 2007 Page 209 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Table 7.3 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111×× Legend: ×: Don't care Not specified 2 bytes specified as extended repeat area by the lower 1 bit of the address 4 bytes specified as extended repeat area by the lower 2 bits of the address 8 bytes specified as extended repeat area by the lower 3 bits of the address 16 bytes specified as extended repeat area by the lower 4 bits of the address 32 bytes specified as extended repeat area by the lower 5 bits of the address 64 bytes specified as extended repeat area by the lower 6 bits of the address 128 bytes specified as extended repeat area by the lower 7 bits of the address 256 bytes specified as extended repeat area by the lower 8 bits of the address 512 bytes specified as extended repeat area by the lower 9 bits of the address 1 kbyte specified as extended repeat area by the lower 10 bits of the address 2 kbytes specified as extended repeat area by the lower 11 bits of the address 4 kbytes specified as extended repeat area by the lower 12 bits of the address 8 kbytes specified as extended repeat area by the lower 13 bits of the address 16 kbytes specified as extended repeat area by the lower 14 bits of the address 32 kbytes specified as extended repeat area by the lower 15 bits of the address 64 kbytes specified as extended repeat area by the lower 16 bits of the address 128 kbytes specified as extended repeat area by the lower 17 bits of the address 256 kbytes specified as extended repeat area by the lower 18 bits of the address 512 kbytes specified as extended repeat area by the lower 19 bits of the address 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 16 Mbytes specified as extended repeat area by the lower 24 bits of the address 32 Mbytes specified as extended repeat area by the lower 25 bits of the address 64 Mbytes specified as extended repeat area by the lower 26 bits of the address 128 Mbytes specified as extended repeat area by the lower 27 bits of the address Setting prohibited Rev.2.00 Oct. 16, 2007 Page 210 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.3.8 DMA Module Request Select Register (DMRSR) DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 7.5. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 7.4 Transfer Modes Table 7.4 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 7.4 Transfer Modes Address Register Address Mode Transfer mode Dual address • • • Normal transfer Repeat transfer Activation Source • Auto request (activated by CPU) On-chip module interrupt External request Common Function • Total transfer size: 1 to 4 Gbytes or not specified Offset addition Extended repeat area function DSAR/ DACK DACK/ DDAR Source DSAR Destination DDAR Block transfer Repeat or block size • = 1 to 65,536 bytes, 1 to 65,536 words, or • 1 to 65,536 longwords Single address • • • Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin The same settings as above are available other than address register setting (e.g., above transfer modes can be specified) One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) • • Rev.2.00 Oct. 16, 2007 Page 211 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count. 7.5 7.5.1 (1) Operations Address Modes Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Rev.2.00 Oct. 16, 2007 Page 212 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the operation in dual address mode. DMA read cycle DMA write cycle Bφ Address bus RD WR TEND DSAR DDAR Figure 7.2 Example of Signal Timing in Dual Address Mode Address TA Transfer Address TB Address BA Address update setting is as follows: Source address increment Fixed destination address Figure 7.3 Operations in Dual Address Mode Rev.2.00 Oct. 16, 2007 Page 213 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 6, Bus Controller (BSC). The DMAC accesses an external device with DACK as the transfer source or destination by outputting the strobe signal to the external device (DACK) and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an example of operation in single address mode. External address bus LSI External memory External data bus DMAC DACK DREQ External device with DACK Data flow Figure 7.4 Data Flow in Single Address Mode Rev.2.00 Oct. 16, 2007 Page 214 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Transfer from external memory to external device with DACK DMA cycle Bφ Address bus RD WR DACK Data bus TEND Data output by external memory DSAR Address for external memory space RD signal for external memory space Transfer from external device with DACK to external memory DMA cycle Bφ Address bus RD WR DACK Data bus TEND Data output by external device with DACK WR signal for external memory space DDAR Address for external memory space Figure 7.5 Example of Signal Timing in Single Address Mode Address T Transfer DACK Address B Figure 7.6 Operations in Single Address Mode Rev.2.00 Oct. 16, 2007 Page 215 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.2 (1) Transfer Modes Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows the operation in normal transfer mode. Auto request transfer in dual address mode: DMA transfer cycle Bus cycle TEND External request transfer in single address mode: DREQ Bus cycle DACK DMA DMA Read Write Last DMA transfer cycle Read Write Figure 7.7 Example of Signal Timing in Normal Transfer Mode Address TA Transfer Address TB Total transfer size (DTCR) Address BA Address BB Figure 7.8 Operations in Normal Transfer Mode Rev.2.00 Oct. 16, 2007 Page 216 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) Repeat Transfer Mode In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 × data access size. The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the repeat area returns to the transfer start address when the repeat size of transfers is completed. This operation is repeated until the total transfer size specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0. In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the CPU when the repeat size of transfers is completed. When the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an interrupt is requested to the CPU when the ESIE bit in DMDR is set to 1. The timings of the TEND signal are the same as in normal transfer mode. Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set. When the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end interrupt can also be requested to the CPU when the repeat size of transfers is completed. Address TA Transfer Repeat size = BKSZH × data access size Address TB Address BA Total transfer size (DTCR) Operation when the repeat area is specified to the source side Address BB Figure 7.9 Operations in Repeat Transfer Mode Rev.2.00 Oct. 16, 2007 Page 217 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (3) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 × data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When the external request is selected as an activation source, the low level detection of the DREQ signal (DREQS = 0) should be selected. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 7.5.5, Extended Repeat Area Function. Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer conditions are as follows: • Address mode: single address mode • Data access size: byte • 1-block size: three bytes The block transfer mode operations in single address mode and in dual address mode are shown in figures 7.11 and 7.12, respectively. DREQ Transfer cycles for one block Bus cycle CPU CPU DMAC DMAC DMAC CPU No CPU cycle generated TEND Figure 7.10 Operations in Block Transfer Mode Rev.2.00 Oct. 16, 2007 Page 218 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Address T Block BKSZH × data access size Address B Transfer DACK Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) Address TA First block BKSZH × data access size Address TB Transfer First block Second block Second block Total transfer size (DTCR) Nth block Nth block Address BB Address BA Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) Rev.2.00 Oct. 16, 2007 Page 219 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.3 Activation Sources The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 7.5 is a list of on-chip module interrupts for the DMAC. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single interrupt request as an activation source, when the channel with the highest priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the DMAC. Use the CPU to clear the flag. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit. Rev.2.00 Oct. 16, 2007 Page 220 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Table 7.5 List of On-Chip Module Interrupts to DMAC On-Chip Module A/D_0 A/D_1 TPU_0 TPU_1 TPU_2 TPU_3 TPU_4 TPU_5 SCI_0 SCI_0 SCI_2 SCI_2 SCI_4 SCI_4 SCI_5 SCI_5 DMRSR (Vector Number) 86 87 88 93 97 101 106 110 145 146 153 154 161 162 193 194 On-Chip Module Interrupt Source ADI0 (A/D conversion end interrupt) ADI1 (A/D conversion end interrupt) TGI0A (TGR0A input capture/compare match) TGI1A (TGR1A input capture/compare match) TGI2A (TGR2A input capture/compare match) TGI3A (TGR3A input capture/compare match) TGI4A (TGR4A input capture/compare match) TGI5A (TGR5A input capture/compare match) RXI_0 (receive data full interrupt for SCI channel 0) TXI_0 (transmit data empty interrupt for SCI channel 0) RXI_2 (receive data full interrupt for SCI channel 2) TXI_2 (transmit data empty interrupt for SCI channel 2) RXI_4 (receive data full interrupt for SCI channel 4) TXI_4 (transmit data empty interrupt for SCI channel 4) RXI_5 (receive data full interrupt for SCI channel 5) TXI_5 (transmit data empty interrupt for SCI channel 5) RM0_0 (message reception in Mailbox 0 for RCAN-ET channel 0) RM0_1 (message reception in Mailbox 1 for RCAN-ET channel 1) CMI0_0 (compare match interrupt for motor control PWM channel 0) CMI1_0 (compare match interrupt for motor control PWM channel 1) CMI0_1 (compare match interrupt for 16-bit PWM channel 0) CMI1_1 (compare match interrupt for 16-bit PWM channel 1) SGI_0 (attenuation end interrupt for SDG channel 0) SGI_1 (attenuation end interrupt for SDG channel 1) SGI_2 (attenuation end interrupt for SDG channel 2) SGI_3 (attenuation end interrupt for SDG channel 3) RCAN-ET_0 220 RCAN-ET_1 221 PWM_0 PWM_1 PWM16_0 PWM16_1 SDG_0 SDG_1 SDG_2 SDG_3 224 225 228 229 232 233 236 237 Rev.2.00 Oct. 16, 2007 Page 221 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. To perform a block transfer, select the low level detection. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 8, I/O Ports. When a DMA transfer between on-chip peripheral modules is performed, select an activation source form the auto request and on-chip module interrupt (the external request cannot be used). 7.5.4 Bus Access Modes There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 7.5.8, Priority of Channels. Rev.2.00 Oct. 16, 2007 Page 222 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Figure 7.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: • Address mode: Single address mode • Sampling method of the DREQ signal: Low level detection DREQ Bus cycle CPU CPU DMAC CPU DMAC CPU Bus released temporarily for the CPU Figure 7.13 Example of Timing in Cycle Stealing Mode (2) Burst Access Mode In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until the transfer end condition is satisfied. Even if a transfer is requested from another channel having priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle stealing mode. However, setting the IBCCS bit in BCR2 of the bus controller makes the DMAC release the bus to pass the bus to another bus master. In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). The DMAC is always operated in cycle stealing mode. Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends. Figure 7.14 shows an example of timing in burst mode. Bus cycle CPU CPU DMAC DMAC DMAC CPU CPU No CPU cycle generated Figure 7.14 Example of Timing in Burst Mode Rev.2.00 Oct. 16, 2007 Page 223 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.5 Extended Repeat Area Function The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer. Figure 7.15 shows an example of the extended repeat area operation. Rev.2.00 Oct. 16, 2007 Page 224 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 ... H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Repeat An interrupt request by extended repeat area overflow can be generated. Figure 7.15 Example of Extended Repeat Area Operation When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. Figure 7.16 shows examples when the extended repeat area function is used in block transfer mode. When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in DTCR = 5). External memory Area specified 1st block 2nd block by DSAR transfer transfer H'23FFFE H'23FFFF H'240000 H'240000 H'240000 H'240000 H'240001 H'240001 H'240001 H'240001 Interrupt H'240002 H'240002 H'240002 request H'240003 H'240003 H'240003 generated H'240004 H'240004 H'240004 H'240005 H'240005 H'240005 H'240006 H'240006 H'240006 H'240007 H'240007 H'240007 Block transfer H'240008 continued H'240009 Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode Rev.2.00 Oct. 16, 2007 Page 225 of 916 REJ09B0381-0200 ... ... ... Section 7 DMA Controller (DMAC) 7.5.6 Address Update Function using Offset The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 7.17 shows the address update method. External memory External memory External memory ±0 ±1, 2, or 4 + offset Address not updated Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4 Offset is added to address (addresses are not continuous) (c) Offset addition (a) Address fixed Figure 7.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size. Rev.2.00 Oct. 16, 2007 Page 226 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. (1) Basic Transfer Using Offset Figure 7.18 shows a basic operation of a transfer using the offset addition. Data 1 Address A1 Transfer Offset Data 1 Data 2 Data 3 Data 4 Data 5 : Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4 Data 2 Address A2 = Address A1 + Offset : : : Offset Data 3 Address A3 = Address A2 + Offset Offset Transfer source: Transfer destination: Data 4 Address A4 = Address A3 + Offset Offset addition Increment by 4 (longword) Offset Data 5 Address A5 = Address A4 + Offset Figure 7.18 Operation of Offset Addition In figure 7.18, the offset addition is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means that data at the address which is away from the previous transfer source address by the offset is read from. The data read from the address away from the previous address is written to the consecutive area in the destination side. Rev.2.00 Oct. 16, 2007 Page 227 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) XY Conversion Using Offset Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode. Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 13 Data 10 Data 14 Data 11 Data 15 Data 12 Data 16 1st transfer 2nd transfer 3rd transfer 4th transfer Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 Transfer 1st transfer Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 2nd transfer Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 Transfer source addresses changed by CPU 3rd transfer Data 1 Transfer Data 5 Data 9 Data 13 Transfer source Data 2 addresses Data 6 changed by CPU Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Interrupt Data 16 request generated Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 Offset Address initialized 1st transfer Address initialized Offset 2nd transfer Offset 3rd transfer Interrupt request generated 4th transfer Interrupt request generated Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 7.19, the source address side is specified to the repeat area by DACR and the offset addition is selected. The offset value is set to 4 × data access size (when the data access size is longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address. A repeat size end interrupt is requested when the repeat size of transfers is completed. When a transfer starts, the transfer source address is added to the offset every time data is transferred. The transfer data is written to the destination continuous addresses. When data 4 is transferred meaning that the repeat size of transfers is completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are written to the address of data 5 by the CPU (when the data access size is longword, write the data 1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when the transfer is stopped. Accordingly, operations are repeated and the transfer source data is transposed to the destination area (XY conversion). Rev.2.00 Oct. 16, 2007 Page 228 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Figure 7.29 shows a flowchart of the XY conversion. Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt Set DTE bit to 1 Receives transfer request Transfers data Decrements transfer count and repeat size No Transfer count = 0? Yes Set transfer source address + 4 (Longword transfer) End : User operation : DMAC operation No Repeat size = 0? Yes Initializes transfer source address Generates repeat size end interrupt request Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode (3) Offset Subtraction When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction. Rev.2.00 Oct. 16, 2007 Page 229 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.7 Register during DMA Transfer The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. Rev.2.00 Oct. 16, 2007 Page 230 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and not affected by the address update. While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. Rev.2.00 Oct. 16, 2007 Page 231 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to. (5) DTE Bit in DMDR Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows: • When the total size of transfers is completed • When a transfer is completed by a transfer size error interrupt • When a transfer is completed by a repeat size end interrupt • When a transfer is completed by an extended repeat area overflow interrupt • When a transfer is stopped by an NMI interrupt • When a transfer is stopped by and address error • Reset state • Hardware standby mode • When a transfer is stopped by writing 0 to the DTE bit Rev.2.00 Oct. 16, 2007 Page 232 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0. Figure 7.21 show the procedure for changing the register settings for the channel being transferred. Changing register settings of channel during operation Write 0 to DTE bit [1] [1] Write 0 to the DTE bit in DMDR. [2] Read the DTE bit. [3] Confirm that DTE = 0. DTE = 1 indicates that DMA is transferring. [4] Write the desired values to the registers. Read DTE bit [2] [3] No DTE = 0? Yes Change register settings End of changing register settings [4] Figure 7.21 Procedure for Changing Register Setting for Channel Being Transferred (6) ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. Rev.2.00 Oct. 16, 2007 Page 233 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.8, Interrupt Sources. (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.8, Interrupt Sources. Rev.2.00 Oct. 16, 2007 Page 234 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.8 Priority of Channels The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.6 shows the priority levels among the DMAC channels. Table 7.6 Channel Channel 0 Channel 1 Channel 2 Channel 3 Low Priority among DMAC Channels Priority High The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched. Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2. Channel 0 transfer Bφ Channel 1 transfer Channel 2 transfer Address bus DMAC operation Wait Channel 0 Channel 0 Bus released Channel 1 Bus released Channel 2 Wait Channel 1 Channel 2 Channel 0 Request cleared Channel 1 Request cleared Request Selected retained Selected Request cleared Channel 2 Request Not Request retained selected retained Figure 7.22 Example of Timing for Channel Priority Rev.2.00 Oct. 16, 2007 Page 235 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.9 DMA Basic Bus Cycle Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follow the bus controller settings. CPU cycle T1 Bφ DMAC cycle (one word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Source address Address bus RD Destination address LHWR LLWR Figure 7.23 Example of Bus Timing of DMA Transfer Rev.2.00 Oct. 16, 2007 Page 236 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.10 (1) Bus Cycles in Dual Address Mode Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle Bφ DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle Address bus RD LHWR, LLWR TEND Bus released Bus released Bus released Last transfer cycle Bus released Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary. Rev.2.00 Oct. 16, 2007 Page 237 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle Bφ Address bus RD LHWR LLWR TEND 4m + 1 4m + 2 4m + 4 4n 4n +2 4m + 5 4m + 6 4m + 8 4n + 4 4n + 6 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle Bφ Address bus RD LHWR LLWR TEND 4m 4m + 2 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) Rev.2.00 Oct. 16, 2007 Page 238 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle Bφ Address bus DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle RD LHWR, LLWR TEND Bus released Burst transfer Last transfer cycle Bus released Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access Rev.2.00 Oct. 16, 2007 Page 239 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bφ Address bus RD LHWR, LLWR TEND Bus released Block transfer Bus released Last block transfer cycle Bus released Figure 7.28 Example of Transfer in Block Transfer Mode Rev.2.00 Oct. 16, 2007 Page 240 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Falling Edge Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released Bφ Bus released Bus released DREQ Address bus DMA operation Wait Transfer source Transfer destination Transfer source Transfer destination Read Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge Rev.2.00 Oct. 16, 2007 Page 241 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released Bφ Bus released Bus released DREQ Address bus DMA operation Wait Read Transfer source Transfer destination Transfer source Transfer destination Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Min. of 3 cycles Duration of transfer request disabled Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level Rev.2.00 Oct. 16, 2007 Page 242 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Figure 7.31 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. 1-block transfer Bus released Bφ DMA read cycle DMA write cycle Bus released 1-block transfer DMA read cycle DMA write cycle Bus released DREQ Address bus DMA operation Wait Read Transfer source Transfer destination Transfer source Transfer destination Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level Rev.2.00 Oct. 16, 2007 Page 243 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (6) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.32 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA read cycle DMA read cycle DMA read cycle Bus released Bus released Bus released Bφ DREQ Transfer source Transfer destination Transfer source Transfer destination Address bus Channel Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed Transfer request enable resumed [1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 Rev.2.00 Oct. 16, 2007 Page 244 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.5.11 (1) Bus Cycles in Single Address Mode Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). DMA read cycle Bφ Address bus RD DACK TEND Bus released Bus released Bus released Bus Last transfer Bus released released cycle DMA read cycle DMA read cycle DMA read cycle Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) Rev.2.00 Oct. 16, 2007 Page 245 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). DMA write cycle Bφ DMA write cycle DMA write cycle DMA write cycle Address bus LLWR DACK TEND Bus released Bus released Bus released Last transfer Bus Bus cycle released released Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) Rev.2.00 Oct. 16, 2007 Page 246 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (3) Activation Timing by DREQ Falling Edge Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the single cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released Bφ DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination DACK DMA operation Wait Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles [1] [2] [3] [4] Min. of 3 cycles [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge Rev.2.00 Oct. 16, 2007 Page 247 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Low Level Figure 7.36 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released Bφ DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus DACK DMA operation Transfer source/ Transfer destination Transfer source/ Transfer destination Wait Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level Rev.2.00 Oct. 16, 2007 Page 248 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.37 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released Bφ DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination Channel Request Duration of transfer request disabled which is extended by NRD Duration of transfer Request request disabled Min. of 3 cycles Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 Rev.2.00 Oct. 16, 2007 Page 249 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.6 DMA Transfer End Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMR is cleared to 0 and the ESIF bit in DMDR is set to 1. • In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size • In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below. • In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes • In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes. (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. Rev.2.00 Oct. 16, 2007 Page 250 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred. (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. Rev.2.00 Oct. 16, 2007 Page 251 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed. 7.7 7.7.1 Relationship among DMAC and Other Bus Masters CPU Priority Control Function over DMAC The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function over DMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. If the priority level of the transfer request masked by the CPU priority control function is changed or the CPU priority is changed, the transfer request may be received and the transfer is started. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Transfer requests masked are suspended. If a transfer request is suspended, it is cleared by clearing the DTE bit to 0. Rev.2.00 Oct. 16, 2007 Page 252 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.7.2 Bus Arbitration among DMAC and Other Bus Masters When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU, access to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 6, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and a refresh cycle or an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a cycle of refresh or external bus release is inserted by the BSC (when the CPU external access does not have priority over a DMAC transfer, the transfer is not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and an external bus release cycle may be performed at the same time. Rev.2.00 Oct. 16, 2007 Page 253 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.8 Interrupt Sources The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.7 shows interrupt sources and priority. Table 7.7 Abbr. DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMEEND0 Interrupt Sources and Priority Interrupt Sources Transfer end interrupt by channel 0 transfer counter Transfer end interrupt by channel 1 transfer counter Transfer end interrupt by channel 2 transfer counter Transfer end interrupt by channel 3 transfer counter Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address Priority High DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels is determined by the interrupt controller as shown in table 7.7. For details, see section 5, Interrupt Controller. Rev.2.00 Oct. 16, 2007 Page 254 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 7.38 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 7.39 shows procedure to resume the transfer by clearing a interrupt. Rev.2.00 Oct. 16, 2007 Page 255 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) TSEIE bit DMAC is activated in transfer size error state RPTIE bit DMAC is activated after BKSZ bits are changed from 1 to 0 SARIE bit Extended repeat area overflow occurs in source address DARIE bit Extended repeat area overflow occurs in destination address DTIE bit DTIF bit [Setting condition] When DTCR becomes 0 and transfer ends ESIE bit ESIF bit Transfer escape end interrupt Transfer end interrupt Setting condition is satisfied Figure 7.38 Interrupt and Interrupt Sources Transfer end interrupt handling routine Consecutive transfer processing Registers are specified DTE bit is set to 1 Interrupt handling routine ends (RTE instruction executed) [1] [2] [3] Transfer resumed after interrupt handling routine DTIF and ESIF bits are cleared to 0 Interrupt handling routine ends Registers are specified DTE bit is set to 1 Transfer resume processing end [4] [5] [6] [7] Transfer resume processing end [1] Specify the values in the registers such as transfer counter and address register. [2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or ESIF bit in DMDR to 0 and an interrupt source is cleared. [3] End the interrupt handling routine by the RTE instruction. [4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit. [5] Complete the interrupt handling routine and clear the interrupt mask. [6] Specify the values in the registers such as transfer counter and address register. [7] Set the DTE bit to 1 to resume DMA operation. Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source Rev.2.00 Oct. 16, 2007 Page 256 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) 7.9 Notes on Usage 1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary. ⎯ TENDE bit in DMDR is 1 (the TEND signal output enabled) ⎯ DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer. Rev.2.00 Oct. 16, 2007 Page 257 of 916 REJ09B0381-0200 Section 7 DMA Controller (DMAC) Rev.2.00 Oct. 16, 2007 Page 258 of 916 REJ09B0381-0200 Section 8 I/O Ports Section 8 I/O Ports Table 8.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Ports D to K have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. All of the I/O ports can drive a single TTL load and capacitive loads up to 30 pF. All of the I/O ports can drive Darlington transistors when functioning as output ports. Schmitt-trigger inputs are enabled when a port is used as the IRQ, TPU, and IIC inputs. Table 8.1 Port Functions SchmittTrigger Input*1 IRQ7-A, SCL0 IRQ6-A, SDA0 IRQ5-A, SCL1 IRQ4-A, SDA1 IRQ3-A IRQ2-A IRQ1-A IRQ0-A Input Pull-up MOS Function ⎯ OpenDrain Output Function *2 *2 *2 *2 ⎯ Function Port Description Bit I/O P17/SCL0 P16/SDA0 P15/SCL1 P14/SDA1 P13 P12/SCK2 P11 P10 Input IRQ7-A/ ADTRG1 IRQ6-A IRQ5-A IRQ4-A/ DREQ1_A IRQ3-A/ ADTRG0 IRQ2-A IRQ1-A/ RxD2 IRQ0-A/ DREQ0_A Output ⎯ DACK1_A TEND1_A ⎯ ⎯ DACK0_A TEND0_A TxD2 Port 1 General I/O port 7 also functioning as interrupt inputs, 6 SCI I/Os, DMAC I/Os, A/D 5 converter inputs, and IIC2 I/Os 4 3 2 1 0 Rev.2.00 Oct. 16, 2007 Page 259 of 916 REJ09B0381-0200 Section 8 I/O Ports Function Port Description Bit I/O P27/ TIOCB5 P26/ TIOCA5 P25/ TIOCA4/ P24/ TIOCB4 P23/ TIOCD3/ SCS_1 P22/ TIOCC3/ SSCK_1 P21/ TIOCA3/ SSI_1 P20/ TIOCB3/ SCK0/ SSO_1 P37/ TIOCB2 P36/ TIOCA2 P35/ TIOCB1 P34/ TIOCA1 P33/ TIOCD0 P32/ TIOCC0 P31/ TIOCB0 P30/ TIOCA0 Input ⎯ ⎯ ⎯ ⎯ ⎯ Output ⎯ ⎯ ⎯ ⎯ ⎯ SchmittTrigger Input *1 TIOCB5 TIOCA5 TIOCA4 TIOCB4 TIOCD3 Input Pull-up MOS Function ⎯ OpenDrain Output Function O Port 2 General I/O port 7 also functioning as interrupt inputs, 6 TPU I/Os, SCI I/Os, and SSU* 5 I/Os 4 3 *3 2 ⎯ TxD0 TIOCC3 *3 1 RxD0 ⎯ TIOCA3 *3 0 ⎯ ⎯ TIOCB3 *3 Port 3 General I/O port also functioning as SDG outputs and TPU I/Os 7 6 5 4 3 2 1 0 TCLKD-A ⎯ TCLKC-A ⎯ TCLKB-A TCLKA-A ⎯ ⎯ SGOUT_3 SGOUT_2 SGOUT_1 SGOUT_0 ⎯ ⎯ ⎯ ⎯ TIOCB2, TCLKD-A TIOCA2 TIOCB1, TCLKC-A TIOCA1 TIOCD0, TCLKB-A TIOCC0, TCLKA-A TIOCB0 TIOCA0 ⎯ ⎯ Rev.2.00 Oct. 16, 2007 Page 260 of 916 REJ09B0381-0200 Section 8 I/O Ports Function Port Description Bit 7 6 5 4 3 2 1 0 Port 5 General I/O port also functioning as A/D converter inputs and D/A converter outputs 7 6 5 4 3 2 1 0 Port 6 General I/O port also functioning as SCI I/Os, DMAC I/Os, interrupt inputs, RCAN-ET I/Os, 16-bit PWM outputs, and HUDI inputs 7 6 5 4 3 I/O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P67 P66 P65 P64 P63 Input P47/AN11 P46/AN10 P45/AN9 P44/AN8 P43/AN15 P42/AN14 P41/AN13 P40/AN12 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 IRQ15-B IRQ14-B/ CRx_1 IRQ13-B IRQ12-B/ CRx_0 IRQ11-B/ DREQ3_B/ TMS IRQ10-B/ TRST RxD4/ IRQ9-B IRQ8-B/ DREQ2_B Output ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DA1 DA0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CTx_1 SchmittTrigger Input *1 Input Pull-up MOS Function OpenDrain Output Function Port 4 General I/O port also functioning as A/D converter inputs ⎯ ⎯ ⎯ IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B ⎯ ⎯ ⎯ CTx_0/ DACK3_B TEND3_B PWM3_2 2 1 0 P62/SCK4 P61 P60 DACK2_B TEND2_B TxD4 IRQ10-B IRQ9-B IRQ8-B Rev.2.00 Oct. 16, 2007 Page 261 of 916 REJ09B0381-0200 Section 8 I/O Ports Function Port Description Bit 7 6 5 4 3 2 1 0 Port D General I/O port also functioning as address outputs 7 6 5 4 3 2 1 0 Port E General I/O port also functioning as address outputs 7 6 5 4 3 2 1 0 I/O ⎯ PA6 PA5 PA4 PA3 PA2 PA1 PA0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Input PA7 ⎯ ⎯ ⎯ ⎯ TCK TDI ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Output Bφ AS RD LHWR LLWR PWM2_2 PWM1_2 PWM0_2/ TDO A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 SchmittTrigger Input *1 ⎯ Input Pull-up MOS Function ⎯ OpenDrain Output Function ⎯ Port A General I/O port also functioning as bus control I/Os, 16-bit PWM outputs, and H-UDI I/Os ⎯ O ⎯ ⎯ O ⎯ Rev.2.00 Oct. 16, 2007 Page 262 of 916 REJ09B0381-0200 Section 8 I/O Ports Function Port Description Bit I/O PF7/SCK5 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 PI7/D15 PI6/D14 PI5/D13 PI4/D12 PI3/D11/ SCS_0 PI2/D10/ SSCK_0 PI1/D9/ SSI_0 PI0/D8/ SSO_0 Input ⎯ RxD5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Output A23/ PWM3_1 A22/ PWM2_1 TxD5/A21/ PWM1_1 A20/ PWM0_1 A19/ PWM3_0 A18/ PWM2_0 A17/ PWM1_0 A16/ PWM0_0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SchmittTrigger Input *1 ⎯ Input Pull-up MOS Function O*4 OpenDrain Output Function O*4 Port F General I/O port 7 also functioning as address output, 6 SCI I/O, and 16bit PWM output 5 4 3 2 1 0 Port H General I/O port also functioning as bi-directional data bus 7 6 5 4 3 2 1 0 Port I General I/O port also functioning as bi-directional data bus and SSU* I/O 7 6 5 4 3 2 1 0 ⎯ O ⎯ ⎯ O ⎯ O*5 O*5 O*5 O*5 *3 *3 *3 *3 Rev.2.00 Oct. 16, 2007 Page 263 of 916 REJ09B0381-0200 Section 8 I/O Ports Function Port Description Bit 7 6 5 4 3 2 1 0 Port K General I/O port also functioning as motor control PWM outputs 7 6 5 4 3 2 1 0 I/O PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Input ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Output PWM1H PWM1G PWM1F PWM1E PWM1D PWM1C PWM1B PWM1A PWM2H PWM2G PWM2F PWM2E PWM2D PWM2C PWM2B PWM2A SchmittTrigger Input *1 ⎯ Input Pull-up MOS Function O*4 OpenDrain Output Function ⎯ Port J General I/O port also functioning as motor control PWM outputs ⎯ O*4 ⎯ Notes: 1. Pins other than Schmitt-trigger input pin are CMOS input pins. 2. Open drain is valid only when the IIC function is used. 3. Open drain can be set only when the SSU (Synchronous Serial communication Unit) is used. 4. Input pull-up and open drain cannot be set when the PWM is used. 5. Input pull-up cannot be set when the SSU (Synchronous Serial communication Unit) is used. * SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 264 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.1 Register Descriptions Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Number of Pins 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Registers DDR O O O ⎯ ⎯ O O O O O O O O O DR O O O ⎯ ⎯ O O O O O O O O O PORT O O O O O O O O O O O O O O ICR O O O O O O O O O O O O O O PCR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O O O O O O O ODR ⎯ O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ ⎯ Port Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port D Port E Port F Port H Port I Port J Port K Legend: O: Register exists ⎯: No register exists Rev.2.00 Oct. 16, 2007 Page 265 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.1.1 Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A, D, E, F, H, I, J, and K) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. The initial values of the port A change according to the start-up mode. Bit Bit Name Initial Value R/W 7 Pn7DDR 0 W 6 Pn6DDR 0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 2 Pn2DDR 0 W 1 Pn1DDR 0 W 0 Pn0DDR 0 W Table 8.3 Startup Mode and Initial Value Startup Mode Port Port A Other ports External Extended Mode H'80 Single-Chip Mode H'00 H'00 8.1.2 Data Register (PnDR) (n = 1, 2, 3, 6, A, D, E, F, H, I, J, and K) DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. Bit Bit Name Initial Value R/W 7 Pn7DR 0 R/W 6 Pn6DR 0 R/W 5 Pn5DR 0 R/W 4 Pn4DR 0 R/W 3 Pn3DR 0 R/W 2 Pn2DR 0 R/W 1 Pn1DR 0 R/W 0 Pn0DR 0 R/W Rev.2.00 Oct. 16, 2007 Page 266 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, E, F, H, I, J, and K) PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin state. Bit Bit Name Initial Value R/W 7 Pn7 Undefined R 6 Pn6 Undefined R 5 Pn5 Undefined R 4 Pn4 Undefined R 3 Pn3 Undefined R 2 Pn2 Undefined R 1 Pn1 Undefined R 0 Pn0 Undefined R 8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, E, F, H, I, J, and K) ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. Rev.2.00 Oct. 16, 2007 Page 267 of 916 REJ09B0381-0200 Section 8 I/O Ports If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, an IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00. Bit Bit Name Initial Value R/W 7 Pn7ICR 0 R/W 6 Pn6ICR 0 R/W 5 Pn5ICR 0 R/W 4 Pn4ICR 0 R/W 3 Pn3ICR 0 R/W 2 Pn2ICR 0 R/W 1 Pn1ICR 0 R/W 0 Pn0ICR 0 R/W 8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, and H to K) PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. The initial value of PCR is H'00. Bit Bit Name Initial Value R/W 7 Pn7PCR 0 R/W 6 Pn6PCR 0 R/W 5 Pn5PCR 0 R/W 4 Pn4PCR 0 R/W 3 Pn3PCR 0 R/W 2 Pn2PCR 0 R/W 1 Pn1PCR 0 R/W 0 Pn0PCR 0 R/W Rev.2.00 Oct. 16, 2007 Page 268 of 916 REJ09B0381-0200 Section 8 I/O Ports Table 8.4 Port Port D Input Pull-Up MOS State Pin State Address output Port output Port input OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF Reset Hardware Standby Mode Software Standby Mode OFF OFF ON/OFF Other Operation Port E Address output Port output Port input Port F Address output Port output Port input Port H Data input/output Port output Port input Port I Data input/output Port output Port input Port J Peripheral module output Port output Port input Port K Peripheral module output Port output Port input Legend: OFF: ON/OFF: The input pull-up MOS is always off. If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off. Rev.2.00 Oct. 16, 2007 Page 269 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Bit Bit Name Initial Value R/W 7 Pn7ODR 0 R/W 6 Pn6ODR 0 R/W 5 Pn5ODR 0 R/W 4 Pn4ODR 0 R/W 3 Pn3ODR 0 R/W 2 Pn2ODR 0 R/W 1 Pn1ODR 0 R/W 0 Pn0ODR 0 R/W Rev.2.00 Oct. 16, 2007 Page 270 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: SCL0_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Each port output signal's valid setting is shown below. For details on the corresponding output signals, see the register description of each peripheral module. For the I/O port pins whose initial values change according to the start-up mode, the initial values are indicated as “initial value E” for the start up in external expanded mode (expanded mode with on-chip ROM) and as “initial value S” for the start up in single-chip mode. 8.2.1 (1) Port 1 P17/SCL0/IRQ7-A/ADTRG1 Setting IIC2_0 Module Name IIC2_0 I/O port Note: * Pin Function SCL0 I/O P17 output P17 input (initial value) When specified as I/O port: 1 SCL0_OE* 1 0 0 I/O Port P17DDR ⎯ 1 0 (2) P16/SDA0/IRQ6-A/DACK1_A Setting DMAC_1 IIC2_0 ⎯ 1 0 0 I/O Port P16DDR ⎯ ⎯ 1 0 DACK1_A_OE SDA0_OE* 1 0 0 0 Module Name DMAC_1 IIC2_0 I/O port Note: * Pin Function DACK1_A output SDA0 I/O P16 output P16 input (initial value) When specified as I/O port: 1 Rev.2.00 Oct. 16, 2007 Page 271 of 916 REJ09B0381-0200 Section 8 I/O Ports (3) P15/SCL1/IRQ5-A/TEND1_A Setting DMAC_1 IIC2_0 ⎯ 1 0 0 I/O Port P15DDR ⎯ ⎯ 1 0 TEND1_A_OE SCL1_OE* 1 0 0 0 Module Name DMAC_1 IIC2_0 I/O port Note: * Pin Function TEND1_A output SCL1 I/O P15 output P15 input (initial value) When specified as I/O port: 1 (4) P14/SDA1/IRQ4-A/DREQ1_A Setting IIC2_1 I/O Port P14DDR ⎯ 1 0 Module Name IIC2_1 I/O port Note: * Pin Function SDA1 I/O P14 output P14 input (initial value) SDA1_OE* 1 0 0 When specified as I/O port: 1 (5) P13/IRQ3-A/ADTRG0_A Setting I/O Port Module Name I/O port Pin Function P13 output P13 input (initial value) P13DDR 1 0 Rev.2.00 Oct. 16, 2007 Page 272 of 916 REJ09B0381-0200 Section 8 I/O Ports (6) P12/SCK2/IRQ2-A/DACK0_A Setting DMAC_0 SCI_2 ⎯ 1 0 0 I/O Port P12DDR ⎯ ⎯ 1 0 DACK0_A_OE SCK2_OE 1 0 0 0 Module Name DMAC_0 SCI_2 I/O port Pin Function DACK0_A output SCK2 output P12 output P12 input (initial value) (7) P11/RxD2/IRQ1-A/TEND0_A Setting DMAC_0 I/O Port P11DDR ⎯ 1 0 TEND0_A_OE 1 0 0 Module Name DMAC_0 I/O port Pin Function TEND0_A output P11 output P11 input (initial value) (8) P10/TxD2/IRQ0-A/DREQ0_A Setting SCI_2 I/O Port P10DDR ⎯ 1 0 Module Name SCI_2 I/O port Pin Function TxD2 output P10 output P10 input (initial value) TxD2_OE 1 0 0 Rev.2.00 Oct. 16, 2007 Page 273 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.2 (1) Port 2 P27/TIOCB5 Setting TPU_5 I/O Port P27DDR ⎯ 1 0 Module Name TPU_5 I/O port Pin Function TIOCB5 output P27 output P27 input (initial value) TIOCB5_OE 1 0 0 (2) P26/TIOCA5 Setting TPU_5 I/O Port P26DDR ⎯ 1 0 Module Name TPU_5 I/O port Pin Function TIOCA5 output P26 output P26 input (initial value) TIOCA5_OE 1 0 0 (3) P25/TIOCA4 Setting TPU_4 I/O Port P25DDR ⎯ 1 0 Module Name TPU_4 I/O port Pin Function TIOCA4 output P25 output P25 input (initial value) TIOCA4_OE 1 0 0 Rev.2.00 Oct. 16, 2007 Page 274 of 916 REJ09B0381-0200 Section 8 I/O Ports (4) P24/TIOCB4 Setting TPU_4 I/O Port P24DDR ⎯ 1 0 Module Name TPU_4 I/O port Pin Function TIOCB4 output P24 output P24 input (initial value) TIOCB4_OE 1 0 0 (5) P23/TIOCD3/SCS_1 Setting SSU*_1 TPU_3 TIOCD3_OE ⎯ 1 0 0 I/O Port P23DDR ⎯ ⎯ 1 0 SCS_1_OE 1 0 0 0 Module Name SSU*_1 TPU_3 I/O port Note: * Pin Function SCS_1 output TIOCD3 output P23 output P23 input (initial value) SSU: Synchronous Serial communication Unit (6) P22/TIOCC3/TxD0/SSCK_1 Setting SSU*_1 TPU_3 TIOCC3_OE ⎯ 1 0 0 0 SCI_0 TxD0_OE ⎯ ⎯ 1 0 0 I/O Port P22DDR ⎯ ⎯ ⎯ 1 0 Module Name SSU*_1 TPU_3 SCI_0 I/O port Note: * Pin Function SSCK_1 output TIOCC3 output TxD0 output P22 output P22 input (initial value) SSCK_1_OE 1 0 0 0 0 SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 275 of 916 REJ09B0381-0200 Section 8 I/O Ports (7) P21/TIOCA3/RxD0/SSI_1 Setting SSU*_1 TPU_3 TIOCA3_OE ⎯ 1 0 0 I/O Port P21DDR ⎯ ⎯ 1 0 Module Name SSU*_1 TPU_3 I/O port Note: * Pin Function SSI_1 output TIOCA3 output P21 output P21 input (initial value) SSI_1_OE 1 0 0 0 SSU: Synchronous Serial communication Unit (8) P20/TIOCB3/SCK0/SSO_1 Setting SSU*_1 TPU_3 TIOCB3_OE ⎯ 1 0 0 0 SCI_0 ⎯ ⎯ 1 0 0 I/O Port ⎯ ⎯ ⎯ 1 0 Module Name SSU*_1 TPU_3 SCI_0 I/O port Note: * Pin Function SSO_1 output TIOCB3 output SCK0 output P20 output P20 input (initial value) SSO_1_OE 1 0 0 0 0 SCK0_OE P20DDR SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 276 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.3 (1) Port 3 P37/TIOCB2/TCLKD-A/SGOUT_3 Setting SDG_3 TPU_2 TIOCB2_OE ⎯ 1 0 0 I/O Port P37DDR ⎯ ⎯ 1 0 Module Name SDG_3 TPU_2 I/O port Pin Function SGOUT_3 output TIOCB2 output P37 output P37 input (initial value) SGOUT_3_OE 1 0 0 0 (2) P36/TIOCA2/SGOUT_2 Setting SDG_2 TPU_2 TIOCA2_OE ⎯ 1 0 0 I/O Port P36DDR ⎯ ⎯ 1 0 Module Name SDG_2 TPU_2 I/O port Pin Function SGOUT_2 output TIOCA2 output P36 output P36 input (initial value) SGOUT_2_OE 1 0 0 0 (3) P35/TIOCB1/TCLKC-A/SGOUT_1 Setting SDG_1 TPU_1 TIOCB1_OE ⎯ 1 0 0 I/O Port P35DDR ⎯ ⎯ 1 0 Module Name SDG_1 TPU_1 I/O port Pin Function SGOUT_1 output TIOCB1 output P35 output P35 input (initial value) SGOUT_1_OE 1 0 0 0 Rev.2.00 Oct. 16, 2007 Page 277 of 916 REJ09B0381-0200 Section 8 I/O Ports (4) P34/TIOCA1/SGOUT_0 Setting SDG_0 TPU_1 TIOCA1_OE ⎯ 1 0 0 I/O Port P34DDR ⎯ ⎯ 1 0 Module Name SDG_0 TPU_1 I/O port Pin Function SGOUT_0 output TIOCA1 output P34 output P34 input (initial value) SGOUT_0_OE 1 0 0 0 (5) P33/TIOCD0/TCLKB-A Setting TPU_0 I/O Port P33DDR ⎯ 1 0 Module Name TPU_0 I/O port Pin Function TIOCD0 output P33 output P33 input (initial value) TIOCD0_OE 1 0 0 (6) P32/TIOCC0/TCLKA-A Setting TPU_0 I/O Port P32DDR ⎯ 1 0 Module Name TPU_0 I/O port Pin Function TIOCC0 output P32 output P32 input (initial value) TIOCC0_OE 1 0 0 Rev.2.00 Oct. 16, 2007 Page 278 of 916 REJ09B0381-0200 Section 8 I/O Ports (7) P31/TIOCB0 Setting TPU_0 I/O Port P31DDR ⎯ 1 0 Module Name TPU_0 I/O port Pin Function TIOCB0 output P31 output P31 input (initial value) TIOCB0_OE 1 0 0 (8) P30/TIOCA0 Setting TPU_0 I/O Port P30DDR ⎯ 1 0 Module Name TPU_0 I/O port Pin Function TIOCA0 output P30 output P30 input (initial value) TIOCA0_OE 1 0 0 8.2.4 (1) Port 5 P57/AN7/DA1 Pin Function DA1 output Module Name D/A (2) P56/AN6/DA0 Pin Function DA0 output Module Name D/A Rev.2.00 Oct. 16, 2007 Page 279 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.5 (1) Port 6 P67/IRQ15-B/CTx_1 Setting RCAN-ET_1 I/O Port P67DDR ⎯ 1 0 Module Name RCAN-ET_1 I/O port Pin Function CTx_1 output P67 output P67 input (initial value) CTx_1_OE 1 0 0 (2) P66/IRQ14-B/CRx_1 Setting I/O Port Module Name I/O port Pin Function P66 output P66 input (initial value) P66DDR 1 0 (3) P65/IRQ13-B/CTx_0/DACK3_B Setting DMAC_3 RCAN-ET_0 CTx_0_OE 0 1 0 0 I/O Port P65DDR ⎯ ⎯ 1 0 DACK3_B_OE 1 0 0 0 Module Name DMAC_3 RCAN-ET_0 I/O port Pin Function DACK3_B output CTx_0 output P65 output P65 input (initial value) Rev.2.00 Oct. 16, 2007 Page 280 of 916 REJ09B0381-0200 Section 8 I/O Ports (4) P64/IRQ12-B/CRx_0/TEND3_B Setting DMAC_3 I/O Port P64DDR ⎯ 1 0 TEND3_B_OE 1 0 0 Module Name DMAC_3 I/O port Pin Function TEND3_B output P64 output P64 input (initial value) (5) P63/IRQ11-B/PWM3_2/TMS/DREQ3_B Setting 16-Bit PWM H-UDI HUDI_E ⎯ 1 0 0 I/O Port P63DDR ⎯ ⎯ 1 0 Module Name 16-bit PWM H-UDI I/O port Pin Function PWM3_2 output TMS input P63 output P63 input (initial value) PWM3_2_OE 1 0 0 0 (6) P62/SCK4/IRQ10-B/TRST/DACK2_B Setting DMAC_2 SCI_4 ⎯ 1 0 0 0 H-UDI HUDI_E ⎯ ⎯ 1 0 0 I/O Port P62DDR ⎯ ⎯ ⎯ 1 0 DACK2_B_OE SCK4_OE 1 0 0 0 0 Module Name DMAC_2 SCI_4 H-UDI I/O port Pin Function DACK2_B output SCK4 output TRST input P62 output P62 input (initial value) Rev.2.00 Oct. 16, 2007 Page 281 of 916 REJ09B0381-0200 Section 8 I/O Ports (7) P61/RxD4/IRQ9-B/TEND2_B Setting DMAC_2 I/O Port P61DDR ⎯ 1 0 TEND2_B_OE 1 0 0 Module Name DMAC_2 I/O port Pin Function TEND2_B output P61 output P61 input (initial value) (8) P60/TxD4/IRQ8-B/DREQ2_B Setting SCI_4 I/O Port P60DDR ⎯ 1 0 Module Name SCI_4 I/O port Pin Function TxD4 output P60 output P60 input (initial value) TxD4_OE 1 0 0 8.2.6 (1) Port A PA7/Bφ Setting I/O Port Module Name I/O port Pin Function Bφ output (initial value E) PA7 input (initial value S) PA7DDR 1 0 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Rev.2.00 Oct. 16, 2007 Page 282 of 916 REJ09B0381-0200 Section 8 I/O Ports (2) PA6/AS Setting Bus Controller I/O Port PA6DDR ⎯ 1 0 Module Name Bus controller I/O port Pin Function PA6 output PA6 input (initial value S) AS_OE 0 0 AS output* (initial value E) 1 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Note: * Valid in external expanded mode (EXPE = 1) (3) PA5/RD Setting Bus Controller I/O Port PA5DDR ⎯ 1 0 Module Name Bus controller I/O port Pin Function PA5 output PA5 input (initial value S) RD_OE 0 0 RD output* (initial value E) 1 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 283 of 916 REJ09B0381-0200 Section 8 I/O Ports (4) PA4/LHWR Setting Bus Controller I/O Port PA4DDR ⎯ 1 0 LHWR_OE 1 0 0 Module Name Bus controller I/O port Pin Function LHWR output* (initial value E) PA4 output PA4 input (initial value S) Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Note: * Valid in external expanded mode (EXPE = 1) (5) PA3/LLWR Setting Bus Controller I/O Port PA3DDR ⎯ 1 0 LLWR_OE 1 0 0 Module Name Bus controller I/O port Pin Function LLWR output* (initial value E) PA3 output PA3 input (initial value S) Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 284 of 916 REJ09B0381-0200 Section 8 I/O Ports (6) PA2/PWM2_2/TCK Setting 16-Bit PWM H-UDI HUDI_E ⎯ 1 0 0 I/O Port PA2DDR ⎯ ⎯ 1 0 Module Name 16-bit PWM H-UDI I/O port Pin Function PWM2_2 output TCK input PA2 output PA2 input (initial value) PWM2_2_OE 1 0 0 0 (7) PA1/PWM1_2/TDI Setting 16-Bit PWM H-UDI HUDI_E ⎯ 1 0 0 I/O Port PA1DDR ⎯ ⎯ 1 0 Module Name 16-bit PWM H-UDI I/O port Pin Function PWM1_2 output TDI input PA1 output PA1 input (initial value) PWM1_2_OE 1 0 0 0 (8) PA0/PWM0_2/TDO Setting 16-Bit PWM H-UDI HUDI_E ⎯ 1 0 0 I/O Port PA0DDR ⎯ ⎯ 1 0 Module Name 16-bit PWM H-UDI I/O port Pin Function PWM0_2 output TDO output PA0 output PA1 input (initial value) PWM0_2_OE 1 0 0 0 Rev.2.00 Oct. 16, 2007 Page 285 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.7 (1) Port D PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0 Setting I/O Port Module Name Bus controller Pin Function Address output MCU Operating Mode Expanded mode without on-chip ROM Expanded mode with on-chip ROM Single-chip mode* Other than expanded mode without on-chip ROM PDnDDR ⎯ 1 1 0 I/O port PDn output PDn input (initial value) Notes: n = 7 to 0 * In external expanded mode, an address can be output with PDnDDR = 1. 8.2.8 (1) Port E PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8 Setting I/O Port Module Name Bus controller Pin Function Address output MCU Operating Mode PEnDDR I/O port PEn output PEn input (initial value) Expanded mode without ⎯ on-chip ROM Expanded mode with 1 on-chip ROM Single-chip mode* 1 Other than expanded mode without on-chip ROM 0 Notes: n = 7 to 0 * In external expanded mode, an address can be output with PEnDDR = 1. Rev.2.00 Oct. 16, 2007 Page 286 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.9 (1) Port F PF7/A23/PWM3_1/SCK5 Setting 16-Bit PWM I/O Port A23_OE ⎯ ⎯ ⎯ 1 0 0 0 SCI SCK5_OE ⎯ ⎯ ⎯ ⎯ 1 0 0 I/O Port PF7DDR ⎯ ⎯ ⎯ ⎯ ⎯ 1 0 MCU Operating Module Name Mode Expanded mode 16-bit PWM without on-chip Bus controller ROM Other than 16-bit PWM expanded mode Bus controller without on-chip SCI ROM I/O port Pin Function PWM3_1_OE PWM3_1 output 1 A23 output 0 PWM3_1 output 1 A23 output* SCK5 output PF7 output PF7 input (initial value) 0 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) (2) PF6/A22/PWM2_1/RxD5 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM2_1 output A22 output PWM2_1 output A22 output* PF6 output PF6 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF6DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM2_1_OE A22_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 287 of 916 REJ09B0381-0200 Section 8 I/O Ports (3) PF5/A21/PWM1_1/TxD5 Setting 16-Bit PWM I/O Port A21_OE ⎯ ⎯ ⎯ 1 0 0 0 SCI TxD5_OE ⎯ ⎯ ⎯ ⎯ 1 0 0 I/O Port PF5DDR ⎯ ⎯ ⎯ ⎯ ⎯ 1 0 MCU Operating Module Name Pin Function Mode Expanded mode 16-bit PWM without on-chip Bus controller ROM Other than 16-bit PWM expanded mode Bus controller without on-chip SCI ROM I/O port PWM1_1_OE PWM1_1 output 1 A21 output 0 PWM1_1 output 1 A21 output* TxD5 PF5 output PF5 input (initial value) 0 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) (4) PF4/A20/PWM0_1 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM0_1 output A20 output PWM0_1 output A20 output* PF4 output PF4 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF4DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM0_1_OE A20_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 288 of 916 REJ09B0381-0200 Section 8 I/O Ports (5) PF3/A19/PWM3_0 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM3_0 output A19 output PWM3_0 output A19 output* PF3 output PF3 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF3DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM3_0_OE A19_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) (6) PF2/A18/PWM2_0 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM2_0 output A18 output PWM2_0 output A18 output* PF2 output PF2 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF2DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM2_0_OE A18_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 289 of 916 REJ09B0381-0200 Section 8 I/O Ports (7) PF1/A17/PWM1_0 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM1_0 output A17 output PWM1_0 output A17 output* PF1 output PF1 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF1DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM1_0_OE A17_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) (8) PF0/A16/PWM0_0 Setting MCU Operating Mode Expanded mode without on-chip ROM Other than expanded mode without on-chip ROM 16-Bit PWM Module Name 16-bit PWM Bus controller 16-bit PWM Bus controller I/O port Pin Function PWM0_0 output A16 output PWM0_0 output A16 output* PF0 output PF0 input (initial value) I/O Port ⎯ ⎯ ⎯ 1 0 0 I/O Port PF0DDR ⎯ ⎯ ⎯ ⎯ 1 0 PWM0_0_OE A16_OE 1 0 1 0 0 0 Note: * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 290 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.10 (1) Port H PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0 Setting Bus Controller I/O Port PHnDDR ⎯ 1 0 Module Name Bus controller I/O port Pin Function Data I/O* (initial value E) PHn output PHn input (initial value S) 16-Bit Bus Mode 1 0 0 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: n = 7 to 0 * Valid in external expanded mode (EXPE = 1) 8.2.11 (1) Port I PI7/D15, PI6/D14, PI5/D13, PI4/D12 Setting Bus Controller I/O Port PInDDR ⎯ 1 0 Module Name Bus controller I/O port Pin Function Data I/O* (initial value E) PIn output PIn input (initial value S) 16-Bit Bus Mode 1 0 0 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: n = 7 to 4 * Valid in external expanded mode (EXPE = 1) Rev.2.00 Oct. 16, 2007 Page 291 of 916 REJ09B0381-0200 Section 8 I/O Ports (2) PI3/D11/SCS_0 Setting SSU_0* 2 Bus Controller I/O Port 16-Bit Bus Mode ⎯ 1 0 0 PI3DDR ⎯ ⎯ 1 0 Module Name SSU_0* 2 Pin Function SCS_0 output Data I/O* (initial value E) PI3 output PI3 input (initial value S) 1 SCS_0_OE 1 0 0 0 Bus controller I/O port Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external expanded mode (EXPE = 1) 2. When the SSU_0 is used, always access in 8-bit bus mode. SSU: Synchronous Serial communication Unit (3) PI2/D10/SSCK_0 Setting SSU_0* 2 Bus Controller I/O Port 16-Bit Bus Mode ⎯ 1 0 0 PI2DDR ⎯ ⎯ 1 0 Module Name SSU_0* Bus controller I/O port 2 Pin Function SSCK_0 output 1 Data I/O* (initial value E) PI2 output PI2 input (initial value S) SSCK_0_OE 1 0 0 0 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external expanded mode (EXPE = 1) 2. When the SSU_0 is used, always access in 8-bit bus mode. SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 292 of 916 REJ09B0381-0200 Section 8 I/O Ports (4) PI1/D9/SSI_0 2 SSU_0* Module Name SSU_0* Bus controller I/O port 2 Setting Bus Controller I/O Port 16-Bit Bus Mode ⎯ 1 0 0 PI1DDR ⎯ ⎯ 1 0 Pin Function SSI_0 output 1 Data I/O* (initial value E) PI1 output PI1 input (initial value S) SSI_0_OE 1 0 0 0 Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external expanded mode (EXPE = 1) 2. When the SSU_0 is used, always access in 8-bit bus mode. SSU: Synchronous Serial communication Unit (5) PI0/D8/SSO_0 2 SSU_0* Module Name SSU_0* 2 Setting Bus Controller I/O Port 16-Bit Bus Mode ⎯ 1 0 0 PI0DDR ⎯ ⎯ 1 0 Pin Function SSO_0 output Data I/O* (initial value E) PI0 output PI0 input (initial value S) 1 SSO_0_OE 1 0 0 0 Bus controller I/O port Legend: Initial value E: Initial value in external expanded mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external expanded mode (EXPE = 1) 2. When the SSU_0 is used, always access in 8-bit bus mode. SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 293 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.2.12 (1) Port J PJ7/PWM1H, PJ6/PWM1G, PJ5/PWM1F, PJ4/PWM1E, PJ3/PWM1D, PJ2/PWM1C, PJ1/PWM1B, PJ0/PWM1A Setting PWM I/O Port PJnDDR ⎯ 1 0 Module Name PWM I/O port Notes: x = A to H n = 7 to 0 Pin Function PWM1x output PJn output PJn input (initial value) PWM1x_OE 1 0 0 8.2.13 (1) Port K PK7/PWM2H, PK6/PWM2G, PK5/PWM2F, PK4/PWM2E, PK3/PWM2D, PK2/PWM2C, PK1/PWM2B, PK0/PWM2A Setting PWM I/O Port PKnDDR ⎯ 1 0 Module Name PWM I/O port Notes: x = A to H n = 7 to 0 Pin Function PWM2x output PKn output PKn input (initial value) PWM2x_OE 1 0 0 Rev.2.00 Oct. 16, 2007 Page 294 of 916 REJ09B0381-0200 Section 8 I/O Ports Table 8.5 Available Output Signals and Settings in Each Port Output Specification Signal Name Output Signal Name SCL0 SDA0 SCL1 SDA1 Signal Selection Register Settings Peripheral Module Settings ICCRA_0.ICE = 1 DACR_1.AMS = 1, DMDR_1.DACKE = 1 ICCRA_0.ICE = 1 DMDR_1.TENDE = 1 ICCRA_1.ICE = 1 ICCRA_1.ICE = 1 DACR_0.AMS = 1, DMDR_0.DACKE = 1 When SCMR_2.SMIF = 1: SCR_2.TE = 1 or SCR_2.RE = 1 while SMR_2.GM = 0, SCR_2.CKE[1,0] = 01 or while SMR_2.GM = 1 When SCMR_2.SMIF = 0: SCR_2.TE = 1 or SCR_2.RE = 1 while SMR_2.C/A = 0, SCR_2.CKE[1,0] = 01 or while SMR_2.C/A = 1, SCR_2.CKE1 = 0 Port P1 7 6 5 4 3 2 SCL0_OE SDA0_OE SCL1_OE SDA1_OE DACK1_A_OE DACK1_A TEND1_A_OE TEND1_A DACK0_A_OE DACK0_A SCK2_OE SCK2 1 0 P2 7 6 5 4 3 TEND0_A_OE TEND0_A TxD2_OE TIOCB5_OE TIOCA5_OE TIOCA4_OE TIOCB4_OE SCS_1_OE TxD2 TIOCB5 TIOCA5 TIOCA4 TIOCB4 SCS_1 DMDR_0.TENDE = 1 SCR_2.TE = 1 TPU.TIOR_5.IOB3 = 0, TPU.TIOR_5.IOB[1,0] = 01/10/11 TPU.TIOR_5.IOA3 = 0, TPU.TIOR_5.IOA[1,0] = 01/10/11 TPU.TIOR_4.IOA3 = 0, TPU.TIOR_4.IOA[1,0] = 01/10/11 TPU.TIOR_4.IOB3 = 0, TPU.TIOR_4.IOB[1,0] = 01/10/11 SSU.SSCRH_1.CSS1 = 1, SSU.SSCRH_1.CSS0 = 0, or SSU.SSCRH_1.CSS1 = 1, SSU.SSCRH_1.CSS0 = 1 while SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1 TIOCD3_OE 2 SSCK1_OE TIOCC3_OE TxD0_OE 1 SSI1_OE TIOCA3_OE TIOCD3 SSCK_1 TIOCC3 TxD0 SSI_1 TIOCA3 TPU.TMDR_3.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 SSU.SSCRH_1.MSS1 = 1, SSU.SSCRH_1.SCKS = 1 TPU.TMDR_3.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 SCR_0.TE = 1 SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0, SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 Rev.2.00 Oct. 16, 2007 Page 295 of 916 REJ09B0381-0200 Section 8 I/O Ports Signal Selection Register Settings Peripheral Module Settings When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1, or SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_1.SSUMS = 1: SSU.SSER_1.TE = 1 Port P2 0 Output Specification Signal Name SSO1_OE Output Signal Name SSO_1 TIOCB3_OE SCK0_OE TIOCB3 SCK0 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 When SCMR_0.SMIF = 1: SCR_0.TE = 1 or SCR_0.RE = 1 while SMR_0.GM = 0, SCR_0.CKE[1,0] = 01 or while SMR_0.GM = 1 When SCMR_0.SMIF = 0: SCR_0.TE = 1 or SCR_0.RE = 1 while SMR_0.C/A = 0, SCR_0.CKE[1,0] = 01 or while SMR_0.C/A = 1, SCR_0.CKE1 = 0 P3 7 6 5 4 3 2 1 0 SGOUT3_OE TIOCB2_OE SGOUT2_OE TIOCA2_OE SGOUT1_OE TIOCB1_OE SGOUT0_OE TIOCA1_OE TIOCD0_OE TIOCC0_OE TIOCB0_OE TIOCA0_OE SGOUT3 TIOCB2 SGOUT2 TIOCA2 SGOUT1 TIOCB1 SGOUT0 TIOCA1 TIOCD0 TIOCC0 TIOCB0 TIOCA0 SDG3.SGCR1.SGE = 1 TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11 SDG2.SGCR1.SGE = 1 TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11 SDG1.SGCR1.SGE = 1 TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11 SDG0.SGCR1.SGE = 1 TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11 TPU.TMDR_0.BFB = 0, TPU.TIORL_0.IOD3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 TPU.TMDR_0.BFA = 0, TPU.TIORL_0.IOC3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11 TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11 P4 P5 Rev.2.00 Oct. 16, 2007 Page 296 of 916 REJ09B0381-0200 Section 8 I/O Ports Signal Selection Register Settings Peripheral Module Settings RCAN-ET_1.MBCR.MBCRn = 0, RCAN-ET_1.TXRP.TXRn = 1 while RCAN-ET_1.RCANMON.RCANE = 1, RCAN-ET_1.RCANMON.TxSTP = 0 (n = 1 to 15) RCAN-ET_0.MBCR.MBCRn = 0, RCAN-ET_0.TXRP.TXRn = 1 while RCAN-ET_0.RCANMON.RCANE = 1, RCAN-ET_0.RCANMON.TxSTP = 0 (n = 1 to 15) DACR_3.AMS = 1, DMDR_3.DACKE = 1 DMDR_3.TENDE = 1 PWOCR3.OE32 = 1 PSELR2.PGSEL1 = 1 DACR_2.AMS = 1, DMDR_2.DACKE = 1 When SCMR_4.SMIF = 1: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.GM = 0, SCR_4.CKE[1,0] = 01 or while SMR_4.GM = 1 When SCMR_4.SMIF = 0: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.C/A = 0, SCR_4.CKE[1,0] = 01 or while SMR_4.C/A = 1, SCR_4.CKE1 = 0 HUDI_E 1 0 PA 7 6 5 4 3 2 1 0 TxD4_OE Bφ_OE AS_OE RD_OE LHWR_OE LLWR_OE PWM2_2_OE HUDI_E PWM1_2_OE HUDI_E PWM0_2_OE HUDI_E TRST TxD4 Bφ AS RD LHWR LLWR PWM2_2 TCK PWM1_2 TDI PWM0_2 TDO PSELR2.PGSEL1 = 1 DMDR_2.TENDE = 1 SCR_4.TE = 1 PADDR.PA7DDR = 1, SCKCR.POSEL1 = 0 SYSCR.EXPE = 1, PFCR2.ASOE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 PWOCR3.OE22 = 1 PSELR2.PGSEL1 = 1 PWOCR3.OE12 = 1 PSELR2.PGSEL1 = 1 PWOCR3.OE02 = 1 PSELR2.PGSEL1 = 1 TEND2_B_OE TEND2_B Port P6 7 Output Specification Signal Name CTx_1_OE Output Signal Name CTx_1 6 5 CTx_0_OE CTx_0 DACK3_B_OE DACK3_B 4 3 2 TEND3_B_OE TEND3_B PWM3_2_OE HUDI_E SCK4_OE PWM3_2 TMS SCK4 DACK2_B_OE DACK2_B Rev.2.00 Oct. 16, 2007 Page 297 of 916 REJ09B0381-0200 Section 8 I/O Ports Signal Selection Register Settings Peripheral Module Settings SYSCR.EXPE = 1, PDDDR.PD7DDR = 1 SYSCR.EXPE = 1, PDDDR.PD6DDR = 1 SYSCR.EXPE = 1, PDDDR.PD5DDR = 1 SYSCR.EXPE = 1, PDDDR.PD4DDR = 1 SYSCR.EXPE = 1, PDDDR.PD3DDR = 1 SYSCR.EXPE = 1, PDDDR.PD2DDR = 1 SYSCR.EXPE = 1, PDDDR.PD1DDR = 1 SYSCR.EXPE = 1, PDDDR.PD0DDR = 1 SYSCR.EXPE = 1, PEDDR.PE7DDR = 1 SYSCR.EXPE = 1, PEDDR.PE6DDR = 1 SYSCR.EXPE = 1, PEDDR.PE5DDR = 1 SYSCR.EXPE = 1, PEDDR.PE4DDR = 1 SYSCR.EXPE = 1, PEDDR.PE3DDR = 1 SYSCR.EXPE = 1, PEDDR.PE2DDR = 1 SYSCR.EXPE = 1, PEDDR.PE1DDR = 1 SYSCR.EXPE = 1, PEDDR.PE0DDR = 1 PWOCR2.OE31 = 1 SYSCR.EXPE = 1, PFCR4.A23E = 1 When SCMR_5.SMIF = 1: SCR_5.TE = 1 or SCR_5.RE = 1 while SMR_5.GM = 0, SCR_5.CKE[1, 0] = 01, or SMR_5.GM = 1 Port PD 7 6 5 4 3 2 1 0 PE 7 6 5 4 3 2 1 0 PF 7 Output Specification Signal Name A7_OE A6_OE A5_OE A4_OE A3_OE A2_OE A1_OE A0_OE A15_OE A14_OE A13_OE A12_OE A11_OE A10_OE A9_OE A8_OE PWM3_1_OE A23_OE SCK5_OE Output Signal Name A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 PWM3_1 A23 SCK5 When SCMR_5.SMIF = 0: SCR_5.TE = 1 or SCR_5.RE = 1 while SMR_5.C/A = 0, SCR_5.CKE[1, 0] = 01 or SMR_5.C/A = 1, SCR_5.CKE1 = 0 6 5 PWM2_1_OE A22_OE PWM1_1_OE A21_OE TxD5_OE PWM2_1 A22 PWM1_1 A21 TxD5 PWM0_1 A20 PWM3_0 A19 PWOCR2.OE21 = 1 SYSCR.EXPE = 1, PFCR4.A22E = 1 PWOCR2.OE11 = 1 SYSCR.EXPE = 1, PFCR4.A21E = 1 SCR_5.TE = 1 PWOCR2.OE01 = 1 SYSCR.EXPE = 1, PFCR4.A20E = 1 PWOCR1.OE30 = 1 SYSCR.EXPE = 1, PFCR4.A19E = 1 4 3 PWM0_1_OE A20_OE PWM3_0_OE A19_OE Rev.2.00 Oct. 16, 2007 Page 298 of 916 REJ09B0381-0200 Section 8 I/O Ports Signal Selection Register Settings Peripheral Module Settings PWOCR1.OE20 = 1 SYSCR.EXPE = 1, PFCR4.A18E = 1 PWOCR1.OE10 = 1 SYSCR.EXPE = 1, PFCR4.A17E = 1 PWOCR1.OE00 = 1 SYSCR.EXPE = 1, PFCR4.A16E = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 When ABWCR.ABW[H,L]n = 11: SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0, or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 Port PF 2 1 0 PH 7 6 5 4 3 2 1 0 PI 7 6 5 4 3 Output Specification Signal Name PWM2_0_OE A18_OE PWM1_0_OE A17_OE PWM0_0_OE A16_OE D7_E D6_E D5_E D4_E D3_E D2_E D1_E D0_E D15_E D14_E D13_E D12_E SCS0_OE Output Signal Name PWM2_0 A18 PWM1_0 A17 PWM0_0 A16 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 SCS0 D11_E 2 SSCK0_OE D10_E 1 SSI_0_OE D11 SSCK0 D10 SSI0 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 When ABWCR.ABW[H,L]n = 11: SSU.SSCRH_0.MSS1 = 1, SSU.SSCRH_0.SCKS = 1 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 When ABWCR.ABW[H,L]n = 11: SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0, SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 D9_E D9 Rev.2.00 Oct. 16, 2007 Page 299 of 916 REJ09B0381-0200 Section 8 I/O Ports Signal Selection Register Settings Peripheral Module Settings When ABWCR.ABW[H,L]n = 11: When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1: SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1, or SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0: SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 When SSU.SSCRL_0.SSUMS = 1: SSU.SSER_0.TE = 1 Port PI 0 Output Specification Signal Name SSO_0_OE Output Signal Name SSO0 D8_E PJ 7 6 5 4 3 2 1 0 PK 7 6 5 4 3 2 1 0 PWM1H_OE PWM1G_OE PWM1F_OE PWM1E_OE PWM1D_OE PWM1C_OE PWM1B_OE PWM1A_OE PWM2H_OE PWM2G_OE PWM2F_OE PWM2E_OE PWM2D_OE PWM2C_OE PWM2B_OE PWM2A_OE D8 PWM1H PWM1G PWM1F PWM1E PWM1D PWM1C PWM1B PWM1A PWM2H PWM2G PWM2F PWM2E PWM2D PWM2C PWM2B PWM2A SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 PWOCR1.OE1H = 1 PWOCR1.OE1G = 1 PWOCR1.OE1F = 1 PWOCR1.OE1E = 1 PWOCR1.OE1D = 1 PWOCR1.OE1C = 1 PWOCR1.OE1B = 1 PWOCR1.OE1A = 1 PWOCR2.OE2H = 1 PWOCR2.OE2G = 1 PWOCR2.OE2F = 1 PWOCR2.OE2E = 1 PWOCR2.OE2D = 1 PWOCR2.OE2C = 1 PWOCR2.OE2B = 1 PWOCR2.OE2A = 1 Note: SSU: Synchronous Serial communication Unit Rev.2.00 Oct. 16, 2007 Page 300 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.3 Port Function Controller The port function controller incorporates the following registers. • Port function control register 2 (PFCR2) • Port function control register 4 (PFCR4) • Port function control register 9 (PFCR9) 8.3.1 Port Function Control Register 2 (PFCR2) PFCR2 enables/disables the bus control output. Bit Bit Name Initial Value R/W 7 ⎯ 0 R 6 ⎯ 0 R 5 ⎯ 0 R 4 ⎯ 0 R 3 ⎯ 0 R 2 ⎯ 0 R 1 ASOE 1 R/W 0 ⎯ 0 R Bit 7 to 2 Bit Name ⎯ Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 ASOE 1 R/W AS Output Enable Enables/disables the AS output 0: Specifies pin PA6 as I/O port 1: Specifies pin PA6 as AS output pin 0 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev.2.00 Oct. 16, 2007 Page 301 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.3.2 Port Function Control Register 4 (PFCR4) PFCR4 enables/disables the address output. Bit Bit Name Initial Value R/W 7 A23E Undefined* R/W 6 A22E Undefined* R/W 5 A21E Undefined* R/W 4 A20E Undefined* R/W 3 A19E Undefined* R/W 2 A18E Undefined* R/W 1 A17E Undefined* R/W 0 A16E Undefined* R/W Bit 7 Bit Name A23E Initial Value R/W Description Address A23 Enable Enables/disables the address output (A23) 0: Disables the A23 output 1: Enables the A23 output Undefined* R/W 6 A22E Undefined* R/W Address A22 Enable Enables/disables the address output (A22) 0: Disables the A22 output 1: Enables the A22 output 5 A21E Undefined* R/W Address A21 Enable Enables/disables the address output (A21) 0: Disables the A21 output 1: Enables the A21 output 4 A20E Undefined* R/W Address A20 Enable Enables/disables the address output (A20) 0: Disables the A20 output 1: Enables the A20 output Rev.2.00 Oct. 16, 2007 Page 302 of 916 REJ09B0381-0200 Section 8 I/O Ports Bit 3 Bit Name A19E Initial Value R/W Description Address A19 Enable Enables/disables the address output (A19) 0: Disables the A19 output 1: Enables the A19 output Undefined* R/W 2 A18E Undefined* R/W Address A18 Enable Enables/disables the address output (A18) 0: Disables the A18 output 1: Enables the A18 output 1 A17E Undefined* R/W Address A17 Enable Enables/disables the address output (A17) 0: Disables the A17 output 1: Enables the A17 output 0 A16E Undefined* R/W Address A16 Enable Enables/disables the address output (A16) 0: Disables the A16 output 1: Enables the A16 output Note: * The initial value depends on the operating mode. Rev.2.00 Oct. 16, 2007 Page 303 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.3.3 Port Function Control Register 9 (PFCR9) PFCR9 selects the multiple functions for the TPU (unit 0) I/O pins. Bit Bit Name Initial Value R/W 7 TPUMS5 0 R/W 6 TPUMS4 0 R/W 5 TPUMS3A 0 R/W 4 TPUMS3B 0 R/W 3 TPUMS2 0 R/W 2 TPUMS1 0 R/W 1 TPUMS0A 0 R/W 0 TPUMS0B 0 R/W Bit 7 Bit Name TPUMS5 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA5 function 0: Specifies pin P26 as output compare output and input capture 1: Specifies P27 as input capture input and P26 as output compare 6 TPUMS4 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA4 function 0: Specifies P25 as output compare output and input capture 1: Specifies P24 as input capture input and P25 as output compare 5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA3 function 0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare 4 TPUMS3B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC3 function 0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare Rev.2.00 Oct. 16, 2007 Page 304 of 916 REJ09B0381-0200 Section 8 I/O Ports Bit 3 Bit Name TPUMS2 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare 2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA1 function 0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA0 function 0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare 0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC0 function 0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare Rev.2.00 Oct. 16, 2007 Page 305 of 916 REJ09B0381-0200 Section 8 I/O Ports 8.4 8.4.1 Usage Notes Notes on Input Buffer Control Register (ICR) Setting • When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin state. Before changing the ICR setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. • If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. Care must be taken for each module settings for unused input functions. • When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR. 8.4.2 Notes on Port Function Control Register (PFCR) Settings • Port function controller controls the I/O port. Before enabling a port function, select the input/output destination. • When changing input pins, this LSI may malfunction due to the internal edge. To change input pins, the following procedure must be performed. 1. Disable the input function by the corresponding on-chip peripheral module settings 2. Select another input pin by PFCR 3. Enable its input function by the corresponding on-chip peripheral module settings • If a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. Rev.2.00 Oct. 16, 2007 Page 306 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. Table 9.1 lists the 16-bit timer unit functions and figure 9.1 is a block diagram. 9.1 Features • Maximum 16-pulse input/output • Selection of eight counter input clocks for each channel • The following operations can be set for each channel: ⎯ Waveform output at compare match ⎯ Input capture function ⎯ Counter clear operation ⎯ Synchronous operations: • Multiple timer counters (TCNT) can be written to simultaneously • Simultaneous clearing by compare match and input capture possible • Simultaneous input/output for registers possible by counter synchronous operation • Maximum of 15-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channels 0 and 3 • Phase counting mode settable independently for each of channels 1, 2, 4, and 5 • Cascaded operation • Fast access via internal 16-bit bus • 26 interrupt sources • Automatic transfer of register data • Conversion start trigger for the A/D converter can be generated • Module stop mode can be set Rev.2.00 Oct. 16, 2007 Page 307 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 Item Count clock TPU Functions Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Pφ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB TCNT2 TGRA_1 TGRB_1 ⎯ TIOCA1 TIOCB1 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 ⎯ TIOCA2 TIOCB2 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture O O O O O O ⎯ O TGRA_3 compare match or input capture Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKC TCNT5 TGRA_4 TGRB_4 ⎯ TIOCA4 TIOCB4 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 ⎯ TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture Compare 0 output match 1 output output Toggle output O O O TGR compare match or input capture O O O O O O O ⎯ TGRA_1 compare match or input capture TGR compare match or input capture O O O O O O O ⎯ TGRA_2 compare match or input capture TGR compare match or input capture O O O O O O O ⎯ TGRA_4 compare match or input capture TGR compare match or input capture O O O O O O O ⎯ TGRA_5 compare match or input capture Input capture function O Synchronous operation PWM mode O O Phase counting mode ⎯ Buffer operation DMAC activation O TGRA_0 compare match or input capture Rev.2.00 Oct. 16, 2007 Page 308 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Item A/D converter trigger Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 TGRA_0 compare match or input capture 5 sources TGRA_1 compare match or input capture 4 sources TGRA_2 compare match or input capture 4 sources TGRA_3 compare match or input capture 5 sources TGRA_4 compare match or input capture 4 sources TGRA_5 compare match or input capture 4 sources Interrupt sources •Compare •Compare •Compare •Compare •Compare •Compare match or match or match or match or match or match or input input input input input input capture capture capture capture capture capture 4A 1A 2A 3A 0A 5A •Compare •Compare •Compare •Compare •Compare •Compare match or match or match or match or match or match or input input input input input input capture capture capture capture capture capture 3B 1B 2B 0B 4B 5B •Compare •Overflow •Overflow •Compare •Overflow •Overflow match or •Underflow •Underflow match or •Underflow •Underflow input input capture capture 3C 0C •Compare match or input capture 0D •Overflow Legend: O : Possible ⎯ : Not possible •Compare match or input capture 3D •Overflow Rev.2.00 Oct. 16, 2007 Page 309 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TGRA TIOR TMDR Channel 2 TSR Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal TGRA TIOR TIER TCR TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins Channel 0: TIOCA0 TIOCB0 TIOCC0 TIOCD0 Channel 1: TIOCA1 TIOCB1 Channel 2: TIOCA2 TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 9.1 Block Diagram of TPU Rev.2.00 Oct. 16, 2007 Page 310 of 916 REJ09B0381-0200 TGRA Section 9 16-Bit Timer Pulse Unit (TPU) 9.2 Input/Output Pins Table 9.2 shows TPU pin configurations. Table 9.2 Pin Configuration I/O Function Channel Symbol All TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin Rev.2.00 Oct. 16, 2007 Page 311 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3 Register Descriptions The TPU has the following registers in each channel. • Channel 0 ⎯ Timer control register_0 (TCR_0) ⎯ Timer mode register_0 (TMDR_0) ⎯ Timer I/O control register H_0 (TIORH_0) ⎯ Timer I/O control register L_0 (TIORL_0) ⎯ Timer interrupt enable register_0 (TIER_0) ⎯ Timer status register_0 (TSR_0) ⎯ Timer counter_0 (TCNT_0) ⎯ Timer general register A_0 (TGRA_0) ⎯ Timer general register B_0 (TGRB_0) ⎯ Timer general register C_0 (TGRC_0) ⎯ Timer general register D_0 (TGRD_0) • Channel 1 ⎯ Timer control register_1 (TCR_1) ⎯ Timer mode register_1 (TMDR_1) ⎯ Timer I/O control register _1 (TIOR_1) ⎯ Timer interrupt enable register_1 (TIER_1) ⎯ Timer status register_1 (TSR_1) ⎯ Timer counter_1 (TCNT_1) ⎯ Timer general register A_1 (TGRA_1) ⎯ Timer general register B_1 (TGRB_1) • Channel 2 ⎯ Timer control register_2 (TCR_2) ⎯ Timer mode register_2 (TMDR_2) ⎯ Timer I/O control register_2 (TIOR_2) ⎯ Timer interrupt enable register_2 (TIER_2) ⎯ Timer status register_2 (TSR_2) ⎯ Timer counter_2 (TCNT_2) ⎯ Timer general register A_2 (TGRA_2) ⎯ Timer general register B_2 (TGRB_2) Rev.2.00 Oct. 16, 2007 Page 312 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 3 ⎯ Timer control register_3 (TCR_3) ⎯ Timer mode register_3 (TMDR_3) ⎯ Timer I/O control register H_3 (TIORH_3) ⎯ Timer I/O control register L_3 (TIORL_3) ⎯ Timer interrupt enable register_3 (TIER_3) ⎯ Timer status register_3 (TSR_3) ⎯ Timer counter_3 (TCNT_3) ⎯ Timer general register A_3 (TGRA_3) ⎯ Timer general register B_3 (TGRB_3) ⎯ Timer general register C_3 (TGRC_3) ⎯ Timer general register D_3 (TGRD_3) • Channel 4 ⎯ Timer control register_4 (TCR_4) ⎯ Timer mode register_4 (TMDR_4) ⎯ Timer I/O control register _4 (TIOR_4) ⎯ Timer interrupt enable register_4 (TIER_4) ⎯ Timer status register_4 (TSR_4) ⎯ Timer counter_4 (TCNT_4) ⎯ Timer general register A_4 (TGRA_4) ⎯ Timer general register B_4 (TGRB_4) • Channel 5 ⎯ Timer control register_5 (TCR_5) ⎯ Timer mode register_5 (TMDR_5) ⎯ Timer I/O control register_5 (TIOR_5) ⎯ Timer interrupt enable register_5 (TIER_5) ⎯ Timer status register_5 (TSR_5) ⎯ Timer counter_5 (TCNT_5) ⎯ Timer general register A_5 (TGRA_5) ⎯ Timer general register B_5 (TGRB_5) • Common Registers ⎯ Timer start register (TSTR) ⎯ Timer synchronous register (TSYR) Rev.2.00 Oct. 16, 2007 Page 313 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 9.3 and 9.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 9.5. When the input clock is counted using both edges, the input clock period is halved (e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is Pφ/4 or slower. This setting is ignored if the input clock is Pφ/1, or when overflow/underflow of another channel is selected. Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 9.6 to 9.11 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Rev.2.00 Oct. 16, 2007 Page 314 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.3 Channel 0, 3 CCLR2 to CCLR0 (Channels 0 and 3) Bit 7 CCLR2 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 1 1 0 0 1 1 0 1 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev.2.00 Oct. 16, 2007 Page 315 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.4 Channel 1, 2, 4, 5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Bit 7 2 Reserved* 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Table 9.5 Input Clock Edge Selection Input Clock Internal Clock Counted at falling edge Counted at rising edge Counted at both edges External Clock Counted at rising edge Counted at falling edge Counted at both edges Clock Edge Selection CKEG1 0 0 1 Legend: ×: Don't care CKEG0 0 1 × Rev.2.00 Oct. 16, 2007 Page 316 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.6 Channel 0 TPSC2 to TPSC0 (Channel 0) Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 9.7 Channel 1 TPSC2 to TPSC0 (Channel 1) Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on Pφ/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev.2.00 Oct. 16, 2007 Page 317 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.8 Channel 2 TPSC2 to TPSC0 (Channel 2) Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on Pφ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 9.9 Channel 3 TPSC2 to TPSC0 (Channel 3) Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input Internal clock: counts on Pφ/1024 Internal clock: counts on Pφ/256 Internal clock: counts on Pφ/4096 Rev.2.00 Oct. 16, 2007 Page 318 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.10 TPSC2 to TPSC0 (Channel 4) Channel 4 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on Pφ/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 9.11 TPSC2 to TPSC0 (Channel 5) Channel 5 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on Pφ/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev.2.00 Oct. 16, 2007 Page 319 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 ⎯ 1 R 6 ⎯ 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Bit 7, 6 5 Bit Name Initial Value All 1 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Buffer Operation B Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation ⎯ BFB 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 Set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 9.12 for details. Rev.2.00 Oct. 16, 2007 Page 320 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.12 MD3 to MD0 Bit 3 1 MD3* 0 0 0 0 0 0 0 0 1 Bit 2 2 MD2* 0 0 0 0 1 1 1 1 × Bit 1 MD1 0 0 1 1 0 0 1 1 × Bit 0 MD0 0 1 0 1 0 1 0 1 × Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ⎯ Legend: ×: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 9.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports. Rev.2.00 Oct. 16, 2007 Page 321 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) • TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W • TIORL_0, TIORL_3 Bit Bit Name Initial Value R/W 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W • TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 9.13, 9.15, 9.16, 9.17, 9.19, and 9.20. I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 9.21, 9.23, 9.24, 9.25, 9.27, and 9.28. Rev.2.00 Oct. 16, 2007 Page 322 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) • TIORL_0, TIORL_3 Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 9.22 and 9.26. Description I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 9.14 and 9.18. Rev.2.00 Oct. 16, 2007 Page 323 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.13 TIORH_0 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* Legend: ×: Don't care Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev.2.00 Oct. 16, 2007 Page 324 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.14 TIORL_0 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 × × Input capture 2 register* TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 Legend: ×: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Oct. 16, 2007 Page 325 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.15 TIOR_1 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 326 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.16 TIOR_2 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 × × × Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 327 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.17 TIORH_3 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* Legend: ×: Don't care Note: When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and Pφ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev.2.00 Oct. 16, 2007 Page 328 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.18 TIORL_3 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 × × Input capture 2 register* TGRD_3 Function Output compare 2 register* TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 Legend: ×: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and Pφ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Oct. 16, 2007 Page 329 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.19 TIOR_4 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 × Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 330 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.20 TIOR_5 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 × × × Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 × Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 331 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.21 TIORH_0 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 332 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.22 TIORL_0 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 × × Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: ×: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Oct. 16, 2007 Page 333 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.23 TIOR_1 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 334 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.24 TIOR_2 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 × × × Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 335 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.25 TIORH_3 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 336 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.26 TIORL_3 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 × × Input capture register* TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down Legend: ×: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Oct. 16, 2007 Page 337 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.27 TIOR_4 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 × Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × × Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 338 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.28 TIOR_5 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 × × × Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 × Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges Legend: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 339 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial Value R/W 7 TTGE 0 R/W 6 ⎯ 1 R 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 ⎯ TCIEU 1 0 R R/W Reserved This is a read-only bit and cannot be modified. Underflow Interrupt Enable Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled Rev.2.00 Oct. 16, 2007 Page 340 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGIED Initial value 0 R/W R/W Description TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev.2.00 Oct. 16, 2007 Page 341 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial Value R/W Note: 7 TCFD 1 R 6 ⎯ 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* * Only 0 can be written to bits 5 to 0, to clear flags. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 ⎯ TCFU 1 0 R Reserved This is a read-only bit and cannot be modified. R/(W)* Underflow Flag Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] • When the TCNT value underflows (changes from H'0000 to H'FFFF) When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • Rev.2.00 Oct. 16, 2007 Page 342 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 4 Bit Name TCFV Initial value 0 R/W Description Status flag that indicates that a TCNT overflow has occurred. [Setting condition] • When the TCNT value overflows (changes from H'FFFF to H'0000) When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Overflow Flag [Clearing condition] • 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] • • When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • Rev.2.00 Oct. 16, 2007 Page 343 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGFC Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] • • When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • • When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • Rev.2.00 Oct. 16, 2007 Page 344 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 0 Bit Name TGFA Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] • • When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • Note: * Only 0 can be written to clear the flag. Rev.2.00 Oct. 16, 2007 Page 345 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8 9.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA−TGRC and TGRB−TGRD. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 15 14 13 12 11 10 9 8 Rev.2.00 Oct. 16, 2007 Page 346 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W 6 ⎯ 0 R/W 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. ⎯ 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev.2.00 Oct. 16, 2007 Page 347 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W 6 ⎯ 0 R/W 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. ⎯ 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible) Rev.2.00 Oct. 16, 2007 Page 348 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4 9.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 9.2 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Start count [5] Operation selection Select counter clock [1] Periodic counter Free-running counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] Figure 9.2 Example of Counter Operation Setting Procedure Rev.2.00 Oct. 16, 2007 Page 349 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 9.3 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 9.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 9.4 illustrates periodic counter operation. Rev.2.00 Oct. 16, 2007 Page 350 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software activation TGF Figure 9.4 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 9.5 shows an example of the setting procedure for waveform output by a compare match. [1] Select initial value from 0-output or 1-output, and compare match output value from 0-output, 1-output, or toggle-output, by means of TIOR. The set initial value is output on the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Output selection Select waveform output mode [1] Set output timing [2] Start count [3] Figure 9.5 Example of Setting Procedure for Waveform Output by Compare Match Rev.2.00 Oct. 16, 2007 Page 351 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 9.6 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1-output 0-output Time Figure 9.6 Example of 0-Output/1-Output Operation Figure 9.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle-output Toggle-output TIOCB TIOCA Figure 9.7 Example of Toggle Output Operation Rev.2.00 Oct. 16, 2007 Page 352 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, Pφ/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if Pφ/1 is selected. (a) Example of setting procedure for input capture operation Figure 9.8 shows an example of the setting procedure for input capture operation. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] Set the CST bit in TSTR to 1 to start the count operation. Select input capture input [1] Start count [2] Figure 9.8 Example of Setting Procedure for Input Capture Operation Rev.2.00 Oct. 16, 2007 Page 353 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 9.9 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 9.9 Example of Input Capture Operation Rev.2.00 Oct. 16, 2007 Page 354 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 9.10 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Figure 9.10 Example of Synchronous Operation Setting Procedure Rev.2.00 Oct. 16, 2007 Page 355 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 9.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 9.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 9.11 Example of Synchronous Operation Rev.2.00 Oct. 16, 2007 Page 356 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 9.29 shows the register combinations used in buffer operation. Table 9.29 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.12. Compare match signal Buffer register Timer general register Comparator TCNT Figure 9.12 Compare Match Buffer Operation Rev.2.00 Oct. 16, 2007 Page 357 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 9.13. Input capture signal Timer general register Buffer register TCNT Figure 9.13 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 9.14 shows an example of the buffer operation setting procedure. Buffer operation [1] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Select TGR function Set buffer operation [2] Start count [3] Figure 9.14 Example of Buffer Operation Setting Procedure Rev.2.00 Oct. 16, 2007 Page 358 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (2) (a) Examples of Buffer Operation When TGR is an output compare register Figure 9.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 9.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 9.15 Example of Buffer Operation (1) Rev.2.00 Oct. 16, 2007 Page 359 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 9.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 9.16 Example of Buffer Operation (2) Rev.2.00 Oct. 16, 2007 Page 360 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 9.30 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5 (1) Example of Cascaded Operation Setting Procedure Figure 9.17 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. Start count [2] Figure 9.17 Example of Cascaded Operation Setting Procedure Rev.2.00 Oct. 16, 2007 Page 361 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (2) Examples of Cascaded Operation Figure 9.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 9.18 Example of Cascaded Operation (1) Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 9.19 Example of Cascaded Operation (2) Rev.2.00 Oct. 16, 2007 Page 362 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. (a) PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. (b) PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronous register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. Rev.2.00 Oct. 16, 2007 Page 363 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) The correspondence between PWM output pins and registers is shown in table 9.31. Table 9.31 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev.2.00 Oct. 16, 2007 Page 364 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 9.20 shows an example of the PWM mode setting procedure. PWM mode [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the [1] input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the Select counter clock Select counter clearing source [2] TGR to be used as the TCNT clearing source. [3] Use TIOR to designate TGR as an output Select waveform output level [3] compare register, and select the initial value and output value. [4] Set the cycle in TGR selected in [2], and set the duty in the other TGRs. Set TGR [4] Set PWM mode [5] [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 9.20 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 9.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the duty cycle. Rev.2.00 Oct. 16, 2007 Page 365 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 9.21 Example of PWM Mode Operation (1) Figure 9.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 Counter cleared by TGRB_1 compare match TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 9.22 Example of PWM Mode Operation (2) Rev.2.00 Oct. 16, 2007 Page 366 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB H'0000 TGRB changed TGRB changed Time TIOCA 0% duty TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty TGRB changed Time TIOCA TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty 0% duty TGRB changed Time TIOCA Figure 9.23 Example of PWM Mode Operation (3) Rev.2.00 Oct. 16, 2007 Page 367 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.32 shows the correspondence between external clock pins and channels. Table 9.32 Clock Input Pins in Phase Counting Mode External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 9.24 shows an example of the phase counting mode setting procedure. Rev.2.00 Oct. 16, 2007 Page 368 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode Select phase counting mode [1] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 9.24 Example of Phase Counting Mode Setting Procedure (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 9.25 shows an example of phase counting mode 1 operation, and table 9.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.25 Example of Phase Counting Mode 1 Operation Rev.2.00 Oct. 16, 2007 Page 369 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.33 Up-/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev.2.00 Oct. 16, 2007 Page 370 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 9.26 shows an example of phase counting mode 2 operation, and table 9.34 summarizes the TCNT up-/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.26 Example of Phase Counting Mode 2 Operation Table 9.34 Up-/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Up-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Rev.2.00 Oct. 16, 2007 Page 371 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (c) Phase counting mode 3 Figure 9.27 shows an example of phase counting mode 3 operation, and table 9.35 summarizes the TCNT up-/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.27 Example of Phase Counting Mode 3 Operation Table 9.35 Up-/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Up-count Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Rev.2.00 Oct. 16, 2007 Page 372 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 9.28 shows an example of phase counting mode 4 operation, and table 9.36 summarizes the TCNT up-/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.28 Example of Phase Counting Mode 4 Operation Table 9.36 Up-/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev.2.00 Oct. 16, 2007 Page 373 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (3) Phase Counting Mode Application Example Figure 9.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up-/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Rev.2.00 Oct. 16, 2007 Page 374 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 + + - TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 9.29 Phase Counting Mode Application Example Rev.2.00 Oct. 16, 2007 Page 375 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.5 Interrupt Sources There are three kinds of TPU interrupt sources. TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 5, Interrupt Controller. Table 9.37 lists the TPU interrupt sources. Table 9.37 TPU Interrupts Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 DMAC Activation O ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ Rev.2.00 Oct. 16, 2007 Page 376 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Channel Name 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Interrupt Source TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow Interrupt Flag TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 DMAC Activation O ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ O ⎯ ⎯ ⎯ Legend: O : Possible ⎯ : Not possible Note: This table shows the initial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Rev.2.00 Oct. 16, 2007 Page 377 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 9.6 DMAC Activation The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. 9.7 A/D Converter Activation The TGRA input capture/compare match for each channel can activate the A/D converter. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev.2.00 Oct. 16, 2007 Page 378 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.8 9.8.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 9.30 shows TCNT count timing in internal clock operation, and figure 9.31 shows TCNT count timing in external clock operation. Pφ Internal clock Falling edge Rising edge Falling edge TCNT input clock TCNT N−1 N N+1 N+2 Figure 9.30 Count Timing in Internal Clock Operation Pφ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N−1 N N+1 N+2 Figure 9.31 Count Timing in External Clock Operation Rev.2.00 Oct. 16, 2007 Page 379 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.32 shows output compare output timing. Pφ TCNT input clock TCNT N N+1 TGR Compare match signal TIOC pin N Figure 9.32 Output Compare Output Timing (3) Input Capture Signal Timing Figure 9.33 shows input capture signal timing. Pφ Input capture input Input capture signal N N+1 N+2 TCNT TGR N N+2 Figure 9.33 Input Capture Input Signal Timing Rev.2.00 Oct. 16, 2007 Page 380 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 9.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.35 shows the timing when counter clearing by input capture occurrence is specified. Pφ Compare match signal Counter clear signal TCNT TGR N H'0000 N Figure 9.34 Counter Clear Timing (Compare Match) Pφ Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 9.35 Counter Clear Timing (Input Capture) Rev.2.00 Oct. 16, 2007 Page 381 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (5) Buffer Operation Timing Figures 9.36 and 9.37 show the timings in buffer operation. Pφ TCNT Compare match signal TGRA, TGRB TGRC, TGRD n N n n+1 N Figure 9.36 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT N N+1 TGRA, TGRB TGRC, TGRD n N N+1 n N Figure 9.37 Buffer Operation Timing (Input Capture) 9.8.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 9.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. Rev.2.00 Oct. 16, 2007 Page 382 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) Pφ TCNT input clock TCNT N N+1 N TGR Compare match signal TGF flag TGI interrupt Figure 9.38 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 9.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. Pφ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 9.39 TGI Interrupt Timing (Input Capture) Rev.2.00 Oct. 16, 2007 Page 383 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 9.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 9.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. Pφ TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 9.40 TCIV Interrupt Setting Timing Pφ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 9.41 TCIU Interrupt Setting Timing Rev.2.00 Oct. 16, 2007 Page 384 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figures 9.43 and 9.44 show the timing for status flag clearing by the DMAC. TSR write cycle T1 T2 Pφ TSR address Address Write Status flag Interrupt request signal Figure 9.42 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with Pφ after the DMAC transfer has started, as shown in figure 9.43. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DMAC transfers, it will take up to five clock cycles (Pφ) for clearing them, as shown in figure 9.44. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (Pφ) from the beginning of the transfer. Rev.2.00 Oct. 16, 2007 Page 385 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) DMAC read cycle T2 T1 Pφ Address Source address DMAC write cycle T2 T1 Destination address Status flag Period in which the next transfer request is masked Interrupt request signal Figure 9.43 Timing for Status Flag Clearing by DMAC Activation (1) DMAC read cycle Pφ Address DMAC write cycle Source address Period in which the next transfer request is masked Destination address Status flag Period of flag clearing Interrupt request signal Period of interrupt request signal clearing Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (2) Rev.2.00 Oct. 16, 2007 Page 386 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9 9.9.1 Usage Notes Module Stop Mode Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 9.9.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.45 shows the input clock conditions in phase counting mode. Phase Phase difference difference Overlap Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference, Overlap ≥ 1.5 states Pulse width ≥ 2.5 states Figure 9.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev.2.00 Oct. 16, 2007 Page 387 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Pφ (N + 1) f: Counter frequency Pφ: Operating frequency N: TGR set value 9.9.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.46 shows the timing in this case. TCNT write cycle T1 Pφ Address TCNT address T2 Write Counter clear signal TCNT N H'0000 Figure 9.46 Conflict between TCNT Write and Clear Operations 9.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.47 shows the timing in this case. Rev.2.00 Oct. 16, 2007 Page 388 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT write cycle T1 T2 Pφ Address TCNT address Write TCNT input clock TCNT N TCNT write data M Figure 9.47 Conflict between TCNT Write and Increment Operations 9.9.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 9.48 shows the timing in this case. TGR write cycle T1 T2 Pφ Address TGR address Write Compare match signal TCNT N Prohibited N+1 TGR N TGR write data M Figure 9.48 Conflict between TGR Write and Compare Match Rev.2.00 Oct. 16, 2007 Page 389 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 9.49 shows the timing in this case. TGR write cycle T2 T1 Pφ Address Write Compare match signal Buffer register N Data written to buffer register Buffer register address M TGR M Figure 9.49 Conflict between Buffer Register Write and Compare Match 9.9.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.50 shows the timing in this case. Rev.2.00 Oct. 16, 2007 Page 390 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) TGR read cycle T2 T1 Pφ Address TGR address Read Input capture signal TGR Internal data bus X M M Figure 9.50 Conflict between TGR Read and Input Capture 9.9.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.51 shows the timing in this case. TGR write cycle T2 T1 Pφ Address Write Input capture signal TCNT M TGR address TGR M Figure 9.51 Conflict between TGR Write and Input Capture Rev.2.00 Oct. 16, 2007 Page 391 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.52 shows the timing in this case. Buffer register write cycle T2 T1 Pφ Buffer register address Address Write Input capture signal TCNT TGR N M N Buffer register M Figure 9.52 Conflict between Buffer Register Write and Input Capture Rev.2.00 Oct. 16, 2007 Page 392 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Pφ TCNT input clock TCNT Counter clear signal TGF flag Prohibited TCFV flag H'FFFF H'0000 Figure 9.53 Conflict between Overflow and Counter Clearing Rev.2.00 Oct. 16, 2007 Page 393 of 916 REJ09B0381-0200 Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.12 Conflict between TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.54 shows the operation timing when there is conflict between TCNT write and overflow. TGR write cycle T2 T1 Pφ Address TCNT address Write TCNT write data H'FFFF Prohibited M TCNT TCFV flag Figure 9.54 Conflict between TCNT Write and Overflow 9.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 9.9.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev.2.00 Oct. 16, 2007 Page 394 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) Section 10 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 10.1 shows a block diagram of the WDT. 10.1 Features • Selectable from eight counter input clocks • Switchable between watchdog timer mode and interval timer mode ⎯ In watchdog timer mode If the counter overflows, this LSI can be initialized internally. ⎯ In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select Internal reset signal* Reset control Pφ/2 Pφ/64 Pφ/128 Pφ/512 Pφ/2048 Pφ/8192 Pφ/32768 Pφ/131072 Internal clocks RSTCSR TCNT TCSR Bus interface Module bus WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the RSTCSR setting. Figure 10.1 Block Diagram of WDT WDT0120A_000020030600 Rev.2.00 Oct. 16, 2007 Page 395 of 916 REJ09B0381-0200 Internal bus Section 10 Watchdog Timer (WDT) 10.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 10.5.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 10.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 10.2.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 R 3 — 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 396 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] • When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] • Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows while RSTE = 1, this LSI is initialized initially. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 ⎯ All 1 R Reserved These are read-only bits and cannot be modified. Rev.2.00 Oct. 16, 2007 Page 397 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for Pφ = 20 MHz is indicated in parentheses. 000: Clock Pφ/2 (cycle: 25.6 μs) 001: Clock Pφ/64 (cycle: 819.2 μs) 010: Clock Pφ/128 (cycle: 1.6 ms) 011: Clock Pφ/512 (cycle: 6.6 ms) 100: Clock Pφ/2048 (cycle: 26.2 ms) 101: Clock Pφ/8192 (cycle: 104.9 ms) 110: Clock Pφ/32768 (cycle: 419.4 ms) 111: Clock Pφ/131072 (cycle: 1.68 s) Note: * Only 0 can be written to this bit, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 398 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) 10.2.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 — 0 R/W 4 — 1 R 3 — 1 R 2 — 1 R 1 — 1 R 0 — 1 R Note: * Only 0 can be written to this bit, to clear the flag. Bit 7 Bit Name WOVF Initial Value 0 R/W Description R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] • When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF [Clearing condition] • 6 RSTE 0 R/W Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows 5 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 to 0 Note: * ⎯ All 1 R Reserved These are read-only bits and cannot be modified. Only 0 can be written to this bit, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 399 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) 10.3 10.3.1 Operation Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT overflows without being rewritten because of a system crash or other error, this LSI is initialized internally. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow (TCNT has overflowed), the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The internal reset signal is output for 519 cycles of Pφ. When RSTE = 1, a signal to initialize this LSI internally is generated. Since this signal initializes the system click control register (SCKCR), the multiplication ratio of P φ clock is also initialized. When RSTE = 0, the signal is not generated, meaning that the SCKCR value and multiplication ratio of P φ clock remain unchanged. TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Internal reset signal* 519 cycles Notes: * If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. Time H'00 written to TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 to TCNT Figure 10.2 Operation in Watchdog Timer Mode Rev.2.00 Oct. 16, 2007 Page 400 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) 10.3.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request Figure 10.3 Operation in Interval Timer Mode 10.4 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 10.1 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF Rev.2.00 Oct. 16, 2007 Page 401 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) 10.5 10.5.1 Usage Notes Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 10.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 10.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 10.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: 15 Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) TCSR write: Address: H'FFA4 (TCSR) 15 H'A5 8 7 Write data 0 8 H'5A 7 Write data 0 Writing 0 to the WOVF bit in RSTCSR: 15 Address: H'FFA6 (RSTCSR) 8 H'A5 7 H'00 0 Figure 10.4 Writing to TCNT, TCSR, and RSTCSR Rev.2.00 Oct. 16, 2007 Page 402 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) (2) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 10.5.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 10.5 shows this operation. TCNT write cycle T1 Pφ Address T2 Internal write signal TCNT input clock TCNT N Counter write data M Figure 10.5 Conflict between TCNT Write and Increment 10.5.3 Changing Values of Bits CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed. 10.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode. Rev.2.00 Oct. 16, 2007 Page 403 of 916 REJ09B0381-0200 Section 10 Watchdog Timer (WDT) 10.5.5 Transition to Watchdog Timer Mode or Software Standby Mode When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1. Rev.2.00 Oct. 16, 2007 Page 404 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) Section 11 Watch Timer (WAT) The watch timer (WAT) is comprised of a counter that operates on the system clock and a 16-bit timer that operates on the subclock. Figure 11.1 shows a block diagram of the WAT. 11.1 Features • Counter input clock selectable from eight types of main clocks and one type of subclock. • Selectable modes include compare match timer mode and interval timer mode. • Compare match timer mode ⎯ The compare match cycle can be changed using the watch timer constant register (WTCOR). ⎯ WCMI interrupts are generated when the watch timer counter (WTCNT) and the watch timer constant register (WTCOR) match. • Interval timer mode ⎯ The WCM interrupt is generated whenever watch timer counter (WTCNT) overflow occurs. WTSR WCMI (Interrupt request signal) Interrupt controller Clock selection Pφ/2 Pφ/64 Pφ/128 Pφ/512 Pφ/2048 Pφ/8192 Pφ/32768 Pφ/131072 φSUB Comparison circuit WTCNT WTCOR WTCR Module bus Bus interface Legend: WTCR: WTCNT: WTCOR: WTSR: Watch timer control register Watch timer counter Watch timer constant register Watch timer status register Figure 11.1 Block Diagram of WAT Rev.2.00 Oct. 16, 2007 Page 405 of 916 REJ09B0381-0200 Internal bus Section 11 Watch Timer (WAT) 11.2 Register Descriptions The WAT has the following registers. • Watch timer counter (WTCNT) • Watch timer control register (WTCR) • Watch timer status register (WTSR) • Watch timer constant register (WTCOR) 11.2.1 Watch Timer Counter (WTCNT) WTCNT is a 16-bit readable/writable up-counter. When the TME bit in WTCR is set to 1, WTCR starts incrementing on the internal clock selected by bits CKS2 to CKS0 and PSS in WTCR. WTCNT is initialized to H'0000 when the TME bit in WTCR is cleared to 0. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8 Rev.2.00 Oct. 16, 2007 Page 406 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.2.2 Watch Timer Control Register (WTCR) WTCR selects the input clock for WTCNT and mode. Bit: Bit name: Initial value: R/W: 7 — 0 — 6 CMT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 IE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 Bit Name ⎯ Initial Value 0 R/W ⎯ Description Reserved This bit is always read as 0. The write value should also be 0. 6 CMT/IT 0 R/W Timer Mode Select Selects whether the WAT is used as a compare match timer or an interval timer. 0: Compare match timer mode 1: Interval timer mode 5 TME 0 R/W Timer Enable Starts WTCNT counting when this bit is set to 1. When this bit is cleared, WTCNT stops counting and is initialized to H'0000*. 4 PSS 0 R/W Counter Select Selects the base clock for WTCNT. This bit must be set to 1 when the WAT is operated as the watch timer. 0: Operated on a Pφ base clock 1: Operated on a φSUB base clock. 3 IE 0 R/W Interrupt Enable 0: Disables Interrupts 1: Enables compare-match or overflow flag interrupts Rev.2.00 Oct. 16, 2007 Page 407 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 These bits select a clock input to WTCNT. Description in parentheses ( ) indicates the clock status when the PSS bit is 1. 000: Pφ/2 (φSUB) 001: Pφ/64 (Stopped) 010: Pφ/128 (Stopped) 011: Pφ/512 (Stopped) 100: Pφ/2048 (Stopped) 101: Pφ/8192 (Stopped) 110: Pφ/32768 (Stopped) 111: Pφ/131072 (Stopped) Note: * After the TME bit change from 1 to 0 is detected, WTCNT is initialized to H'0000. 11.2.3 Watch Timer Status Register (WTSR) The WTSR consists of several status flags. Bit: Bit name: Initial value: R/W: Note: 7 CMF/OVF 0 R/(W)* 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 0 WTCNT_WF WTCR_WF 0 R 0 R * Only 0 can be written to clear the flag. Rev.2.00 Oct. 16, 2007 Page 408 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) Bit 7 Bit Name CMF/OVF Initial Value 0 R/W Description R/(W)* Compare Match/Overflow Flag Indicates if a compare match or an overflow occurs on WTCNT. [Setting conditions] • • • When WTCOR and WTCNT values match in compare match mode. When WTCNT overflows When 0 is written to after WTSR is read from with CMF/OVF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] 6 to 2 ⎯ All 0 ⎯ Reserved These bits are always read as 0. The write value should always be 0. 1 WTCNT_WF 0 R Timer Counter Write Flag The flag is set to 1 when rewriting WTCNT is started. The flag is cleared to 0 when rewriting is completed. WTCNT must be read from or written to when this flag is 0. If WTCNT is written to when this flag is 1, the WTCNT value is not modified. [Setting condition] • • When rewriting WTCNT is started (during rewriting) When rewriting WTCNT is completed [Clearing condition] Rev.2.00 Oct. 16, 2007 Page 409 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) Bit 0 Bit Name WTCR_WF Initial Value 0 R/W R Description Timer Control Register Write Flag The flag is set to 1 when rewriting WTCR is started. The flag is cleared to 0 when rewriting is completed. WTCR must be read from or written to when this flag is 0. If WTCR is written to when this flag is 1, the WTCR value is not modified. [Setting condition] • • When rewriting WTCR is started (during rewriting) When rewriting WTCR is completed [Clearing condition] Note: * Only 0 can be written to clear the flag. 11.2.4 Watch Timer Constant Register (WTCOR) WTCOR is a 16-bit readable/writable register. When the WTCOR value matches the WTCNT value in compare match mode, the compare match flag is set. In interval timer mode, the compare match flag is not set even though the WTCOR value matches the WTCNT value. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 15 14 13 12 11 10 9 8 Rev.2.00 Oct. 16, 2007 Page 410 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.3 11.3.1 Operation Mode Operation in Compare Match Timer Follow the procedure below to select the use as compare match timer mode. (1) Initial Settings Make sure that WTCNT is stopped (the TME bit in WTCR is 0) for the following settings. • Specify the timer cycle with WTCOR. • Enter the initial values for WTCNT. • The CMT/IT, PSS, IE, and CKS2 to CKS0 bits in WTCR are used to set timer operating mode, operating clock and interrupt enable/disable status. Clearing the XTALSTP bit in SUBCKCR to 0 enables WTCNT operation to continue in software standby mode. For details of SUBCKCR, see section 23, Clock Pulse Generator. (2) Activation • The TME bit in WTCR is set to 1 after confirming that the WTCR value has been rewritten (the WTCR_WF bit in WTSR is 0). • WTCNT begins incrementing once the WTCR value has been rewritten (the WTCR_WF bit in WTSR is 0). • The CMF/OVF bit in WTSR is set to 1 each time the WTCNT and WTCOR values match. • A timer interrupt is generated if the IE bit in WTCR is set to 1. (3) Stopping • If the TME bit in WTCR is set to 0, WTCNT will stop incrementing and TCNT is initialized to H'0000 after WTCR is rewritten (the WTCR_WF bit in WTSR is 0). Rev.2.00 Oct. 16, 2007 Page 411 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) WTCNT value H'FFFF WTCOR value Matched Initial value of WTCNT H'00 TME = 1 Interrupt TME = 0 TME = 1 Time WTCR_WF value in WTSR 1 0 WTCNT_WF value 1 0 CMF/OVF value 1 0 CMF is cleared WTCNT WTCOR CMF N-4 N-3 N-2 N-1 N H'0000 H'0001 H'0002 H'0003 Figure 11.2 Operation in Compare Match Timer Mode Rev.2.00 Oct. 16, 2007 Page 412 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.3.2 Operation in Interval Timer Mode Follow the procedure below to select the use as interval timer mode. (1) Initial Settings Make sure that WTCNT is stopped (the TME bit in WTCR is 0) for the following settings. • Enter the initial values for WTCNT. • The CMT/IT, PSS, IE, and CKS2 to CKS0 bits in WTCR are used to set timer operating mode, operating clock, and interrupt enable/disable status. Clearing the XTALSTP bit in SUBCKCR to 0 enables WTCNT operation to continue in software standby mode. For details of SUBCKCR, see section 23, Clock Pulse Generator. (2) Activation • The TME bit in WTCR is set to 1 after confirming that the WTCR value has been rewritten (the WTCR_WF bit in WTSR is 0). • WTCNT begins incrementing once the WTCR value has been rewritten (the WTCR_WF bit in WTSR is 0). • The CMF/OVF bit in WTSR is set to 1 when the WTCNT value changes from H'FFFF to H'0000. • A timer interrupt is generated if the IE bit in WTCR is set to 1. (3) Stopping • If the TME bit in WTCR is cleared to 0, WTCNT will stop incrementing and WTCNT will be initialized to H'0000 after WTCR is rewritten (the WTCR_WF bit in WTSR is 0). Rev.2.00 Oct. 16, 2007 Page 413 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) WTCNT value H'FFFF Overflowed Initial value of WTCNT H'00 WTCR_WF value in WTSR 1 0 WTCNT_WF value 1 0 CMF/OVF value 1 0 CMF is cleared TME= 1 Interrupt TME = 0 TME = 1 Time WTCNT Overflow signal OVF H'FFFC H'FFFD H'FFFE H'FFFF H'0000 H'0001 H'0002 H'0003 Figure 11.3 Operation in Interval Timer Mode Rev.2.00 Oct. 16, 2007 Page 414 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.4 11.4.1 Usage Notes Precautions for Accessing Registers Due to the time required to rewrite the write values in WTCNT and WTCR, WTSR is provided to indicate the current write status. (1) Writing to WTCR Make sure that the WTSR flag has been rewritten (WTCR_WF = 0) when writing to WTCR. If WTCR is written to when rewriting is in progress (WTCR_WF = 1), the register value is not modified. (2) Writing to WTCNT Make sure that the WTSR flag has been rewritten (WTCNT_WF = 0) when writing to WTCNT. If WTCNT is written to when rewriting is in progress (WTCNT_WF = 1), the register value is not modified. WTCNT includes two internal counters, one that operates on the system clock and the other on the subclock. The counter to be written to is selected by the PSS bit in WTCR. Therefore, when writing to WTCNT after rewriting the PSS bit in WTCR, make sure that both WTCR and WTCNT have been rewritten (WTCR_WF = 0 and WTCNT_WF = 0). (3) Reading from WTCNT or WTCR When reading from WTCNT or WTCR, make sure that the WTSR flag has been rewritten (WTCR_WF = 0 or WTCNT_WF = 0). If WTCNT or WTCR is read from during rewriting (WTCR_WF = 1 or WTCNT_WF = 1), the read value may be undefined. WTCNT includes two internal counters, one that operates on the system clock and the other on the subclock. The counter to be read from is selected by the PSS bit in WTCR. Therefore, when reading from WTCNT after rewriting the PSS bit in WTCR, make sure that both WTCR and WTCNT have been rewritten (WTCR_WF = 0 and WTCNT_WF = 0). Rev.2.00 Oct. 16, 2007 Page 415 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.4.2 Conflict between Write and Increment Processes of WTCNT Even in instances where counter increments occur on the T2 state during the WTCNT write cycle, the increments will be ignored and writing to WTCNT will take precedence. This process is shown in figure 11.4. T1 φ Address T2 Internal write signal WTCNT input clock Counter write data WTCNT N Figure 11.4 Conflict between WTCNT Write and Increment 11.4.3 Rewriting Bits CKS2 to CKS0 Note that incrementation errors may occur if bits CKS2 to CKS0 in WTCR are rewritten during counter operation. Always make sure to stop timer operation (clearing the TME bit to 0) prior to rewriting bits CKS2 to CKS0. 11.4.4 Switching between Compare Match Timer and Interval Timer Modes Note that switching between compare match timer and interval timer modes during counter operation may result in operational error. Always make sure to stop timer operation (clearing the TME bit to 0) prior to switching the timer modes. 11.4.5 Rewriting PSS Bit Note that rewriting the PSS bit during counter operation may result in operational error. Always make sure to stop timer operation (clearing the TME bit to 0) prior to rewriting the PSS bit. Rev.2.00 Oct. 16, 2007 Page 416 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) 11.4.6 WTCOR Setting Value and WTCNT Rewrite Value in Compare Match Timer Mode Make sure the following condition is satisfied in compare match timer mode: (WTCNT rewrite value) < (WTCOR setting value) 11.4.7 Interrupt Vector Address The interrupt vector address used during normal operation and that of software standby mode differ. For details, see section 5, Interrupt Controller. Rev.2.00 Oct. 16, 2007 Page 417 of 916 REJ09B0381-0200 Section 11 Watch Timer (WAT) Rev.2.00 Oct. 16, 2007 Page 418 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has four independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. Figure 12.1 shows a block diagram of the SCI. 12.1 Features • Choice of asynchronous or clocked synchronous serial communication mode • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. • On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). • Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) • Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DMAC. • Module stop mode can be set Asynchronous Mode: • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCI0030A_000020030600 Rev.2.00 Oct. 16, 2007 Page 419 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity error during reception • Data can be automatically re-transmitted on receiving an error signal during transmission • Both direct convention and inverse convention are supported Module data bus RDR TDR SCMR SSR SCR BRR Pφ Baud rate generator Pφ/4 Pφ/16 Pφ/64 Clock RxD RSR TSR SMR Transmission/ reception control TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register Legend: RSR: RDR: TSR: TDR: SMR: Figure 12.1 Block Diagram of SCI Rev.2.00 Oct. 16, 2007 Page 420 of 916 REJ09B0381-0200 Internal data bus Bus interface Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the SCI. Table 12.1 Pin Configuration Channel 0 Pin Name* SCK0 RxD0 TxD0 2 SCK2 RxD2 TxD2 4 SCK4 RxD4 TxD4 5 SCK5 RxD5 TxD5 Note: * I/O I/O Input Output I/O Input Output I/O Input Output I/O Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Channel 4 clock input/output Channel 4 receive data input Channel 4 transmit data output Channel 5 clock input/output Channel 5 receive data input Channel 5 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev.2.00 Oct. 16, 2007 Page 421 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes: Normal serial communication interface mode and smart card interface mode. The bits, therefore, are described separately for each mode in the corresponding register sections. Channel 0: • Receive shift register_0 (RSR_0) • Transmit shift register_0 (TSR_0) • Receive data register_0 (RDR_0) • Transmit data register_0 (TDR_0) • Serial mode register_0 (SMR_0) • Serial control register_0 (SCR_0) • Serial status register_0 (SSR_0) • Smart card mode register_0 (SCMR_0) • Bit rate register_0 (BRR_0) Channel 2: • Receive shift register_2 (RSR_2) • Transmit shift register_2 (TSR_2) • Receive data register_2 (RDR_2) • Transmit data register_2 (TDR_2) • Serial mode register_2 (SMR_2) • Serial control register_2 (SCR_2) • Serial status register_2 (SSR_2) • Smart card mode register_2 (SCMR_2) • Bit rate register_2 (BRR_2) Rev.2.00 Oct. 16, 2007 Page 422 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Channel 4: • Receive shift register_4 (RSR_4) • Transmit shift register_4 (TSR_4) • Receive data register_4 (RDR_4) • Transmit data register_4 (TDR_4) • Serial mode register_4 (SMR_4) • Serial control register_4 (SCR_4) • Serial status register_4 (SSR_4) • Smart card mode register_4 (SCMR_4) • Bit rate register_4 (BRR_4) Channel 5: • Receive shift register_5 (RSR_5) • Transmit shift register_5 (TSR_5) • Receive data register_5 (RDR_5) • Transmit data register_5 (TDR_5) • Serial mode register_5 (SMR_5) • Serial control register_5 (SCR_5) • Serial status register_5 (SSR_5) • Smart card mode register_5 (SCMR_5) • Bit rate register_5 (BRR_5) Rev.2.00 Oct. 16, 2007 Page 423 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.3.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 12.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 12.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0 Rev.2.00 Oct. 16, 2007 Page 424 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. • When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W • When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Rev.2.00 Oct. 16, 2007 Page 425 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (valid only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode) When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev.2.00 Oct. 16, 2007 Page 426 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Initial Value 0 Bit 7 Bit Name GM R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 12.7.6, Data Transmission (Except in Block Transfer Mode) and 12.7.8, Clock Output Control. 6 5 BLK PE 0 0 R/W R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 12.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 12.7.2, Data Format (Except in Block Transfer Mode). Rev.2.00 Oct. 16, 2007 Page 427 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 3 2 Bit Name BCP1 BCP0 Initial Value 0 0 R/W R/W R/W Description Basic Clock Pulse 1 and 0 These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 12.3.9, Bit Rate Register (BRR). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). Note: etu: Elementary Time Unit (time for transfer of 1 bit) 12.3.6 Serial Control Register (SCR) SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 12.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. • When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Rev.2.00 Oct. 16, 2007 Page 428 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) • When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Value 0 Bit 7 Bit Name TIE R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. Rev.2.00 Oct. 16, 2007 Page 429 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 4 Bit Name RE Initial Value 0 R/W R/W Description Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 12.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled. Rev.2.00 Oct. 16, 2007 Page 430 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name TEIE Initial Value 0 R/W R/W Description Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. Clock Enable 1 and 0 These bits select the clock source and SCK pin function. • Asynchronous mode 00: On-chip baud rate generator (SCK pin functions as I/O port.) 01: On-chip baud rate generator (Outputs a clock with the same frequency as the bit rate from the SCK pin.) 1×: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) • Clocked synchronous mode 0×: Internal clock (SCK pin functions as clock output.) 1×: External clock (SCK pin functions as clock input.) 1 0 CKE1 CKE0 0 0 R/W R/W Note: ×: Don't care Rev.2.00 Oct. 16, 2007 Page 431 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Rev.2.00 Oct. 16, 2007 Page 432 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 12.7.8, Clock Output Control. • When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1×: Reserved • When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. • When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 433 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) • When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Value 1 Bit 7 Bit Name TDRE R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • • • • When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC to write data to TDR (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] Rev.2.00 Oct. 16, 2007 Page 434 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 6 Bit Name RDRF Initial Value 0 R/W Description R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] • When 0 is written to ORER after reading ORER = 1 Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.2.00 Oct. 16, 2007 Page 435 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial Value 0 R/W Description Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] • When 0 is written to FER after reading FER = 1 Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) • R/(W)* Framing Error 3 PER 0 R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] • When 0 is written to PER after reading PER = 1 Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) • Rev.2.00 Oct. 16, 2007 Page 436 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End [Setting conditions] • • When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC to write data to TDR (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 437 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • • • • When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC to write data to TDR (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] 6 RDRF 0 R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • Rev.2.00 Oct. 16, 2007 Page 438 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] • When 0 is written to ORER after reading ORER = 1 Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Overrun Error 4 ERS 0 R/(W)* Error Signal Status [Setting condition] • • When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] Rev.2.00 Oct. 16, 2007 Page 439 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] • When 0 is written to PER after reading PER = 1 Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Parity Error Rev.2.00 Oct. 16, 2007 Page 440 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] • • When both the TE and ERS bits in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] • • When 0 is written to TEND after reading TEND = 1 When a TXI interrupt request is issued allowing DMAC to write the next data to TDR (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 0 Note: * MPB MPBT 0 0 R R/W Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Only 0 can be written, to clear the flag. Rev.2.00 Oct. 16, 2007 Page 441 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Bit 7 to 4 3 Bit Name ⎯ SDIR Initial Value All 1 0 R/W ⎯ R/W Description Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 ⎯ SMIF 1 0 ⎯ R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode Rev.2.00 Oct. 16, 2007 Page 442 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode Clocked synchronous mode Smart card interface mode Bit Rate N= Pφ × 106 64 × 2 N= 2n – 1 Error −1 Error (%) = { Pφ × 106 B × 64 × 2 −1 2n – 1 – 1 } × 100 × (N + 1) ×B Pφ × 106 8×2 2n – 1 ×B −1 N= Pφ × 106 S×2 2n + 1 Error (%) = { ×B – 1 } × 100 B × S × 2 2n + 1 × (N + 1) Pφ × 106 Legend: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) Pφ: Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 SMR Setting BCP0 0 1 0 1 S 32 64 372 256 Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate settable for each operating frequency. Tables 12.6 and 12.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. Tables 12.5 and 12.7 show the maximum bit rates with external clock input. Rev.2.00 Oct. 16, 2007 Page 443 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency Pφ (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 8 n 2 2 1 1 0 0 0 0 0 0 ⎯ N 141 103 207 103 207 103 51 25 12 7 ⎯ Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 ⎯ n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.00 –2.34 Operating Frequency Pφ (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 ⎯ N 248 181 90 181 90 181 90 45 22 13 ⎯ 14 Error (%) –0.17 0.16 0.16 0.16 0.16 0.16 0.16 –0.93 –0.93 0.00 ⎯ n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 Rev.2.00 Oct. 16, 2007 Page 444 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency Pφ (MHz) 17.2032 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) n 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) –0.12 0.16 0.16 0.16 0.16 0.16 0.16 –0.69 1.02 0.00 –2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 0.00 1.73 Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 Maximum Bit Rate (bit/s) 460800 500000 537600 562500 614400 625000 Pφ (MHz) 8 9.8304 10 12 12.288 14 n 0 0 0 0 0 0 N 0 0 0 0 0 0 Pφ (MHz) 14.7456 16 17.2032 18 19.6608 20 n 0 0 0 0 0 0 N 0 0 0 0 0 0 Rev.2.00 Oct. 16, 2007 Page 445 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ (MHz) 8 9.8304 10 12 12.288 14 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 Pφ (MHz) 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 230400 250000 268800 281250 307200 312500 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency Pφ (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* ⎯ ⎯ ⎯ 1 1 0 0 0 0 0 0 ⎯ ⎯ ⎯ 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 ⎯ ⎯ 2 1 1 0 0 0 0 0 0 0 0 ⎯ ⎯ 124 249 124 199 99 49 19 9 4 1 0* 8 N n 10 N n 16 N n 20 N Legend: Blank : Setting prohibited. ⎯ : Can be set, but there will be error. * : Continuous transmission or reception is not possible. Rev.2.00 Oct. 16, 2007 Page 446 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) Pφ (MHz) 8 10 12 14 External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 Pφ (MHz) 16 18 20 External Input Clock (MHz) 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2666666.7 3000000.0 3333333.3 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency Pφ (MHz) Bit Rate (bit/s) 9600 n 0 N 0 7.1424 Error (%) n 0.00 0 N 1 10.00 Error (%) n 30 0 N 1 10.7136 Error (%) n 25 0 N 1 13.00 Error (%) 8.99 Operating Frequency Pφ (MHz) Bit Rate (bit/s) 9600 n 0 14.2848 N 1 Error (%) n 0.00 0 N 1 16.00 Error (%) n 12.01 0 N 2 18.00 Error (%) n 15.99 0 N 2 20.00 Error (%) 6.60 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) Pφ (MHz) 7.1424 10.00 10.7136 13.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 n 0 0 0 0 N 0 0 0 0 Pφ (MHz) 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 19200 21505 24194 26882 n 0 0 0 0 N 0 0 0 0 Rev.2.00 Oct. 16, 2007 Page 447 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 bit or 1 or 2 bits none One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev.2.00 Oct. 16, 2007 Page 448 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.1 Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 12.5, Multiprocessor Communication Function. Table 12.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 — 1 0 S 8-bit data MPB STOP 0 — 1 1 S 8-bit data MPB STOP STOP 1 — 1 0 S 7-bit data MPB STOP 1 — 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.2.00 Oct. 16, 2007 Page 449 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 – 1 ) – (L – 0.5) F – | D – 0.5 | (1 + F ) } × 100 2N N [%] ... Formula (1) M: Reception margin N: Ratio of bit rate to clock (N = 16) D: Duty cycle of clock (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = ( 0.5 – 1 ) × 100 2 × 16 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode Rev.2.00 Oct. 16, 2007 Page 450 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) Rev.2.00 Oct. 16, 2007 Page 451 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] [2] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] [4] Set the data transfer format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] [5] No 1-bit interval elapsed Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Figure 12.5 Sample SCI Initialization Flowchart Rev.2.00 Oct. 16, 2007 Page 452 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.5 Serial Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.2.00 Oct. 16, 2007 Page 453 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Initialization Start transmission [1] Read TDRE flag in SSR No [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No TEND = 1 Yes Break output Yes Clear DR to 0 and set DDR to 1 No [4] Clear TE bit in SCR to 0 Figure 12.7 Sample Serial Transmission Flowchart Rev.2.00 Oct. 16, 2007 Page 454 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER ERI interrupt request generated by framing error 1 frame RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.2.00 Oct. 16, 2007 Page 455 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Table 12.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flowchart for serial data reception. Table 12.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev.2.00 Oct. 16, 2007 Page 456 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No resumed if any of these flags are set to Error processing 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DMAC is initiated by an RXI interrupt and reads data from RDR. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] Figure 12.9 Sample Serial Reception Flowchart (1) Rev.2.00 Oct. 16, 2007 Page 457 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.9 Sample Serial Reception Flowchart (2) Rev.2.00 Oct. 16, 2007 Page 458 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with the multiprocessor bit cleared to 0. The receiving station skips data until data with the multiprocessor bit set to 1 is sent. When data with the multiprocessor bit set to 1 is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with the multiprocessor bit set to 1 is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with the multiprocessor bit set to 1 is received. On reception of a receive character with the multiprocessor bit set to 1, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev.2.00 Oct. 16, 2007 Page 459 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Transmitting station Communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) H'AA (MPB = 0) ID transmission cycle = receiving station specification Legend: MPB: Multiprocessor bit Data transmission cycle = Data transmission to receiving station specified by ID Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev.2.00 Oct. 16, 2007 Page 460 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission Read TDRE flag in SSR No [1] [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1 No No [4] Clear TE bit in SCR to 0 Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart Rev.2.00 Oct. 16, 2007 Page 461 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) D1 D7 Stop Start bit MPB bit 1 1 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 (mark state) 1 Idle state MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID1 If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station’s ID Start bit 0 D0 Data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Data 2 Matches this station’s ID, MPIE bit set to 1 so reception continues, and again data is received in RXI interrupt processing routine (b) Data matches station’s ID Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.2.00 Oct. 16, 2007 Page 462 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ∨ ORER = 1 No Read RDRF flag in SSR No [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] [2] Yes [3] RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR FER ∨ ORER = 1 No Read RDRF flag in SSR No Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev.2.00 Oct. 16, 2007 Page 463 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER, PER, and FER flags in SSR to 0 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.2.00 Oct. 16, 2007 Page 464 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * Holds a high level except during continuous transfer. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First) 12.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0. Rev.2.00 Oct. 16, 2007 Page 465 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] 1-bit interval elapsed? Yes No Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.15 Sample SCI Initialization Flowchart Rev.2.00 Oct. 16, 2007 Page 466 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev.2.00 Oct. 16, 2007 Page 467 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TEI interrupt request generated Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Initialization Start transmission [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 12.17 Sample Serial Transmission Flowchart Rev.2.00 Oct. 16, 2007 Page 468 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception. Rev.2.00 Oct. 16, 2007 Page 469 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Initialization Start reception Read ORER flag in SSR ORER = 1 No Yes [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [2] [3] Error processing No No [3] (Continued below) [4] SCI state check and receive data read: [4] Read SSR and check that the RDRF flag is set to 1, then read the receive RDRF = 1 data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from Yes 0 to 1 can also be identified by an RXI interrupt. Read receive data in RDR and clear RDRF flag in SSR to 0 [5] Serial reception continuation procedure: To continue serial reception, before All data received [5] the MSB (bit 7) of the current frame is Yes received, reading the RDRF flag, reading RDR, and clearing the RDRF Clear RE bit in SCR to 0 flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DMAC is initiated by a receive data full interrupt (RXI) and Error processing reads data from RDR. Overrun error processing Read RDRF flag in SSR Clear ORER flag in SSR to 0 Figure 12.19 Sample Serial Reception Flowchart 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction. Rev.2.00 Oct. 16, 2007 Page 470 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] Read TDRE flag in SSR No [2] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes [5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to No 0. Also, before the MSB (bit 7) of [5] All data received? the current frame is transmitted, read 1 from the TDRE flag to Yes confirm that writing is possible. Then write data to TDR and clear Clear TE and RE bits in SCR to 0 the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically Note: When switching from transmit or receive operation to when the DMAC is initiated by a simultaneous transmit and receive operations, first clear the receive data full interrupt (RXI) and TE bit and RE bit to 0, then set both these bits to 1 reads data from RDR. simultaneously. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev.2.00 Oct. 16, 2007 Page 471 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7 Operation in Smart Card Interface Mode The SCI supports the IC card (smart card) interface, conforming to ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 12.7.1 Sample Connection Figure 12.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card Figure 12.21 Pin Connection for Smart Card Interface Rev.2.00 Oct. 16, 2007 Page 472 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7.2 Data Format (Except in Block Transfer Mode) Figure 12.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. • If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. • If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from the transmitting station Legend: Ds: Start bit D0 to D7: Data bits Output from the receiving station Dp: Parity bit DE: Error signal Figure 12.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) Rev.2.00 Oct. 16, 2007 Page 473 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 12.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 12.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 12.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. • Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. • During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. • Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. • Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. Rev.2.00 Oct. 16, 2007 Page 474 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the basic clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 12.25. The reception margin here is determined by the following formula. M = | (0.5 – 1 ) – (L – 0.5) F – 2N | D – 0.5 | (1 + F ) | × 100% N M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Duty cycle of clock (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below. M= ( 0.5 – 1 ) × 100% = 49.866% 2 × 372 372 clock cycles 186 clock cycles 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 185 371 0 185 371 0 Start bit D0 D1 Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate) Rev.2.00 Oct. 16, 2007 Page 475 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Set the ICR bit of the corresponding pin to 1. 3. Clear the error flags ERS, PER, and ORER in SSR to 0. 4. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 5. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 6. Set the value corresponding to the bit rate in BRR. 7. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 8. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. Rev.2.00 Oct. 16, 2007 Page 476 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 12.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 12.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, TEND remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC). Rev.2.00 Oct. 16, 2007 Page 477 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) (n + 1) th transfer frame Ds D0 D1 D2 D3 D4 Transfer from TDR to TSR TEND [2] FER/ERS [1] Transfer from TDR to TSR Transfer from TDR to TSR [4] [3] Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 12.27 shows the TEND flag set timing. I/O data TXI (TEND interrupt) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu GM = 0 11.0 etu GM = 1 Legend: Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 12.27 TEND Flag Set Timing during Transmission Rev.2.00 Oct. 16, 2007 Page 478 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? Yes No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No Error processing No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 12.28 Sample Transmission Flowchart Rev.2.00 Oct. 16, 2007 Page 479 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 12.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 12.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 12.4, Operation in Asynchronous Mode. (n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode Rev.2.00 Oct. 16, 2007 Page 480 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? Yes No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No No Error processing All data received? Yes Clear RE bit in SCR to 0 Figure 12.30 Sample Reception Flowchart 12.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 12.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Given pulse width Given pulse width Figure 12.31 Clock Output Fixing Timing Rev.2.00 Oct. 16, 2007 Page 481 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. • At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output. • At mode switching ⎯ At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode. ⎯ At transition from smart card interface mode to software standby mode 1. Clear software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 12.32 Clock Stop and Restart Procedure Rev.2.00 Oct. 16, 2007 Page 482 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.8 12.8.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 12.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Table 12.12 SCI Interrupt Sources Name ERI RXI TXI TEI Interrupt Source Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, or PER RDRF TDRE TEND DMAC Activation Not possible Possible Possible Not possible Low Priority High Rev.2.00 Oct. 16, 2007 Page 483 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.8.2 Interrupts in Smart Card Interface Mode Table 12.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 12.13 SCI Interrupt Sources Name ERI RXI TXI Interrupt Source Receive error or error signal detection Receive data full Transmit data empty Interrupt Flag ORER, PER, or ERS RDRF TDRE DMAC Activation Not possible Possible Possible Low Priority High Data transmission/reception using the DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. Rev.2.00 Oct. 16, 2007 Page 484 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.9 12.9.1 Usage Notes Module Stop Mode Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 12.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 12.9.3 Mark State and Break Detection When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev.2.00 Oct. 16, 2007 Page 485 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.9.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. 12.9.6 Writing to Registers during SCI Transmit or Receive Do not write to SCR or SCMR during an SCI transmit or receive operation. The transmit or receive operation may not complete properly if SCR or SCMR is written to while it is in progress. 12.9.7 Restrictions on Using DMAC • When the external clock source is used as a synchronization clock, update TDR by the DMAC and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 12.33). • When using the DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the DMAC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 12.33 Sample Transmission Using DMAC in Clocked Synchronous Mode Rev.2.00 Oct. 16, 2007 Page 486 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) 12.9.8 (1) SCI Operations during Mode Transitions Transmission Before making the transition to module stop mode or software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during module stop mode or software standby mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 12.34 shows a sample flowchart for mode transition during transmission. Figures 12.35 and 12.36 show the port pin states during mode transition. (2) Reception Before making the transition to module stop mode or software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Rev.2.00 Oct. 16, 2007 Page 487 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Figure 12.37 shows a sample flowchart for mode transition during reception. Transmission All data transmitted? Yes Read TEND flag in SSR No [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and clearing the TDRE bit to 0 after clearing software standby mode. [2] Clear the TIE and TEIE bits to 0 when they are 1. [3] Module stop mode is included. TEND = 1 Yes TE = 0 [2] No Make transition to software standby mode Cancel software standby mode [3] Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 12.34 Sample Flowchart for Mode Transition during Transmission Rev.2.00 Oct. 16, 2007 Page 488 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Transmission start Transition to Software standby Transmission end software standby mode canceled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 12.35 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) Transition to Software standby software standby mode canceled mode Transmission start Transmission end TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 12.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) Rev.2.00 Oct. 16, 2007 Page 489 of 916 REJ09B0381-0200 Section 12 Serial Communication Interface (SCI) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. [2] Module stop mode is included. RE = 0 Make transition to software standby mode Cancel software standby mode [2] Change operating mode? Yes Initialization No RE = 1 Start reception Figure 12.37 Sample Flowchart for Mode Transition during Reception Rev.2.00 Oct. 16, 2007 Page 490 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Section 13 I C Bus Interface 2 (IIC2) This LSI has a two-channel I C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 13.1 shows the block diagram of the I2C bus interface 2. Figure 13.2 shows an example of I/O pin connections to external circuits. 2 2 13.1 Features • Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. • Start and stop conditions generated automatically in master mode • Selection of acknowledge output levels when receiving • Automatic loading of acknowledge bit when transmitting • Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission or reception is not yet possible, drive the SCL signal low until preparations are completed • Six interrupt sources Transmit-data-empty (including slave-address match), transmit-end, receive-data-full (including slave-address match), arbitration lost, NACK detection, and stop condition detection • Direct bus drive Two pins, the SCL and SDA pins function as NMOS open-drain outputs. Rev.2.00 Oct. 16, 2007 Page 491 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Transfer clock generator SCL Output control Transmission/ reception control circuit ICCRA ICCRB ICMR Noise canceler ICDRT SAR SDA Output control ICDRS Noise canceler Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICEIR Interrupt generator ICSR Legend: ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register A I2C bus control register B I2C mode register I2C status register I2C interrupt enable register I2C transmit data register I2C receive data register I2C bus shift register Slave address register Figure 13.1 Block Diagram of I C Bus Interface 2 2 Rev.2.00 Oct. 16, 2007 Page 492 of 916 REJ09B0381-0200 Internal data bus Interrupt request Section 13 I2C Bus Interface 2 (IIC2) Vcc Vcc SCL in SCL out SCL SCL SDA in SDA out SDA SDA SCL SDA (Master) SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 13.2 Connections to the External Circuit by the I/O Pins 13.2 Input/Output Pins 2 Table 13.1 shows the pin configuration of the I C bus interface 2. Table 13.1 Pin configuration of the I C bus interface 2 Channel 0 Abbreviation SCL0 SDA0 1 SCL1 SDA1 I/O I/O I/O I/O I/O Function Channel 0 serial clock I/O pin Channel 0 serial data I/O pin Channel 1 serial clock I/O pin Channel 1 serial data I/O pin 2 Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this manual. Rev.2.00 Oct. 16, 2007 Page 493 of 916 REJ09B0381-0200 SCL SDA Section 13 I2C Bus Interface 2 (IIC2) 13.3 2 Register Descriptions The I C bus interface 2 has the following registers. Channel 0: • I C bus control register A_0 (ICCRA_0) 2 2 2 2 2 • I C bus control register B_0 (ICCRB_0) • I C bus mode register_0 (ICMR_0) • I C bus interrupt enable register_0 (ICIER_0) • I C bus status register_0 (ICSR_0) • Slave address register_0 (SAR_0) • I C bus transmit data register_0 (ICDRT_0) 2 2 2 • I C bus receive data register_0 (ICDRR_0) • I C bus shift register_0 (ICDRS_0) Channel 1: • I C bus control register A_1 (ICCRA_1) 2 2 2 2 2 • I C bus control register B_1 (ICCRB_1) • I C bus mode register_1 (ICMR_1) • I C bus interrupt enable register_1 (ICIER_1) • I C bus status register_1 (ICSR_1) • Slave address register_1 (SAR_1) • I C bus transmit data register_1 (ICDRT_1) 2 2 2 • I C bus receive data register_1 (ICDRR_1) • I C bus shift register_1 (ICDRS_1) Rev.2.00 Oct. 16, 2007 Page 494 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.3.1 I C Bus Control Register A (ICCRA) 2 2 ICCRA enables or disables I C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W 7 ICE 0 R/W 6 RCVD 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I C Bus Interface Enable 0: This module is halted 1: This bit is enabled for transfer operations (SCL and SDA pins are bus drive state) 2 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select When arbitration is lost in master mode, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. Operating modes are described below according to MST and TRS combination. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Transfer Clock Select 3 to 0 These bits are valid only in master mode. Make setting according to the required transfer rate. For details on the transfer rate, see table 13.2. Rev.2.00 Oct. 16, 2007 Page 495 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Table 13.2 Transfer Rate Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Pφ/28 Pφ/40 Pφ/48 Pφ/64 Pφ/168 Pφ/100 Pφ/112 Pφ/128 Pφ/56 Pφ/80 Pφ/96 Pφ/128 Pφ/336 Pφ/200 Pφ/224 Pφ/256 Pφ = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 47.6 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 23.8 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate Pφ = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 29.8 kHz 50.0 kHz 44.6 kHz 39.1 kHz Pφ = 20 MHz 714 kHz 500 kHz 417 kHz 313 kHz 119 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz Rev.2.00 Oct. 16, 2007 Page 496 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.3.2 I C Bus Control Register B (ICCRB) 2 ICCRB issues start/stop condition, manipulates the SDA pin, monitors the SCL pin, and controls 2 reset in the I C control module. Bit Bit Name Initial Value R/W 7 BBSY 0 R/W 6 SCP 1 R/W 5 SDAO 1 R 4 ⎯ 1 R/W 3 SCLO 1 R 2 ⎯ 1 ⎯ 1 IICRST 0 R/W 0 ⎯ 1 ⎯ Bit 7 Initial Bit Name Value BBSY 0 R/W R/W Description Bus Busy This bit indicates whether the I C bus is occupied or released and to issue start and stop conditions in master mode. This bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SDA = high, assuming that the stop condition has been issued. Follow this procedure also when repeating a start condition. To issue a start or stop condition, use the MOV instruction. 2 6 SCP 1 R/W Start/Stop Condition Issue This bit controls the issuance of start or stop condition in master mode. To issue a start condition, write 1 to BBSY and 0 to SCP. A repeated start condition is issued in the same way. To issue a stop condition, write 0 to BBSY and 0 to SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R This bit monitors the output level of SDA. 0: When reading, the SDA pin outputs a low level 1: When reading the SDA pin outputs a high level 4 ⎯ 1 R/W Reserved The write value should always be 1. Rev.2.00 Oct. 16, 2007 Page 497 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 3 Initial Bit Name Value SCLO 1 R/W R Description This bit monitors the SCL output level. When reading and SCLO is 1, the SCL pin outputs a high level. When reading and SCLO is 0, the SCL pin outputs a low level. 2 1 ⎯ IICRST 1 0 ⎯ R/W Reserved This bit is always read as 0. IIC Control Module Reset This bit reset the IIC control module except the I C registers. If hang-up occurs because of communication 2 failure during I C operation, by setting this bit to 1, the 2 0 ⎯ 1 ⎯ Reserved This bit is always read as 1. 13.3.3 I C Bus Mode Register (ICMR) 2 ICMR selects MSB first or LSB first, controls the master mode wait and selects the number of transfer bits. Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W 6 WAIT 0 R/W 5 ⎯ 1 ⎯ 4 ⎯ 1 ⎯ 3 BCWP 1 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W Bit 7 6 Bit Name ⎯ WAIT Initial Value 0 0 R/W R/W R/W Description Reserved The write value should always be 0. Wait Insertion This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When this bit is set to 1, after the falling of the clock for the last data bit, the low period is extended for two transfer clocks. When this bit is cleared to 0, data and the acknowledge bit are transferred consecutively with no waits inserted. The setting of this bit is invalid in slave mode. Rev.2.00 Oct. 16, 2007 Page 498 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 5, 4 3 Bit Name ⎯ BCWP Initial Value All 1 1 R/W ⎯ R/W Description Reserved These bits are always read as 1. BC Write Protect This bit controls the modification of the BC2 to BC0 bits. When modifying, this bit should be cleared to 0 and the MOV instruction should be used. 0: When writing, the values of BC2 to BC0 are set 1: When reading, 1 is always read When writing, the settings of BC2 to BC0 are invalid. 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. The settings of these bits should be made during intervals between transfer frames. When setting these bits to a value other than 000, the setting should be made while the SCL line is low. The value return to 000 at the end of a data transfer including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 I C control module can be reset without setting the ports and initializing the registers. 2 Rev.2.00 Oct. 16, 2007 Page 499 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.3.4 I C Bus Interrupt Enable Register (ICIER) 2 ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received. Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 TEIE 0 R/W 5 RIE 0 R/W 4 NAKIE 0 R/W 3 STIE 0 R/W 2 ACKE 0 R/W 1 ACKBR 0 R 0 ACKBT 0 R/W Bit 7 Initial Bit Name Value TIE 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI) request. 0: Transmit data empty interrupt (TXI) request is disabled 1: Transmit data empty interrupt (TXI) request is enabled 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) request at the rising of the ninth clock while the TDRE bit in ICSR is set to 1. The TEI request can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt (TEI) request is disabled 1: Transmit end interrupt (TEI) request is enabled 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive full interrupt (RXI) request when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. The RXI request can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt (RXI) request is disabled 1: Receive data full interrupt (RXI) request is enabled Rev.2.00 Oct. 16, 2007 Page 500 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 4 Initial Bit Name Value NAKIE 0 R/W R/W Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt (NAKI) request when the NACKF and AL bits in ICSR are set to 1. The NAKI request can be canceled by clearing the NACKF or AL bit, or the NAKIE bit to 0. 0: NACK receive interrupt (NAKI) request is disabled 1: NACK receive interrupt (NAKI) request is enabled 3 STIE 0 R/W Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt (STPI) request is disabled 1: Stop condition detection interrupt (STPI) request is enabled 2 ACKE 0 R/W Acknowledge Bit Decision Select 0: The value of the acknowledge bit is ignored and continuous transfer is performed 1: If the acknowledge bit is 1, continuous transfer is suspended 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing 1: 1 is sent at the acknowledge timing Rev.2.00 Oct. 16, 2007 Page 501 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.3.5 I C Bus Status Register (ICSR) 2 ICSR confirms the interrupt request flags and status. Bit Bit Name Initial Value R/W 7 TDRE 0 R/W 6 TEND 0 R/W 5 RDRF 0 R/W 4 NACKF 0 R/W 3 STOP 0 R/W 2 AL 0 R/W 1 AAS 0 R/W 0 ADZ 0 R/W Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting condition] • • • • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set to 1 When the start condition has been issued In slave mode, after changing from receive mode to transmit mode When 0 is written to this bit after reading TDRE = 1 When data is written to ICDRT (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • 6 TEND 0 R/W Transmit End [Setting condition] • When the ninth clock of SCL rises while the TDRE flag is 1 When 0 is written to this bit after reading TEND = 1 When data is written to ICDRT (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • Rev.2.00 Oct. 16, 2007 Page 502 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 5 Bit Name RDRF Initial Value 0 R/W R/W Description Receive Data Register Full [Setting condition] • When receive data is transferred from ICDRS to ICDRR When 0 is written to this bit after reading RDRF = 1 When data is read from ICDRR (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] • • 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is set to 1 When 0 is written to this bit after reading NACKF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • 3 STOP 0 R/W Stop Condition Detection Flag [Setting conditions] • • When a stop condition is detected after the frame transfer completion in master mode In slave mode, when the slave address in the first byte after detecting the start condition and the address set in SAR match, and then a stop condition is detected. When 0 is written to this bit after reading STOP = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • Rev.2.00 Oct. 16, 2007 Page 503 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 2 Bit Name AL Initial Value 0 R/W R/W Description Arbitration Lost Flag This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the 2 bus at nearly the same time, the I C bus monitors SDA, 2 and if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] • When the internal SDA and the SDA pin level disagree at the rising of SCL in master transmit mode When the SDA pin outputs a high level in master mode while a start condition is detected When 0 is written to this bit after reading AL = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) • [Clearing condition] • 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 when the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • • When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode When 0 is written to this bit after reading AAS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • Rev.2.00 Oct. 16, 2007 Page 504 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Bit 0 Bit Name ADZ Initial Value 0 R/W R/W Description General Call Address Recognition Flag This bit is valid in slave receive mode. [Setting condition] • When the general call address is detected in slave receive mode When 0 is written to this bit after reading ADZ = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] • 13.3.6 Slave Address Register (SAR) SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device. Bit Bit Name Initial Value R/W 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 ⎯ 0 R/W Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 ⎯ 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Slave Address 6 to 0 These bits set a unique address differing from the 2 addresses of other slave devices connected to the I C bus. Reserved Although this bit is readable/writable, only 0 should be written to. Rev.2.00 Oct. 16, 2007 Page 505 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.3.7 I C Bus Transmit Data Register (ICDRT) 2 ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a 2 space in the I C bus shift register, it transfers the transmit data which has been written to ICDRT to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting data to ICDRS, continuous transmission is possible. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 13.3.8 I C Bus Receive Data Register (ICDRR) 2 ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register; therefore, this register cannot be written to by the CPU. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 13.3.9 I C Bus Shift Register (ICDRS) 2 ICDRS is an 8-bit write-only register that is used to transmit/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after one by of data is received. This register cannot be read from the CPU. Bit Bit Name Initial Value R/W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 7 6 5 4 3 2 1 0 Rev.2.00 Oct. 16, 2007 Page 506 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.4 13.4.1 Operation I C Bus Format 2 2 2 Figure 13.3 shows the I C bus formats. Figure 13.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m ≥1) (b) I2C bus format (start condition retransmission) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 ≥1) Figure 13.3 I C Bus Formats 2 SDA SCL 1 to 7 S SLA 8 R/W 9 A 1 to 7 DATA 2 8 9 A 1 to 7 DATA 8 9 A P Figure 13.4 I C Bus Timing Legend: S: SLA: R/W: A: P: Start condition. The master device drives SDA from high to low while SCL is high. Slave address Indicates the direction of data transfer; from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge. The receive device drives SDA low. Stop condition. The master device drives SDA from low to high while SCL is high. DATA: Transferred data Rev.2.00 Oct. 16, 2007 Page 507 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.4.2 2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device return an acknowledge signal. Figures 13.5 and 13.6 show the operating timings in master transmit mode. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (Initial setting) 2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV instruction. (The start condition is issued.) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0, data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the receive device while CKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev.2.00 Oct. 16, 2007 Page 508 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W A Bit 7 Bit 6 Slave address SDA (Slave output) TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS Address + R/W Data 1 User processing [2] Instruction of start condition issuance [4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte) Figure 13.5 Master Transmit Mode Operation Timing 1 SCL (Master output) SDA (Master output) SDA (Slave output) TDRE 9 1 2 3 4 5 6 7 8 9 Bit 7 A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A/A TEND ICDRT Data n ICDRS User processing Data n [5] Write data to ICDRT [6] Issue stop condition. Clear TEND [7] Set slave receive mode Figure 13.6 Master Transmit Mode Operation Timing 2 Rev.2.00 Oct. 16, 2007 Page 509 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 13.7 and 13.8 show the operation timings in master receive mode. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDDR is read (dummy read), reception is started, the receive clock pulse is output, and data is received, in synchronization with the internal clock. The master mode outputs the level specified by the ACKBT in ICIER to SDA, at the ninth receive clock pulse. 3. After the reception of the first frame data is completed, the RDRF bit in ICSR is set to 1 at the rising of the ninth receive clock pulse. At this time, the received data is read by reading ICDRR. At the same time, RDRF is cleared. 4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set. If the eighth receive clock pulse falls after reading ICDRR by other processing while RDRF is 1, SCL is fixed to a low level until ICDRR is read. 5. If the next frame is the last receive data, set the RCVD bit in ICCR1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition is issued. 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RCVD to 0. 8. The operation returns to the slave receive mode. Rev.2.00 Oct. 16, 2007 Page 510 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A Bit 7 9 1 Master receive mode 2 3 4 5 6 7 8 9 A 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS RDRF ICDRS Data 1 ICDRR Data 1 User processing [1] Clear TEND and TRS, then TDRE [2] Read ICDRR (dummy read) [3] Read ICDRR Figure 13.7 Master Receive Mode Operation Timing 1 Rev.2.00 Oct. 16, 2007 Page 511 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) SDA (Slave output) RDRF 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCVD ICDRS Data n-1 Data n ICDRR User processing Data n-1 Data n [5] Set RCVD then read ICDRR [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode Figure 13.8 Master Receive Mode Operation Timing 2 13.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the receive clock pulse and returns an acknowledge signal. Figures 13.9 and 13.10 show the operation timings in slave transmit mode. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following the detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing the transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for end processing, and read ICDRR (dummy read) to free SCL. 5. Clear TDRE. Rev.2.00 Oct. 16, 2007 Page 512 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE A 9 Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2 ICDRR User processing [2] Write data (data 1) to ICDRT [2] Write data (data 2) to ICDRT [2] Write data (data 3) to ICDRT Figure 13.9 Slave Transmit Mode Operation Timing 1 Rev.2.00 Oct. 16, 2007 Page 513 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 A 1 2 3 4 5 6 7 8 9 A/A Slave receive mode TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Clear TRS and read ICDRR (dummy read) [5] Clear TDRE Figure 13.10 Slave Transmit Mode Operation Timing 2 Rev.2.00 Oct. 16, 2007 Page 514 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and the transmit data, and the slave device returns an acknowledge signal. Figures 13.11 and 13.12 show the operation timings in slave receive mode. The reception procedure and operations in slave receive mode are described below. 1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. Set the MST and TRS bits in ICCRA to select slave receive mode and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data shows the slave address and R/W, it is not used). 3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is fixed to a low level until RDRF is cleared. The change of the acknowledge (ACKBT) setting before clearing RDRF to be returned to the master device is reflected in the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF A A 9 1 2 3 4 5 6 7 8 9 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR (dummy read) [2] Read ICDRR Figure 13.11 Slave Receive Mode Operation Timing 1 Rev.2.00 Oct. 16, 2007 Page 515 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 2 3 4 5 6 7 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A A/A RDRF ICDRS Data 1 Data 2 ICDRR User processing [3] Set ACKBT [3] Read ICDRR Data 1 [4] Read ICDRR Figure 13.12 Slave Receive Mode Operation Timing 2 13.4.6 Noise Canceller The logic levels at the SCL and SDA pins are routed through the noise cancellers before being latched internally. Figure 13.13 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The signal input to SCL (or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock Sampling clock SCL input or SDA input C D Q D C Q Latch Latch Compare match detection circuit Internal SCL or internal SDA System clock period Sampling clock Figure 13.13 Block Diagram of Noise Canceller Rev.2.00 Oct. 16, 2007 Page 516 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.4.7 Example of Use 2 Sample flowcharts in respective modes that use the I C bus interface are shown in figures 13.14 to 13.17. Start Initial settings Read BBSY in ICCRB No [1] BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCRA Write BBSY = 1 and SCP = 0 Write the transmit data in ICDRT Read TEND in ISCR No [5] TEND = 1? Yes Read ACKBR in ICIER [6] ACKBR = 0? Yes Transmit mode? Yes Write the transmit data to ICDRT Read TDRE in ICSR TDRE = 1? Yes No Last byte? Yes Write the transmit data to ICDRT Read TEND in ICSR No [10] TEND = 1? Yes Clear TEND in ICSR Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [14] STOP = 1? Yes Set MST = 0 and TRS = 0 in ICCRA Clear TRDE in ICSR End [11] [12] [13] [9] No Master receive mode No [2] [3] [1] [2] [3] [4] [5] [6] [7] Detect the state of the SCL and SDA lines Set to master transmit mode Issue the start condition Set the transmit data for the first byte (slave address + R/W) Wait for 1 byte of data to be transmitted Detect the acknowledge bit, transferred from the specified slave device Set the transmit data for the second and subsequent data (except for the last byte) Wait for ICDRT empty Set the last byte of transmit data [4] [8] [9] [7] [10] [8] Wait for the completion of transmission of the last byte Clear the TEND flag Clear the STOP flag Issue the stop condition Wait for the creation of the stop condition Set to slave receive mode. Clear TDRE. [11] [12] [13] [14] [15] [15] Figure 13.14 Sample Flowchart of Master Transmit Mode Rev.2.00 Oct. 16, 2007 Page 517 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Master receive mode Clear TEND in ICSR Set TRS = 0 (ICCRA) Clear TDRE in ICSR Set ACKBT = 0 (ICIER) Dummy read ICDRR Dummy read ICSR No RDRF = 1? Yes [4] [2] [3] [1] [1] Clear TEND, set to master receive mode, then clear TDRE* [2] Set acknowledge to the transmitting device* [3] Dummy read ICDRR* [4] Wait for 1 byte of data to be received [5] Check if (last receive -1) [6] Read the receive data [7] Set acknowledge of the last byte. Disable continuous reception (RCVD = 1). [8] Read receive data of (last byte -1). Yes [5] Last receive -1? No [9] Wait for the last byte to be received [10] Clear the STOP flag Read ICDRR [6] [11] Issue the stop condition [12] Wait for the creation of stop condition Set ACKBT = 1 (ICIER) [7] [13] Read the receive data of the last byte [14] Clear RCVD to 0 [15] Set to slave receive mode Set RCVD = 1 (ICCRA) Read ICDRR Read RDRF in ICSR No [9] RDRF = 1? Yes [8] Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [10] [11] [12] STOP = 1? Yes Read ICDRR Set RCVD = 0 (ICCRA) Set MST = 0 (ICCRA) End Note: * [13] [14] [15] Do not generate an interrupt during steps [1] to [3]. Figure 13.15 Sample Flowchart for Master Receive Mode Rev.2.00 Oct. 16, 2007 Page 518 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Slave transmit mode Clear AAS in ICSR [1] [1] Clear the AAS flag. [2] Set the transmit data for ICDRT (except the last byte). [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [3] TDRE = 1? Yes No Last byte? Yes Write the transmit data to ICDRT Read TEND in ICSR No [5] TEND = 1? Yes Clear TEND in ICSR Set TRS = 0 (ICCRA) Dummy read ICDRR Clear TDRE in ICSR End [4] [6] Clear the TEND flag. [7] Set to slave receive mode. [8] Dummy read ICDRR to free the SCL line. [9] Clear the TDRE flag. [5] Wait for the last byte of data to be transmitted. Write the transmit data to ICDRT Read TRD in ICSR No [6] [7] [8] [9] Figure 13.16 Sample Flowchart for Slave Transmit Mode Rev.2.00 Oct. 16, 2007 Page 519 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) Slave receive mode Clear AAS in ICSR Set ACKBT = 0 in ICIER Dummy read ICDRR Read RDRF in ICSR No RDRF = 1? Yes The last reception -1? No Read ICDRR Yes [5] [4] [5] [6] [7] [8] [9] Detect (last reception -1) Read the receive data. Set the acknowledge for the last byte. Read the receive data of (last byte -1). Wait for the reception of the last byte to be completed. [1] [2] [3] [1] [2] [3] [4] Clear the AAS flag. Set the acknowledge for the transmit device. Dummy read ICDRR Wait for 1 byte of data to be received* [6] [10] Read the last byte of receive data. Set ACKBT = 1 in ICIER Read ICDRR Read RDRF in ICSR No [7] [8] [9] RDRF = 1? Yes Read ICDRR End [10] Figure 13.17 Sample Flowchart for Slave Receive Mode Rev.2.00 Oct. 16, 2007 Page 520 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 13.3 shows the contents of each interrupt request. Table 13.3 Interrupt Requests Interrupt Request Transmit Data Empty Transmit End Receive Data Full Stop Recognition NACK Detection Arbitration Lost Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE = 1) ⋅ (TIE = 1) (TEND = 1) ⋅ (TEIE = 1) (RDRF = 1) ⋅ (RIE = 1) (STOP = 1) ⋅ (STIE = 1) {(NACKF = 1) + (AL = 1)} ⋅ (NAKIE = 1) If an interrupt condition described in table 13.3 is set to 1 and if the I bit in CCR is cleared to 0, the CPU executes the exception handling corresponding to the interrupt. During the exception handling, appropriate interrupt source needs to be cleared. However, note that TDRE and TEND are cleared automatically by writing transmit data to ICDRT and that RDRF is also cleared automatically by reading ICDRR. Especially not that TDRE is set to 1 again simultaneously when transmit data is written to ICDRT; thus, additional clearing TDRE may cause one more byte to be transmitted erroneously. Rev.2.00 Oct. 16, 2007 Page 521 of 916 REJ09B0381-0200 Section 13 I2C Bus Interface 2 (IIC2) 13.6 Bit Synchronous Circuit This module has a possibility that the high-level period is shortened in the two states described below. In master mode, • When SCL is driven low by the slave device • When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or pull-up resistance) Therefore, this module monitors SCL and communicates bit by bit in synchronization. Figure 13.18 shows the timing of the bit synchronous circuit, and table 13.4 shows the time when SCL output changes from low to Hi-Z and the period which SCL is monitored. SCL monitor timing reference clock SCL VIH Internal SCL Figure 13.18 Timing of the Bit Synchronous Circuit Table 13.4 Time for Monitoring SCL CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc Rev.2.00 Oct. 16, 2007 Page 522 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Section 14 Controller Area Network (RCAN-ET) 14.1 14.1.1 Summary Overview This document primarily describes the programming interface for the RCAN-ET module. It serves to facilitate the hardware/software interface so that engineers involved in the RCAN-ET implementation can ensure the design is successful. 14.1.2 Scope The CAN Data Link Controller function is not described in this document. It is the responsibility of the reader to investigate the CAN Specification Document (see references). The interfaces from the CAN Controller are described, in so far as they pertain to the connection with the User Interface. The programming model is described in some detail. It is not the intention of this document to describe the implementation of the programming interface, but to simply present the interface to the underlying CAN functionality. The document places no constraints upon the implementation of the RCAN-ET module in terms of process, packaging or power supply criteria. These issues are resolved where appropriate in implementation specifications. 14.1.3 Audience In particular this document provides the design reference for software authors who are responsible for creating a CAN application using this module. In the creation of the RCAN-ET user interface LSI engineers must use this document to understand the hardware requirements. Rev.2.00 Oct. 16, 2007 Page 523 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.1.4 References 1. CAN Specification Version 2.0 part A, Robert Bosch GmbH, 1991 2. CAN Specification Version 2.0 part B, Robert Bosch GmbH, 1991 3. Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany, 1997 4. Road vehicles - Controller area network (CAN): Part 1: Data link layer and physical signalling (ISO-11898-1, 2003) 14.1.5 Features • Supports CAN specification 2.0B • Bit timing compliant with ISO-11898-1 • 16 Mailbox version • Clock 16 to 24 MHz* • 15 programmable Mailboxes for transmit/receive + 1 receive-only mailbox • Sleep mode for low power consumption and automatic recovery from sleep mode by detecting CAN bus activity • Programmable receive filter mask (standard and extended identifier) supported by all Mailboxes • Programmable CAN data rate up to 1Mbit/s • Transmit message queuing with internal priority sorting mechanism against the problem of priority inversion for real-time applications • Data buffer access without software handshake requirement in reception • Flexible micro-controller interface • Flexible interrupt structure Note: * Refer to section 23.7.1, Notes on Clock Pulse Generator. Rev.2.00 Oct. 16, 2007 Page 524 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.2 14.2.1 Architecture Block Diagram The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox, Mailbox Control, and CAN Interface. Figure 14.1 shows the block diagram of the RCAN-ET Module. The bus interface timing is designed according to the peripheral bus I/F required for each product. CRx CAN Interface REC Can Core TEC CTx BCR Transmit Buffer Receive Buffer Control Signals Status Signals Micro Processor Interface TXPR TXCR TXACK ABACK RFPR UMSR 32-bit internal Bus System MCR 16-bit peripheral bus GSR IRR IMR RXPR MBIMR Mailbox Control Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 control0 LAFM DATA Mailbox 0 to 15 (RAM) Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 control1 Mailbox 0 to 15 (register) Figure 14.1 RCAN-ET Architecture Rev.2.00 Oct. 16, 2007 Page 525 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.2.2 Important Although core of RCAN-ET is designed based on a 32-bit bus system, the whole RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord (32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual, LongWord access means the two consecutive accesses. (1) Micro Processor Interface (MPI) The MPI allows communication between the Renesas CPU and RCAN-ET's registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so that the RCAN-ET can automatically exit the Sleep mode. It contains registers such as MCR, IRR, GSR and IMR. (2) Mailbox The Mailboxes consists of RAM configured as message buffers and registers. There are 16 Mailboxes, and each mailbox has the following information. • CAN message control (identifier, rtr, ide,etc) • CAN message data (for CAN Data frames) • Local Acceptance Filter Mask for reception • CAN message control (dlc) • 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, AutoTransmission for Remote Request bit, New Message Control bit Rev.2.00 Oct. 16, 2007 Page 526 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) (3) Mailbox Control The Mailbox Control handles the following functions: • For received messages, compare the IDs and generate appropriate RAM addresses/data to store messages from the CAN Interface into the Mailbox and set/clear appropriate registers accordingly. • To transmit messages, RCAN-ET will run the internal arbitration to pick the correct priority message, and load the message from the Mailbox into the Tx-buffer of the CAN Interface and set/clear appropriate registers accordingly. • Arbitrates Mailbox accesses between the CPU and the Mailbox Control. • Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, MBIMR, and UMSR. (4) CAN Interface This block conforms to the requirements for the CAN Bus Data Link Controller which is specified in Ref. [2, 4]. It fulfils all the functions of the standard Data Link Controller as specified by the OSI 7 Layer Reference model. This functional entity also provides the registers and the logic which are specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error Counter, the Bit Configuration Registers and various useful Test Modes. This block also contains functional entities to hold the data received and the data to be transmitted for the CAN Data Link Controller. 14.2.3 Input/Output Pins Table 14.1 lists the RCAN-ET input and output pins. Table 14.1 Pin Configuration of the RCAN-ET Channel 0 Name Transmit data pin Receive data pin 1 Transmit data pin Receive data pin Abbreviation CTx_0 CRx_0 CTx_1 CRx_1 I/O Output Input Output Input Function CAN-bus transmit pin CAN-bus receive pin CAN-bus transmit pin CAN-bus receive pin Rev.2.00 Oct. 16, 2007 Page 527 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.2.4 Memory Map The diagram of the memory map is shown in figure 14.2. Bit 15 H'000 H'002 H'004 H'006 H'008 H'00A H'00C Master Control Register (MCR) General Status Register(GSR) Bit Configuration Register 1 (BCR1) Bit Configuration Register 0 (BCR0) Interrupt Register (IRR) Interrupt Mask Register (IMR) Transmit Error Counter (TEC) Receive Error Counter (REC) H'100 H'0A4 Bit 0 H'0A0 Bit 15 Bit 0 H'020 H'022 Transmit Pending Request Register (TXPR1) Transmit Pending Request Register (TXPR0) H'104 Mailbox-0 Control 0 (STDID, EXTID, RTR, IDE) LAFM H'108 H'02A Transmit Cancel Register (TXCR0) H'10A H'10C H'032 Transmit Acknowledge Register (TXACK0) H'10E H'110 0 2 Mailbox 0 Data (8 bytes) 1 3 5 7 4 6 Mailbox-0 Control 1 (NMC, MBC, DLC) H'03A Abort Acknowledge Register (ABACK0) H'120 H'042 Receive Pending Register (RXPR0) H'140 H'04A Mailbox-2 Control/LAFM/Data etc. Mailbox-1 Control/LAFM/Data etc. Remote Frame Pending Register (RFPR0) H'160 Mailbox-3 Control/LAFM/Data etc. H'052 Mailbox Interrupt Mask Register (MBIMR0) H'05A Unread Message Status Register (UMSR0) H'2E0 Mailbox-15 Control/LAFM/Data etc. Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed. Addresses shown above are offset addresses. As for actual addresses, see section 25, List of Registers. Figure 14.2 RCAN-ET Memory Map Rev.2.00 Oct. 16, 2007 Page 528 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.3 14.3.1 Mailbox Mailbox Structure Mailboxes play a role as message buffers to transmit/receive CAN frames. Each Mailbox is comprised of 3 identical storage fields: Message Control, Local Acceptance Filter Mask, and Message Data. Table 14.2 shows the address map for the control, LAFM, data and addresses for each mailbox. Table 14.2 Address Map for Each Mailbox Address Control 0 Mailbox 0 (Receive Only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 bytes H'100 to H'103 H'120 to H'123 H'140 to H'143 H'160 to H'163 H'180 to H'183 H'1A0 to H'1A3 H'1C0 to H'1C3 H'1E0 to H'1E3 H'200 to H'203 H'220 to H'223 H'240 to H'243 H'260 to H'263 H'280 to H'283 H'2A0 to H'2A3 H'2C0 to H'2C3 H'2E0 to H'2E3 LAFM 4 bytes H'104 to H'107 H'124 to H'127 H'144 to H'147 H'164 to H'167 H'184 to H'187 H'1A4 to H'1A7 H'1C4 to H'1C7 H'1E4 to H'1E7 H'204 to H'207 H'224 to H'227 H'244 to H'247 H'264 to H'267 H'284 to H'287 H'2A4 to H'2A7 H'2C4 to H'2C7 H'2E4 to H'2E7 Data 8 bytes H'108 to H'10F H'128 to H'12F H'148 to H'14F H'168 to H'16F H'188 to H'18F H'1A8 to H'1AF H'1C8 to H'1CF H'1E8 to H'1EF H'208 to H'20F H'228 to H'22F H'248 to H'24F H'268 to H'26F H'288 to H'28F H'2A8 to H'2AF H'2C8 to H'2CF H'2E8 to H'2EF Control 1 2 bytes H'110 to H'111 H'130 to H'131 H'150 to H'151 H'170 to H'171 H'190 to H'191 H'1B0 to H'1B1 H'1D0 to H'1D1 H'1F0 to H'1F1 H'210 to H'211 H'230 to H'231 H'250 to H'251 H'270 to H'271 H'290 to H'291 H'2B0 to H'2B1 H'2D0 to H'2D1 H'2F0 to H'2F1 Mailbox-0 is a receive-only box, and all the other Mailboxes can operate as both receive and transmit boxes, dependant upon the MBC (Mailbox Configuration) bits in the Message Control. Figure 14.3 shows the structure of a Mailbox in detail. Rev.2.00 Oct. 16, 2007 Page 529 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Table 14.3 Roles of Mailboxes Tx MB15 to 1 MB0 OK ⎯ Rx OK OK MB0 (reception MB) Regiter Name Address 15 MB[0].CONTROL0H MB[0].CONTROL0L MB[0].LAFMH MB[0].LAFML MB[0].MSG_DATA[0][1] MB[0].MSG_DATA[2][3] MB[0].MSG_DATA[4][5] MB[0].MSG_DATA[6][7] MB[0].CONTROL1H, L H'100 H'102 H'104 H'106 H'108 H'10A H'10C H'10E H'110 0 0 NMC IDE_ LAFM Byte: 8-bit access, Word: 16-bit access, LW (LongWord): 32-bit access Data Bus 14 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Word/LW Word EXTID_ LAFM[17:16] Access Size Field Name IDE RTR STDID[10:0] EXTID[15:0] EXTID[17:16] Control 0 0 0 STDID_LAFM[10:0] EXTID_LAFM[15:0] Word/LW Word LAFM MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 0 0 MBC[2:0] 0 0 0 MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 0 DLC[3:0] Byte/Word/LW Byte/Word Byte/Word/LW Byte/Word Byte/Word Control 1 Data MB1 to 15 (MB for transmission/reception) Register Name Address 15 MB[n].CONTROL0H MB[n].CONTROL0L MB[n].LAFMH MB[n].LAFML H'100 + n*32 H'102 + n*32 H'104 + n*32 H'106 + n*32 IDE_ LAFM Data Bus 14 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Size Field Name IDE RTR STDID[10:0] EXTID[15:0] EXTID[17:16] Word/LW Control 0 Word 0 0 STDID_LAFM[10:0] EXTID_LAFM[15:0] EXTID_ LAFM[17:16] Word/LW LAFM Word Byte/Word/LW Data Byte/Word Byte/Word/LW Byte/Word MB[n].MSG_DATA[0][1] H'108 + n*32 MB[n].MSG_DATA[2][3] H'10A + n*32 MB[n].MSG_DATA[4][5] H'10C + n*32 MB[n].MSG_DATA[6][7] H'10E + n*32 MB[n].CONTROL1H, L H'110 + n*32 0 0 MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 NMC ATX DART MBC[2:0] 0 0 0 MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 0 DLC[3:0] Byte/Word Control 1 Notes: n = 1 to 15 (Mailbox number) 1. All bits shadowed in grey are reserved and the write value should be 0. The value returned by a read may not always be 0 and should not be relied upon. 2. MBC1 bit in mailbox is fixed to 1. 3. ATX and DART are not supported by mailbox-0, and the MBC setting of mailbox-0 is limited. 4. When the MCR15 bit is 1, the order of STDID, RTR, IDE and EXTID of both message control and LAFM differs from HCAN2. Figure 14.3 Mailbox-n Structure Rev.2.00 Oct. 16, 2007 Page 530 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.3.2 Message Control Field STDID[10:0]: These bits set the identifier (standard identifier) of data frames and remote frames. EXTID[17:0]: These bits set the identifier (extended identifier) of data frames and remote frames. RTR (Remote Transmission Request bit) : Used to distinguish between data frames and remote frames. This bit is overwritten by received CAN Frames depending on Data Frames or Remote Frames. Important: Please note that, when ATX bit is set with the setting MBC = 001(bin), the RTR bit will never be set. When a Remote Frame is received, the CPU can be notified by the corresponding RFPR set or IRR[2] (Remote Frame Request Interrupt), however, as RCAN-ET needs to transmit the current message as a Data Frame, the RTR bit remains unchanged. Important: In order to support automatic answer to remote frame when MBC = B'001 is used and ATX = 1 the RTR flag must be programmed to zero to allow data frame to be transmitted. Note: When a Mailbox is specified to send a remote frame request, the DLC used for transmission is the one stored into the Mailbox. RTR 0 1 Description Data frame Remote frame IDE (Identifier Extension bit) : Used to distinguish between the standard format and extended format of CAN data frames and remote frames. IDE 0 1 Description Standard format Extended format Rev.2.00 Oct. 16, 2007 Page 531 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) • Mailbox-0 Bit: 15 0 Initial value: R/W: 0 R 14 0 0 R 13 NMC 0 R/W 12 0 0 R 11 0 0 R 1 R/W 10 9 MBC[2:0] 1 R/W 1 R/W 8 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 0 R/W 3 2 1 0 DLC[3:0] 0 R/W 0 R/W 0 R/W Note: MBC[1] of MB0 is always "1". • Mailbox-15 to 1 Bit: 15 0 Initial value: R/W: 0 R 14 0 0 R 13 NMC 0 R/W 12 11 10 9 MBC[2:0] 1 R/W 1 R/W 1 R/W 8 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 0 R/W 3 2 1 0 ATX DART 0 R/W 0 R/W DLC[3:0] 0 R/W 0 R/W 0 R/W NMC (New Message Control): When this bit is set to '0', the Mailbox of which the RXPR or RFPR bit is already set does not store the new message but maintains the old one and sets the UMSR correspondent bit. When this bit is set to '1', the Mailbox of which the RXPR or RFPR bit is already set overwrites with the new message and sets the UMSR correspondent bit. Important: Please note that if a remote frame is overwritten with a data frame or vice versa could be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this case the RTR bit within the Mailbox Control Field should be relied upon. NMC 0 1 Description Overrun mode (Initial value) Overwrite mode ATX (Automatic Transmission of Data Frame): When this bit is set to '1' and a Remote Frame is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same Mailbox using the current contents of the message data and updated DLC by setting the corresponding TXPR automatically. The scheduling of transmission is still governed by ID priority or Mailbox priority as configured with the Message Transmission Priority control bit (MCR2). In order to use this function, MBC[2:0] needs to be programmed to be B'001. When a transmission is performed by this function, the DLC (Data Length Code) to be used is the one that has been received. Application needs to guarantee that the DLC of the remote frame correspond to the DLC of the data frame requested. Important: When ATX is used and MBC = B'001 the filter for the IDE bit cannot be used since ID of remote frame has to be exactly the same as that of data frame as the reply message. Rev.2.00 Oct. 16, 2007 Page 532 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Important: Please note that, when this function is used, the RTR bit will never be set despite receiving a Remote Frame. When a Remote Frame is received, the CPU will be notified by the corresponding RFPR set, however, as RCAN-ET needs to transmit the current message as a Data Frame, the RTR bit remains unchanged. Important: Please note that in case of overrun condition (UMSR flag set when the Mailbox has its NMC = 0), the message received is discarded. In case a remote frame is causing overrun into a Mailbox configured with ATX = 1, a request to automatically transmit the corresponding message may be accepted. ATX 0 1 Description Automatic Transmission of Data Frame disabled (Initial value) Automatic Transmission of Data Frame enabled DART (Disable Automatic Re-Transmission): When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. In effect, when this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is set to '0', RCAN-ET tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. DART 0 1 Description Re-transmission enabled (Initial value) Re-Transmission disabled MBC[2:0] (Mailbox Configuration): These bits configure the nature of each Mailbox as in table 14.4. When MBC = B'111, the Mailbox is inactive, i.e., it does not receive or transmit a message regardless of TXPR or other settings. The MBC = '110', '101' and '100' settings are prohibited. When the MBC is set to any other value, the LAFM field becomes available. Please don't set TXPR when MBC is set as reception. There is no hardware protection, and TXPR remains set. MBC[1] of Mailbox-0 is fixed to "1" by hardware. Rev.2.00 Oct. 16, 2007 Page 533 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Table 14.4 Mailbox Function Setting Data Frame MBC[2] MBC[1] MBC[0] Transmit Remote Frame Transmit Data Frame Receive Remote Frame Receive Remarks 0 0 0 0 0 1 Yes Yes Yes Yes No No No Yes • • • • Not allowed for Mailbox-0 Can be used with ATX* Not allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used 0 0 1 1 1 1 Note: 1 1 0 0 1 1 * 0 1 0 1 0 1 No No No No Yes Yes Yes No • • • • Setting prohibited Setting prohibited Setting prohibited Mailbox inactive (Initial value) In order to support automatic retransmission, RTR shall be "0" when MBC = 001(bin) and ATX=1. When using ATX with the setting 1, the filter for IDE must not be used. DLC[3:0] (Data Length Code): These bits encode the number of data bytes from 0,1, 2, …, 8 that will be transmitted in a data frame. Please note that when a remote frame request is transmitted the DLC value to be used must be the same as the DLC of the data frame that is requested. DLC[3] 0 0 0 0 0 0 0 0 1 DLC[2] 0 0 0 0 1 1 1 1 x DLC[1] 0 0 1 1 0 0 1 1 x DLC[0] 0 1 0 1 0 1 0 1 x Description Data Length = 0 bytes (Initial value) Data Length = 1 byte Data Length = 2 bytes Data Length = 3 bytes Data Length = 4 bytes Data Length = 5 bytes Data Length = 6 bytes Data Length = 7 bytes Data Length = 8 bytes Rev.2.00 Oct. 16, 2007 Page 534 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.3.3 Local Acceptance Filter Mask (LAFM) This area is used as Local Acceptance Filter Mask (LAFM) for receive boxes. LAFM: When MBC is set to 001, 010, 011 (Bin), this field is used as LAFM Field. LAFM allows a Mailbox to accept more than one identifier. The LAFM is comprised of two 16-bit read/write areas as in figure 14.4. 15 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Name MB[N].LAFMH MB[N].LAFML Address Acces Size Word/LW Feld Name LAFM Field IDE_ H'104 + N*32 LAFM STDID_LAFM[10:0] EXTID_LAFM[15:0] EXTID_ LAFM[17:16] H'106 + N*32 Word Note: N = 0 to 15 (Mailbox number) Figure 14.4 Acceptance Filter If a bit is set in the LAFM, then the corresponding bit of a received CAN identifier is ignored when the RCAN-ET searches a Mailbox with the matching CAN identifier. If the bit is cleared, then the corresponding bit of a received CAN identifier must match to the STDID/IDE/EXTID set in the mailbox to be stored. The structure of the LAFM is same as the message control in a Mailbox. If this function is not required, it must be filled with '0'. Important: RCAN-ET starts to find a matching identifier from Mailbox-15 down to Mailbox-0. As soon as RCAN-ET finds one matching, it stops the search. The message will be stored or not depending on the NMC and RXPR/RFPR flags. This means that, even using LAFM, a received message can only be stored into 1 Mailbox. Important: When a message is received and a matching Mailbox is found, the whole message is stored into the Mailbox. This means that, if the LAFM is used, the STDID, RTR, IDE and EXTID may differ to the ones originally set as they are updated with the STDID, RTR, IDE, and EXTID of the received message. STDID_LAFM[10:0] — Filter mask bits for the CAN base identifier [10:0] bits. STDID_LAFM[10:0] Description 0 1 Corresponding STD_ID bit is cared Corresponding STD_ID bit is "don't cared" Rev.2.00 Oct. 16, 2007 Page 535 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) EXTID_LAFM[17:0] — Filter mask bits for the CAN Extended identifier [17:0] bits. EXTID_LAFM[17:0] Description 0 1 Corresponding EXT_ID bit is cared Corresponding EXT_ID bit is "don't cared" IDE_LAFM — Filter mask bit for the CAN IDE bit. IDE_LAFM 0 1 Description Corresponding IDE_ID bit is cared Corresponding IDE_ID bit is "don't cared" 14.3.4 Message Data Fields Storage for the CAN message data that is transmitted or received. MSG_DATA[0] corresponds to the first data byte that is transmitted or received. The bit order on the CAN bus is bit 7 through to bit 0. Rev.2.00 Oct. 16, 2007 Page 536 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.4 RCAN-ET Control Registers The following sections describe RCAN-ET control registers. The address is mapped as in table 14.5. Important: These registers can only be accessed in Word size (16-bit). Table 14.5 RCAN-ET Control Registers Configuration Description Master Control Register General Status Register Baud Rate Configuration Register 1 Baud Rate Configuration Register 0 Interrupt Register Interrupt Register Error Counter Register Address 000 002 004 006 008 00A 00C Name MCR GSR BCR1 BCR0 IRR IMR TEC/REC Access Size (bits) Word Word Word Word Word Word Word 14.4.1 Master Control Register (MCR) The MCR is a 16-bit read/write register that controls RCAN-ET. • MCR (Address = H'000) Bit: 15 14 13 — 12 — 11 — 10 9 TST[2:0] 8 7 6 5 4 — 3 — 2 1 0 MCR15 MCR14 MCR7 MCR6 MCR5 MCR2 MCR1 MCR0 Initial value: 1 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 1 R/W Bit 15—ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE, and EXTID of both message control and LAFM. Bit 15 : MCR15 0 1 Description RCAN-ET is the same as HCAN2 RCAN-ET is not the same as HCAN2 (Initial value) Rev.2.00 Oct. 16, 2007 Page 537 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) MCR15 (ID Reorder) = 0 Address H'100 + N*32 H'102 + N*32 H'104 + N*32 H'106 + N*32 0 15 0 14 13 12 11 10 9 STDID[10:0] 8 7 6 5 4 3 RTR 2 IDE 1 0 Access Size Word/LW Feld Name Control 0 EXTID[17:16] EXTID[15:0] STDID_LAFM[10:0] EXTID_LAFM[15:0] 0 IDE_ LAFM EXTID_LAFM [17:16] Word Word/LW LAFM Field Word MCR15 (ID Reorder) = 1 Address H'100 + N*32 H'102 + N*32 H'104 + N*32 H'106 + N*32 Note: N = 0 to 15 (Mailbox number) IDE_ LAFM 15 IDE 14 RTR 13 0 12 11 10 9 8 7 STDID[10:0] 6 5 4 3 2 1 0 Access Size Word/LW Feld Name Control 0 EXTID[17:16] EXTID[15:0] 0 0 STDID_LAFM[10:0] EXTID_LAFM[15:0] EXTID_LAFM [17:16] Word Word/LW LAFM Field Word Figure 14.5 ID Reorder This bit can be modified only in reset mode. Bit 14—Auto Halt Bus Off (MCR14): If both this bit and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters Bus Off. Bit 14 : MCR14 0 1 Description RCAN-ET remains in Bus Off for normal recovery sequence (128 ×11 Recessive Bits) (Initial value) RCAN-ET moves directly into Halt Mode after it enters Bus Off if MCR6 is set. This bit can be modified only in reset mode. Bit 13—Reserved: The written value should always be '0' and the returned value is '0'. Bit 12—Reserved: The written value should always be '0' and the returned value is '0'. Bit 11—Reserved: The written value should always be '0' and the returned value is '0'. Rev.2.00 Oct. 16, 2007 Page 538 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Bits 10 to 8—Test Mode (TST[2:0]): These bits enable/disable the test modes. Please note that before activating the Test Mode it is requested to move RCAN-ET into Halt mode or Reset mode. This is to avoid that the transition to Test Mode could affect a transmission/reception in progress. For details, please refer to section 14.6.2, Test Mode Settings. Please note that the test modes are allowed only for diagnosis and tests and not when RCAN-ET is used in normal operation. Bit 10: TST2 0 0 0 0 1 1 1 1 Bit 9: TST1 0 0 1 1 0 0 1 1 Bit 8: TST0 0 1 0 1 0 1 0 1 Description Normal Mode (initial value) Listen-Only Mode (Receive-Only Mode) Self Test Mode 1 (External) Self Test Mode 2 (Internal) Write Error Counter Error Passive Mode Setting prohibited Setting prohibited Bit 7—Auto-Wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is set, the RCAN-ET automatically cancels the sleep mode (MCR5) by detecting CAN bus activity (dominant bit). If MCR7 is cleared the RCAN-ET does not automatically cancel the sleep mode. RCAN-ET cannot store the message that wakes it up. Note: MCR7 cannot be modified while in sleep mode. Bit 7 : MCR7 0 1 Description Auto-wake by CAN bus activity disabled (Initial value) Auto-wake by CAN bus activity enabled Rev.2.00 Oct. 16, 2007 Page 539 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Bit 6—Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering immediately to Error Active mode. Bit 6 : MCR6 0 1 Description Don't enter Halt mode even if MCR1 is set during Bus Off, but wait up to end of recovery sequence (Initial value) Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are asserted. Bit 5—Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while RCAN-ET is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep mode. This mode will be exited in two ways: 1. by writing a '0' to this bit position, 2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus. If Auto wake up mode is disabled, RCAN-ET will ignore all CAN bus activities until the sleep mode is terminated. When leaving this mode the RCAN-ET will synchronize to the CAN bus (by checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2 method is used, RCAN-ET will miss the first message to receive. CAN transceivers stand-by mode will also be unable to cope with the first message when exiting stand by mode, and the software needs to be designed in this manner. In sleep mode only the following registers can be accessed: MCR, GSR, IRR, and IMR. Important: RCAN-ET is required to be in Halt mode before requesting to enter in Sleep mode. That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts are cleared RCAN-ET must leave the Halt mode and enter Sleep mode simultaneously (by writing MCR[5] = 1 and MCR[1] = 0 at the same time). Bit 5 : MCR5 0 1 Description RCAN-ET sleep mode released (Initial value) Transition to RCAN-ET sleep mode enabled Rev.2.00 Oct. 16, 2007 Page 540 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Bit 4—Reserved: The written value should always be '0' and the returned value is '0'. Bit 3—Reserved: The written value should always be '0' and the returned value is '0'. Bit 2—Message Transmission Priority (MCR2): MCR2 selects the order of transmission for pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-15 as the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for transmission). If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same time). This bit can be modified only in Reset or Halt mode. Bit 2 : MCR2 0 1 Description Transmission order determined by message identifier priority (Initial value) Transmission order determined by mailbox number priority (Mailbox-15 → Mailbox-1) Bit 1—Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its current operation and then enter Halt mode (where it is cut off from the CAN bus). The RCAN-ET remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does not join the CAN bus activity and does not store messages or transmit messages. All the user registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or intermission state regardless of MCR6, RCAN-ET will enter Halt Mode within one Bit Time. If MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be notified by IRR0 and GSR4. If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters Bus Off. Rev.2.00 Oct. 16, 2007 Page 541 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) In the Halt mode, the RCAN-ET setting can be modified with the exception of the Bit Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a '0' in order to re-join the CAN bus. After this bit has been cleared, RCAN-ET waits until it detects 11 recessive bits, and then joins the CAN bus. Note: After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1 until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1 is set this can be cleared only after entering Halt mode or through a reset operation (software or hardware). Note: Transition into or recovery from HALT mode, is only possible if the BCR1 and BCR0 registers are configured to a proper Baud Rate. Bit 1 : MCR1 0 1 Description Halt mode request clear Halt mode transition request Bit 0—Reset Request (MCR0): Controls resetting of the RCAN-ET module. When this bit is changed from '0' to '1' the RCAN-ET controller enters its reset routine, re-initializing the internal logic, which then sets GSR3 and IRR0 to notify the reset mode. All user registers are initialised. RCAN-ET can be reset while this bit is set (configuration mode). This bit has to be cleared by writing a '0' to join the CAN bus. After this bit is cleared, the RCAN-ET waits until it detects 11 recessive bits, and then joins the CAN bus. The Baud Rate needs to be set up to a proper value in order to sample the value on the CAN Bus. After Power On Reset, this bit and GSR3 are always set. This means that a reset request has been made and RCAN-ET needs to be set. The Reset Request is equivalent to a Power On Reset but controlled by Software. Bit 0 : MCR0 0 1 Description Reset mode request clear CAN Interface reset mode transition request (Initial value) Rev.2.00 Oct. 16, 2007 Page 542 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) 14.4.2 General Status Register (GSR) The GSR is a 16-bit read-only register that indicates the status of RCAN-ET. • GSR (Address = H'002) Bit: 15 — Initial value: R/W: 0 R 14 — 0 R 13 — 0 R 12 — 0 R 11 — 0 R 10 — 0 R 9 — 0 R 8 — 0 R 7 — 0 R 6 — 0 R 5 4 3 2 1 0 GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 0 R 0 R 1 R 1 R 0 R 0 R Bits 15 to 6⎯Reserved: The written value should always be '0' and the returned value is '0'. Bit 5—Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error Passive or not. This bit will be set high as soon as the RCAN-ET enters the Error Passive state and is cleared when the module enters again the Error Active state (this means the GSR5 will stay high during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5 and GSR0 must be considered. Bit 5 : GSR5 0 1 Description RCAN-ET is not in Error Passive or in Bus Off status (Initial value) [Reset condition] RCAN-ET is in Error Active state RCAN-ET is in Error Passive (if GSR0 = 0) or Bus Off (if GSR0 = 1) [Setting condition] When TEC ≥128 or REC ≥128 or error passive test mode is selected Rev.2.00 Oct. 16, 2007 Page 543 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Bit 4—Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep state or not. Please note that the clearing time of this flag is not the same as the setting time of IRR12. Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP. RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits sleep mode only after two additional transmission clocks on the CAN Bus. Bit 4 : GSR4 0 1 Description RCAN-ET is not in the Halt state or Sleep state (Initial value) Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1) [Setting condition] If MCR1 is set and the CAN bus is either in intermission or idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving to Bus Off when MCR14 and MCR6 are both set Bit 3—Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not. Bit 3 : GSR3 0 1 Description RCAN-ET is not in the reset state Reset state (Initial value) [Setting condition] After an RCAN-ET internal reset (due to software or hardware reset) Bit 2—Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK is set at the 7th bit of End Of Frame. GSR2 is set at the 3rd bit of intermission if there are no more messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset, or halt transition. Bit 2 : GSR2 0 1 Description RCAN-ET is in Bus Off or a transmission is in progress [Setting condition] Not in Bus Off and no transmission in progress (Initial value) Rev.2.00 Oct. 16, 2007 Page 544 of 916 REJ09B0381-0200 Section 14 Controller Area Network (RCAN-ET) Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Bit 1 : GSR1 0 1 Description [Reset condition] When (TEC

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