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HAT2168H

HAT2168H

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

  • 描述:

    HAT2168H - Silicon N Channel Power MOS FET Power Switching - Renesas Technology Corp

  • 数据手册
  • 价格&库存
HAT2168H 数据手册
HAT2168H Silicon N Channel Power MOS FET Power Switching REJ03G0046-0600Z Rev.6.00 Jun.02.2003 Features • • • • • High speed switching Capable of 4.5 V gate drive Low drive current High density mounting Low on-resistance RDS(on) = 6.0 mΩ typ. (at VGS = 10 V) Outline LFPAK 5 5 D 3 12 4 4 G 1, 2, 3 Source 4 Gate 5 Drain SSS 123 Rev.6.00, Jun.02.2003, page 1 of 10 HAT2168H Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel to Case Thermal Resistance Channel temperature Storage temperature Symbol VDSS VGSS ID ID(pulse)Note1 IDR IAP Note 2 Ratings 30 ±20 30 120 30 15 22 15 8.33 150 – 55 to + 150 Unit V V A A A A mJ W °C/W °C °C EAR Note 2 Pch Note3 θch-C Tch Tstg Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tch = 25°C, Rg ≥ 50 Ω 3. Tc=25°C Rev.6.00, Jun.02.2003, page 2 of 10 HAT2168H Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol Min V(BR)DSS 30 Typ — — — — — 6.0 8.8 50 1730 400 130 0.55 11 5 2.4 8 20 40 4 0.85 25 Max — — ±10 1 2.5 7.9 13.5 — — — — — — — — — — — — 1.10 — Unit V V µA µA V mΩ mΩ S pF pF pF Ω nc nc nc ns ns ns ns V ns VDD = 10 V VGS = 4.5 V ID = 30 A VGS = 10 V, ID = 15 A VDD ≅ 10 V RL = 0.67 Ω Rg = 4.7 Ω IF = 30 A, VGS = 0 Note4 IF = 30 A, VGS = 0 diF/ dt = 100 A/ µs Test Conditions ID = 10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 30 V, VGS = 0 VDS = 10 V, I D = 1 mA ID = 15 A, VGS = 10 V Note4 ID = 15 A, VGS = 4.5 V Note4 ID = 15 A, VDS = 10 V Note4 VDS = 10 V VGS = 0 f = 1 MHz Gate to source breakdown voltage V(BR)GSS ±20 Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Gate Resistance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time IGSS IDSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss Rg Qg Qgs Qgd td(on) tr td(off) tf trr — — 1.0 — — 30 — — — — — — — — — — — — — Body–drain diode forward voltage VDF Body–drain diode reverse recovery time Notes: 4. Pulse test Rev.6.00, Jun.02.2003, page 3 of 10 HAT2168H Main Characteristics Power vs. Temperature Derating 40 Pch (W) I D (A) Maximum Safe Operation Area 500 10 µs 100 DC 30 10 Channel Dissipation Drain Current Op PW era 1m 10 =1 s 0µ s 20 tio nT 0m c= s 1 Operation in this area is 0.1 limited by RDS(on) Ta = 25°C 1 shot Pulse 25 °C 10 0 50 100 150 Tc (°C) 200 Case Temperature 0.01 0.1 0.3 1 3 10 30 100 Drain to Source Voltage V DS (V) Typical Output Characteristics 50 10 V 3.2 V I D (A) (A) Typical Transfer Characteristics 50 V DS = 10 V Pulse Test 40 40 4.5 V 3.0 V 30 2.8 V ID Drain Current 30 Drain Current 20 2.6 V VGS = 2.4 V 20 Tc = 75°C 25°C -25°C 10 10 Pulse Test 0 2 4 6 Drain to Source Voltage 8 10 V DS (V) 0 1 2 3 Gate to Source Voltage 5 4 V GS (V) Rev.6.00, Jun.02.2003, page 4 of 10 HAT2168H Drain to Source Saturation Voltage vs. Gate to Source Voltage 250 Pulse Test Static Drain to Source on State Resistance vs. Drain Current 100 Pulse Test 50 20 10 5 2 1 1 0.3 3 10 100 30 Drain Current I D (A) 1000 VGS = 4.5 V V DS(on) (mV) 200 Drain to Source Voltage 150 I D = 20 A 100 10 A 50 5A 0 4 8 12 Gate to Source Voltage 16 V GS (V) 20 Drain to Source On State Resistance R DS(on) (m Ω) 10 V Static Drain to Source on State Resistance R DS(on) (m Ω) Pulse Test 16 I D = 20 A Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 20 Forward Transfer Admittance vs. Drain Current 100 30 10 3 1 0.3 0.1 0.1 V DS = 10 V Pulse Test 0.3 1 3 10 30 100 25°C Tc = -25°C 75°C 12 V GS = 4.5 V 8 5 A, 10 A, 20 A 4 0 -25 10 V 10 A, 5A 0 25 50 75 100 125 150 Case Temperature Tc (°C) Drain Current I D (A) Rev.6.00, Jun.02.2003, page 5 of 10 HAT2168H Body-Drain Diode Reverse Recovery Time 100 10000 3000 1000 300 100 30 10 0 VGS = 0 f = 1 MHz 5 10 15 20 25 30 Coss Crss Typical Capacitance vs. Drain to Source Voltage Reverse Recovery Time trr (ns) Capacitance C (pF) Ciss 50 20 di/dt = 100 A/µs VGS = 0, Ta = 25°C 0.3 1 3 10 30 100 Reverse Drain Current I DR (A) 10 0.1 Drain to Source Voltage V DS (V) Dynamic Input Characteristics Switching Characteristics 20 V DS (V) 50 V GS (V) I D = 30 A V GS V DD = 25 V 10 V 5V 100 t d(off) tr Switching Time t (ns) 40 16 30 Drain to Source Voltage 30 V DS 20 12 Gate to Source Voltage 10 t d(on) tf 8 10 V DD = 25 V 10 V 5V 8 16 24 32 Gate Charge Qg (nc) 4 0 40 3 V GS = 10 V , VDS = 10 V Rg = 4.7 Ω, duty < 1 % 0.2 1 2 10 30 Drain Current I D (A) 100 0 1 0.1 Rev.6.00, Jun.02.2003, page 6 of 10 HAT2168H Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating 25 I AP = 15 A V DD = 15 V duty < 0.1 % Rg > 50 Ω 50 (A) 10 V 40 5V V GS = 0 30 20 Reverse Drain Current IDR 15 20 10 10 Pulse Test 0 0.4 0.8 1.2 1.6 V SD (V) 2.0 5 0 25 Source to Drain Voltage 50 75 100 125 150 Channel Temperature Tch (˚C) Avalanche Test Circuit EAR = Avalanche Waveform 1 2 L • IAP2 • VDSS VDSS - V DD V DS Monitor L I AP Monitor V (BR)DSS I AP VDD ID V DS Rg Vin 15 V D. U. T 50 Ω 0 VDD Rev.6.00, Jun.02.2003, page 7 of 10 HAT2168H Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance γ s (t) Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 0.05 θch - c(t) = γs (t) • θch - c θch - c = 8.33°C/ W, Tc = 25°C PDM 0.03 0.02 1 0.0 1 D= PW T PW T sh p ot uls e 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (s) Rev.6.00, Jun.02.2003, page 8 of 10 HAT2168H Package Dimensions As of January, 2003 Unit: mm 4.9 5.3 Max 4.0 ± 0.2 5 0.25 –0.03 +0.05 3.3 1.0 3.95 1 4 6.1 –0.3 +0.1 0˚ – 8˚ 1.1 Max +0.03 0.07 –0.04 0.75 Max 1.27 0.10 *0.40 ± 0.06 0.25 M 0.6 –0.20 1.3 Max +0.25 *0.20 –0.03 +0.05 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) LFPAK — — 0.080 g Rev.6.00, Jun.02.2003, page 9 of 10 4.2 HAT2168H Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.6.00, Jun.02.2003, page 10 of 10
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