HCTS541DMSR

DATASHEET HCTS541MS FN3073 Rev 1.00 August 1995 Radiation Hardened Non-Inverting Octal Buffer/Line Driver, Three-State Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) OE1 1 20 VCC A0 2 19 OE2 A1 3 18 Y0 A2 4 17 Y1 A3 5 16 Y2 A4 6 15 Y3 A5 7 14 Y4 A6 8 13 Y5 A7 9 12 Y6 GND 10 11 Y7 • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW • Input Current Levels Ii  5A at VOL, VOH VCC OE1 1 20 A0 2 19 OE2 The Intersil HCTS541MS is a Radiation Hardened noninverting octal buffer/line driver, three-state outputs. The output enable pins (OEN1 and OEN2) control the three-state outputs. If either enable is high the outputs will be in the high impedance state. For data output both enables (OEN1 and OEN2) must be low. A1 3 18 Y0 A2 4 17 Y1 A3 5 16 Y2 A4 6 15 Y3 A5 7 14 Y4 A6 8 13 Y5 The HCTS541MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. A7 9 12 Y6 10 11 Y7 Description GND The HCTS54 is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCTS541DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP HCTS541KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack HCTS541D/Sample +25oC Sample 20 Lead SBDIP HCTS541K/Sample +25oC Sample 20 Lead Ceramic Flatpack HCTS541HMSR +25oC Die Die FN3073 Rev 1.00 August 1995 Page 1 of 10 HCTS541MS Functional Block Diagram VDD P TTL P P 2 N N P 18 N N OE TTL 17 3 VDD TTL TTL 16 4 P = P N TTL 15 5 TTL 14 6 TTL 13 7 TTL 12 8 TTL 1 OE 19 TTL TRUTH TABLE INPUTS OE1 OE2 An OUTPUTS L L H H H X X Z X H X Z L L L L H = High Voltage Level, L = Low Voltage Level, X = Immaterial, Z = High Impedance FN3073 Rev 1.00 August 1995 Page 2 of 10 HCTS541MS Absolute Maximum Ratings Reliability Information Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input  10mA DC Drain Current, Any One Output 25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. Operating Conditions Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . . 500ns Max Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Three-State Output Leakage Current Noise Immunity Functional Test TEMPERATURE MIN MAX UNITS 1 +25oC - 40 A 2, 3 +125oC, -55oC - 750 A 1 +25oC 7.2 - mA 2, 3 +125oC, -55oC 6.0 - mA 1 +25oC -7.2 - mA 2, 3 +125oC, -55oC -6.0 - mA VCC = 4.5V, VIH = 2.25V, IOL = 50A, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIH = 2.75V, IOL = 50A, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 2.25V, IOH = -50A, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 2.75V, IOH = -50A, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND 1 +25oC - 0.5 A 2, 3 +125oC, -55oC - 5.0 A 1 +25oC - 1 A 2, 3 +125oC, -55oC - 50 A 7, 8A, 8B +25oC, +125oC, -55oC - - - SYMBOL ICC IOL IOH VOL VOH IIN IOZ FN LIMITS GROUP A SUBGROUPS (NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V Applied Voltage = 0V or VCC, VCC = 5.5V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V (Note 2) NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO  4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”. FN3073 Rev 1.00 August 1995 Page 3 of 10 HCTS541MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Data to Output Enable to Output TPZL TPZH Disable to Output TEMPERATURE MIN MAX UNITS VCC = 4.5V 9 +25oC 2 20 ns VCC = 4.5V 10, 11 +125oC, -55oC 2 22 ns VCC = 4.5V 9 +25oC 2 23 ns 10, 11 +125oC, -55oC 2 26 ns 9 +25oC 2 20 ns 10, 11 +125oC, -55oC 2 21 ns 9 +25oC 2 22 ns 10, 11 +125oC, -55oC 2 23 ns 9 +25oC 2 21 ns 10, 11 +125oC, -55oC 2 22 ns SYMBOL TPHL, TPLH VCC = 4.5V TPLZ VCC = 4.5V TPHZ LIMITS GROUP A SUBGROUPS (NOTES 1, 2) CONDITIONS VCC = 4.5V NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Capacitance Power Dissipation CPD Input Capacitance Output Transition Time CIN TTHL, TTLH CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1 +25oC - 38 pF 1 +125oC, -55oC - 60 pF 1 +25oC - 10 pF 1 +125oC - 10 pF 1 +25oC - 12 ns 1 +125oC, -55oC - 18 ns VCC = 5.0V, f = 1MHz VCC = 5.0V, f = 1MHz VCC = 4.5V NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER SYMBOL (NOTES 1, 2) CONDITIONS TEMPERATURE MIN MAX UNITS Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V +25oC 6.0 - mA FN3073 Rev 1.00 August 1995 Page 4 of 10 HCTS541MS TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) 200K RAD LIMITS PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL TEMPERATURE MIN MAX UNITS Output Current (Source) IOH VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V +25oC -6.0 - mA Output Voltage Low VOL VCC = 4.5V or 5.5V, VIH = VCC/2, VIL = 0.8V, IOL = 50A +25oC - 0.1 V Output Voltage High VOH VCC = 4.5V or 5.5V, VIH = VCC/2, VIL = 0.8V, IOH = -50A +25oC VCC -0.1 - V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - 5 A Three-State Output Leakage Current IOZ Applied Voltage = 0V or VCC, VCC = 5.5V +25oC - 50 A Noise Immunity Functional Test FN VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 3) +25oC - - - Data to Output TPHL, TPLH VCC = 4.5V +25oC 2 22 ns Enable to Output TPZL VCC = 4.5V +25oC 2 26 ns TPZH VCC = 4.5V +25oC 2 21 ns TPLZ VCC = 4.5V +25oC 2 23 ns TPHZ VCC = 4.5V +25oC 2 22 ns Disable to Output NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO  4.0V is recognized as a logic “1”, and VO  0.5V is recognized as a logic “0”. TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12A IOL/IOH 5 -15% of 0 Hour IOZL/IOZH 5 200nA PARAMETER TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 FN3073 Rev 1.00 August 1995 READ AND RECORD Page 5 of 10 HCTS541MS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. Alternated Group A Inspection in accordance with Method 5005 of MIL-STD-883 may be exercised. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V  0.5V VCC = 6V  0.5V 50kHz 25kHz - 20 - - - 1 - 9, 19, 20 - - 11 - 18 20 1, 19 2-9 STATIC BURN-IN I TEST CONNECTIONS (Note 1) 11 - 18 1 - 10, 19 STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 18 10 DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) - 10 NOTES: 1. Each pin except VCC and GND will have a resistor of 10k  5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 680  5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V  0.5V 11 - 18 10 1 - 9, 19, 20 NOTE: Each pin except VCC and GND will have a resistor of 47K  5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. FN3073 Rev 1.00 August 1995 Page 6 of 10 HCTS541MS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Delta Calculation (T0-T1) 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. FN3073 Rev 1.00 August 1995 Page 7 of 10 HCTS541MS AC Timing Diagrams AC Load Circuit DUT TEST POINT VIH INPUT VS CL VIL TPLH RL TPHL VOH CL = 50pF VS OUTPUT RL = 500 VOL TTLH VOH TTHL 80% 20% VOL 80% 20% OUTPUT AC VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V VSS 0 V Three-State Low Load Circuit Three-State Low Timing Diagrams VIH VS INPUT RL VIL TPZL TPLZ VT TEST POINT DUT VOZ VW OUTPUT VOL CL CL = 50pF RL = 500 THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VT 1.30 V VW 0.90 V 0 V GND FN3073 Rev 1.00 August 1995 Page 8 of 10 HCTS541MS Three-State High Timing Diagrams Three-State High Load Circuit VIH TEST POINT DUT VS INPUT VIL TPZH RL TPHZ RL = 500 VOH VT CL = 50pF VW OUTPUT VOZ CL THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VT 1.30 V VW 3.60 V 0 V GND © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3073 Rev 1.00 August 1995 Page 9 of 10 HCTS541MS Type: SiO2 Thickness: 13kÅ  2.6kÅ Die Characteristics DIE DIMENSIONS: 101 x 85 mils WORST CASE CURRENT DENSITY: