HD6417750RF200V

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7750, SH7750S, SH7750R Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series Rev.7.02 Sep 2013 Page ii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (2012.4) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page iii of lii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. 5. Reading from/Writing to Reserved Bit of Each Register Note: Treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned. Page iv of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Preface The SH-4 (SH7750 Group: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Group is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, two serial communication interfaces (SCI, SCIF), real-tim1e clock (RTC), user break controller (UBC), bus state controller (BSC) and smart card interface. This LSI can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA, as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus. Target Readers: This manual is designed for use by people who design application systems using the SH7750, SH7750S, or SH7750R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7750, SH7750S, and SH7750R. The SH-4 Software Manual contains detailed information of executable instructions. Please read the Software Manual together with this manual. How to Use the Book: • To understand general functions → Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. • To understanding CPU functions → Refer to the separate SH-4 Software Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page v of lii • User manuals for SH7750, SH7750S, and SH7750R Name of Document Document No. SH7750, SH7750S, SH7750R Group Hardware Manual This manual SH-4 Software Manual REJ09B0318-0600 • User manuals for development tools Name of Document Document No. SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual REJ10J1571-0100 SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0400 High-performance Embedded Workshop User's Manual REJ10J1737-0100 Page vi of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Main Revisions for This Edition Item Page Revision (See Manual for Details) All ⎯ Added ONPAC-BGA products (HD6417750SBA200V and HD6417750RBA240HV) 1.1 SH7750, SH7750S, SH7750R Groups Features 8 Table amended Item Features Product lineup Abbreviation Voltage (Internal) Operating Frequency Model No. Package SH7750S 1.95 V 200 MHz HD6417750SBP200 256-pin BGA Table 1.1 LSI Features HD6417750SBA200 208-pin QFP HD6417750SF200 SH7750R 1.8 V 167 MHz HD6417750SF167 1.5 V 133 MHz HD6417750SVF133 HD6417750SVBT133 264-pin CSP 1.5 V 240 MHz HD6417750RBG240 292-pin BGA HD6417750RBP240 256-pin BGA HD6417750RBA240H Section 22 Electrical Characteristics ⎯ 22.1 Absolute Maximum 895 Ratings Table 22.1 Absolute Maximum Ratings Added descriptions of HD6417750RBA240HV and HD6417750SBA200V Table and table note amended Item Symbol Value I/O, PLL, RTC, CPG power supply voltage VDDQ VDD-PLL1/2 VDD-RTC VDD-CPG –0.3 to 4.2, –0.3 to 4.6* 1 Unit Internal power supply voltage VDD –0.3 to 2.5, –0.3 to 2.1* 1 Input voltage Vin –0.3 to VDDQ +0.3 Operating temperature Topr –20 to 75, –40 to 85* Storage temperature Tstg –55 to 125 V V V 2 °C °C Notes: 1. HD6417750R only 2. HD6417750RBA240HV only 22.2 DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) 896, 897 Table title amended and note added Notes: 3. Ta = –40 to 85°C for the HD6417750RBA240HV. Ta = –20 to +75°C*3 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page vii of lii Item Page 22.2 DC Characteristics 900, 901 Table title amended and note added Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*3) Revision (See Manual for Details) Notes: 3. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417750RBA240HV. Ta = –20 to +75°C*4 Table 22.6 DC Characteristics (HD6417750SBP200 (V), HD6417750SBA200V) 904 Table title amended 22.3 AC Characteristics 920 Table title amended Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V*, HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*) Table title amended and note added Note: * This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 22.3.1 Clock and Control 922,923 Table title amended and note added Signal Timing Item Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*2, CL = 30 pF Page viii of lii Standby return oscillation settling time 1* 1 Standby return oscillation settling time 2* 1 Standby return oscillation settling time 3* 1 Notes: 1. When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Item Page Revision (See Manual for Details) 22.3.1 Clock and Control 926, 927 Table title amended and note added Signal Timing Item Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*2) Standby return oscillation settling time 1* 1 Standby return oscillation settling time 2* 1 Standby return oscillation settling time 3* 1 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*3, CL = 30 pF Notes: 1. When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417750RBA240HV. 930 Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V) Table title amended 22.3.2 Control Signal Timing Table title and table amended 946 Table 22.32 Control Signal Timing Item Table 22.33 Control Signal Timing 947 Symbol HD6417750R BP240 (V) HD6417750R BP200 (V) HD6417750R BG240 (V) HD6417750R BG200 (V) HD6417750R BA240HV HD6417750R BA240HV*5 HD6417750R F240 (V) *1 *1 *1 Min Max Min Max Min Max HD6417750R F200 (V) *1 Min Max Unit Figure Unit Figure Table title, table and table note amended HD6417750V F128 (V) *2 Item Symbol Min Max HD6417750 SVF133 (V) HD6417750S VBT133 (V) * Min 2 Max HD6417750F 167 (V) HD6417750S F167 (V) HD6417750S F200 (V) *3 Min Max HD6417750B P200M (V) HD6417750S BP200 (V) HD6417750S BA200V *4 Min Max Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*6, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 5. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 6. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page ix of lii Item Page Revision (See Manual for Details) 22.3.3 Bus Timing 950,951 Table and table note amended Table 22.34 Bus Timing (1) HD6417750R BP240 (V) HD6417750R BP200 (V) HD6417750R BG240 (V) HD6417750R BG200 (V) HD6417750R BA240HV HD6417750R 2 BA240HV* * Item Symbol Min 1 * Max Min HD6417750R F240 (V) 1 * Max Min HD6417750R F200 (V) 1 *1 Max Min Max Unit Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*3, CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417750RBA240HV. Table 22.35 Bus Timing (2) 952, 953 Table amended HD6417750 SVF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750 SVBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V * Item 22.3.4 Peripheral Module 1003, Signal Timing 1005 Symbol Min 1 Max * Min 2 Max *3 Min Max Unit Notes Table and table note amended Table 22.37 Peripheral Module Signal Timing (1) HD6417750 RBP240 (V) HD6417750 RBP200 (V) HD6417750 RBG240 (V) HD6417750R BG200 (V) HD6417750 RBA240HV HD6417750 RBA240HV*3 *2 Module Item Symbol Min HD6417750 F240 (V) *2 Max Min HD6417750 RF200 (V) *2 Max Min *2 Max Min Max Unit Figure Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF*4, PLL2 on 3. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417750RBA240HV. Table 22.38 Peripheral Module Signal Timing (2) 1005, 1006 Table amended HD6417750S VF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750S VBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V * Module Table 22.39 Peripheral Module Signal Timing (3) 1007 Symbol Min Max * Min 3 Max *4 Min Max Unit Figure Unit Figure Table amended Module Page x of lii Item 2 Item Symbol HD6417750S VF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750S VBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *2 *3 Min Max Min Max *4 Min Max R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Item Page Revision (See Manual for Details) Appendix B Package Dimensions 1023 Figure title amended 1027 Figure newly added 1067 Table and table note amended Figure B.1 Package Dimensions (256-Pin BGA: Devices Other than HD6417750RBA240HV and HD6417750SBA200V) Figure B.5 Package Dimensions (256-Pin BGA: HD6417750RBA240HV and HD6417750SBA200V) Appendix I Product Lineup Table I.1 SH7750/ SH7750S/SH7750R Product Lineup Product Name Voltage Operating Frequency Operating Temperature*1 Part Number*2 Package SH7750S 1.95 V 200 MHz –20 to 75˚C HD6417750SBP200 (V) 256-pin BGA –20 to 75˚C HD6417750SBA200V SH7750R –20 to 75˚C HD6417750SF200 (V) 208-pin QFP 1.8 V 167 MHz –20 to 75˚C HD6417750SF167 (V) 208-pin QFP 1.5 V 133 MHz –20 to 75˚C HD6417750SVF133 (V) 1.5 V 240 MHz –30 to 70˚C HD6417750SVBT133 (V) 264-pin CSP –20 to 75˚C HD6417750RBP240 (V) 256-pin BGA –20 to 75˚C HD6417750RBA240HV Notes: 1. Contact a Renesas sales office regarding product versions with specifications for a wider temperature range (–40 to +85°C). The wide temperature range (–40 to +85°C) is the standard specification for the HD6417751RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xi of lii All trademarks and registered trademarks are the property of their respective owners. Page xii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 SH7750, SH7750S, SH7750R Groups Features .................................................................... 1 Block Diagram ....................................................................................................................... 9 Pin Arrangement .................................................................................................................. 10 Pin Functions ....................................................................................................................... 14 1.4.1 Pin Functions (256-Pin BGA)................................................................................. 14 1.4.2 Pin Functions (208-Pin QFP).................................................................................. 24 1.4.3 Pin Functions (264-Pin CSP) .................................................................................. 32 1.4.4 Pin Functions (292-Pin BGA)................................................................................. 42 Section 2 Programming Model ............................................................................53 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Data Formats........................................................................................................................ 53 Register Configuration......................................................................................................... 54 2.2.1 Privileged Mode and Banks .................................................................................... 54 2.2.2 General Registers.................................................................................................... 57 2.2.3 Floating-Point Registers.......................................................................................... 59 2.2.4 Control Registers .................................................................................................... 62 2.2.5 System Registers..................................................................................................... 63 Memory-Mapped Registers.................................................................................................. 65 Data Format in Registers...................................................................................................... 66 Data Formats in Memory ..................................................................................................... 66 Processor States ................................................................................................................... 67 Processor Modes .................................................................................................................. 69 Section 3 Memory Management Unit (MMU) ....................................................71 3.1 3.2 3.3 Overview.............................................................................................................................. 71 3.1.1 Features................................................................................................................... 71 3.1.2 Role of the MMU.................................................................................................... 71 3.1.3 Register Configuration............................................................................................ 74 3.1.4 Caution.................................................................................................................... 74 Register Descriptions ........................................................................................................... 75 Address Space...................................................................................................................... 79 3.3.1 Physical Address Space .......................................................................................... 79 3.3.2 External Memory Space.......................................................................................... 82 3.3.3 Virtual Address Space............................................................................................. 83 3.3.4 On-Chip RAM Space.............................................................................................. 84 3.3.5 Address Translation ................................................................................................ 85 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xiii of lii 3.4 3.5 3.6 3.7 3.8 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ...................... 85 3.3.7 Address Space Identifier (ASID) ............................................................................ 85 TLB Functions ..................................................................................................................... 86 3.4.1 Unified TLB (UTLB) Configuration ...................................................................... 86 3.4.2 Instruction TLB (ITLB) Configuration................................................................... 90 3.4.3 Address Translation Method................................................................................... 90 MMU Functions................................................................................................................... 93 3.5.1 MMU Hardware Management................................................................................ 93 3.5.2 MMU Software Management ................................................................................. 93 3.5.3 MMU Instruction (LDTLB).................................................................................... 93 3.5.4 Hardware ITLB Miss Handling .............................................................................. 94 3.5.5 Avoiding Synonym Problems................................................................................. 95 MMU Exceptions................................................................................................................. 96 3.6.1 Instruction TLB Multiple Hit Exception................................................................. 96 3.6.2 Instruction TLB Miss Exception............................................................................. 96 3.6.3 Instruction TLB Protection Violation Exception .................................................... 98 3.6.4 Data TLB Multiple Hit Exception .......................................................................... 98 3.6.5 Data TLB Miss Exception ...................................................................................... 99 3.6.6 Data TLB Protection Violation Exception............................................................ 100 3.6.7 Initial Page Write Exception................................................................................. 101 Memory-Mapped TLB Configuration ............................................................................... 102 3.7.1 ITLB Address Array ............................................................................................. 103 3.7.2 ITLB Data Array 1................................................................................................ 104 3.7.3 ITLB Data Array 2................................................................................................ 105 3.7.4 UTLB Address Array............................................................................................ 106 3.7.5 UTLB Data Array 1 .............................................................................................. 107 3.7.6 UTLB Data Array 2 .............................................................................................. 108 Usage Notes ....................................................................................................................... 109 Section 4 Caches................................................................................................ 111 4.1 4.2 4.3 Overview............................................................................................................................ 111 4.1.1 Features................................................................................................................. 111 4.1.2 Register Configuration.......................................................................................... 113 Register Descriptions......................................................................................................... 114 Operand Cache (OC) ......................................................................................................... 116 4.3.1 Configuration........................................................................................................ 116 4.3.2 Read Operation ..................................................................................................... 120 4.3.3 Write Operation .................................................................................................... 121 4.3.4 Write-Back Buffer ................................................................................................ 122 4.3.5 Write-Through Buffer........................................................................................... 122 Page xiv of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 4.4 4.5 4.6 4.7 4.3.6 RAM Mode........................................................................................................... 123 4.3.7 OC Index Mode .................................................................................................... 124 4.3.8 Coherency between Cache and External Memory ................................................ 125 4.3.9 Prefetch Operation ................................................................................................ 125 4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only) ................................... 125 Instruction Cache (IC)........................................................................................................ 128 4.4.1 Configuration ........................................................................................................ 128 4.4.2 Read Operation ..................................................................................................... 130 4.4.3 IC Index Mode ...................................................................................................... 131 Memory-Mapped Cache Configuration (SH7750, SH7750S) ........................................... 131 4.5.1 IC Address Array .................................................................................................. 131 4.5.2 IC Data Array........................................................................................................ 132 4.5.3 OC Address Array ................................................................................................ 133 4.5.4 OC Data Array ...................................................................................................... 135 Memory-Mapped Cache Configuration (SH7750R).......................................................... 136 4.6.1 IC Address Array .................................................................................................. 137 4.6.2 IC Data Array........................................................................................................ 138 4.6.3 OC Address Array ................................................................................................ 139 4.6.4 OC Data Array ...................................................................................................... 141 4.6.5 Summary of the Memory-Mapping of the OC...................................................... 142 Store Queues ...................................................................................................................... 142 4.7.1 SQ Configuration.................................................................................................. 142 4.7.2 SQ Writes.............................................................................................................. 143 4.7.3 Transfer to External Memory................................................................................ 143 4.7.4 SQ Protection........................................................................................................ 145 4.7.5 Reading the SQs (SH7750R Only) ....................................................................... 145 4.7.6 SQ Usage Notes .................................................................................................... 146 Section 5 Exceptions..........................................................................................149 5.1 5.2 5.3 5.4 5.5 Overview............................................................................................................................ 149 5.1.1 Features................................................................................................................. 149 5.1.2 Register Configuration.......................................................................................... 149 Register Descriptions ......................................................................................................... 150 Exception Handling Functions........................................................................................... 151 5.3.1 Exception Handling Flow ..................................................................................... 151 5.3.2 Exception Handling Vector Addresses ................................................................. 151 Exception Types and Priorities .......................................................................................... 152 Exception Flow .................................................................................................................. 155 5.5.1 Exception Flow ..................................................................................................... 155 5.5.2 Exception Source Acceptance............................................................................... 156 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xv of lii 5.6 5.7 5.8 5.5.3 Exception Requests and BL Bit ............................................................................ 158 5.5.4 Return from Exception Handling.......................................................................... 158 Description of Exceptions.................................................................................................. 158 5.6.1 Resets.................................................................................................................... 159 5.6.2 General Exceptions............................................................................................... 164 5.6.3 Interrupts............................................................................................................... 178 5.6.4 Priority Order with Multiple Exceptions .............................................................. 181 Usage Notes ....................................................................................................................... 182 Restrictions ........................................................................................................................ 183 Section 6 Floating-Point Unit (FPU)................................................................. 185 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Overview............................................................................................................................ 185 Data Formats...................................................................................................................... 185 6.2.1 Floating-Point Format........................................................................................... 185 6.2.2 Non-Numbers (NaN) ............................................................................................ 187 6.2.3 Denormalized Numbers ........................................................................................ 188 Registers ............................................................................................................................ 189 6.3.1 Floating-Point Registers ....................................................................................... 189 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 191 6.3.3 Floating-Point Communication Register (FPUL) ................................................. 192 Rounding............................................................................................................................ 193 Floating-Point Exceptions.................................................................................................. 193 Graphics Support Functions............................................................................................... 195 6.6.1 Geometric Operation Instructions......................................................................... 195 6.6.2 Pair Single-Precision Data Transfer...................................................................... 196 Usage Notes ....................................................................................................................... 197 6.7.1 Rounding Mode and Underflow Flag ................................................................... 197 6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ...................................... 198 6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction ....................... 199 6.7.4 Notes on Double-Precision FADD and FSUB Instructions .................................. 199 6.7.5 Notes on FPU Double-Precision Operation Instructions (SH7750 Only)............. 200 Section 7 Instruction Set.................................................................................... 209 7.1 7.2 7.3 7.4 Execution Environment ..................................................................................................... 209 Addressing Modes ............................................................................................................. 211 Instruction Set .................................................................................................................... 215 Usage Notes ....................................................................................................................... 227 7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD) .............................................................................................................. 227 Page xvi of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 8 Pipelining ...........................................................................................231 8.1 8.2 8.3 8.4 Pipelines............................................................................................................................. 231 Parallel-Executability......................................................................................................... 238 Execution Cycles and Pipeline Stalling ............................................................................. 242 Usage Notes ....................................................................................................................... 258 Section 9 Power-Down Modes ..........................................................................259 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Overview............................................................................................................................ 259 9.1.1 Types of Power-Down Modes .............................................................................. 259 9.1.2 Register Configuration.......................................................................................... 261 9.1.3 Pin Configuration.................................................................................................. 261 Register Descriptions ......................................................................................................... 262 9.2.1 Standby Control Register (STBCR)...................................................................... 262 9.2.2 Peripheral Module Pin High Impedance Control.................................................. 264 9.2.3 Peripheral Module Pin Pull-Up Control................................................................ 265 9.2.4 Standby Control Register 2 (STBCR2)................................................................. 265 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) ...................................... 267 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) ..................... 268 Sleep Mode ........................................................................................................................ 268 9.3.1 Transition to Sleep Mode...................................................................................... 268 9.3.2 Exit from Sleep Mode........................................................................................... 269 Deep Sleep Mode............................................................................................................... 269 9.4.1 Transition to Deep Sleep Mode ............................................................................ 269 9.4.2 Exit from Deep Sleep Mode ................................................................................. 269 Standby Mode .................................................................................................................... 270 9.5.1 Transition to Standby Mode.................................................................................. 270 9.5.2 Exit from Standby Mode....................................................................................... 271 9.5.3 Clock Pause Function ........................................................................................... 271 Module Standby Function.................................................................................................. 272 9.6.1 Transition to Module Standby Function ............................................................... 272 9.6.2 Exit from Module Standby Function .................................................................... 273 Hardware Standby Mode (SH7750S, SH7750R Only) ...................................................... 274 9.7.1 Transition to Hardware Standby Mode ................................................................. 274 9.7.2 Exit from Hardware Standby Mode ...................................................................... 274 9.7.3 Usage Notes .......................................................................................................... 275 STATUS Pin Change Timing ............................................................................................ 275 9.8.1 In Reset ................................................................................................................. 276 9.8.2 In Exit from Standby Mode .................................................................................. 277 9.8.3 In Exit from Sleep Mode....................................................................................... 279 9.8.4 In Exit from Deep Sleep Mode ............................................................................. 281 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xvii of lii 9.9 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) ............................ 283 Usage Notes ....................................................................................................................... 286 9.9.1 Note on Current Consumption .............................................................................. 286 Section 10 Clock Oscillation Circuits ............................................................... 287 10.1 Overview............................................................................................................................ 287 10.1.1 Features................................................................................................................. 287 10.2 Overview of CPG............................................................................................................... 289 10.2.1 Block Diagram of CPG......................................................................................... 289 10.2.2 CPG Pin Configuration......................................................................................... 292 10.2.3 CPG Register Configuration................................................................................. 292 10.3 Clock Operating Modes ..................................................................................................... 293 10.4 CPG Register Description.................................................................................................. 295 10.4.1 Frequency Control Register (FRQCR) ................................................................. 295 10.5 Changing the Frequency .................................................................................................... 298 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ............ 298 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............. 298 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)....................... 299 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ...................... 299 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ................................ 299 10.6 Output Clock Control......................................................................................................... 299 10.7 Overview of Watchdog Timer ........................................................................................... 300 10.7.1 Block Diagram...................................................................................................... 300 10.7.2 Register Configuration.......................................................................................... 301 10.8 WDT Register Descriptions............................................................................................... 301 10.8.1 Watchdog Timer Counter (WTCNT).................................................................... 301 10.8.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 302 10.8.3 Notes on Register Access ..................................................................................... 305 10.9 Using the WDT.................................................................................................................. 305 10.9.1 Standby Clearing Procedure ................................................................................. 305 10.9.2 Frequency Changing Procedure............................................................................ 306 10.9.3 Using Watchdog Timer Mode .............................................................................. 306 10.9.4 Using Interval Timer Mode .................................................................................. 307 10.10 Notes on Board Design ...................................................................................................... 307 10.11 Usage Notes ....................................................................................................................... 309 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S)... 309 Section 11 Realtime Clock (RTC)..................................................................... 311 11.1 Overview............................................................................................................................ 311 11.1.1 Features................................................................................................................. 311 Page xviii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 11.2 11.3 11.4 11.5 11.1.2 Block Diagram...................................................................................................... 312 11.1.3 Pin Configuration.................................................................................................. 313 11.1.4 Register Configuration.......................................................................................... 313 Register Descriptions ......................................................................................................... 315 11.2.1 64 Hz Counter (R64CNT)..................................................................................... 315 11.2.2 Second Counter (RSECCNT) ............................................................................... 316 11.2.3 Minute Counter (RMINCNT) ............................................................................... 316 11.2.4 Hour Counter (RHRCNT)..................................................................................... 317 11.2.5 Day-of-Week Counter (RWKCNT)...................................................................... 317 11.2.6 Day Counter (RDAYCNT) ................................................................................... 318 11.2.7 Month Counter (RMONCNT) .............................................................................. 318 11.2.8 Year Counter (RYRCNT) ..................................................................................... 319 11.2.9 Second Alarm Register (RSECAR) ...................................................................... 320 11.2.10 Minute Alarm Register (RMINAR)...................................................................... 320 11.2.11 Hour Alarm Register (RHRAR) ........................................................................... 321 11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................. 321 11.2.13 Day Alarm Register (RDAYAR).......................................................................... 322 11.2.14 Month Alarm Register (RMONAR) ..................................................................... 323 11.2.15 RTC Control Register 1 (RCR1)........................................................................... 323 11.2.16 RTC Control Register 2 (RCR2)........................................................................... 325 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only) ................................................................................................... 327 Operation ........................................................................................................................... 329 11.3.1 Time Setting Procedures ....................................................................................... 329 11.3.2 Time Reading Procedures ..................................................................................... 330 11.3.3 Alarm Function ..................................................................................................... 332 Interrupts............................................................................................................................ 333 Usage Notes ....................................................................................................................... 333 11.5.1 Register Initialization............................................................................................ 333 11.5.2 Carry Flag and Interrupt Flag in Standby Mode ................................................... 333 11.5.3 Crystal Oscillator Circuit ...................................................................................... 333 11.5.4 RTC Register Settings (SH7750 only).................................................................. 334 Section 12 Timer Unit (TMU) ...........................................................................337 12.1 Overview............................................................................................................................ 337 12.1.1 Features................................................................................................................. 337 12.1.2 Block Diagram...................................................................................................... 338 12.1.3 Pin Configuration.................................................................................................. 338 12.1.4 Register Configuration.......................................................................................... 339 12.2 Register Descriptions ......................................................................................................... 341 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xix of lii 12.2.1 Timer Output Control Register (TOCR)............................................................... 341 12.2.2 Timer Start Register (TSTR) ................................................................................ 342 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) ............................................... 343 12.2.4 Timer Constant Registers (TCOR) ....................................................................... 344 12.2.5 Timer Counters (TCNT) ....................................................................................... 344 12.2.6 Timer Control Registers (TCR) ............................................................................ 345 12.2.7 Input Capture Register 2 (TCPR2) ....................................................................... 350 12.3 Operation ........................................................................................................................... 350 12.3.1 Counter Operation ................................................................................................ 350 12.3.2 Input Capture Function ......................................................................................... 353 12.4 Interrupts............................................................................................................................ 355 12.5 Usage Notes ....................................................................................................................... 355 12.5.1 Register Writes ..................................................................................................... 355 12.5.2 Underflow Flag Writes (SH7750 only)................................................................. 356 12.5.3 TCNT Register Reads........................................................................................... 356 12.5.4 Resetting the RTC Frequency Divider.................................................................. 356 12.5.5 External Clock Frequency .................................................................................... 356 Section 13 Bus State Controller (BSC) ............................................................. 357 13.1 Overview............................................................................................................................ 357 13.1.1 Features................................................................................................................. 357 13.1.2 Block Diagram...................................................................................................... 359 13.1.3 Pin Configuration.................................................................................................. 360 13.1.4 Register Configuration.......................................................................................... 364 13.1.5 Overview of Areas................................................................................................ 365 13.1.6 PCMCIA Support ................................................................................................. 368 13.2 Register Descriptions......................................................................................................... 372 13.2.1 Bus Control Register 1 (BCR1) ............................................................................ 372 13.2.2 Bus Control Register 2 (BCR2) ............................................................................ 381 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)................................................ 383 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)................................................ 384 13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 388 13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 391 13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 399 13.2.8 Memory Control Register (MCR)......................................................................... 401 13.2.9 PCMCIA Control Register (PCR) ........................................................................ 409 13.2.10 Synchronous DRAM Mode Register (SDMR) ..................................................... 413 13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................. 415 13.2.12 Refresh Timer Counter (RTCNT)......................................................................... 418 13.2.13 Refresh Time Constant Register (RTCOR) .......................................................... 419 Page xx of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 13.2.14 Refresh Count Register (RFCR) ........................................................................... 420 13.2.15 Notes on Accessing Refresh Control Registers .................................................... 420 13.3 Operation ........................................................................................................................... 421 13.3.1 Endian/Access Size and Data Alignment.............................................................. 421 13.3.2 Areas ..................................................................................................................... 433 13.3.3 SRAM Interface.................................................................................................... 438 13.3.4 DRAM Interface ................................................................................................... 447 13.3.5 Synchronous DRAM Interface ............................................................................. 465 13.3.6 Burst ROM Interface ............................................................................................ 497 13.3.7 PCMCIA Interface................................................................................................ 500 13.3.8 MPX Interface....................................................................................................... 511 13.3.9 Byte Control SRAM Interface .............................................................................. 529 13.3.10 Waits between Access Cycles............................................................................... 534 13.3.11 Bus Arbitration ..................................................................................................... 536 13.3.12 Master Mode ......................................................................................................... 539 13.3.13 Slave Mode ........................................................................................................... 540 13.3.14 Partial-Sharing Master Mode................................................................................ 541 13.3.15 Cooperation between Master and Slave................................................................ 542 13.3.16 Notes on Usage ..................................................................................................... 543 Section 14 Direct Memory Access Controller (DMAC) ...................................545 14.1 Overview............................................................................................................................ 545 14.1.1 Features................................................................................................................. 545 14.1.2 Block Diagram (SH7750, SH7750S) .................................................................... 547 14.1.3 Pin Configuration (SH7750, SH7750S)................................................................ 549 14.1.4 Register Configuration (SH7750, SH7750S)........................................................ 550 14.2 Register Descriptions (SH7750, SH7750S) ....................................................................... 552 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 552 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)................................... 553 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).......................... 554 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3).................................... 555 14.2.5 DMA Operation Register (DMAOR) ................................................................... 564 14.3 Operation ........................................................................................................................... 567 14.3.1 DMA Transfer Procedure ..................................................................................... 567 14.3.2 DMA Transfer Requests ....................................................................................... 569 14.3.3 Channel Priorities ................................................................................................. 573 14.3.4 Types of DMA Transfer........................................................................................ 576 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 585 14.3.6 Ending DMA Transfer .......................................................................................... 599 14.4 Examples of Use ................................................................................................................ 602 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxi of lii 14.5 14.6 14.7 14.8 14.9 14.4.1 Examples of Transfer between External Memory and an External Device with DACK........................................................................................................... 602 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 603 14.5.1 Operation .............................................................................................................. 603 14.5.2 Pins in DDT Mode................................................................................................ 605 14.5.3 Transfer Request Acceptance on Each Channel ................................................... 608 14.5.4 Notes on Use of DDT Module .............................................................................. 631 Configuration of the DMAC (SH7750R)........................................................................... 634 14.6.1 Block Diagram of the DMAC............................................................................... 634 14.6.2 Pin Configuration (SH7750R) .............................................................................. 636 14.6.3 Register Configuration (SH7750R) ...................................................................... 637 Register Descriptions (SH7750R)...................................................................................... 640 14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)........................................... 640 14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) .................................. 640 14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) ......................... 641 14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) ................................... 641 14.7.5 DMA Operation Register (DMAOR) ................................................................... 645 Operation (SH7750R) ........................................................................................................ 647 14.8.1 Channel Specification for a Normal DMA Transfer............................................. 647 14.8.2 Channel Specification for DDT-Mode DMA Transfer ......................................... 647 14.8.3 Transfer Channel Notification in DDT Mode....................................................... 648 14.8.4 Clearing Request Queues by DTR Format ........................................................... 649 14.8.5 Interrupt-Request Codes ....................................................................................... 649 Usage Notes ....................................................................................................................... 652 Section 15 Serial Communication Interface (SCI)............................................ 655 15.1 Overview............................................................................................................................ 655 15.1.1 Features................................................................................................................. 655 15.1.2 Block Diagram...................................................................................................... 657 15.1.3 Pin Configuration.................................................................................................. 658 15.1.4 Register Configuration.......................................................................................... 658 15.2 Register Descriptions......................................................................................................... 659 15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 659 15.2.2 Receive Data Register (SCRDR1) ........................................................................ 660 15.2.3 Transmit Shift Register (SCTSR1) ....................................................................... 660 15.2.4 Transmit Data Register (SCTDR1)....................................................................... 661 15.2.5 erial Mode Register (SCSMR1)............................................................................ 661 15.2.6 Serial Control Register (SCSCR1)........................................................................ 664 15.2.7 Serial Status Register (SCSSR1) .......................................................................... 667 15.2.8 Serial Port Register (SCSPTR1) ........................................................................... 671 Page xxii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 676 15.3 Operation ........................................................................................................................... 684 15.3.1 Overview............................................................................................................... 684 15.3.2 Operation in Asynchronous Mode ........................................................................ 686 15.3.3 Multiprocessor Communication Function............................................................. 698 15.3.4 Operation in Synchronous Mode .......................................................................... 707 15.4 SCI Interrupt Sources and DMAC ..................................................................................... 717 15.5 Usage Notes ....................................................................................................................... 718 Section 16 Serial Communication Interface with FIFO (SCIF) ........................725 16.1 Overview............................................................................................................................ 725 16.1.1 Features................................................................................................................. 725 16.1.2 Block Diagram...................................................................................................... 727 16.1.3 Pin Configuration.................................................................................................. 728 16.1.4 Register Configuration.......................................................................................... 729 16.2 Register Descriptions ......................................................................................................... 729 16.2.1 Receive Shift Register (SCRSR2)......................................................................... 729 16.2.2 Receive FIFO Data Register (SCFRDR2) ............................................................ 730 16.2.3 Transmit Shift Register (SCTSR2) ....................................................................... 730 16.2.4 Transmit FIFO Data Register (SCFTDR2) ........................................................... 731 16.2.5 Serial Mode Register (SCSMR2).......................................................................... 731 16.2.6 Serial Control Register (SCSCR2)........................................................................ 734 16.2.7 Serial Status Register (SCFSR2) .......................................................................... 737 16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 744 16.2.9 FIFO Control Register (SCFCR2) ........................................................................ 745 16.2.10 FIFO Data Count Register (SCFDR2) .................................................................. 749 16.2.11 Serial Port Register (SCSPTR2) ........................................................................... 750 16.2.12 Line Status Register (SCLSR2) ............................................................................ 756 16.3 Operation ........................................................................................................................... 757 16.3.1 Overview............................................................................................................... 757 16.3.2 Serial Operation .................................................................................................... 758 16.4 SCIF Interrupt Sources and the DMAC ............................................................................. 769 16.5 Usage Notes ....................................................................................................................... 770 Section 17 Smart Card Interface ........................................................................775 17.1 Overview............................................................................................................................ 775 17.1.1 Features................................................................................................................. 775 17.1.2 Block Diagram...................................................................................................... 776 17.1.3 Pin Configuration.................................................................................................. 777 17.1.4 Register Configuration.......................................................................................... 777 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxiii of lii 17.2 Register Descriptions......................................................................................................... 778 17.2.1 Smart Card Mode Register (SCSCMR1) .............................................................. 778 17.2.2 Serial Mode Register (SCSMR1).......................................................................... 779 17.2.3 Serial Control Register (SCSCR1)........................................................................ 780 17.2.4 Serial Status Register (SCSSR1) .......................................................................... 781 17.3 Operation ........................................................................................................................... 782 17.3.1 Overview .............................................................................................................. 782 17.3.2 Pin Connections .................................................................................................... 783 17.3.3 Data Format .......................................................................................................... 784 17.3.4 Register Settings ................................................................................................... 785 17.3.5 Clock..................................................................................................................... 787 17.3.6 Data Transmit/Receive Operations ....................................................................... 790 17.4 Usage Notes ....................................................................................................................... 797 Section 18 I/O Ports........................................................................................... 803 18.1 Overview............................................................................................................................ 803 18.1.1 Features................................................................................................................. 803 18.1.2 Block Diagrams .................................................................................................... 804 18.1.3 Pin Configuration.................................................................................................. 811 18.1.4 Register Configuration.......................................................................................... 813 18.2 Register Descriptions......................................................................................................... 814 18.2.1 Port Control Register A (PCTRA)........................................................................ 814 18.2.2 Port Data Register A (PDTRA) ............................................................................ 815 18.2.3 Port Control Register B (PCTRB) ........................................................................ 816 18.2.4 Port Data Register B (PDTRB)............................................................................. 817 18.2.5 GPIO Interrupt Control Register (GPIOIC).......................................................... 818 18.2.6 Serial Port Register (SCSPTR1) ........................................................................... 819 18.2.7 Serial Port Register (SCSPTR2) ........................................................................... 821 Section 19 Interrupt Controller (INTC)............................................................. 825 19.1 Overview............................................................................................................................ 825 19.1.1 Features................................................................................................................. 825 19.1.2 Block Diagram...................................................................................................... 825 19.1.3 Pin Configuration.................................................................................................. 827 19.1.4 Register Configuration.......................................................................................... 827 19.2 Interrupt Sources................................................................................................................ 828 19.2.1 NMI Interrupt........................................................................................................ 828 19.2.2 IRL Interrupts ....................................................................................................... 829 19.2.3 On-Chip Peripheral Module Interrupts ................................................................. 831 19.2.4 Interrupt Exception Handling and Priority............................................................ 832 Page xxiv of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 19.3 Register Descriptions ......................................................................................................... 835 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ................................................ 835 19.3.2 Interrupt Control Register (ICR)........................................................................... 837 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)......... 839 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only)............................... 840 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ................................ 841 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) ............... 842 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) ................................................................................................... 842 19.4 INTC Operation ................................................................................................................. 843 19.4.1 Interrupt Operation Sequence ............................................................................... 843 19.4.2 Multiple Interrupts ................................................................................................ 845 19.4.3 Interrupt Masking with MAI Bit........................................................................... 845 19.5 Interrupt Response Time.................................................................................................... 846 19.6 Usage Notes ....................................................................................................................... 847 19.6.1 NMI Interrupts (SH7750 and SH7750S Only)...................................................... 847 Section 20 User Break Controller (UBC) ..........................................................851 20.1 Overview............................................................................................................................ 851 20.1.1 Features................................................................................................................. 851 20.1.2 Block Diagram...................................................................................................... 852 20.2 Register Descriptions ......................................................................................................... 854 20.2.1 Access to UBC Control Registers......................................................................... 854 20.2.2 Break Address Register A (BARA) ...................................................................... 855 20.2.3 Break ASID Register A (BASRA)........................................................................ 856 20.2.4 Break Address Mask Register A (BAMRA)......................................................... 856 20.2.5 Break Bus Cycle Register A (BBRA)................................................................... 857 20.2.6 Break Address Register B (BARB) ...................................................................... 859 20.2.7 Break ASID Register B (BASRB) ........................................................................ 859 20.2.8 Break Address Mask Register B (BAMRB) ......................................................... 859 20.2.9 Break Data Register B (BDRB) ............................................................................ 859 20.2.10 Break Data Mask Register B (BDMRB)............................................................... 860 20.2.11 Break Bus Cycle Register B (BBRB) ................................................................... 861 20.2.12 Break Control Register (BRCR) ........................................................................... 861 20.3 Operation ........................................................................................................................... 864 20.3.1 Explanation of Terms Relating to Accesses.......................................................... 864 20.3.2 Explanation of Terms Relating to Instruction Intervals ........................................ 864 20.3.3 User Break Operation Sequence ........................................................................... 865 20.3.4 Instruction Access Cycle Break ............................................................................ 866 20.3.5 Operand Access Cycle Break................................................................................ 867 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxv of lii 20.3.6 Condition Match Flag Setting............................................................................... 868 20.3.7 Program Counter (PC) Value Saved ..................................................................... 868 20.3.8 Contiguous A and B Settings for Sequential Conditions ...................................... 869 20.3.9 Usage Notes .......................................................................................................... 870 20.4 User Break Debug Support Function ................................................................................. 872 20.5 Examples of Use ................................................................................................................ 874 20.6 User Break Controller Stop Function................................................................................. 876 20.6.1 Transition to User Break Controller Stopped State............................................... 876 20.6.2 Cancelling the User Break Controller Stopped State............................................ 876 20.6.3 Examples of Stopping and Restarting the User Break Controller......................... 877 Section 21 High-performance User Debug Interface (H-UDI) ......................... 879 21.1 Overview............................................................................................................................ 879 21.1.1 Features................................................................................................................. 879 21.1.2 Block Diagram...................................................................................................... 879 21.1.3 Pin Configuration.................................................................................................. 881 21.1.4 Register Configuration.......................................................................................... 882 21.2 Register Descriptions......................................................................................................... 883 21.2.1 Instruction Register (SDIR) .................................................................................. 883 21.2.2 Data Register (SDDR) .......................................................................................... 885 21.2.3 Bypass Register (SDBPR) .................................................................................... 886 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) .......................................... 886 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) ........................................... 887 21.3 Operation ........................................................................................................................... 891 21.3.1 TAP Control ......................................................................................................... 891 21.3.2 H-UDI Reset ......................................................................................................... 892 21.3.3 H-UDI Interrupt .................................................................................................... 892 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)................................................................................................... 893 21.4 Usage Notes ....................................................................................................................... 893 Section 22 Electrical Characteristics ................................................................. 895 22.1 Absolute Maximum Ratings .............................................................................................. 895 22.2 DC Characteristics ............................................................................................................. 896 22.3 AC Characteristics ............................................................................................................. 920 22.3.1 Clock and Control Signal Timing ......................................................................... 922 22.3.2 Control Signal Timing .......................................................................................... 946 22.3.3 Bus Timing ........................................................................................................... 950 22.3.4 Peripheral Module Signal Timing....................................................................... 1003 22.3.5 AC Characteristic Test Conditions ..................................................................... 1015 Page xxvi of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 22.3.6 Delay Time Variation Due to Load Capacitance ................................................ 1016 Appendix A Address List ................................................................................1017 Appendix B Package Dimensions....................................................................1023 Appendix C Mode Pin Settings .......................................................................1029 Appendix D CKIO2ENB Pin Configuration ...................................................1033 Appendix E Pin Functions ...............................................................................1035 E.1 E.2 Pin States.......................................................................................................................... 1035 Handling of Unused Pins ................................................................................................. 1038 Appendix F Synchronous DRAM Address Multiplexing Tables ...................1039 Appendix G Prefetching of Instructions and its Side Effects ..........................1061 Appendix H Power-On and Power-Off Procedures.........................................1063 H.1 H.2 H.3 Power-On Stipulations ..................................................................................................... 1063 Power-Off Stipulations .................................................................................................... 1063 Common Stipulations for Power-On and Power-Off ....................................................... 1064 Appendix I Product Lineup..............................................................................1067 Appendix J Version Registers..........................................................................1069 Index .......................................................................................................1071 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxvii of lii Page xxviii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Overview Block Diagram of SH7750/SH7750S/SH7750R Group Functions ............................... 9 Pin Arrangement (256-Pin BGA) ................................................................................ 10 Pin Arrangement (208-Pin QFP) ................................................................................. 11 Pin Arrangement (264-Pin CSP) ................................................................................. 12 Pin Arrangement (292-Pin BGA) ................................................................................ 13 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Programming Model Data Formats ............................................................................................................... 53 CPU Register Configuration in Each Processor Mode................................................ 56 General Registers ........................................................................................................ 58 Floating-Point Registers .............................................................................................. 61 Data Formats In Memory ............................................................................................ 67 Processor State Transitions.......................................................................................... 68 Section 3 Memory Management Unit (MMU) Figure 3.1 Role of the MMU ........................................................................................................ 73 Figure 3.2 MMU-Related Registers.............................................................................................. 75 Figure 3.3 Physical Address Space (MMUCR.AT = 0) ............................................................... 79 Figure 3.4 P4 Area........................................................................................................................ 81 Figure 3.5 External Memory Space .............................................................................................. 82 Figure 3.6 Virtual Address Space (MMUCR.AT = 1).................................................................. 83 Figure 3.7 UTLB Configuration ................................................................................................... 86 Figure 3.8 Relationship between Page Size and Address Format................................................. 87 Figure 3.9 ITLB Configuration..................................................................................................... 90 Figure 3.10 Flowchart of Memory Access Using UTLB.............................................................. 91 Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................... 92 Figure 3.12 Operation of LDTLB Instruction............................................................................... 94 Figure 3.13 Memory-Mapped ITLB Address Array................................................................... 103 Figure 3.14 Memory-Mapped ITLB Data Array 1 ..................................................................... 104 Figure 3.15 Memory-Mapped ITLB Data Array 2 ..................................................................... 105 Figure 3.16 Memory-Mapped UTLB Address Array ................................................................. 107 Figure 3.17 Memory-Mapped UTLB Data Array 1.................................................................... 108 Figure 3.18 Memory-Mapped UTLB Data Array 2.................................................................... 109 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxix of lii Section 4 Caches Figure 4.1 Cache and Store Queue Control Registers ................................................................ 114 Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S)............................................. 117 Figure 4.3 Configuration of Operand Cache (SH7750R) ........................................................... 118 Figure 4.4 Configuration of Write-Back Buffer ......................................................................... 122 Figure 4.5 Configuration of Write-Through Buffer.................................................................... 122 Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) ......................................... 128 Figure 4.7 Configuration of Instruction Cache (SH7750R)........................................................ 129 Figure 4.8 Memory-Mapped IC Address Array ......................................................................... 132 Figure 4.9 Memory-Mapped IC Data Array ............................................................................... 133 Figure 4.10 Memory-Mapped OC Address Array ...................................................................... 134 Figure 4.11 Memory-Mapped OC Data Array ........................................................................... 135 Figure 4.12 Memory-Mapped IC Address Array ....................................................................... 138 Figure 4.13 Memory-Mapped IC Data Array ............................................................................. 139 Figure 4.14 Memory-Mapped OC Address Array ...................................................................... 140 Figure 4.15 Memory-Mapped OC Data Array ........................................................................... 141 Figure 4.16 Store Queue Configuration...................................................................................... 143 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Exceptions Register Bit Configurations....................................................................................... 150 Instruction Execution and Exception Handling......................................................... 155 Example of General Exception Acceptance Order.................................................... 157 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Floating-Point Unit (FPU) Format of Single-Precision Floating-Point Number.................................................. 185 Format of Double-Precision Floating-Point Number ................................................ 186 Single-Precision NaN Bit Pattern.............................................................................. 188 Floating-Point Registers ............................................................................................ 190 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Pipelining Basic Pipelines .......................................................................................................... 232 Instruction Execution Patterns................................................................................... 233 Examples of Pipelined Execution.............................................................................. 245 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Power-Down Modes STATUS Output in Power-On Reset ........................................................................ 276 STATUS Output in Manual Reset............................................................................. 276 STATUS Output in Standby → Interrupt Sequence.................................................. 277 STATUS Output in Standby → Power-On Reset Sequence ..................................... 277 Page xxx of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figure 9.5 STATUS Output in Standby → Manual Reset Sequence.......................................... 278 Figure 9.6 STATUS Output in Sleep → Interrupt Sequence...................................................... 279 Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence.......................................... 279 Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence.............................................. 280 Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence ............................................ 281 Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence .............................. 281 Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence .................................. 282 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) ........... 283 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) .............. 284 Figure 9.14 Timing When Power Other than VDD-RTC Is Off................................................. 285 Figure 9.15 Timing When VDD-RTC Power Is Off → On........................................................ 285 Section 10 Clock Oscillation Circuits Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) .................................................... 289 Figure 10.1 (2) Block Diagram of CPG (SH7750R) .................................................................. 290 Figure 10.2 Block Diagram of WDT .......................................................................................... 300 Figure 10.3 Writing to WTCNT and WTCSR............................................................................ 305 Figure 10.4 Points for Attention when Using Crystal Resonator................................................ 307 Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ........................................ 308 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 312 Examples of Time Setting Procedures..................................................................... 329 Examples of Time Reading Procedures................................................................... 331 Example of Use of Alarm Function......................................................................... 332 Example of Crystal Oscillator Circuit Connection .................................................. 334 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Timer Unit (TMU) Block Diagram of TMU .......................................................................................... 338 Example of Count Operation Setting Procedure ..................................................... 351 TCNT Auto-Reload Operation ................................................................................ 352 Count Timing when Operating on Internal Clock ................................................... 352 Count Timing when Operating on External Clock .................................................. 353 Count Timing when Operating on On-Chip RTC Output Clock............................. 353 Operation Timing when Using Input Capture Function .......................................... 354 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Bus State Controller (BSC) Block Diagram of BSC............................................................................................ 359 Correspondence between Virtual Address Space and External Memory Space...... 365 External Memory Space Allocation ........................................................................ 367 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxxi of lii Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2) ............................................................ 385 Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR.................................................. 421 Figure 13.6 Basic Timing of SRAM Interface............................................................................ 439 Figure 13.7 Example of 64-Bit Data Width SRAM Connection ................................................ 440 Figure 13.8 Example of 32-Bit Data Width SRAM Connection ................................................ 441 Figure 13.9 Example of 16-Bit Data Width SRAM Connection ................................................ 442 Figure 13.10 Example of 8-Bit Data Width SRAM Connection ................................................ 443 Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) ........................................... 444 Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) ......... 445 Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) ..... 446 Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) .............................. 448 Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) .............................. 449 Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) ................... 450 Figure 13.17 Basic DRAM Access Timing ................................................................................ 452 Figure 13.18 DRAM Wait State Timing .................................................................................... 453 Figure 13.19 DRAM Burst Access Timing ................................................................................ 454 Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)........................... 455 Figure 13.21 Burst Access Timing in DRAM EDO Mode......................................................... 456 Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0)............................................................ 457 Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0)............................................................ 458 Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0)................................................................... 459 Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0)................................................................... 460 Figure 13.23 CAS-Before-RAS Refresh Operation.................................................................... 461 Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)............. 462 Figure 13.25 DRAM Self-Refresh Cycle Timing....................................................................... 464 Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3).......... 466 Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3).......... 467 Figure 13.28 Basic Timing for Synchronous DRAM Burst Read .............................................. 469 Figure 13.29 Basic Timing for Synchronous DRAM Single Read............................................. 471 Figure 13.30 Basic Timing for Synchronous DRAM Burst Write ............................................. 473 Figure 13.31 Basic Timing for Synchronous DRAM Single Write............................................ 474 Figure 13.32 Burst Read Timing ................................................................................................ 476 Figure 13.33 Burst Read Timing (RAS Down, Same Row Address)......................................... 477 Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)................................ 478 Figure 13.35 Burst Write Timing ............................................................................................... 479 Page xxxii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figure 13.36 Burst Write Timing (Same Row Address)............................................................. 480 Figure 13.37 Burst Write Timing (Different Row Addresses) ................................................... 481 Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle .................................................................................. 483 Figure 13.39 Auto-Refresh Operation ........................................................................................ 485 Figure 13.40 Synchronous DRAM Auto-Refresh Timing.......................................................... 485 Figure 13.41 Synchronous DRAM Self-Refresh Timing ........................................................... 487 Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 490 Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) ..................... 491 Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4) ................. 492 Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM........................................ 494 Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width (256 Mbits) ............................................................................................................ 495 Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width (TRAS[2:0] = 001, TRC[2:0] = 001)..................................................................... 496 Figure 13.47 Burst ROM Basic Access Timing ......................................................................... 498 Figure 13.48 Burst ROM Wait Access Timing........................................................................... 499 Figure 13.49 Burst ROM Wait Access Timing........................................................................... 500 Figure 13.50 Example of PCMCIA Interface ............................................................................. 504 Figure 13.51 Basic Timing for PCMCIA Memory Card Interface ............................................. 505 Figure 13.52 Wait Timing for PCMCIA Memory Card Interface .............................................. 506 Figure 13.53 PCMCIA Space Allocation ................................................................................... 507 Figure 13.54 Basic Timing for PCMCIA I/O Card Interface ..................................................... 508 Figure 13.55 Wait Timing for PCMCIA I/O Card Interface ...................................................... 509 Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 510 Figure 13.57 Example of 64-Bit Data Width MPX Connection ................................................. 512 Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) ............................................................................................... 513 Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) ............................................................................................... 514 Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) ............................................................................................... 515 Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) ............................................................................................... 516 Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .............................................. 517 Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .............................................. 518 Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .............................................. 519 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxxiii of lii Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .............................................. 520 Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................................. 521 Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ... 522 Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................................. 523 Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ... 524 Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) ............................................... 525 Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .............................................. 526 Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .............................................. 527 Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .............................................. 528 Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM............................................ 530 Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) ............................................... 531 Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ...................... 532 Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait).............................................................. 533 Figure 13.78 Waits between Access Cycles ............................................................................... 535 Figure 13.79 Arbitration Sequence............................................................................................. 538 Section 14 Direct Memory Access Controller (DMAC) Figure 14.1 Block Diagram of DMAC ....................................................................................... 548 Figure 14.2 DMAC Transfer Flowchart ..................................................................................... 568 Figure 14.3 Round Robin Mode ................................................................................................. 574 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode................................ 575 Figure 14.5 Data Flow in Single Address Mode......................................................................... 577 Figure 14.6 DMA Transfer Timing in Single Address Mode..................................................... 578 Figure 14.7 Operation in Dual Address Mode............................................................................ 579 Figure 14.8 Example of Transfer Timing in Dual Address Mode .............................................. 580 Figure 14.9 Example of DMA Transfer in Cycle Steal Mode .................................................... 581 Figure 14.10 Example of DMA Transfer in Burst Mode............................................................ 581 Figure 14.11 Bus Handling with Two DMAC Channels Operating........................................... 585 Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle)................................................................ 588 Page xxxiv of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................................................. 589 Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle)................................................................ 590 Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................................................. 591 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus .......................................................................................................... 592 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection)................................................................................................... 593 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection)................................................................................................... 594 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection).................................................................................................... 595 Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)................................................................................................... 596 Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection).................................................................................................... 597 Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write) .................................................... 598 Figure 14.23 On-Demand Transfer Mode Block Diagram ......................................................... 603 Figure 14.24 System Configuration in On-Demand Data Transfer Mode .................................. 605 Figure 14.25 Data Transfer Request Format............................................................................... 606 Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001).................................................. 609 Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001)............................................... 610 Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ........... 611 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 612 Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 613 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer..................................................... 614 Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer..................................................... 615 Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) .... 616 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxxv of lii Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer)................................................................. 617 Figure 14.35 Read from Synchronous DRAM Precharge Bank ................................................. 618 Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ..................... 618 Figure 14.37 Read from Synchronous DRAM (Row Hit) .......................................................... 619 Figure 14.38 Write to Synchronous DRAM Precharge Bank..................................................... 619 Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)......................... 620 Figure 14.40 Write to Synchronous DRAM (Row Hit).............................................................. 620 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 621 Figure 14.42 DDT Mode Setting ................................................................................................ 622 Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device → External Bus Data Transfer ................................................................................... 622 Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus → External Device Data Transfer .............................................................................. 623 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer ............... 624 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer ............... 625 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus ............................................................. 626 Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus......................................................................................... 627 Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 ............................................ 628 Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 ............................................ 629 Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2....... 630 Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2....... 631 Figure 14.53 Block Diagram of the DMAC ............................................................................... 635 Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)............................................ 646 Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 650 Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 ..................................... 651 Page xxxvi of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Serial Communication Interface (SCI) Block Diagram of SCI............................................................................................. 657 MD0/SCK Pin ......................................................................................................... 674 MD7/TxD Pin.......................................................................................................... 675 RxD Pin ................................................................................................................... 675 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 687 Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode)............................................................................................. 689 Figure 15.7 Sample SCI Initialization Flowchart ....................................................................... 690 Figure 15.8 Sample Serial Transmission Flowchart ................................................................... 691 Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 693 Figure 15.10 Sample Serial Reception Flowchart (1)................................................................. 694 Figure 15.10 Sample Serial Reception Flowchart (2)................................................................. 695 Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ......................................................................................................... 697 Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........................................... 699 Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ........................................ 700 Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ......................................................................... 702 Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 704 Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 705 Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ......................................................................... 706 Figure 15.17 Data Format in Synchronous Communication ...................................................... 707 Figure 15.18 Sample SCI Initialization Flowchart ..................................................................... 709 Figure 15.19 Sample Serial Transmission Flowchart ................................................................. 710 Figure 15.20 Example of SCI Transmit Operation ..................................................................... 712 Figure 15.21 Sample Serial Reception Flowchart (1)................................................................. 713 Figure 15.21 Sample Serial Reception Flowchart (2)................................................................. 714 Figure 15.22 Example of SCI Receive Operation....................................................................... 715 Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception ........................... 716 Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode ...................................... 720 Figure 15.25 Example of Synchronous Transmission by DMAC .............................................. 721 Figure 15.26 Example Countermeasure on SH7750................................................................... 723 Figure 15.27 Clock Input Timing of SCK Pin ............................................................................ 723 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxxvii of lii Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF........................................................................................... 727 MD8/RTS2 Pin........................................................................................................ 753 CTS2 Pin ................................................................................................................. 754 MD1/TxD2 Pin........................................................................................................ 755 MD2/RxD2 Pin ....................................................................................................... 755 Sample SCIF Initialization Flowchart ..................................................................... 761 Sample Serial Transmission Flowchart ................................................................... 762 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................... 764 Figure 16.9 Example of Operation Using Modem Control (CTS2)............................................ 764 Figure 16.10 Sample Serial Reception Flowchart (1)................................................................. 765 Figure 16.10 Sample Serial Reception Flowchart (2)................................................................. 766 Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 768 Figure 16.12 Example of Operation Using Modem Control (RTS2).......................................... 769 Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode ...................................... 772 Figure 16.14 Overrun Error Flag ................................................................................................ 774 Section 17 Smart Card Interface Figure 17.1 Block Diagram of Smart Card Interface.................................................................. 776 Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections................................ 783 Figure 17.3 Smart Card Interface Data Format .......................................................................... 784 Figure 17.4 TEND Generation Timing....................................................................................... 786 Figure 17.5 Sample Start Character Waveforms ........................................................................ 787 Figure 17.6 Difference in Clock Output According to GM Bit Setting...................................... 790 Figure 17.7 Sample Initialization Flowchart .............................................................................. 791 Figure 17.8 Sample Transmission Processing Flowchart ........................................................... 793 Figure 17.9 Sample Reception Processing Flowchart ................................................................ 795 Figure 17.10 Receive Data Sampling Timing in Smart Card Mode ........................................... 797 Figure 17.11 Retransfer Operation in SCI Receive Mode .......................................................... 799 Figure 17.12 Retransfer Operation in SCI Transmit Mode ........................................................ 799 Figure 17.13 Procedure for Stopping and Restarting the Clock ................................................. 800 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 I/O Ports 16-Bit Port............................................................................................................... 804 4-Bit Port................................................................................................................. 805 MD0/SCK Pin ......................................................................................................... 806 MD7/TxD Pin.......................................................................................................... 807 RxD Pin................................................................................................................... 807 Page xxxviii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 MD1/TxD2 Pin........................................................................................................ 808 MD2/RxD2 Pin........................................................................................................ 808 CTS2 Pin ................................................................................................................. 809 MD8/RTS2 Pin........................................................................................................ 810 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Interrupt Controller (INTC) Block Diagram of INTC.......................................................................................... 826 Example of IRL Interrupt Connection..................................................................... 829 Interrupt Operation Flowchart................................................................................. 844 Section 20 User Break Controller (UBC) Figure 20.1 Block Diagram of User Break Controller................................................................ 852 Figure 20.2 User Break Debug Support Function Flowchart ..................................................... 873 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 High-performance User Debug Interface (H-UDI) Block Diagram of H-UDI Circuit............................................................................ 880 TAP Control State Transition Diagram ................................................................... 891 H-UDI Reset............................................................................................................ 892 Section 22 Electrical Characteristics Figure 22.1 EXTAL Clock Input Timing ................................................................................... 940 Figure 22.2 (1) CKIO Clock Output Timing .............................................................................. 940 Figure 22.2 (2) CKIO Clock Output Timing .............................................................................. 940 Figure 22.3 Power-On Oscillation Settling Time ....................................................................... 941 Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET) .............................. 941 Figure 22.5 Power-On Oscillation Settling Time ....................................................................... 942 Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET) .............................. 942 Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI)................................... 943 Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0)..................... 943 Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt.............. 944 Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt............................... 944 Figure 22.11 Manual Reset Input Timing................................................................................... 945 Figure 22.12 Mode Input Timing ............................................................................................... 945 Figure 22.13 Control Signal Timing........................................................................................... 948 Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode ..................................................... 948 Figure 22.14 (2) Pin Drive Timing for Software Standby Mode ................................................ 949 Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)..................................................... 956 Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)...................................... 957 Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait).... 958 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xxxix of lii Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/ Hold Time Insertion, AnS = 1, AnH = 1) .............................................................. 959 Figure 22.19 Burst ROM Bus Cycle (No Wait) ......................................................................... 960 Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait).................................................................... 961 Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ................................................................................................ 962 Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ........................ 963 Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ........................................... 964 Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)....................................................................... 965 Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) .......................................... 966 Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3).............. 967 Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst ((RASD = 1, CAS Latency = 3) ............................................................................ 968 Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................................... 969 Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................................... 970 Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010)......................................... 971 Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).............. 972 Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010)................................................................... 973 Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (RASD = 1, TPC[2:0] = 001) ................................................................................ 974 Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001) ................................................................................ 975 Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)................................................................................................... 976 Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)............................................................................................................. 977 Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET)................................................................................................................ 978 Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010.......................................... 979 Page xl of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) .................................................................................................... 980 Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) .................................................................................................... 981 Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) ........................ 982 Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)............................................. 983 Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) ................................................... 984 Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) ................................................... 985 Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) .................................................................................................... 986 Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) .................................................................................................... 987 Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)............................................. 988 Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ............................................ 989 Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ............................................ 990 Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001)..................................................................... 991 Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001)..................................................................... 992 Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) ................................. 993 Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait ................................................................ 994 Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait ................................................................ 995 Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing).............................................................................. 996 Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) .......................................... 997 Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) .......................................... 998 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xli of lii Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait) .................................... 999 Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) .............................. 1000 Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait)............................................................ 1001 Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1)..... 1002 Figure 22.61 TCLK Input Timing ............................................................................................ 1011 Figure 22.62 RTC Oscillation Settling Time at Power-On....................................................... 1011 Figure 22.63 SCK Input Clock Timing .................................................................................... 1011 Figure 22.64 SCI I/O Synchronous Mode Clock Timing ......................................................... 1012 Figure 22.65 I/O Port Input/Output Timing.............................................................................. 1012 Figure 22.66 (a) DREQ/DRAK Timing ................................................................................... 1012 Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing .................................. 1013 Figure 22.67 TCK Input Timing............................................................................................... 1013 Figure 22.68 RESET Hold Timing........................................................................................... 1014 Figure 22.69 H-UDI Data Transfer Timing.............................................................................. 1014 Figure 22.70 Pin Break Timing ................................................................................................ 1014 Figure 22.71 NMI Input Timing............................................................................................... 1014 Figure 22.72 Output Load Circuit ............................................................................................ 1015 Figure 22.73 Load Capacitance vs. Delay Time....................................................................... 1016 Appendix B Package Dimensions Figure B.1 Package Dimensions (256-Pin BGA: Devices Other than HD6417750RBA240HV and HD6417750SBA200V) ................................................................................... 1023 Figure B.2 Package Dimensions (208-Pin QFP) ...................................................................... 1024 Figure B.3 Package Dimensions (264-Pin CSP)....................................................................... 1025 Figure B.4 Package Dimensions (292-Pin BGA) ..................................................................... 1026 Figure B.5 Package Dimensions (256-Pin BGA: HD6417750RBA240HV and HD6417750SBA200V) .......................................................................................... 1027 Appendix D CKIO2ENB Pin Configuration Figure D.1 CKIO2ENB Pin Configuration............................................................................... 1033 Appendix G Prefetching of Instructions and its Side Effects Figure G.1 Instruction Prefetch ................................................................................................ 1061 Page xlii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Appendix H Power-On and Power-Off Procedures Figure H.1 Power-On Procedure 1 ........................................................................................... 1064 Figure H.2 Power-On Procedure 2 ........................................................................................... 1065 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xliii of lii Page xliv of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Tables Section 1 Overview Table 1.1 LSI Features ................................................................................................................ 1 Table 1.2 Pin Functions............................................................................................................. 14 Table 1.3 Pin Functions............................................................................................................. 24 Table 1.4 Pin Functions............................................................................................................. 32 Table 1.5 Pin Functions............................................................................................................. 42 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................... 55 Section 3 Memory Management Unit (MMU) Table 3.1 MMU Registers......................................................................................................... 74 Section 4 Caches Table 4.1 Cache Features (SH7750, SH7750S) ...................................................................... 111 Table 4.2 Cache Features (SH7750R) ..................................................................................... 112 Table 4.3 Features of Store Queues......................................................................................... 112 Table 4.4 Cache Control Registers.......................................................................................... 113 Section 5 Exceptions Table 5.1 Exception-Related Registers ................................................................................... 149 Table 5.2 Exceptions ............................................................................................................... 152 Table 5.3 Types of Reset......................................................................................................... 161 Section 6 Floating-Point Unit (FPU) Table 6.1 Floating-Point Number Formats and Parameters .................................................... 186 Table 6.2 Floating-Point Ranges ............................................................................................. 187 Table 6.3 Incorrect Operation Result ...................................................................................... 203 Table 6.4 FDIV DRm, DRn (DRn/DRm → DRn) ................................................................. 204 Table 6.5 FADD DRm, DRn (DRn + DRm → DRn) FSUB DRm, DRn (DRn − DRm → DRn) ............................................................................................ 205 Table 6.6 FMUL DRm, DRn (DRn*DRm → DRn) .............................................................. 205 Table 6.7 TRAP Routine Processing....................................................................................... 207 Section 7 Instruction Set Table 7.1 Addressing Modes and Effective Addresses ........................................................... 211 Table 7.2 Notation Used in Instruction List ............................................................................ 215 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xlv of lii Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Fixed-Point Transfer Instructions............................................................................ 216 Arithmetic Operation Instructions........................................................................... 218 Logic Operation Instructions................................................................................... 220 Shift Instructions ..................................................................................................... 221 Branch Instructions ................................................................................................. 222 System Control Instructions .................................................................................... 223 Floating-Point Single-Precision Instructions........................................................... 225 Floating-Point Double-Precision Instructions ......................................................... 226 Floating-Point Control Instructions......................................................................... 226 Floating-Point Graphics Acceleration Instructions ................................................. 227 Section 8 Pipelining Table 8.1 Instruction Groups................................................................................................... 238 Table 8.2 Parallel-Executability.............................................................................................. 242 Table 8.3 Execution Cycles..................................................................................................... 249 Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes............................. 260 Table 9.2 Power-Down Mode Registers ................................................................................. 261 Table 9.3 Power-Down Mode Pins ......................................................................................... 261 Table 9.4 State of Registers in Standby Mode ........................................................................ 270 Section 10 Clock Oscillation Circuits Table 10.1 CPG Pins ................................................................................................................. 292 Table 10.2 CPG Register........................................................................................................... 292 Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) .................................................. 293 Table 10.3 (2) Clock Operating Modes (SH7750R)................................................................. 293 Table 10.4 FRQCR Settings and Internal Clock Frequencies ................................................... 294 Table 10.5 WDT Registers........................................................................................................ 301 Section 11 Realtime Clock (RTC) Table 11.1 RTC Pins ................................................................................................................. 313 Table 11.2 RTC Registers ......................................................................................................... 313 Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) ................................ 333 Section 12 Timer Unit (TMU) Table 12.1 TMU Pins................................................................................................................ 338 Table 12.2 TMU Registers ........................................................................................................ 339 Table 12.3 TMU Interrupt Sources ........................................................................................... 355 Page xlvi of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 13 Bus State Controller (BSC) Table 13.1 BSC Pins ................................................................................................................. 360 Table 13.2 BSC Registers ......................................................................................................... 364 Table 13.3 External Memory Space Map.................................................................................. 366 Table 13.4 PCMCIA Interface Features.................................................................................... 368 Table 13.5 PCMCIA Support Interfaces ................................................................................... 369 Table 13.6 MPX Interface is Selected (Areas 0 to 6)................................................................ 398 Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 423 Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 424 Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment ........................... 425 Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment ........................... 426 Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment............................. 427 Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment.................. 428 Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment.................. 429 Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ........................ 430 Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ........................ 431 Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment .......................... 432 Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing.... 451 Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ............................ 468 Table 13.17 Cycles for which Pipeline Access is Possible ......................................................... 484 Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ................ 502 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Direct Memory Access Controller (DMAC) DMAC Pins............................................................................................................. 549 DMAC Pins in DDT Mode ..................................................................................... 550 DMAC Registers..................................................................................................... 550 Selecting External Request Mode with RS Bits ...................................................... 570 Selecting On-Chip Peripheral Module Request Mode with RS Bits ....................... 572 Supported DMA Transfers ...................................................................................... 576 Relationship between DMA Transfer Type, Request Mode, and Bus Mode .......... 582 External Request Transfer Sources and Destinations in Normal DMA Mode ........ 583 External Request Transfer Sources and Destinations in DDT Mode ...................... 584 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings ......................................................... 602 DMAC Pins............................................................................................................. 636 DMAC Pins in DDT Mode ..................................................................................... 637 Register Configuration ............................................................................................ 638 Channel Selection by DTR Format (DMAOR.DBL = 1)........................................ 646 Notification of Transfer Channel in Eight-Channel DDT Mode............................. 648 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xlvii of lii Table 14.16 Function of BAVL .................................................................................................. 648 Table 14.17 DTR Format for Clearing Request Queues ............................................................. 649 Table 14.18 DMAC Interrupt-Request Codes............................................................................. 650 Section 15 Serial Communication Interface (SCI) Table 15.1 SCI Pins .................................................................................................................. 658 Table 15.2 SCI Registers........................................................................................................... 659 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode .................. 677 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode..................... 681 Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................. 682 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 683 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)..................... 683 Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection ......................................... 685 Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection .......................... 686 Table 15.10 Serial Transfer Formats (Asynchronous Mode) ...................................................... 688 Table 15.11 Receive Error Conditions........................................................................................ 696 Table 15.12 SCI Interrupt Sources.............................................................................................. 718 Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data............................................... 719 Table 15.14 Peripheral Module Signal Timing ........................................................................... 724 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 SCIF Pins ................................................................................................................ 728 Table 16.2 SCIF Registers ........................................................................................................ 729 Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection ......................................... 758 Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection ............................................... 758 Table 16.5 Serial Transmit/Receive Formats ............................................................................ 759 Table 16.6 SCIF Interrupt Sources............................................................................................ 770 Section 17 Smart Card Interface Table 17.1 Smart Card Interface Pins ....................................................................................... 777 Table 17.2 Smart Card Interface Registers ............................................................................... 777 Table 17.3 Smart Card Interface Register Settings ................................................................... 785 Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings ..................................... 788 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)........ 788 Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ..................... 788 Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ............. 789 Table 17.8 Register Settings and SCK Pin State....................................................................... 789 Table 17.9 Smart Card Mode Operating States and Interrupt Sources...................................... 796 Page xlviii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 18 I/O Ports Table 18.1 20-Bit General-Purpose I/O Port Pins ..................................................................... 811 Table 18.2 SCI I/O Port Pins..................................................................................................... 812 Table 18.3 SCIF I/O Port Pins .................................................................................................. 812 Table 18.4 I/O Port Registers .................................................................................................... 813 Section 19 Interrupt Controller (INTC) Table 19.1 INTC Pins ............................................................................................................... 827 Table 19.2 INTC Registers........................................................................................................ 827 Table 19.3 IRL3–IRL0 Pins and Interrupt Levels..................................................................... 830 Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1)......................... 831 Table 19.5 Interrupt Exception Handling Sources and Priority Order ...................................... 833 Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers............................................ 836 Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register ......................... 839 Table 19.8 Bit Assignments ...................................................................................................... 842 Table 19.9 Interrupt Response Time ......................................................................................... 846 Section 20 User Break Controller (UBC) Table 20.1 UBC Registers......................................................................................................... 853 Section 21 High-performance User Debug Interface (H-UDI) Table 21.1 H-UDI Pins.............................................................................................................. 881 Table 21.2 H-UDI Registers...................................................................................................... 882 Table 21.3 Configuration of the Boundary Scan Register......................................................... 888 Section 22 Electrical Characteristics Table 22.1 Absolute Maximum Ratings.................................................................................... 895 Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV)........................................................................................ 896 Table 22.3 DC Characteristics (HD6417750RF240 (V)) .......................................................... 898 Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*3)..................................................................................... 900 Table 22.5 DC Characteristics (HD6417750RF200 (V)) .......................................................... 902 Table 22.6 DC Characteristics (HD6417750SBP200 (V), HD6417750SBA200V).................. 904 Table 22.7 DC Characteristics (HD6417750SF200 (V)) .......................................................... 906 Table 22.8 DC Characteristics (HD6417750BP200M (V)) ...................................................... 908 Table 22.9 DC Characteristics (HD6417750SF167 (V)) .......................................................... 910 Table 22.10 DC Characteristics (HD6417750F167 (V))............................................................. 912 Table 22.11 DC Characteristics (HD6417750SVF133 (V))........................................................ 914 Table 22.12 DC Characteristics (HD6417750SVBT133 (V))..................................................... 916 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page xlix of lii Table 22.13 DC Characteristics (HD6417750VF128 (V)).......................................................... 918 Table 22.14 Permissible Output Currents ................................................................................... 919 Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV)........................................................................................ 920 Table 22.16 Clock Timing (HD6417750RF240 (V)).................................................................. 920 Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V*, HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*)...................................................................................... 920 Table 22.18 Clock Timing (HD6417750RF200 (V)).................................................................. 920 Table 22.19 Clock Timing (HD6417750SF200 (V)) .................................................................. 921 Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) .............................. 921 Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) ................... 921 Table 22.22 Clock Timing (HD6417750VF128 (V)).................................................................. 921 Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV).............................................. 922 Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V))................................... 924 Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*2)........................................... 926 Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V))................................... 928 Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V).................................................. 930 Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V)) ................................... 932 Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V), HD6417750SF167 (V))........................................................................................... 934 Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) ..................................................................................... 936 Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V))................................... 938 Table 22.32 Control Signal Timing............................................................................................. 946 Table 22.33 Control Signal Timing............................................................................................. 947 Table 22.34 Bus Timing (1) ........................................................................................................ 950 Table 22.35 Bus Timing (2) ........................................................................................................ 952 Table 22.36 Bus Timing (3) ........................................................................................................ 954 Table 22.37 Peripheral Module Signal Timing (1) ................................................................... 1003 Table 22.38 Peripheral Module Signal Timing (2) ................................................................... 1005 Table 22.39 Peripheral Module Signal Timing (3) ................................................................... 1007 Table 22.40 Peripheral Module Signal Timing (4) ................................................................... 1008 Table 22.41 Peripheral Module Signal Timing (5) ................................................................... 1010 Appendix A Address List Table A.1 Address List .......................................................................................................... 1017 Page l of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Appendix E Pin Functions Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State ......................... 1035 Appendix I Product Lineup Table I.1 SH7750/SH7750S/SH7750R Product Lineup ....................................................... 1067 Appendix J Version Registers Table J.1 Register Configuration .......................................................................................... 1069 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page li of lii Page lii of lii R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Section 1 Overview 1.1 SH7750, SH7750S, SH7750R Groups Features This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 and SH7750S have an 8-Kbyte instruction cache and a 16-Kbyte data cache. The SH7750R has a 16-Kbyte instruction cache and a 32-Kbyte data cache. This LSI has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions. The features of this LSI are summarized in table 1.1. Table 1.1 LSI Features Item Features LSI • Superscalar architecture: Parallel execution of two instructions • External buses ⎯ Separate 26-bit address and 64-bit data buses ⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Item Features CPU • Renesas original SuperH architecture • 32-bit internal data bus • General register file: ⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3) ⎯ Fixed 16-bit instruction length for improved code efficiency ⎯ Load-store architecture ⎯ Delayed branch instructions ⎯ Conditional execution ⎯ C-based instruction set Page 2 of 1076 • Superscalar architecture (providing simultaneous execution of two instructions) including FPU • Instruction execution time: Maximum 2 instructions/cycle • Virtual address space: 4 Gbytes (448-Mbyte external memory space) • Space identifier ASIDs: 8 bits, 256 virtual address spaces • On-chip multiplier • Five-stage pipeline R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Item Features FPU • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 • Floating-point registers: 32 bits × 16 × 2 banks (single-precision 32 bits × 16 or double-precision 64 bits × 8) × 2 banks • 32-bit CPU-FPU floating-point communication register (FPUL) • Supports FMAC (multiply-and-accumulate) instruction • Supports FDIV (divide) and FSQRT (square root) instructions • Supports FLDI0/FLDI1 (load constant 0/1) instructions • Instruction execution times ⎯ Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision) ⎯ Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only. • 3-D graphics instructions (single-precision only): ⎯ 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency) ⎯ 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 3 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Item Features Clock pulse generator (CPG) • Choice of main clock: ⎯ SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL ⎯ SH7750R: 1, 6, or 12 times EXTAL • Clock modes: ⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Note: Maximum frequency varies with models. • Power-down modes ⎯ Sleep mode ⎯ Standby mode ⎯ Module standby function Memory management unit (MMU) Page 4 of 1076 • Single-channel watchdog timer • 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) • Single virtual mode and multiple virtual memory mode • Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, 1 Mbyte • 4-entry fully-associative TLB for instructions • 64-entry fully-associative TLB for instructions and operands • Supports software-controlled replacement and random-counter replacement algorithm • TLB contents can be accessed directly by address mapping R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 1 Overview Features Cache memory • [SH7750, SH7750S] Instruction cache (IC) ⎯ 8 Kbytes, direct mapping ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯ 512 entries, 32-byte block length ⎯ Normal mode (16-Kbyte cache) ⎯ Index mode ⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM) ⎯ Choice of write method (copy-back or write-through) Cache memory [SH7750R] • Single-stage copy-back buffer, single-stage write-through buffer • Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) • Store queue (32 bytes × 2 entries) • Instruction cache (IC) ⎯ 16 Kbytes, 2-way set associative ⎯ 256 entries/way, 32-byte block length ⎯ Cache-double-mode (16-Kbyte cache) ⎯ Index mode ⎯ SH7750/SH7750S-compatible mode (8 Kbytes, direct mapping) • Operand cache (OC) ⎯ 32 Kbytes, 2-way set associative ⎯ 512 entries/way, 32-byte block length ⎯ Cache-double-mode (32-Kbyte cache) ⎯ Index mode ⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM) ⎯ SH7750/SH7750S-compatible mode (16 Kbytes, direct mapping) • Single-stage copy-back buffer, single-stage write-through buffer • Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) • Store queue (32 bytes × 2 entries) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 5 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Item Features Interrupt controller (INTC) • Five independent external interrupts: NMI, IRL3 to IRL0 • 15-level encoded external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module • Supports debugging by means of user break interrupts • Two break channels • Address, data value, access type, and data size can all be set as break conditions • Supports sequential break function • Supports external memory access User break controller (UBC) Bus state controller (BSC) ⎯ 64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ⎯ Bus size (8, 16, 32, or 64 bits) ⎯ Number of wait cycles (hardware wait function also supported) ⎯ Connection of DRAM, synchronous DRAM, and burst ROM possible by setting space type ⎯ Supports fast page mode and DRAM EDO ⎯ Supports PCMCIA interface ⎯ Chip select signals (CS0 to CS6) output for relevant areas • DRAM/synchronous DRAM refresh functions ⎯ Programmable refresh interval ⎯ Supports CAS-before-RAS refresh mode and self-refresh mode Page 6 of 1076 • DRAM/synchronous DRAM burst access function • Big endian or little endian mode can be set R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Features Direct memory access controller (DMAC) • Section 1 Overview Physical address DMA controller: ⎯ SH7750, SH7750S: 4-channel ⎯ SH7750R: 8-channel • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes • Address modes: ⎯ Single address mode ⎯ Dual address mode Timer unit (TMU) • Transfer requests: External, on-chip module, or auto-requests • Bus modes: Cycle-steal or burst mode • Supports on-demand data transfer • Auto-reload 32-bit timer: ⎯ SH7750, SH7750S: 3-channel ⎯ SH7750R: 5-channel • Input capture function • Choice of seven counter input clocks Realtime clock (RTC) • On-chip clock and calendar functions • Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) Serial communication interface (SCI, SCIF) • Two full-duplex communication channels (SCI, SCIF) • Channel 1 (SCI): ⎯ Choice of asynchronous mode or synchronous mode ⎯ Supports smart card interface • Channel 2 (SCIF): ⎯ Supports asynchronous mode ⎯ Separate 16-byte FIFOs provided for transmitter and receiver R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 7 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Item Features Product lineup Abbreviation Voltage (Internal) Operating Frequency Model No. Package SH7750 1.95 V 200 MHz HD6417750BP200M 256-pin BGA 1.8 V 167 MHz HD6417750F167 208-pin QFP 1.5 V 128 MHz HD6417750VF128 1.95 V 200 MHz HD6417750SBP200 SH7750S 256-pin BGA HD6417750SBA200 HD6417750SF200 SH7750R 1.8 V 167 MHz HD6417750SF167 1.5 V 133 MHz HD6417750SVF133 1.5 V 240 MHz 208-pin QFP HD6417750SVBT133 264-pin CSP HD6417750RBG240 292-pin BGA HD6417750RBP240 256-pin BGA HD6417750RBA240H 200 MHz Page 8 of 1076 HD6417750RF240 208-pin QFP HD6417750RBG200 292-pin BGA HD6417750RBP200 256-pin BGA HD6417750RF200 208-pin QFP R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 1.2 Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram of this LSI. Cache and TLB controller RTC TMU O cache 32-bit data 32-bit data BSC Address SCI (SCIF) Peripheral address bus INTC 16-bit peripheral data bus CPG UTLB SH-4 Core DMAC 64-bit data ITLB Upper 32-bit data Lower 32-bit data 64-bit data (store) Lower 32-bit data 29-bit address I cache FPU 64-bit data 32-bit data (load) UBC 32-bit data (store) 32-bit address (data) 32-bit data (instructions) 32-bit address (instructions) CPU External bus interface 26-bit address Legend: BSC: CPG: DMAC: FPU: INTC: ITLB: Bus state controller Clock pulse generator Direct memory access controller Floating-point unit Interrupt controller Instruction TLB (translation lookaside buffer) 64-bit data UTLB: RTC: SCI: SCIF: TMU: UBC: Unified TLB (translation lookaside buffer) Realtime clock Serial communication interface Serial communication interface with FIFO Timer unit User break controller Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 9 of 1076 Section 1 Overview 1 G D35 D43 H D36 D42 J D2 D12 D3 D11 D4 D10 D5 D9 9 10 11 12 13 14 15 16 17 VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 18 19 20 NMI IRL3 IRL2 IRL1 IRL0 MD1/TXD2 MD0/SCK D63 D48 D62 CTS2 CS4 CS5 RD2 D49 D61 CA* MD2/RXD2 D50 D60 RD/WR2 D51 D59 D52 D58 BGA256 (Top view) K D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 L M N P BACK/BSREQ BREQ/BSACK R DREQ1 DREQ0 RXD T U V W Y D8 D7 CKE WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 D6 8 DRAK1 DRAK0 D1 D13 7 CKIO CKIO2 A6 A5 A4 A3 A2 CS3 CS2 RAS RD/CASS/FRAME RD/WR WE2/CAS2/DQM2/ICIORD WE3/CAS3/DQM3/ICIOWR WE6/CAS6/DQM6 WE7/CAS7/DQM7/REG D23 D24 D22 D0 D14 6 A1 A0 F D34 D44 D39 D15 5 VSS-PLL2 D D33 D45 D38 D40 4 TRST C E D41 3 B D32 D46 D37 2 A VSS-PLL1 RDY RESET CS0 CS1 CS6 BS D47 MD3/CE2A A25 A24 A23 A22 A21 A20 A19 A18 MD7/TXD SCK2/MRESET MD8/RTS2 TCLK Pin Arrangement EXTAL CKIO2ENB XTAL VSS-CPG VDD-CPG(3.3V) VDD-PLL1(3.3V) VDD-PLL2(3.3V) TDI TCK TMS TDO ASEBRK/BRKACK MD6/IOIS16 STATUS1 STATUS0 DACK1 DACK0 MD5/RAS2 MD4/CE2B 1.3 SH7750, SH7750S, SH7750R Group VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.2 Pin Arrangement (256-Pin BGA) Page 10 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 CA* VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 SCK2/MRESET MD7/TXD MD8/RTS2 TCLK CTS2 A23 A22 A21 A20 A19 A18 A0 DACK1 DACK0 MD5/RAS2 MD4/CE2B MD3/CE2A A25 A24 TDO ASEBRK/BRKACK MD6/IOIS16 STATUS1 STATUS0 A1 VSS (internal) VDDQ (IO) VSSQ (IO) NMI IRL3 IRL2 IRL1 IRL0 MD2/RXD2 MD1/TXD2 MD0/SCK D63 D48 D62 D49 D61 D50 D60 D51 D59 D52 D58 D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 DREQ1 DREQ0 RXD WE7/CAS7/DQM7/REG D23 D24 D22 RAS RD/CASS/FRAME RD/WR WE2/CAS2/DQM2/IOICRD WE3/CAS3/DQM3/IOICWR WE6/CAS6/DQM6 D8 D7 CKE D11 D4 D10 D5 D9 D6 BACK/BSREQ BREQ/BSACK VDD (internal) CS3 CS2 D12 D3 Top view A6 A5 A4 A3 A2 DRAK1 DRAK0 D15 D0 D14 D1 D13 D2 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 QFP208 A12 A11 A10 A9 A8 A7 CKIO D43 D36 D42 D37 D41 D38 D40 D39 A14 A13 D46 D33 D45 D34 D44 D35 WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 D47 D32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 RDY RESET CS0 CS1 CS4 CS5 CS6 BS Section 1 Overview 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 EXTAL XTAL VSS-CPG VDD-CPG(3.3V) VSS-PLL1 VDD-PLL1(3.3V) VSS-PLL2 VDD-PLL2(3.3V) TRST TDI TCK TMS SH7750, SH7750S, SH7750R Group Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.3 Pin Arrangement (208-Pin QFP) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 11 of 1076 Section 1 Overview 1 2 SH7750, SH7750S, SH7750R Group 3 4 5 6 7 8 9 10 11 12 13 A0 VDDQ VDDQ A20 VDD TCLK 14 15 16 17 EXTAL2 IRL2 A VSS-CPG XTAL RESET CS4 EXTAL VDD-CPG TRST TDO MD6/IOIS16 VSS-RTC XTAL2 B VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD IRL3 CA C RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI MD5/RAS2 A23 VSS MD8/RTS2 VSSQ SCK2/ MRESET D48 RD/WR2 A21 A19 D49 VDDQ D63 MD0/SCK D62 D50 VDDQ VDD VSSQ VSS D61 D52 VDDQ D51 VSSQ D60 D59 VSSQ D57 D53 D54 D58 VDDQ D CS0 VSSQ CKIO2ENB TDI VDD A1 CTS2 VSSQ IRL0 IRL1 E BS CS1 CS5 CS6 TMS ASEBRK/ BRKACK VDDQ VDD D47 VDDQ RD2 D32 D33 STATUS1 D45 VDDQ D46 VSS VSSQ D34 VDDQ D43 D44 D35 VSSQ D36 VDDQ D38 D42 D41 D37 VSSQ D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17 D2 D4 D3 VDDQ D13 A14 VSSQ D5 D11 D12 A16 VSSQ VDDQ VDDQ MD4/CE2B VSSQ MD2/RXD2 VSSQ F DACK1 VSSQ A25 G H CSP264 (Top view) J K L M A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20 VDD A11 VSSQ VSSQ CS2 VSSQ D25 A17 VSS A12 A8 VDDQ VDDQ RAS VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/WR D24 WE1/CAS1/ DQM1 A15 VSSQ A10 CKIO A5 DRAK1 CS3 VDDQ N P VDDQ WE4/CAS4/ WE0/CAS0/ DQM4 DQM0 RD/CASS/ VSSQ FRAME DREQ1 R D6 BREQ/ BSACK D10 BACK/ BSREQ VSSQ D8 D9 D7 CKE WE5/CAS5/ DQM5 WE3/CAS3/ WE6/CAS6/ WE2/CAS2/ RXD DQM3/ICIOWR DQM6 DQM2/ICIORD T D22 VSSQ DREQ0 D23 VSSQ U VDDQ WE7/CAS7/ DQM7/REG VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.4 Pin Arrangement (264-Pin CSP) Page 12 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 1 Overview EXTAL VSS-PLL1 XTAL VDD-CPG(3.3V) VSS-CPG VSS-PLL2 VDD-PLL1(3.3V) TRST VDD-PLL2(3.3V) TMS TCK MD6/IOIS16 ASEBRK/BRKACK STATUS0 STATUS1 A0 A1 DACK0 DACK1 MD5/RAS2 MD4/CE2B MD3/CE2A A25 A24 A23 A22 A21 A20 A19 A18 SCK2/MRESET MD7/TXD TCLK CTS2 VDD-RTC(3.3V) VSS-RTC EXTAL2 IRL3 SH7750, SH7750S, SH7750R Group 1 H D43 D36 J D13 D3 D12 D10 D4 D9 D5 BACK/ BSREQ 10 11 12 13 14 15 16 17 18 19 20 NMI IRL1 IRL2 MD2/RXD2 IRL0 RD/WR2 CS4 BS TDI BGA292 (Top view) MD0/SCK D62 D48 D61 CA MD1/TXD2 D63 D49 D60 D50 D59 D51 D58 D53 D52 D37 K D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D21 D25 DREQ1 L M P D11 R D7 WE4/CAS4/DQM4 CKIO2 N D26 WE2/CAS2/ DQM2/ICIORD T U V W WE7/CAS7/DQM7/ REG Y D6 D8 CKE WE5/CAS5/DQM5 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 CKIO BREQ/ BSACK 9 A5 A6 A3 A4 DRAK1 A2 CS3 DRAK0 RAS CS2 RD/WR RD/CASS/FRAME WE6/CAS6/DQM6 WE3/CAS3/DQM3/ICIOWR D24 D23 D22 DREQ0 RXD D14 D2 8 MD8/ RTS2 D44 D35 D15 D1 7 XTAL2 VSS-RTC E G D40 D0 6 D D45 D34 D38 5 C F D41 D39 4 B D46 D33 D42 3 TDO D47 D32 2 A CKIO2ENB RDY RESET CS0 CS1 CS5 CS6 RD2 VDDQ (IO) VDD (internal) VSS Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.5 Pin Arrangement (292-Pin BGA) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 13 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group 1.4 Pin Functions 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions Memory Interface No. Pin No. Pin Name 1 B2 2 B1 3 4 I/O Function RDY I Bus ready RESET I Reset C2 CS0 O Chip select 0 CS0 CS0 C1 CS1 O Chip select 1 CS1 CS1 5 D4 CS4 O Chip select 4 CS4 CS4 6 D3 CS5 O Chip select 5 CS5 CE1A CS5 7 D2 CS6 O Chip select 6 CS6 CE1B CS6 8 D1 BS O Bust start (BS) (BS) (BS) (BS) 9 E4 VSSQ Power IO GND (0 V) 10 E3 RD2 O CAS OE FRAME 11 F3 VDDQ Power IO VDD (3.3 V) 12 F4 VSSQ Power IO GND (0 V) 13 E2 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port) 14 E1 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port) 15 G3 VDD Power Internal VDD (1.8 V) 16 G4 VSS Power Internal GND (0 V) 17 F2 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port) 18 F1 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port) 19 H3 VDDQ Power IO VDD (3.3 V) 20 H4 VSSQ Power IO GND (0 V) 21 G2 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port) 22 G1 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port) 23 H2 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port) 24 H1 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port) 25 J3 VDDQ Power IO VDD (3.3 V) 26 J4 VSSQ Power IO GND (0 V) Page 14 of 1076 RD/CASS/ FRAME Reset SRAM DRAM SDRAM PCMCIA MPX RDY RDY RDY RESET (BS) OE R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface No. Pin No. Pin Name I/O Function 27 J2 D43 I/O 28 J1 D36 I/O 29 K2 D42 30 K1 31 K3 32 K4 VSSQ Power IO GND (0 V) 33 L1 D41 I/O 34 L2 D38 I/O 35 M1 D40 36 M2 D39 37 L3 VDDQ Power IO VDD (3.3 V) 38 L4 VSSQ Power IO GND (0 V) 39 N1 D15 I/O Data A15 40 N2 D0 I/O Data A0 41 P1 D14 I/O Data A14 42 P2 D1 I/O Data A1 43 M3 VDDQ Power IO VDD (3.3 V) 44 M4 VSSQ Power IO GND (0 V) 45 R1 D13 I/O Data A13 46 R2 D2 I/O Data A2 47 P3 VDD Power Internal VDD 48 P4 VSS Power Internal GND (0 V) 49 T1 D12 I/O Data A12 Data A3 SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) I/O Data/port (Port) (Port) (Port) (Port) (Port) D37 I/O Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) I/O Data/port (Port) (Port) (Port) (Port) (Port) I/O Data/port (Port) (Port) (Port) (Port) (Port) 50 T2 D3 I/O 51 R3 VDDQ Power IO VDD (3.3 V) 52 R4 VSSQ Power IO GND (0 V) Reset 53 U1 D11 I/O Data A11 54 U2 D4 I/O Data A4 55 V1 D10 I/O Data A10 56 V2 D5 I/O Data A5 57 T3 VDDQ Power IO VDD (3.3 V) 58 T4 VSSQ Power IO GND (0 V) 59 W1 D9 I/O R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Data A9 Page 15 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Memory Interface Pin No. Pin Name I/O 60 Y1 D6 I/O Data 61 U3 BACK/ BSREQ O Bus acknowledge/ bus request 62 V3 BREQ/ BSACK I Bus request/bus acknowledge 63 W2 D8 I/O Data No. Function Reset SRAM DRAM SDRAM PCMCIA MPX A6 A8 64 Y2 D7 I/O Data 65 W3 CKE O Clock output enable 66 V5 VDDQ Power IO VDD (3.3 V) 67 U5 VSSQ Power IO GND (0 V) 68 Y3 WE5/CAS5/ O DQM5 D47–D40 select signal WE5 CAS5 DQM5 69 W4 WE4/CAS4/ O DQM4 D39–D32 select signal WE4 CAS4 DQM4 70 Y4 WE1/CAS1/ O DQM1 D15–D8 select signal WE1 CAS1 DQM1 71 W5 WE0/CAS0/ O DQM0 D7–D0 select signal WE0 CAS0 DQM0 72 Y5 A17 O Address 73 V6 VDDQ Power IO VDD (3.3 V) 74 U6 VSSQ Power IO GND (0 V) 75 W6 A16 O Address 76 Y6 A15 O Address 77 V7 VDD Power Internal VDD 78 U7 VSS Power Internal GND (0 V) 79 W7 A14 O Address 80 Y7 A13 O Address 81 V8 VDDQ Power IO VDD (3.3 V) 82 U8 VSSQ Power IO GND (0 V) 83 V4 NC 84 W8 A12 O Address 85 Y8 A11 O Address Page 16 of 1076 A7 CKE WE1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface No. Pin No. Pin Name I/O Function 86 W9 A10 O Address 87 V9 VDDQ Power IO VDD (3.3 V) 88 U9 VSSQ Power IO GND (0 V) 89 Y9 A9 O Address 90 W10 A8 O Address 91 Y10 A7 O Address 92 Y11 CKIO O Clock output 93 V10 VDDQ Power IO VDD (3.3 V) 94 U10 VSSQ Power IO GND (0 V) 95 W11 CKIO2 O CKIO* 96 Y12 A6 O Address 97 W12 A5 O Address 98 Y13 A4 O Address 99 V11 VDDQ Power IO VDD (3.3 V) 1 Reset SRAM DRAM SDRAM PCMCIA MPX CKIO CKIO CKIO CKIO CKIO CKIO 100 U11 VSSQ Power IO GND (0 V) 101 W13 A3 O Address 102 Y14 A2 O Address 103 V12 DRAK1 O DMAC1 request acknowledge 104 U13 DRAK0 O DMAC0 request acknowledge 105 V13 VDDQ Power IO VDD (3.3 V) 106 U12 VSSQ Power IO GND (0 V) 107 W14 CS3 O Chip select 3 CS3 (CS3) CS3 CS3 Chip select 2 CS2 (CS2) CS2 CS2 RAS RAS 108 Y15 CS2 O 109 V14 VDD Power Internal VDD 110 U14 VSS Power Internal GND (0 V) 111 W15 RAS O RAS 112 Y16 RD/CASS/ FRAME O Read/CAS/ FRAME 113 V15 VDDQ Power IO VDD (3.3 V) 114 U15 VSSQ Power IO GND (0 V) 115 W16 RD/WR O R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Read/write OE CAS OE FRAME RD/WR RD/WR RD/WR RD/WR RD/WR Page 17 of 1076 Section 1 Overview No. Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 116 Y17 WE2/CAS2/ O DQM2/ ICIORD D23–D16 select signal WE2 CAS2 DQM2 ICIORD 117 W17 WE3/CAS3/ O DQM3/ ICIOWR D31–D24 select signal WE3 CAS3 DQM3 ICIOWR 118 Y18 WE6/CAS6/ O DQM6 D55–D48 select signal WE6 CAS6 DQM6 119 V16 VDDQ Power IO VDD (3.3 V) 120 U16 VSSQ Power IO GND (0 V) 121 W18 WE7/CAS7/ O DQM7/REG WE7 CAS7 DQM7 D63–D56 select signal REG 122 Y19 D23 I/O Data A23 123 W19 D24 I/O Data A24 124 Y20 D22 I/O Data A22 125 V17 RXD I SCI data input 126 U17 DREQ0 I Request from DMAC0 127 U18 DREQ1 I Request from DMAC1 128 W20 D25 I/O Data 129 T18 VDDQ Power IO VDD (3.3 V) 130 T17 VSSQ Power IO GND (0 V) 131 V19 D21 I/O Data 132 V20 D26 I/O Data 133 U19 D20 I/O Data 134 U20 D27 I/O Data 135 R18 VDDQ Power IO VDD (3.3 V) 136 R17 VSSQ Power IO GND (0 V) 137 T19 D19 I/O Data Data 138 T20 D28 I/O 139 P18 VDD Power Internal VDD 140 P17 VSS Power Internal GND (0 V) 141 R19 D18 I/O Data 142 R20 D29 I/O Data Page 18 of 1076 A25 A21 A20 A19 A18 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group No. Pin No. Memory Interface Pin Name I/O Function 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 D17 I/O Data 146 P20 D30 I/O Data 147 N19 D16 I/O Data 148 N20 D31 I/O Data 149 M18 VDDQ Power IO VDD (3.3 V) 150 M17 VSSQ Power IO GND (0 V) 151 M19 D55 I/O Data 152 M20 D56 I/O Data 153 L19 D54 I/O Data 154 L20 D57 I/O Data 155 L18 VDDQ Power IO VDD (3.3 V) 156 L17 VSSQ Power IO GND (0 V) 157 K20 D53 I/O Data 158 K19 D58 I/O Data 159 J20 D52 I/O Data 160 J19 D59 I/O Data 161 K18 VDDQ Power IO VDD (3.3 V) 162 K17 VSSQ Power IO GND (0 V) 163 H20 D51 I/O Data/port 164 H19 D60 I/O Data 165 G20 D50 I/O Data/port 166 G19 D61 I/O Data 167 J18 VDDQ Power IO VDD (3.3 V) 168 J17 VSSQ Power IO GND (0 V) 169 F20 D49 I/O Data/port 170 F19 D62 I/O Data 171 G18 VDD Power Internal VDD 172 G17 VSS Power Internal GND (0 V) 173 E20 D48 I/O Data/port 174 E19 D63 I/O Data 175 F18 VDDQ Power IO VDD (3.3 V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Section 1 Overview Reset SRAM DRAM SDRAM PCMCIA MPX A17 A16 (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) ACCSIZE1 (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Page 19 of 1076 Section 1 Overview No. Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 E18 RD/WR2 O RD/WR 179 D20 MD0/SCK I/O Mode/SCI clock 180 D19 MD1/TXD2 I/O 181 D18 Reset SRAM DRAM SDRAM PCMCIA MPX RD/WR RD/WR RD/WR RD/WR RD/WR SCK SCK SCK SCK SCK Mode SCIF data MD1 output TXD2 TXD2 TXD2 TXD2 TXD2 MD2/RXD2 I Mode/SCIF data MD2 input RXD2 RXD2 RXD2 RXD2 RXD2 182 C20 IRL0 I Interrupt 0 183 C19 IRL1 I Interrupt 1 184 B20 IRL2 I Interrupt 2 185 C18 IRL3 I Interrupt 3 186 A20 NMI I Nonmaskable interrupt 187 B19 XTAL2 O RTC crystal resonator pin 188 A19 EXTAL2 I RTC crystal resonator pin 189 B18 VSS-RTC Power RTC GND (0 V) 190 A18 VDD-RTC Power RTC VDD (3.3 V) 191 D17 CA I 192 C17 VSS Power Internal GND (0 V) 193 B17 VDDQ Power IO VDD (3.3 V) 194 C16 CTS2 I/O SCIF data control (CTS) 195 A17 TCLK I/O RTC/TMU clock 196 B16 MD8/RTS2 I/O MD8 RTS2 RTS2 RTS2 RTS2 RTS2 197 C15 VDDQ Power IO VDD (3.3 V) 198 D15 VSSQ Power IO GND (0 V) 199 B15 MD7/TXD I/O MD7 TXD TXD TXD TXD TXD Page 20 of 1076 MD0 *2 Mode/SCIF data control (RTS) Mode/SCI data output R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group No. Pin No. Section 1 Overview Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 200 A16 SCK2/ MRESET I SCIF clock/ manual reset MRESET SCK2 SCK2 SCK2 201 C14 VDD Power Internal VDD 202 D14 VSS Power Internal GND (0 V) 203 A15 A18 O Address 204 B14 A19 O Address 205 C13 VDDQ Power IO VDD (3.3 V) 206 D13 VSSQ Power IO GND (0 V) 207 A14 A20 O Address 208 B13 A21 O Address 209 A13 A22 O Address 210 B12 A23 O Address SCK2 211 C12 VDDQ Power IO VDD (3.3 V) 212 D12 VSSQ Power IO GND (0 V) 213 A12 A24 O Address 214 B11 A25 O Address 215 A11 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 216 A10 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 217 C11 VDDQ Power IO VDD (3.3 V) 218 D11 VSSQ Power IO GND (0 V) 219 B10 MD5/RAS2 I/O Mode/RAS (DRAM) 220 A9 DACK0 O DMAC0 bus acknowledge 221 B9 DACK1 O DMAC1 bus acknowledge 222 C8 A0 O Address 223 C10 VDDQ Power IO VDD (3.3 V) 224 D10 VSSQ Power IO GND (0 V) 225 D8 A1 O Address 226 A8 STATUS0 O Status 227 B8 STATUS1 O Status R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 MD5 SCK2 RAS2 Page 21 of 1076 Section 1 Overview No. Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset 228 A7 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) MD6 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power IO GND (0 V) 231 B7 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 232 A6 TDO O Data out (H-UDI) 233 C7 VDD Power Internal VDD 234 D7 VSS Power Internal GND (0 V) 235 B6 TMS I Mode (H-UDI) 236 A5 TCK I Clock (H-UDI) 237 B5 TDI I Data in (H-UDI) 238 C4 TRST I Reset (H-UDI) 239 C3 CKIO2ENB I 240 C6 NC 241 A4 VDD-PLL2 Power PLL2 VDD (3.3V) 242 D6 VSS-PLL2 Power PLL2 GND (0V) 243 B4 VDD-PLL1 Power PLL1 VDD (3.3V) 244 D5 VSS-PLL1 Power PLL1 GND (0V) 245 A3 VDD-CPG Power CPG VDD (3.3V) 246 B3 VSS-CPG Power CPG GND (0V) 247 A2 XTAL O Crystal resonator 248 A1 EXTAL I External input clock/crystal resonator 249 C5 NC Page 22 of 1076 SRAM DRAM SDRAM PCMCIA MPX IOIS16 CKIO2, RD2, RD/WR2 enable R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group No. Pin No. Section 1 Overview Memory Interface Pin Name 250 D16 NC 251 H17 NC 252 H18 NC 253 N3 NC 254 N4 NC 255 U4 NC 256 V18 NC I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. NC pins must be left completely open, and not connected to a power supply, GND, etc. 1. CKIO2 is not connected to PLL2. 2. Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 23 of 1076 Section 1 Overview 1.4.2 SH7750, SH7750S, SH7750R Group Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Memory Interface Pin No. Pin Name I/O Function 1 RDY I Bus ready 2 RESET I Reset 3 CS0 O Chip select 0 CS0 CS0 4 CS1 O Chip select 1 CS1 CS1 5 CS4 O Chip select 4 CS4 6 CS5 O Chip select 5 CS5 7 CS6 O Chip select 6 CS6 CE1B CS6 8 BS O Bust start (BS) (BS) (BS) (BS) (BS) 9 VDDQ Power IO VDD (3.3 V) 10 VSSQ Power IO GND (0 V) 11 D47 I/O Data/port (Port) (Port) (Port) (Port) (Port) 12 D32 I/O Data/port (Port) (Port) (Port) (Port) (Port) 13 VDD Power Internal VDD 14 VSS Power Internal GND (0 V) 15 D46 I/O Data/port (Port) (Port) (Port) (Port) (Port) 16 D33 I/O Data/port (Port) (Port) (Port) (Port) (Port) 17 D45 I/O Data/port (Port) (Port) (Port) (Port) (Port) 18 D34 I/O Data/port (Port) (Port) (Port) (Port) (Port) 19 D44 I/O Data/port (Port) (Port) (Port) (Port) (Port) 20 D35 I/O Data/port (Port) (Port) (Port) (Port) (Port) 21 VDDQ Power IO VDD (3.3 V) 22 VSSQ Power IO GND (0 V) 23 D43 I/O Data/port (Port) (Port) (Port) (Port) (Port) 24 D36 I/O Data/port (Port) (Port) (Port) (Port) (Port) 25 D42 I/O Data/port (Port) (Port) (Port) (Port) (Port) 26 D37 I/O Data/port (Port) (Port) (Port) (Port) (Port) 27 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port) 28 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port) 29 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port) Page 24 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX RDY RDY RDY RESET CS4 CE1A CS5 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. Section 1 Overview Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 30 D39 I/O Data/port 31 VDDQ Power IO VDD (3.3 V) (Port) (Port) (Port) 32 VSSQ Power IO GND (0 V) 33 D15 I/O Data A15 34 D0 I/O Data A0 (Port) (Port) 35 D14 I/O Data A14 36 D1 I/O Data A1 37 D13 I/O Data A13 38 D2 I/O Data A2 39 VDD Power Internal VDD (1.8 V) 40 VSS Power Internal GND (0 V) 41 D12 I/O Data A12 42 D3 I/O Data A3 43 VDDQ Power IO VDD (3.3 V) 44 VSSQ Power IO GND (0 V) 45 D11 I/O Data A11 46 D4 I/O Data A4 47 D10 I/O Data A10 48 D5 I/O Data A5 49 D9 I/O Data A9 50 D6 I/O Data A6 51 BACK/ BSREQ O Bus acknowledge/ bus request 52 BREQ/ BSACK I Bus request/bus acknowledge 53 D8 I/O Data A8 54 D7 I/O Data A7 55 CKE O Clock output enable 56 VDDQ Power IO VDD (3.3 V) 57 VSSQ Power IO GND (0 V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 CKE Page 25 of 1076 Section 1 Overview Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 58 WE5/CAS5/ O DQM5 D47–D40 select signal WE5 CAS5 DQM5 59 WE4/CAS4/ O DQM4 D39–D32 select signal WE4 CAS4 DQM4 60 WE1/CAS1/ O DQM1 D15–D8 select signal WE1 CAS1 DQM1 61 WE0/CAS0/ O DQM0 D7–D0 select signal WE0 CAS0 DQM0 62 A17 O Address 63 A16 O Address 64 A15 O Address 65 VDD Power Internal VDD 66 VSS Power Internal GND (0 V) 67 A14 O Address 68 A13 O Address 69 VDDQ Power IO VDD (3.3 V) 70 VSSQ Power IO GND (0 V) 71 A12 O Address 72 A11 O Address 73 A10 O Address 74 A9 O Address 75 A8 O Address 76 A7 O Address 77 CKIO O Clock output 78 VDDQ Power IO VDD (3.3 V) 79 VSSQ Power IO GND (0 V) 80 A6 O Address 81 A5 O Address 82 A4 O Address 83 A3 O Address 84 A2 O Address 85 DRAK1 O DMAC1 request acknowledge Page 26 of 1076 CKIO CKIO WE1 CKIO R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. Pin Name I/O Function 86 DRAK0 O DMAC0 request acknowledge 87 VDDQ Power IO VDD (3.3 V) 88 VSSQ Power IO GND (0 V) 89 CS3 O Reset SRAM DRAM SDRAM PCMCIA MPX Chip select 3 CS3 (CS3) CS3 CS3 CS2 (CS2) CS2 CS2 RAS RAS 90 CS2 O Chip select 2 91 VDD Power Internal VDD 92 VSS Power Internal GND (0 V) 93 RAS O RAS 94 RD/CASS/ FRAME O Read/CAS/ FRAME OE 95 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR 96 WE2/CAS2/ O DQM2/ ICIORD D23–D16 select signal WE2 CAS2 DQM2 ICIORD 97 WE3/CAS3/ O DQM3/ ICIOWR D31–D24 select signal WE3 CAS3 DQM3 ICIOWR 98 WE6/CAS6/ O DQM6 D55–D48 select signal WE6 CAS6 DQM6 WE7 CAS7 DQM7 CAS OE FRAME RD/WR 99 VDDQ Power IO VDD (3.3 V) 100 VSSQ Power IO GND (0 V) 101 WE7/CAS7/ O DQM7/REG D63–D56 select signal 102 D23 I/O Data A23 103 D24 I/O Data A24 104 D22 I/O Data A22 105 RXD I SCI Data input 106 DREQ0 I Request from DMAC0 107 DREQ1 I Request from DMAC1 108 D25 I/O Data A25 109 D21 I/O Data A21 110 D26 I/O Data 111 D20 I/O Data R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 REG A20 Page 27 of 1076 Section 1 Overview Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function 112 D27 I/O Data 113 VDDQ Power IO VDD (3.3 V) 114 VSSQ Power IO GND (0 V) 115 D19 I/O Data 116 D28 I/O Data 117 VDD Power Internal VDD 118 VSS Power Internal GND (0 V) 119 D18 I/O Data 120 D29 I/O Data 121 D17 I/O Data 122 D30 I/O Data 123 D16 I/O Data 124 D31 I/O Data 125 VDDQ Power IO VDD (3.3 V) 126 VSSQ Power IO GND (0 V) 127 D55 I/O Data 128 D56 I/O Data 129 D54 I/O Data 130 D57 I/O Data 131 D53 I/O Data 132 D58 I/O Data 133 D52 I/O Data 134 D59 I/O Data 135 VDDQ Power IO VDD (3.3 V) 136 VSSQ Power IO GND (0 V) 137 D51 I/O Data/port 138 D60 I/O Data 139 D50 I/O Data/port 140 D61 I/O Data 141 D49 I/O Data/port 142 D62 I/O Data 143 VDD Power Internal VDD Page 28 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX A19 A18 A17 A16 (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) ACCSIZE1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. Pin Name I/O Function 144 VSS Power Internal GND (0 V) 145 D48 I/O Data/port 146 D63 I/O Data 147 VDDQ Power IO VDD (3.3 V) 148 VSSQ Power IO GND (0 V) 149 MD0/SCK I/O Mode/SCI clock 150 MD1/TXD2 I/O 151 MD2/RXD2 152 Reset SRAM DRAM SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) ACCSIZE2 SCK SCK SCK SCK SCK Mode SCIF data MD1 output TXD2 TXD2 TXD2 TXD2 TXD2 I Mode/SCIF data MD2 input RXD2 RXD2 RXD2 RXD2 RXD2 IRL0 I Interrupt 0 153 IRL1 I Interrupt 1 154 IRL2 I Interrupt 2 155 IRL3 I Interrupt 3 156 NMI I Nonmaskable interrupt 157 XTAL2 O RTC crystal resonator pin 158 EXTAL2 I RTC crystal resonator pin 159 VSS-RTC Power RTC GND (0 V) 160 VDD-RTC Power RTC VDD (3.3 V) 161 CA I * 162 VSS Power Internal GND (0 V) 163 VDDQ Power IO VDD (3.3 V) 164 CTS2 I/O SCIF data control (CTS) 165 TCLK I/O RTC/TMU clock 166 MD8/RTS2 I/O Mode/SCIF data MD8 control (RTS) RTS2 RTS2 RTS2 RTS2 RTS2 167 MD7/TXD I/O Mode/SCI data output TXD TXD TXD TXD TXD R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 MD0 MD7 Page 29 of 1076 Section 1 Overview Pin No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset 168 SCK2/ MRESET I SCIF clock/ manual reset MRESET SCK2 169 VDD Power Internal VDD 170 VSS Power Internal GND (0 V) 171 A18 O Address 172 A19 O Address 173 A20 O Address 174 A21 O Address 175 A22 O Address 176 A23 O Address 177 VDDQ Power IO VDD (3.3 V) 178 VSSQ Power IO GND (0 V) 179 A24 O Address 180 A25 O Address 181 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 182 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 183 MD5/RAS2 I/O Mode/RAS (DRAM) MD5 184 DACK0 O DMAC0 bus acknowledge 185 DACK1 O DMAC1 bus acknowledge 186 A0 O Address 187 VDDQ Power IO VDD (3.3 V) 188 VSSQ Power IO GND (0 V) 189 A1 O Address 190 STATUS0 O Status 191 STATUS1 O Status 192 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) 193 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) Page 30 of 1076 MD6 SRAM DRAM SDRAM PCMCIA MPX SCK2 SCK2 SCK2 SCK2 RAS2 IOIS16 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. Pin Name I/O Function 194 TDO O Data out (H-UDI) 195 VDD Power Internal VDD 196 VSS Power Internal GND (0 V) 197 TMS I Mode (H-UDI) 198 TCK I Clock (H-UDI) 199 TDI I Data in (H-UDI) 200 TRST I Reset (H-UDI) 201 VDD-PLL2 Power PLL2 VDD (3.3V) 202 VSS-PLL2 Power PLL2 GND (0V) 203 VDD-PLL1 Power PLL1 VDD (3.3V) 204 VSS-PLL1 Power PLL1 GND (0V) 205 VDD-CPG Power CPG VDD (3.3V) 206 VSS-CPG Power CPG GND (0V) 207 XTAL O Crystal resonator 208 EXTAL I External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package. For a QFP package, the maximum operating frequency of the external bus is 84 MHz. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 31 of 1076 Section 1 Overview 1.4.3 SH7750, SH7750S, SH7750R Group Pin Functions (264-Pin CSP) Table 1.4 Pin Functions Memory Interface Pin No. No. Pin Name 1 C2 2 B1 3 I/O Function RDY I Bus ready RESET I Reset D3 CS0 O Chip select 0 CS0 CS0 4 E2 CS1 O Chip select 1 CS1 CS1 5 B2 CS4 O Chip select 4 CS4 CS4 6 E3 CS5 O Chip select 5 CS5 7 E4 CS6 O Chip select 6 CS6 8 E1 BS O Bus start (BS) 9 F4 RD2 O RD/CASS/ FRAME OE 10 F3 VDDQ Power IO VDD (3.3 V) 11 D4 VSSQ Power IO GND (0 V) 12 F2 D47 I/O Data/port (Port) 13 F5 D32 I/O Data/port 14 F1 VDD Power Internal VDD (1.5 V) 15 G4 VSS Power Internal GND (0 V) 16 G3 D46 I/O 17 F6 D33 I/O 18 G2 VDDQ Power IO VDD (3.3 V) 19 G5 VSSQ Power IO GND (0 V) 20 G1 D45 I/O 21 G6 D34 I/O 22 H3 D44 I/O 23 H4 D35 I/O Data/port 24 H1 VDDQ Power IO VDD (3.3 V) 25 H5 VSSQ Power IO GND (0 V) 26 H2 D43 I/O 27 H6 D36 28 J3 D42 Page 32 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX RDY RDY RDY RESET CE1A CS5 CE1B CS6 (BS) (BS) (BS) CAS OE FRAME (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) I/O Data/port (Port) (Port) (Port) (Port) (Port) I/O Data/port (Port) (Port) (Port) (Port) (Port) Data/port (BS) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function Data/port Reset SRAM DRAM SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) 29 J5 D37 I/O 30 J1 VDDQ Power IO VDD (3.3 V) 31 J6 VSSQ Power IO GND (0 V) 32 J4 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port) 33 J2 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port) 34 K6 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port) 35 K1 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port) 36 K5 VDDQ Power IO VDD (3.3 V) 37 K3 VSSQ Power IO GND (0 V) 38 K4 D15 I/O Data 39 K2 D0 I/O Data A0 40 L6 D14 I/O Data A14 41 L1 D1 I/O Data A1 42 L5 VDDQ Power IO VDD (3.3 V) 43 L3 VSSQ Power IO GND (0 V) 44 M5 D13 I/O Data A13 45 M1 D2 I/O Data A2 46 L4 VDD Power Internal VDD (1.5 V) 47 L2 VSS Power Internal GND (0 V) 48 N5 D12 I/O Data A12 49 M3 D3 I/O Data A3 50 M4 VDDQ Power IO VDD (3.3 V) 51 N1 VSSQ Power IO GND (0 V) 52 N4 D11 I/O Data A11 53 M2 D4 I/O Data A4 54 R3 D10 I/O Data A10 55 N3 D5 I/O Data A5 56 P3 VDDQ Power IO VDD (3.3 V) 57 P1 VSSQ Power IO GND (0 V) 58 U1 D9 I/O Data A9 59 R1 D6 I/O Data A6 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 A15 Page 33 of 1076 Section 1 Overview Pin No. No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 60 T1 BACK/ BSREQ O Bus acknowledge/ bus request 61 R2 BREQ/ BSACK I Bus request/bus acknowledge 62 T3 D8 I/O Data A8 63 U2 D7 I/O Data A7 64 R4 CKE O Clock output enable 65 T5 VDDQ Power IO VDD (3.3 V) 66 T2 VSSQ Power IO GND (0 V) 67 R5 WE5/CAS5/ O DQM5 D47–D40 select signal WE5 CAS5 DQM5 68 P5 WE4/CAS4/ O DQM4 D39–D32 select signal WE4 CAS4 DQM4 69 U5 WE1/CAS1/ O DQM1 D15–D8 select signal WE1 CAS1 DQM1 70 P6 WE0/CAS0/ O DQM0 D7–D0 select signal WE0 CAS0 DQM0 71 R6 A17 O Address 72 P4 VDDQ Power IO VDD (3.3 V) 73 T6 VSSQ Power IO GND (0 V) 74 N6 A16 O Address 75 U6 A15 O Address 76 P7 VDD Power Internal VDD (1.5 V) 77 R7 VSS Power Internal GND (0 V) 78 M6 A14 O Address 79 T7 A13 O Address 80 N7 VDDQ Power IO VDD (3.3 V) 81 U7 VSSQ Power IO GND (0 V) 82 R8 A12 O Address 83 P8 A11 O Address 84 U8 A10 O Address 85 N8 VDDQ Power IO VDD (3.3 V) Page 34 of 1076 CKE WE1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function 86 T8 VSSQ Power IO GND (0 V) 87 M8 A9 O Address 88 R9 A8 O Address 89 N9 A7 O Address 90 U9 CKIO O Clock output 91 M9 VDDQ Power IO VDD (3.3 V) 92 P9 VSSQ Power IO GND (0 V) 93 T9 CKIO2 O CKIO* 94 M10 A6 O Address 95 U10 A5 O Address 96 N10 A4 O Address 97 R10 VDDQ Power IO VDD (3.3 V) 98 P10 VSSQ Power IO GND (0 V) 99 T10 Reset SRAM DRAM SDRAM PCMCIA MPX CKIO CKIO CKIO CKIO CKIO CKIO A3 O Address 100 M11 A2 O Address 101 U11 DRAK1 O DMAC1 request acknowledge 102 N11 DRAK0 O DMAC0 request acknowledge 103 R11 VDDQ Power IO VDD (3.3 V) 104 N12 VSSQ Power IO GND (0 V) 105 U12 CS3 O Chip select 3 CS3 (CS3) CS3 CS3 106 P11 CS2 O Chip select 2 CS2 (CS2) CS2 CS2 107 T11 VDD Power Internal VDD (1.5 V) 108 N13 VSS Power Internal GND (0 V) 109 R12 RAS O RAS RAS RAS 110 P12 RD/CASS/ FRAME O Read/CAS/ FRAME 111 U13 VDDQ Power IO VDD (3.3 V) 112 P13 VSSQ Power IO GND (0 V) 113 T12 RD/WR O 114 R15 WE2/CAS2/ O DQM2/ ICIORD R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 OE CAS OE FRAME Read/write RD/WR RD/WR RD/WR RD/WR D23–D16 select signal WE2 CAS2 DQM2 RD/WR ICIORD Page 35 of 1076 Section 1 Overview Pin No. No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 115 R13 WE3/CAS3/ O DQM3/ ICIOWR D31–D24 select signal WE3 CAS3 DQM3 116 R14 WE6/CAS6/ O DQM6 D55–D48 select signal WE6 CAS6 DQM6 117 U14 VDDQ Power IO VDD (3.3 V) 118 U17 VSSQ Power IO GND (0 V) 119 U15 WE7/CAS7/ O DQM7/REG D63–D56 select signal WE7 CAS7 DQM7 120 U16 D23 I/O Data A23 121 T13 D24 I/O Data A24 122 T15 D22 I/O Data A22 123 R16 RXD I SCI1 data input 124 T17 DREQ0 I Request from DMAC0 125 P17 DREQ1 I Request from DMAC1 126 P15 D25 I/O Data 127 N16 VDDQ Power IO VDD (3.3 V) 128 T16 VSSQ Power IO GND (0 V) 129 N15 D21 I/O Data 130 N14 D26 I/O Data 131 N17 D20 I/O Data 132 M14 D27 I/O Data 133 M15 VDDQ Power IO VDD (3.3 V) 134 P14 Power IO GND (0 V) VSSQ 135 M16 D19 I/O Data 136 M13 D28 I/O Data 137 M17 VDD Power Internal VDD (1.5 V) 138 L14 VSS Power Internal GND (0 V) 139 L15 D18 I/O Data 140 M12 D29 I/O Data 141 L16 VDDQ Power IO VDD (3.3 V) 142 L13 VSSQ Power IO GND (0 V) Page 36 of 1076 ICIOWR REG A25 A21 A20 A19 A18 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function 143 L17 D17 I/O Data 144 L12 D30 I/O Data 145 K15 D16 I/O Data 146 K14 D31 I/O Data 147 K17 VDDQ Power IO VDD (3.3 V) 148 K13 VSSQ Power IO GND (0 V) 149 K16 D55 I/O Data 150 K12 D56 I/O Data 151 J15 D54 I/O Data 152 J13 D57 I/O Data 153 J17 VDDQ Power IO VDD (3.3 V) 154 J12 VSSQ Power IO GND (0 V) 155 J14 D53 I/O D58 I/O Data 157 H12 D52 I/O Data 158 H17 D59 I/O Data 159 H13 VDDQ Power IO VDD (3.3 V) 160 H15 VSSQ Power IO GND (0 V) 161 H14 D51 I/O Data/port 162 H16 D60 I/O Data 163 G12 D50 I/O Data/port 164 G17 D61 I/O Data 165 G13 VDDQ Power IO VDD (3.3 V) 166 G15 VSSQ Power IO GND (0 V) 167 F13 D49 I/O Data/port 168 F17 D62 I/O Data 169 G14 VDD Power Internal VDD (1.5 V) 170 G16 VSS Power Internal GND (0 V) 171 E13 D48 I/O Data/port 172 F15 D63 I/O Data 173 F14 VDDQ Power IO VDD (3.3 V) 174 E17 VSSQ Power IO GND (0 V) Sep 24, 2013 SRAM DRAM SDRAM PCMCIA MPX A17 A16 Data 156 J16 R01UH0456EJ0702 Rev. 7.02 Reset (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) ACCSIZE1 (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Page 37 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Memory Interface Pin No. No. Pin Name 175 E14 176 F16 I/O Function RD/WR2 O RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR MD0/SCK I/O Mode/SCI1 clock MD0 SCK SCK SCK SCK SCK 177 C15 MD1/TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 178 E15 MD2/RXD2 I Mode/SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 179 D15 IRL0 I Interrupt 0 180 D17 IRL1 I Interrupt 1 181 A17 IRL2 I Interrupt 2 182 B17 IRL3 I Interrupt 3 183 C16 NMI I Nonmaskable interrupt 184 A15 XTAL2 O RTC crystal resonator pin 185 A16 EXTAL2 I RTC crystal resonator pin 186 A14 VSS-RTC Power RTC GND (0 V) 187 C14 VDD-RTC Power RTC VDD (3.3 V) 188 B13 CA I 189 C13 VDDQ Power IO VDD (3.3 V) 190 D13 CTS2 I/O SCIF data control (CTS) 191 A13 TCLK I/O RTC/TMU clock 192 D12 MD8/RTS2 I/O Mode/SCIF data MD8 control (RTS) RTS2 RTS2 RTS2 RTS2 RTS2 193 C12 VDDQ Power IO VDD (3.3 V) 194 D14 VSSQ Power IO GND (0 V) 195 B12 MD7/TXD I/O Mode/SCI1 data MD7 output TXD TXD TXD TXD TXD 196 E12 SCK2/ MRESET I SCIF clock/ manual reset SCK2 SCK2 SCK2 SCK2 197 A12 VDD Power Internal VDD (1.5 V) Page 38 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX Hardware standby request MRESET SCK2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. No. Pin Name I/O 198 D11 VSS Power Internal GND (0 V) 199 C11 A18 O Address 200 F12 A19 O Address 201 B11 VDDQ Power IO VDD (3.3 V) 202 E11 VSSQ Power IO GND (0 V) 203 A11 A20 O Function Reset SRAM DRAM SDRAM PCMCIA MPX Address 204 F11 A21 O Address 205 C10 A22 O Address 206 D10 A23 O Address 207 A10 VDDQ Power IO VDD (3.3 V) 208 E10 VSSQ Power IO GND (0 V) 209 B10 A24 O Address 210 F10 A25 O Address 211 C9 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 212 E9 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 213 A9 VDDQ Power IO VDD (3.3 V) 214 F9 VSSQ Power IO GND (0 V) 215 D9 MD5/RAS2 I/O Mode/RAS (DRAM) 216 B9 DACK0 O DMAC0 bus acknowledge 217 F8 DACK1 O DMAC1 bus acknowledge 218 A8 A0 O Address 219 E8 VDDQ Power IO VDD (3.3 V) 220 C8 VSSQ Power IO GND (0 V) 221 D8 A1 O Address 222 B8 STATUS0 O Status 223 F7 STATUS1 O Status 224 A7 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) 225 E7 VDDQ Power IO VDD (3.3 V) 226 C7 VSSQ Power IO GND (0 V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 MD5 MD6 RAS2 IOIS16 Page 39 of 1076 Section 1 Overview Pin No. No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function 227 E6 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 228 A6 TDO O Data out (H-UDI) 229 D7 VDD Power Internal VDD (1.5 V) 230 B7 VSS Power Internal GND (0 V) 231 E5 TMS I Mode (H-UDI) 232 C6 TCK I Clock (H-UDI) 233 D6 TDI I Data in (H-UDI) 234 A5 TRST I Reset (H-UDI) 235 D5 CKIO2ENB I 236 B6 VDD-PLL2 Power PLL2 VDD (3.3V) 237 C3 VSS-PLL2 Power PLL2 GND (0V) 238 C5 VDD-PLL1 Power PLL1 VDD (3.3V) 239 C4 VSS-PLL1 Power PLL1 GND (0V) 240 A4 VDD-CPG Power CPG VDD (3.3V) 241 A1 VSS-CPG Power CPG GND (0V) 242 A2 XTAL O Crystal resonator 243 A3 EXTAL I External clock/ crystal resonator 244 B3 NC-1 245 B4 NC-2 246 B5 NC-3 247 B14 NC-4 248 B15 NC-5 249 B16 NC-6 250 C1 NC-7 251 C17 NC-8 252 D1 NC-9 253 D2 NC-10 254 D16 NC-11 255 E16 NC-12 Page 40 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX CKIO2, RD2, RD/WR2 enable R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. No. Pin Name 256 M7 NC-13 257 N2 NC-14 258 P2 NC-15 259 P16 NC-16 260 R17 NC-17 261 T4 NC-18 262 T14 NC-19 263 U3 NC-20 264 U4 NC-21 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. * CKIO2 is not connected to PLL2. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 41 of 1076 Section 1 Overview 1.4.4 SH7750, SH7750S, SH7750R Group Pin Functions (292-Pin BGA) Table 1.5 Pin Functions Memory Interface Pin No. No. Pin Name I/O Function 1 B2 RDY I Bus ready 2 B1 RESET I Reset 3 C2 CS0 O Chip select 0 CS0 CS0 4 C1 CS1 O Chip select 1 CS1 CS1 5 D3 CS4 O Chip select 4 CS4 CS4 6 D2 CS5 O Chip select 5 CS5 7 D1 CS6 O Chip select 6 CS6 8 E3 BS O Bus start (BS) 9 E4 VSS Power GND (0 V) 10 E2 RD2 O 11 F3 VDDQ Power IO VDD (3.3 V) 12 F4 VSS Power GND (0 V) 13 E1 D47 I/O Data/port (Port) 14 F2 D32 I/O Data/port (Port) 15 G3 VDD Power Internal VDD 16 G4 VSS Power GND (0 V) 17 F1 D46 I/O Data/port 18 G2 D33 I/O Data/port 19 H3 VDDQ Power IO VDD (3.3 V) 20 H4 VSS Power GND (0 V) 21 G1 D45 I/O 22 H2 D34 I/O 23 H1 D44 I/O 24 J2 D35 I/O 25 J3 VDDQ Power IO VDD (3.3 V) 26 J4 VSS Power GND (0 V) 27 J1 D43 I/O 28 K2 D36 I/O 29 K1 D42 I/O Data/port Page 42 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX RDY RDY RDY RESET CE1A CS5 CE1B CS6 (BS) (BS) (BS) CAS OE FRAME (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) RD/CASS/ FRAME (BS) OE R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function Data/port Reset SRAM DRAM SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) 30 L3 D37 I/O 31 K3 VDDQ Power IO VDD (3.3 V) 32 K4 VSS Power GND (0 V) 33 L2 D41 I/O Data/port (Port) (Port) (Port) (Port) (Port) 34 L1 D38 I/O Data/port (Port) (Port) (Port) (Port) (Port) 35 M2 D40 I/O Data/port (Port) (Port) (Port) (Port) (Port) 36 M1 D39 I/O Data/port (Port) (Port) (Port) (Port) (Port) 37 M3 VDDQ Power IO VDD (3.3 V) 38 L4 VSS Power GND (0 V) 39 N2 D15 I/O Data A15 40 N1 D0 I/O Data A0 41 P2 D14 I/O Data A14 42 P1 D1 I/O Data A1 43 N3 VDDQ Power IO VDD (3.3 V) 44 M4 VSS Power GND (0 V) 45 R2 D13 I/O Data A13 46 R1 D2 I/O Data A2 47 P3 VDD Power Internal VDD 48 P4 VSS Power GND (0 V) 49 T2 D12 I/O Data A12 50 T1 D3 I/O Data A3 51 R3 VDDQ Power IO VDD (3.3 V) 52 R4 VSS Power GND (0 V) 53 U3 D11 I/O Data A11 54 U2 D4 I/O Data A4 55 U1 D10 I/O Data A10 56 V2 D5 I/O Data A5 57 T3 VDDQ Power IO VDD (3.3 V) 58 T4 VSS Power GND (0 V) 59 V1 D9 I/O Data A9 60 W2 D6 I/O Data A6 61 W1 BACK/ BSREQ O Bus acknowledge/ bus request R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 43 of 1076 Section 1 Overview Pin No. No. SH7750, SH7750S, SH7750R Group Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 62 Y1 BREQ/ BSACK I Bus request/ bus acknowledge 63 Y2 D8 I/O Data A8 64 V3 D7 I/O Data A7 65 W3 CKE O Clock output enable 66 V5 VDDQ Power IO VDD (3.3 V) 67 U5 VSS Power GND (0 V) 68 Y3 WE5/CAS5/ O DQM5 D47–D40 select signal WE5 CAS5 DQM5 69 V4 WE4/CAS4/ O DQM4 D39–D32 select signal WE4 CAS4 DQM4 70 W4 WE1/CAS1/ O DQM1 D15–D8 select signal WE1 CAS1 DQM1 71 Y4 WE0/CAS0/ O DQM0 D7–D0 select signal WE0 CAS0 DQM0 72 W5 A17 O Address 73 V6 VDDQ Power IO VDD (3.3 V) 74 U6 VSS Power GND (0 V) 75 Y5 A16 O Address 76 W6 A15 O Address 77 V7 VDD Power Internal VDD 78 U7 VSS Power GND (0 V) 79 Y6 A14 O Address 80 W7 A13 O Address 81 V8 VDDQ Power IO VDD (3.3 V) 82 U8 VSS Power GND (0 V) 83 U4 VSS Power GND (0 V) 84 Y7 A12 O Address 85 W8 A11 O Address 86 Y8 A10 O Address 87 V9 VDDQ Power IO VDD (3.3 V) 88 U9 VSS Power GND (0 V) 89 W9 A9 O Address 90 Y9 A8 O Address Page 44 of 1076 CKE WE1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function 91 W10 A7 O Address 92 Y10 CKIO O Clock output 93 V10 VDDQ Power IO VDD (3.3 V) 94 U10 VSS Power GND (0 V) 95 V11 CKIO2 O CKIO* 96 W11 A6 O Address 97 Y11 A5 O Address 98 W12 A4 O Address 99 V12 VDDQ Power IO VDD (3.3 V) 100 U12 VSS Power GND (0 V) 101 Y12 Reset SRAM DRAM SDRAM PCMCIA MPX CKIO CKIO CKIO CKIO CKIO CKIO A3 O Address 102 W13 A2 O Address 103 Y13 DRAK1 O DMAC1 request acknowledge 104 W14 DRAK0 O DMAC0 request acknowledge 105 V13 VDDQ Power IO VDD (3.3 V) 106 U13 VSS Power GND (0 V) 107 Y14 CS3 O Chip select 3 CS3 (CS3) CS3 CS3 108 W15 CS2 O Chip select 2 CS2 (CS2) CS2 CS2 RAS RAS 109 V14 VDD Power Internal VDD 110 U14 VSS Power GND (0 V) 111 Y15 RAS O RAS O Read/CAS/ FRAME 112 W16 RD/CASS/ FRAME 113 V15 VDDQ Power IO VDD (3.3 V) 114 U15 VSS Power GND (0 V) 115 Y16 RD/WR O 116 V17 OE CAS OE FRAME Read/write RD/WR RD/WR RD/WR RD/WR WE2/CAS2/ O DQM2/ ICIORD D23–D16 select signal WE2 CAS2 DQM2 ICIORD 117 W17 WE3/CAS3/ O DQM3/ ICIOWR D31–D24 select signal WE3 CAS3 DQM3 ICIOWR WE6/CAS6/ O DQM6 D55–D48 select signal WE6 CAS6 DQM6 118 Y17 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 RD/WR Page 45 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Memory Interface Pin No. No. Pin Name 119 V16 VDDQ Power IO VDD (3.3 V) 120 U16 VSS Power GND (0 V) 121 V18 WE7/CAS7/ O DQM7/REG I/O Function D63–D56 select signal Reset SRAM DRAM SDRAM PCMCIA MPX WE7 CAS7 DQM7 REG 122 W18 D23 I/O Data A23 123 Y18 D24 I/O Data A24 124 Y19 D22 I/O Data A22 125 Y20 RXD I SCI data input 126 W19 DREQ0 I Request from DMAC0 127 W20 DREQ1 I Request from DMAC1 128 V19 D25 I/O Data 129 T18 VDDQ Power IO VDD (3.3 V) 130 T17 VSS Power GND (0 V) 131 V20 D21 I/O Data 132 U18 D26 I/O Data 133 U19 D20 I/O Data 134 U20 D27 I/O Data 135 R18 VDDQ Power IO VDD (3.3 V) 136 R17 VSS Power GND (0 V) 137 T19 D19 I/O Data 138 T20 D28 I/O Data 139 P18 VDD Power Internal VDD 140 P17 VSS Power GND (0 V) 141 R19 D18 I/O Data 142 R20 D29 I/O Data 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSS Power GND (0 V) 145 P19 D17 I/O Data 146 P20 D30 I/O Data 147 N19 D16 I/O Data 148 N20 D31 I/O Data 149 M18 VDDQ Page 46 of 1076 A25 A21 A20 A19 A18 A17 A16 Power IO VDD (3.3 V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function 150 M17 VSS Power GND (0 V) 151 M19 D55 I/O Data 152 M20 D56 I/O Data 153 L19 D54 I/O Data 154 L20 D57 I/O Data 155 L18 VDDQ Power IO VDD (3.3 V) 156 L17 VSS Power GND (0 V) 157 K18 D53 I/O Data 158 K19 D58 I/O Data 159 K20 D52 I/O Data 160 J19 D59 I/O Data 161 J18 VDDQ Power IO VDD (3.3 V) 162 K17 VSS Power GND (0 V) 163 J20 D51 I/O Data/port 164 H19 D60 I/O Data 165 H20 D50 I/O Data/port 166 G19 D61 I/O Data 167 H18 VDDQ Power IO VDD (3.3 V) 168 J17 VSS Power GND (0 V) 169 G20 D49 I/O Data/port 170 F19 I/O Data D62 171 G18 VDD Power Internal VDD 172 G17 VSS Power GND (0 V) 173 F20 D48 I/O Data/port 174 E18 D63 I/O Data 175 F18 VDDQ Power IO VDD (3.3 V) 176 F17 VSS Power GND (0 V) 177 E17 VSS Power GND (0 V) 178 E19 RD/WR2 O Reset RD/WR SRAM DRAM SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) ACCSIZE1 (Port) (Port) (Port) (Port) (Port) ACCSIZE2 RD/WR RD/WR RD/WR RD/WR RD/WR 179 E20 MD0/SCK I/O Mode/SCI Clock MD0 SCK SCK SCK SCK SCK 180 D18 MD1/TXD2 I/O Mode/SCIF data MD1 output TXD2 TXD2 TXD2 TXD2 TXD2 181 D19 MD2/RXD2 I Mode/SCIF data MD2 input RXD2 RXD2 RXD2 RXD2 RXD2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 47 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Memory Interface Pin No. No. Pin Name I/O Function 182 D20 IRL0 I Interrupt 0 183 C19 IRL1 I Interrupt 1 184 C20 IRL2 I Interrupt 2 185 B19 IRL3 I Interrupt 3 186 B20 NMI I Nonmaskable interrupt 187 A20 XTAL2 O RTC crystal resonator pin 188 A19 EXTAL2 I RTC crystal resonator pin 189 B18 VSS-RTC Power RTC GND (0 V) 190 A18 VDD-RTC Power RTC VDD (3.3 V) 191 D17 CA I 192 C17 VDDQ Power IO VDD (3.3 V) 193 C18 VSS-RTC Power RTC GND (0 V) 194 B17 CTS2 I/O SCIF data control (CTS) 195 A17 TCLK I/O RTC/TMU clock 196 C16 MD8/RTS2 I/O Mode/SCIF data MD8 control (RTS) 197 C15 VDDQ Power IO VDD (3.3 V) 198 D15 VSS Power GND (0 V) 199 B16 MD7/TXD I/O Mode/SCI1 data MD7 output 200 A16 SCK2/ MRESET I SCIF clock/ manual reset 201 C14 VDD Power Internal VDD 202 D14 VSS Power GND (0 V) 203 B15 A18 O Address 204 A15 A19 O Address 205 C13 VDDQ Power IO VDD (3.3 V) 206 D13 VSS Power GND (0 V) 207 B14 A20 O Address 208 A14 A21 O Address 209 B13 A22 O Address Page 48 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX RTS2 RTS2 RTS2 RTS2 RTS2 TXD TXD TXD TXD TXD SCK2 SCK2 SCK2 SCK2 Hardware standby MRESET SCK2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 1 Overview Memory Interface Pin No. No. Pin Name I/O Function 210 A13 A23 O Address 211 C12 VDDQ Power IO VDD (3.3 V) 212 D12 VSS Power GND (0 V) 213 B12 A24 O Address 214 A12 A25 O Address 215 B11 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 216 A11 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 217 C11 VDDQ Power IO VDD (3.3 V) 218 D11 VSS Power GND (0 V) 219 C10 MD5/RAS2 I/O Mode/RAS (DRAM) 220 B10 DACK0 O DMAC0 bus acknowledge 221 A10 DACK1 O DMAC1 acknowledge 222 B9 A0 O Address 223 C8 VDDQ Power IO VDD (3.3 V) 224 D8 VSS Power GND (0 V) 225 A9 A1 O Address 226 B8 STATUS0 O Status 227 A8 STATUS1 O Status 228 B7 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSS Power GND (0 V) 231 A7 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 232 C6 TDO O Data out (H-UDI) 233 C7 VDD Power Internal VDD 234 D7 VSS Power GND (0 V) 235 B6 TMS I Mode (H-UDI) 236 A6 TCK I Clock (H-UDI) 237 C5 TDI I Data in (H-UDI) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Reset MD5 MD6 SRAM DRAM SDRAM PCMCIA MPX RAS2 IOIS16 Page 49 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Memory Interface Pin No. No. Pin Name I/O Function 238 B5 TRST I Reset (H-UDI) 239 C4 CKIO2ENB I 240 D6 VSS Power GND (0 V) 241 A5 VDD-PLL2 Power PLL2 VDD (3.3 V) 242 B4 VSS-PLL2 Power PLL2 GND (0 V) 243 A4 VDD-PLL1 Power PLL1 VDD (3.3 V) 244 C3 VSS-PLL1 Power PLL1 GND (0 V) 245 B3 VDD-CPG Power CPG VDD (3.3 V) 246 A3 VSS-CPG Power CPG GND (0 V) 247 A2 XTAL O Crystal resonator 248 A1 EXTAL I External clock/ crystal resonator 249 N4 VSS Power GND (0 V) 250 U11 VSS Power GND (0 V) 251 U17 VSS Power GND (0 V) 252 H17 VSS Power GND (0 V) 253 D16 VSS Power GND (0 V) 254 D10 VSS Power GND (0 V) 255 D5 VSS Power GND (0 V) 256 D4 VSS Power GND (0 V) 257 H8 VSS Power GND (0 V) 258 J8 VSS Power GND (0 V) 259 K8 VSS Power GND (0 V) 260 L8 VSS Power GND (0 V) 261 M8 VSS Power GND (0 V) 262 N8 VSS Power GND (0 V) 263 N9 VSS Power GND (0 V) 264 N10 VSS Power GND (0 V) 265 N11 VSS Power GND (0 V) 266 N12 VSS Power GND (0 V) 267 N13 VSS Power GND (0 V) 268 M13 VSS Power GND (0 V) Page 50 of 1076 Reset SRAM DRAM SDRAM PCMCIA MPX CKIO2, RD2, RD/WR2 enable R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Pin No. No. Section 1 Overview Memory Interface Pin Name I/O Function 269 L13 VSS Power GND (0 V) 270 K13 VSS Power GND (0 V) 271 J13 VSS Power GND (0 V) 272 H13 VSS Power GND (0 V) 273 H12 VSS Power GND (0 V) 274 H11 VSS Power GND (0 V) 275 H10 VSS Power GND (0 V) 276 H9 VSS Power GND (0 V) 277 J9 VSS Power GND (0 V) 278 K9 VSS Power GND (0 V) 279 L9 VSS Power GND (0 V) 280 M9 VSS Power GND (0 V) 281 M10 VSS Power GND (0 V) 282 M11 VSS Power GND (0 V) 283 M12 VSS Power GND (0 V) 284 L12 VSS Power GND (0 V) 285 K12 VSS Power GND (0 V) 286 J12 VSS Power GND (0 V) 287 J11 VSS Power GND (0 V) 288 J10 VSS Power GND (0 V) 289 K10 VSS Power GND (0 V) 290 L10 VSS Power GND (0 V) 291 L11 VSS Power GND (0 V) 292 K11 VSS Power GND (0 V) Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 51 of 1076 Section 1 Overview SH7750, SH7750S, SH7750R Group Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. * CKIO2 is not connected to PLL2. Page 52 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 2 Programming Model Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH-4 are shown in figure 2.1. 7 0 Byte (8 bits) 15 0 Word (16 bits) 0 31 Longword (32 bits) 31 30 Single-precision floating-point (32 bits) s exp 63 62 Double-precision floating-point (64 bits) s 51 exp 0 22 fraction 0 fraction Figure 2.1 Data Formats R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 53 of 1076 Section 2 Programming Model 2.2 Register Configuration 2.2.1 Privileged Mode and Banks SH7750, SH7750S, SH7750R Group Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode. Page 54 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 2 Programming Model Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, R8–R15 Undefined Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC, SGR, DBR Undefined VBR H'00000000 MACH, MACL, PR, FPUL Undefined PC H'A0000000 FPSCR H'00040001 FR0–FR15, XF0–XF15 Undefined System registers Floating-point registers Note: * Initialized by a power-on reset and manual reset. The register configuration in each processor is shown in figure 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 55 of 1076 Section 2 Programming Model 31 SH7750, SH7750S, SH7750R Group 0 31 0 31 0 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SR SSR SR SSR GBR MACH MACL PR GBR MACH MACL PR VBR GBR MACH MACL PR VBR PC PC SPC PC SPC SGR SGR DBR (a) Register configuration in user mode R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) DBR R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processor Mode Page 56 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 2.2.2 Section 2 Programming Model General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode. The SH-4 has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below. • R0_BANK0–R7_BANK0 In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0. In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when SR.RB = 0. • R0_BANK1–R7_BANK1 In user mode, R0_BANK1–R7_BANK1 cannot be accessed. In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 57 of 1076 Section 2 Programming Model SH7750, SH7750S, SH7750R Group SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Programming Note: As the user's R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0–R7 (R0_BANK0–R7_BANK0). After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are undefined. Page 58 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 2.2.3 Section 2 Programming Model Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4). • Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0, FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0, FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0, FPR15_BANK0 FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1, FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1, FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1, FPR15_BANK1 • Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0. When FPSCR.FR = 1, FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1. • Double-precision floating-point registers or single-precision floating-point register pairs, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} • Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} • Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0–XF15 are assigned to FPR0_BANK1–FPR15_BANK1. When FPSCR.FR = 1, XF0–XF15 are assigned to FPR0_BANK0–FPR15_BANK0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 59 of 1076 Section 2 Programming Model SH7750, SH7750S, SH7750R Group • Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = Page 60 of 1076 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 2 Programming Model FPSCR.FR = 0 FV0 FV4 FV8 FV12 XMTRX FPSCR.FR = 1 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 DR0 XD0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 DR0 FV0 DR2 DR4 FV4 DR6 DR8 FV8 DR10 DR12 FV12 DR14 Figure 2.4 Floating-Point Registers Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 61 of 1076 Section 2 Programming Model 2.2.4 SH7750, SH7750S, SH7750R Group Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 — MD RB BL 16 15 14 — FD 10 — 9 8 M Q 7 4 IMASK 3 2 — 1 0 S T Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • MD: Processor mode MD = 0: User mode (some instructions cannot be executed, and some resources cannot be accessed) MD = 1: Privileged mode • RB: General register bank specifier in privileged mode (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1– R7_BANK1 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.) RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0– R7_BANK0 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.) • BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state. • FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F*** instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR) • M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions. • IMASK: Interrupt mask level External interrupts of a same level or a lower level than IMASK are masked. • S: Specifies a saturation operation for a MAC instruction. • T: True/false condition or carry/borrow bit Page 62 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 2 Programming Model Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exceptions. Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. 2.2.5 System Registers Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction or MUL operation result. Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine return instruction (RTS). Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the instruction fetch address. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 63 of 1076 Section 2 Programming Model SH7750, SH7750S, SH7750R Group Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 22 21 20 19 18 17 — FR SZ PR DN 12 11 Cause 7 6 Enable 2 1 Flag 0 RM Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1– FPR15_BANK1 are assigned to XF0–XF15. FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1– FPR15_BANK1 are assigned to FR0–FR15. • SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits). • PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.) • DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero. • Cause: FPU exception cause field • Enable: FPU exception enable field • Flag: FPU exception flag field FPU Error (E) Invalid Operation (V) Division by Zero (Z) Overflow (O) Underflow Inexact (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Page 64 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 2 Programming Model When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared. • RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved • Bits 22 to 31: Reserved Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer between FPU registers and CPU registers is carried out via the FPUL register. Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for double-precision floating-point load or store operations. In little endian mode, two 32-bit data size moves must be executed, with SZ = 0, to load or store a double-precision floating-point number. 2.3 Memory-Mapped Registers Appendix A, Address List shows the control registers mapped to memory. The control registers are double-mapped to the following two memory areas. All registers have two addresses. H'1C00 0000–H'1FFF FFFF H'FC00 0000–H'FFFF FFFF These two areas are used as follows. • H'1C00 0000–H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding filed of the TLB enables access to a memorymapped register. Accessing this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000–H'FFFF FFFF Access to area H'FF00 0000–H'FFFF FFFF in user mode will cause an address error. Memorymapped registers can be referenced in user mode by means of access that involves address translation. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 65 of 1076 Section 2 Programming Model SH7750, SH7750S, SH7750R Group Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. 2.4 Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 Longword 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.5. Page 66 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group A+1 A 31 7 Section 2 Programming Model A+2 23 15 07 07 A+3 A + 11 A + 10 A + 9 7 0 31 07 0 7 0 15 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Word 0 31 Big endian 15 07 07 0 07 0 0 15 Word 1 0 A+8 7 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 Word 1 Longword 23 31 0 Word 0 Longword 0 Address A + 4 Address A Little endian Figure 2.5 Data Formats In Memory Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The SH-4 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The reset state is entered when the RESET pin goes low. The CPU enters the power-on reset state if the MRESET pin is high, and the manual reset state if the MRESET pin is low. For more information on resets, see section 5, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus state controller (BSC) is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 67 of 1076 Section 2 Programming Model SH7750, SH7750S, SH7750R Group contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. From any state when RESET = 0 and MRESET = 1 RESET = 0 and MRESET = 0 Power-on reset state Manual reset state RESET = 0, MRESET = 1 RESET = 1, MRESET = 1 Reset state RESET = 1, MRESET = 0 Exception-handling state Bus request Bus request clearance Interrupt Exception interrupt Bus-released state Bus request Bus request Interrupt End of exception transition processing Bus request clearance Bus request clearance Program execution state SLEEP instruction with STBY bit cleared Sleep mode SLEEP instruction with STBY bit set Standby mode Power-down state Figure 2.6 Processor State Transitions Page 68 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 2.7 Section 2 Programming Model Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which can only be accessed in privileged mode. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 69 of 1076 Section 2 Programming Model Page 70 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH-4. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). The SH-4 has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 Kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 Role of the MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 3.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 71 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided in hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails—that is, if an exception occurs—switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 Kbytes in size). In the following descriptions, the address space in virtual memory in the SH-4 is referred to as virtual address space, and the address space in physical memory as physical address space. Page 72 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Physical memory Section 3 Memory Management Unit (MMU) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 (1) Process 1 Physical memory (2) Process 1 Virtual memory MMU Physical memory Process 2 Process 2 Process 3 Process 3 (3) (4) Figure 3.1 Role of the MMU R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 73 of 1076 Section 3 Memory Management Unit (MMU) 3.1.3 SH7750, SH7750S, SH7750R Group Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbreviation R/W Initial 1 Value* P4 Address*2 Page table entry high register PTEH R/W Undefined H'FF00 0000 H'1F00 0000 32 Page table entry low register PTEL R/W Undefined H'FF00 0004 H'1F00 0004 32 Page table entry assistance register PTEA R/W Undefined H'FF00 0034 H'1F00 0034 32 Translation table base register TTB R/W Undefined H'FF00 0008 H'1F00 0008 32 TLB exception address register TEA R/W Undefined H'FF00 000C H'1F00 000C 32 MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32 Name Area 7 Address*2 Acces s Size Notes: 1. The initial value is the value after a power-on reset or manual reset. 2. This is the address when using the virtual/physical address space P4 area. When making an access from physical address space area 7 using the TLB, the upper 3 bits of the address are ignored. 3.1.4 Caution Operation is not guaranteed if an area designated as a reserved area in this manual is accessed. Page 74 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.2 Section 3 Memory Management Unit (MMU) Register Descriptions There are six MMU-related registers. 1. PTEH 31 10 9 VPN 8 7 0 — — ASID 2. PTEL 31 30 29 28 10 9 PPN — — — 8 7 — V SZ 6 5 PR 4 3 2 1 0 SZ C D SH WT 3. PTEA 31 4 3 2 TC 0 SA 4. TTB 31 0 TTB 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. MMUCR 31 26 25 24 23 LRUI — — 18 17 16 15 URB — — 10 9 URC 8 7 6 5 4 3 2 1 0 SV — — — — — TI — AT SQMD Note: — indicates a reserved bit: the write value must be 0, and a read will return 0. Figure 3.2 MMU-Related Registers R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 75 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. A branch to the P0, P3, or U0 area which uses the updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions after the PTEH update instruction. 2. Page table entry low register (PTEL): Longword access to PTEL can be performed from H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued. 3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEL is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing access from the CPU in the SH7750S and SH7750R with MMUCR.AT = 0, access is always performed using the values of the SA and TC bits in this register. In the SH7750, it is not possible to access a PCMCIA interface area with MMUCR.AT = 0. In this LSI, access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The contents of this register are not changed unless a software directive is issued. 4. Translation table base register (TTB): Longword access to TTB can be performed from H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be freely used by software. 5. TLB exception address register (TEA): Longword access to TEA can be performed from H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software. 6. MMU control register (MMUCR): MMUCR contains the following bits: LRUI: Least recently used ITLB URB: UTLB replace boundary Page 76 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group URC: SQMD: SV: TI: AT: Section 3 Memory Management Unit (MMU) UTLB replace counter Store queue mode bit Single virtual mode bit TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware. • LRUI: Least recently used ITLB. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table means that updating is not performed. LRUI [5] [4] [3] [2] [1] [0] When ITLB entry 0 is used 0 0 0 — — — When ITLB entry 1 is used 1 — — 0 0 — When ITLB entry 2 is used — 1 — 1 — 0 When ITLB entry 3 is used — — 1 — 1 1 Other than the above — — — — — — When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. An asterisk in this table means “don't care”. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 77 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group LRUI [5] [4] [3] [2] [1] [0] ITLB entry 0 is updated 1 1 1 * * * ITLB entry 1 is updated 0 * * 1 1 * ITLB entry 2 is updated * 0 * 0 * 1 ITLB entry 3 is updated * * 0 * 0 0 Other than the above Setting prohibited Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. • URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. • URC: UTLB replace counter. Random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a value is written to URC by software which results in the condition URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction. • SQMD: Store queue mode bit. Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access) • SV: Single virtual mode bit. Bit that switches between single virtual memory mode and multiple virtual memory mode. 0: Multiple virtual memory mode 1: Single virtual memory mode When this bit is changed, ensure that 1 is also written to the TI bit. • TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always returns 0 when read. • AT: Address translation enable bit. Specifies MMU enabling or disabling. 0: MMU disabled 1: MMU enabled Page 78 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. 3.3 Address Space 3.3.1 Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error. External memory space H'0000 0000 P0 area Cacheable H'8000 0000 H'A000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 U0 area Cacheable H'8000 0000 P1 area Cacheable P2 area Non-cacheable Address error H'C000 0000 P3 area Cacheable H'E000 0000 P4 area Non-cacheable Store queue area Privileged mode User mode H'FFFF FFFF Address error H'E000 0000 H'E400 0000 H'FFFF FFFF Figure 3.3 Physical Address Space (MMUCR.AT = 0) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 79 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the values of the SA and TC bits set in the PTEA register. The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR). When the cache is used, with the exception of the P1 area, switching between the copy-back method and the write-through method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3 bits of an address gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. Page 80 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group H'E000 0000 Section 3 Memory Management Unit (MMU) Store queue H'E400 0000 Reserved area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2 H'F800 0000 Reserved area H'FC00 0000 Control register area Figure 3.4 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 4.5.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 4.5.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 3.7.1, ITLB Address Array. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 81 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 4.5.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 4.5.4, OC Data Array. The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 3.7.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2. The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see appendix A, Address List. 3.3.2 External Memory Space The SH-4 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC). H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area) Figure 3.5 External Memory Space Page 82 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.3.3 Section 3 Memory Management Unit (MMU) Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in external memory space is accessed using virtual memory space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical memory space. Virtual memory space is illustrated in figure 3.6. 256 External memory space 256 Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 U0 area Cacheable Address translation possible Area 6 Area 7 P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible Address error P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Store queue area Privileged mode User mode Address error Figure 3.6 Virtual Address Space (MMUCR.AT = 1) In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 83 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Here, access to the PCMCIA interface area by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the TLB enable bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to the control register area. This enables on-chip peripheral module control registers to be accessed from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for physical memory space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces. For details, see section 4.7, Store Queues. 3.3.4 On-Chip RAM Space In the SH-4, half of the instruction cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. Page 84 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.3.5 Section 3 Memory Management Unit (MMU) Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In the SH-4, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception routine. In the TLB miss exception routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 3.4.3, Address Translation Method). 3.3.7 Address Space Identifier (ASID) In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish between processes running simultaneously while sharing the virtual address space. Software can set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 85 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group Note: In single virtual memory mode, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. 3.4 TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 3.7 shows the overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure 3.8 shows the relationship between the address format and page size. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Figure 3.7 UTLB Configuration Page 86 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) • 1-Kbyte page Virtual address 10 9 31 VPN 0 Physical address 10 9 28 Offset PPN 0 Offset • 4-Kbyte page Virtual address 12 11 31 VPN 0 Physical address 12 11 28 Offset PPN 0 Offset • 64-Kbyte page Virtual address 16 15 31 VPN 0 Physical address 16 15 28 Offset PPN 0 Offset • 1-Mbyte page Virtual address 20 19 31 VPN 0 Offset Physical address 20 19 28 PPN 0 Offset Figure 3.8 Relationship between Page Size and Address Format • VPN: Virtual page number For 1-Kbyte page: upper 22 bits of virtual address For 4-Kbyte page: upper 20 bits of virtual address For 64-Kbyte page: upper 16 bits of virtual address For 1-Mbyte page: upper 12 bits of virtual address • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 87 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. • PPN: Physical page number Upper 22 bits of the physical address. With a 1-Kbyte page, PPN bits [28:10] are valid. With a 4-Kbyte page, PPN bits [28:12] are valid. With a 64-Kbyte page, PPN bits [28:16] are valid. With a 1-Mbyte page, PPN bits [28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 3.5.5, Avoiding Synonym Problems). • PR: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read only, in privileged mode 01: Can be read and written in privileged mode 10: Can be read only, in privileged or user mode 11: Can be read and written in privileged mode or user mode Page 88 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0. • SA: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to IOIS16 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space • TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2–A5W0) and PCR (A5PCW1–A5PCW0, A5TED2–A5TED0, A5TEH2– A5TEH0) are used 1: WCR2 (A6W2–A6W0) and PCR (A6PCW1–A6PCW0, A6TED2–A6TED0, A6TEH2– A6TEH0) are used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 89 of 1076 Section 3 Memory Management Unit (MMU) 3.4.2 SH7750, SH7750S, SH7750R Group Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries. The address translation information is almost the same as that in the UTLB, but with the following differences: 1. D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Figure 3.9 ITLB Configuration 3.4.3 Address Translation Method Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB. Page 90 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) Data access to virtual address (VA) VA is in P4 area VA is in P2 area On-chip I/O access 0 VA is in P1 area VA is in P0, U0, or P3 area No CCR.OCE? MMUCR.AT = 1 1 0 Yes CCR.CB? CCR.WT? 0 1 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) No Yes No VPNs match and ASIDs match and V=1 No VPNs match and V = 1 Yes Yes No Only one entry matches Data TLB miss exception Yes SR.MD? 0 (User) 1 (Privileged) PR? 00 or 01 W Data TLB multiple hit exception Memory access 11 10 R/W? R/W? R R 01 or 11 W W D? 0 Data TLB protection violation exception 1 00 or 10 R/W? R/W? R R W Data TLB protection violation exception Initial page write exception C=1 and CCR.OCE = 1 No Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode Memory access (Non-cacheable) Figure 3.10 Flowchart of Memory Access Using UTLB R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 91 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group Instruction access to virtual address (VA) VA is in P4 area Access prohibited VA is in P2 area VA is in P1 area VA is in P0, U0, or P3 area No 0 CCR.ICE? MMUCR.AT = 1 1 Yes No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No No VPNs match and V = 1 VPNs match and ASIDs match and V=1 Yes Only one entry matches Hardware ITLB miss handling Search UTLB Yes Match? Yes No Yes Record in ITLB No SR.MD? Instruction TLB miss exception 0 (User) 1 (Privileged) 0 PR? Instruction TLB multiple hit exception 1 Instruction TLB protection violation exception C=1 and CCR.ICE = 1 No Yes Cache access Memory access (Non-cacheable) Figure 3.11 Flowchart of Memory Access Using ITLB Page 92 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.5 MMU Functions 3.5.1 MMU Hardware Management Section 3 Memory Management Unit (MMU) The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB, and if the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with MMUCR.LRUI. 3.5.2 MMU Software Management Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 3.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH-4 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 93 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group MMUCR 31 26 25 24 23 LRUI — 18 17 16 15 URB — 10 9 8 7 URC SV 3 2 1 0 — TI — AT SQMD Entry specification PTEL 31 PTEH 31 10 9 8 7 VPN — 10 9 8 7 6 5 4 3 2 1 0 29 28 — PPN — V SZ PR SZ C D SHWT 0 PTEA ASID 31 4 3 2 — TC 0 SA Write Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC UTLB Figure 3.12 Operation of LDTLB Instruction 3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH-4 searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. Page 94 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.5.5 Section 3 Memory Management Unit (MMU) Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB or instruction cache. In the SH-4, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-Kbyte page, and bits [13:12] of the virtual address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after translation may differ from bits [13:10] of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. 1. When address translation information whereby a number of 1-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10] values are the same. 2. When address translation information whereby a number of 4-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12] values are the same. 3. Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. 4. Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above restrictions apply to VPN [25]. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 95 of 1076 Section 3 Memory Management Unit (MMU) 3.6 SH7750, SH7750S, SH7750R Group MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 Instruction TLB Multiple Hit Exception An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Page 96 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'040 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 97 of 1076 Section 3 Memory Management Unit (MMU) 3.6.3 SH7750, SH7750S, SH7750R Group Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'0A0 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Page 98 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 99 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. Page 100 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'080 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 101 of 1076 Section 3 Memory Management Unit (MMU) SH7750, SH7750S, SH7750R Group Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. A branch to an area other than the P2 area should be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in physical memory space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. Page 102 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.7.1 Section 3 Memory Management Unit (MMU) ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field bits [1:0]. In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0]. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 10 9 8 7 31 24 23 Address field 1 1 1 1 0 0 1 0 0 E 31 10 9 8 7 Data field VPN Legend: VPN: Virtual page number V: Validity bit E: Entry V 0 ASID ASID: Address space identifier : Reserved bits (0 write value, undefined read value) Figure 3.13 Memory-Mapped ITLB Address Array R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 103 of 1076 Section 3 Memory Management Unit (MMU) 3.7.2 SH7750, SH7750S, SH7750R Group ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry is selected by bits [9:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit [6], C by bit [3], and SH by bit [1]. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 10 9 8 7 31 24 23 Address field 1 1 1 1 0 0 1 1 0 E 31 30 29 28 10 9 8 7 6 5 4 3 2 1 0 Data field PPN Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits 0 V C PR SZ PR: C: SH: : SH Protection key data Cacheability bit Share status bit Reserved bits (0 write value, undefined read value) Figure 3.14 Memory-Mapped ITLB Data Array 1 Page 104 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 3.7.3 Section 3 Memory Management Unit (MMU) ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry is selected by bits [9:8]. In the data field, SA is indicated by bits [2:0], and TC by bit [3]. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 1 1 1 10 9 8 7 0 E 31 4 3 2 0 Data field SA Legend: TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.15 Memory-Mapped ITLB Data Array 2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 105 of 1076 Section 3 Memory Management Unit (MMU) 3.7.4 SH7750, SH7750S, SH7750R Group UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0]. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception results. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB. Page 106 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 3 Memory Management Unit (MMU) 31 24 23 Address field 1 1 1 1 0 1 1 0 10 9 8 7 VPN Legend: VPN: Virtual page number Validity bit V: Entry E: Dirty bit D: 2 1 0 A E 31 30 29 28 Data field 8 7 14 13 D V 0 ASID ASID: Address space identifier Association bit A: Reserved bits (0 write value, undefined read value) : Figure 3.16 Memory-Mapped UTLB Address Array 3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry is selected by bits [13:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0]. The following two kinds of operation can be used on UTLB data array 1: 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 107 of 1076 Section 3 Memory Management Unit (MMU) 31 SH7750, SH7750S, SH7750R Group 24 23 14 13 Address field 1 1 1 1 0 1 1 1 0 10 9 8 7 6 5 4 3 2 1 0 PPN Legend: PPN: Physical page number Validity bit V: Entry E: SZ: Page size bits Dirty bit D: 0 E 31 30 29 28 Data field 8 7 V PR C D SZ SH WT PR: Protection key data C: Cacheability bit SH: Share status bit WT: Write-through bit : Reserved bits (0 write value, undefined read value) Figure 3.17 Memory-Mapped UTLB Data Array 1 3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry is selected by bits [13:8]. In the data field, TC is indicated by bit [3], and SA by bits [2:0]. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. Page 108 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 31 Section 3 Memory Management Unit (MMU) 24 23 Address field 1 1 1 1 0 1 1 1 1 14 13 8 7 0 E 31 4 3 2 Data field 0 SA Legend: TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.18 Memory-Mapped UTLB Data Array 2 3.8 Usage Notes 1. Address Space Identifier (ASID) in Single Virtual Memory Mode Refer to the note in 3.3.7, Address Space Identifier (ASID). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 109 of 1076 Section 3 Memory Management Unit (MMU) Page 110 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches Section 4 Caches 4.1 Overview 4.1.1 Features An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1 The SH7750R has an on-chip 16-Kbyte instruction cache (IC) for instructions and 32-Kbyte operand cache (OC) for data. Half of the memory of the operand cache (16 Kbytes) may alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset. For high-speed writing to external memories, this LSI supports 32 bytes × 2 of store queues (SQ). Table 4.3 lists the features of these SQs. Table 4.1 Cache Features (SH7750, SH7750S) Item Instruction Cache Operand Cache Capacity 8-Kbyte cache 16-Kbyte cache or 8-Kbyte cache + 8-Kbyte RAM Type Direct mapping Direct mapping Line size 32 bytes 32 bytes Entries 256 512 Write method R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Copy-back/write-through selectable Page 111 of 1076 Section 4 Caches Table 4.2 SH7750, SH7750S, SH7750R Group Cache Features (SH7750R) Item Instruction Cache Operand Cache Capacity 16-Kbyte cache 32-Kbyte cache or 16-Kbyte cache + 16-Kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entries/way 512 entries/way Write method Replacement method Table 4.3 Copy-back/write-through selectable LRU (least-recently-used) algorithm LRU algorithm Features of Store Queues Item Store Queues Capacity 2 × 32 bytes Addresses H'E000 0000 to H'E3FF FFFF Write Store instruction (1-cycle write) Write-back Prefetch instruction (PREF instruction) Access right MMU off: according to MMUCR.SQMD MMU on: according to individual page PR Page 112 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.1.2 Section 4 Caches Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Cache Control Registers Name Abbreviation R/W Initial 1 Value* P4 Address*2 Area 7 Address*2 Access Size Cache control register CCR R/W H'0000 0000 H'FF00 001C H'1F00 001C 32 Queue address control register 0 QACR0 R/W Undefined H'FF00 0038 H'1F00 0038 32 Queue address control register 1 QACR1 R/W Undefined H'FF00 003C H'1F00 003C 32 Notes: 1. The initial value is the value after a power-on or manual reset. 2. This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 113 of 1076 Section 4 Caches 4.2 SH7750, SH7750S, SH7750R Group Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 CB EMODE* IIX ICI ICE OIX ORA OCI WT OCE QACR0 31 5 4 2 1 0 AREA QACR1 31 5 4 2 1 0 AREA Notes: indicates reserved bits: 0 must be specified in a write; the read value is 0. * SH7750R only Figure 4.1 Cache and Store Queue Control Registers (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: IIX: ICI: ICE: OIX: ORA: OCI: CB: WT: OCE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S) IC index enable IC invalidation IC enable OC index enable OC RAM enable OC invalidation Copy-back enable Write-through enable OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least Page 114 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. • EMODE: Double-sized cache mode bit In the SH7750R, this bit indicates whether the double-sized cache mode is used or not. This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while the cache is being used. 0: SH7750/SH7750S-compatible mode*1 (initial value) 1: Double-sized cache mode • IIX: IC index enable bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection • ICI: IC invalidation bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns 0 when read. • ICE: IC enable bit Indicates whether or not the IC is to be used. When address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used • OIX: OC index enable bit*2 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection • ORA: OC RAM enable bit*3 When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0. 0: Normal mode (the entire OC is used as a cache) 1: RAM mode (half of the OC is used as a cache and the other half is used as RAM) • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 115 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode • WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode • OCE: OC enable bit Indicates whether or not the OC is to be used. When address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used Notes: 1. No compatibility for RAM mode in OC index mode and address assignment in RAM mode. 2. When the ORA bit is 1 in the SH7750R, the OIX bit should be cleared to 0. 3. When the OIX bit in the SH7750R is 1, the ORA bit should be cleared to 0. (2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off. (3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off. 4.3 Operand Cache (OC) 4.3.1 Configuration The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R's operand cache is 2-way set-associative. Each way consists of 512 cache lines. Figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750S. Page 116 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches Figure 4.3 shows the configuration of the operand cache for the SH7750R. Effective address 31 26 25 13 12 11 10 9 5 4 3 2 1 0 RAM area determination [11:5] OIX ORA [13] [12] 22 MMU Entry selection 9 3 Address array Tag 0 U V Longword (LW) selection Data array LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Write data Hit signal Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 117 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group Effective address 31 13 12 26 25 10 5 4 RAM area judgment [12:5] OIX ORA 2 0 Longword (LW) selection [13] Entry selection 22 Address array (way 0, way 1) 9 0 Tag address U 3 V Data array (way 0, way 1) LRU LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 511 19 bits Compare Compare way 1 way 0 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Read data 1 bit Write data Hit signal Figure 4.3 Configuration of Operand Cache (SH7750R) Page 118 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. • U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7750, SH7750S)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. • Data field The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 119 of 1076 Section 4 Caches 4.3.2 SH7750, SH7750S, SH7750R Group Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: → (3a) • If the tag matches and the V bit is 1 → (3b) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 • If the tag does not match, the V bit is 1, and the U bit is 0 → (3b) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3c) 3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 3c. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. Page 120 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.3.3 Section 4 Caches Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through → (3a) → (3b) • If the tag matches and the V bit is 1 → (3c) → (3d) • If the tag matches and the V bit is 0 → (3c) → (3d) • If the tag does not match and the V bit is 0 → (3d) • If the tag does not match, the V bit is 1, and the U bit is 0 → (3c) → (3d) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3e) 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. A write is also performed to the corresponding external memory using the specified access size. 3c. Cache miss (no copy-back/write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 3d. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 121 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group 3e. Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory. 4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a writeback buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination. Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 Figure 4.4 Configuration of Write-Back Buffer 4.3.5 Write-Through Buffer This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. Physical address bits [28:0] LW0 LW1 Figure 4.5 Configuration of Write-Through Buffer Page 122 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.3.6 Section 4 Caches RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 Kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In the SH7750/SH7750S-compatible mode of the SH7750R, the 8-Kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area. In the double-sized cache mode of the SH7750R, a total of 16 Kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is designated as a RAM area. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. With the SH7750R, the OC index mode is not available in RAM mode. An example of RAM use in the SH7750 or SH7750S is shown below. Here, the 4 Kbytes comprising OC entries 128 to 255 are designated as RAM area 1, and the 4 Kbytes comprising OC entries 384 to 511 as RAM area 2. • When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 KB): Corresponds to RAM area 1 : : : RAM areas 1 and 2 in the SH7750 or SH7750S then repeat every 8 Kbytes up to H'7FFF FFFF. Thus, to secure a continuous 8-Kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF can be used, for example. • When OC index mode is on (CCR.OIX = 1) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 1 : : : H'7DFF F000 to H'7DFF FFFF (4 KB): Corresponds to RAM area 1 H'7E00 0000 to H'7E00 0FFF (4 KB): Corresponds to RAM area 2 H'7E00 1000 to H'7E00 1FFF (4 KB): Corresponds to RAM area 2 : : : H'7FFF F000 to H'7FFF FFFF (4 KB): Corresponds to RAM area 2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 123 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area. Examples of RAM usage with the SH7750R is shown below. • In SH7750/SH7750S-compatible mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 KB): RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 KB): RAM area (entries 256 to 511) : : : In the same pattern, shadows of the RAM area are created in 8-Kbyte blocks until H'7FFF FFFF is reached. • In double-sized cache mode (CCR.EMODE = 1) In this mode, the 8 Kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM area 1 and the 8-Kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2 : : : In the same pattern, shadows of the RAM area are created in 16-Kbyte blocks until H'7FFF FFFF is reached. 4.3.7 OC Index Mode Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. The SH7750R cannot be used in RAM mode when OC index mode is selected. Page 124 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.3.8 Section 4 Caches Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: OCBI @Rn Cache invalidation (no write-back) Purge instruction: OCBP @Rn Cache invalidation (with write-back) Write-back instruction: OCBWB @Rn Cache write-back Allocate instruction: MOVCA.L R0,@Rn Cache allocation 4.3.9 Prefetch Operation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. Prefetch instruction: 4.3.10 PREF @Rn Notes on Using Cache Enhanced Mode (SH7750R Only) When cache enhanced mode (CCR.EMODE = 1) is specified and OC RAM mode (CCR.ORA = 1) is selected, in which half of the operand cache is used as internal RAM, internal RAM data may be updated incorrectly. Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the following four conditions are satisfied. Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified. Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as internal RAM is specified. Condition 3: An exception or an interrupt occurs. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 125 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group Note: This includes a break triggered by a debugging tool swapping an instruction (a break occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped for an instruction). Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four instructions after the instruction associated with the exception or interrupt described in condition 3. This includes cases where the store instruction that accesses internal RAM itself generates an exception. Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary that includes an address that differs by H'2000 from the address accessed by the store instruction that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to H'7C002207 becomes corrupted. Examples Example 1 A store instruction accessing internal RAM occurs within four instructions after an instruction generating a TLB miss exception. MOV.L #H'0C400000, R0 R0 is an address causing a TLB miss. MOV.L #H'7C000204, R1 R1 is an address mapped to internal RAM. MOV.L @R0, R2 TLB miss exception occurs. NOP 1st word NOP 2nd word NOP 3rd word MOV.L R3, @R1 Store instruction accessing internal RAM Example 2 A store instruction accessing internal RAM occurs within four instructions after an instruction causing an interrupt to be accepted. MOV.L #H'7C002000, R1 R1 is an address mapped to internal RAM. MOV.L #H'12345678, R0 An interrupt is accepted after this instruction. NOP 1st word NOP 2nd word NOP 3rd word MOV.L R0, @R1 Store instruction accessing internal RAM Page 126 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches Example 3 A debugging tool generates a break to swap an instruction. Original Instruction String After Instruction Swap Break MOV.L #H'C000000, R0 MOV.L #H'7C000000, R0 Contains address corresponding to R0. ADD R0, R0 TRAPA #H'01 R0 address is not a problem in original instruction string. MOV.L R1, @R0 MOV.L R1, @R0 Internal RAM is accessed by a store operation because ADD is not executed. The store is cancelled, but 2LW starting at H'7C002000 is corrupted. Workarounds: When RAM mode is specified in cache enhanced mode, either of the following workarounds can be used to avoid the problem. Workaround 1: Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which address bits [12:0] are identical and only bit [13] differs must not be used. For example, the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to H'7C002FFF may be used. Note: When a break is used to swap instructions by a debugging tool, etc., a memory access address may be changed when an instruction following the instruction generating the break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be accessed. This will result in the problem described above. However, this phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. Workaround 2: Ensure that there are no instructions that generate an interrupt or exception within four instructions after an instruction that accesses internal RAM. For example, the internal RAM area can be used as a data table that is accessed only by load instructions, with writes to the internal RAM area only being performed when the table is generated. It this case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to ensure that no exceptions due to TLB misses, etc., occur while writing to the table. Note: The problem still may occur when a break is used to swap instructions by a debugging tool. This phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 127 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group 4.4 Instruction Cache (IC) 4.4.1 Configuration The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines. Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S. Figure 4.7 shows the configuration of the instruction cache for the SH7750R. Effective address 31 13 12 11 10 9 26 25 5 4 3 2 1 0 [11:5] IIX [12] Longword (LW) selection 22 MMU Entry selection 8 Address array 0 3 Data array Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 19 255 Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) Page 128 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches Effective address 31 25 5 4 13 12 11 10 2 0 [11:5] IIX [12] Entry selection 22 Longword (LW) selection Address array (way 0, way1) 8 0 3 Data array (way 0, way 1) LRU Tag address V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits MMU 19 255 Compare Compare way 1 way 0 1 bit Read data Hit signal Figure 4.7 Configuration of Instruction Cache (SH7750R) • Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 129 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. 4.4.2 Read Operation When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: • If the tag matches and the V bit is 1 → (3a) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 → (3b) • If the tag does not match and the V bit is 1 → (3b) 3a. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 3b. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. Page 130 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.4.3 Section 4 Caches IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. 4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S) To enable the IC and OC to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 4.5.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 131 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 0 0 0 13 12 5 4 3 2 1 0 Entry 31 10 9 Data field A 1 0 V Tag Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.8 Memory-Mapped IC Address Array 4.5.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. Page 132 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 0 1 13 12 5 4 Entry 31 2 1 0 L 0 Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 133 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 14 13 Address field 1 1 1 1 0 1 0 0 Entry 31 Data field 5 4 3 2 1 0 10 9 A 2 1 0 U V Tag Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.10 Memory-Mapped OC Address Array Page 134 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.5.4 Section 4 Caches OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 Address field 1 1 1 1 0 1 0 1 14 13 5 4 Entry 31 2 1 0 L 0 Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 135 of 1076 Section 4 Caches 4.6 SH7750, SH7750S, SH7750R Group Memory-Mapped Cache Configuration (SH7750R) To enable the management of the IC and OC by software, a program running in the privileged mode is allowed to access their contents. The contents of IC can be read and written by using MOV instructions in a P2-area program running in the privileged mode. Operation is not guaranteed for access from a program in some other area. Any branching to other areas must take place at least 8 instructions after this MOV instruction. The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program running in the privileged mode. Operation is not guaranteed if access is attempted from a program running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area of the physical memory space. The address and data arrays of both the IC and OC are only accessible by their data fields. Longword operations must be used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0 should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750Scompatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that of the SH7750 or SH7750S. Page 136 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.6.1 Section 4 Caches IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [13] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit for that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 137 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group 24 23 31 13 12 5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry A Way 31 10 9 Data field 1 0 V Tag Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. Page 138 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 31 Section 4 Caches 24 23 13 12 Address field 1 1 1 1 0 0 0 1 5 4 Entry 2 1 0 L Way 31 0 Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's address arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 139 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [14] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit for that way is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 15 14 13 Address field 1 1 1 1 0 1 0 0 5 4 3 2 1 0 Entry A Way 31 Data field 10 9 2 1 0 U V Tag Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.14 Memory-Mapped OC Address Array Page 140 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.6.4 Section 4 Caches OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's data arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the way and entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 Address field 1 1 1 1 0 1 0 1 15 14 13 5 4 Entry Way 31 Data field 2 1 0 L 0 Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.15 Memory-Mapped OC Data Array R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 141 of 1076 Section 4 Caches 4.6.5 SH7750, SH7750S, SH7750R Group Summary of the Memory-Mapping of the OC The address ranges to which the OC is memory-mapped in the double-sized cache mode of the SH7750R are summarized below, using examples of data-array access. • In normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 KB ): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 KB ): Way 1 (entries 0 to 511) : : : In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF FFFF. • In RAM mode (CCR. ORA = 1) H'F500 0000 to H'F500 1FFF (8 KB ): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 KB ): Way 1 (entries 0 to 255) : : : In the same pattern, shadows of the cache area are created in 16-Kbyte blocks until H'F5FF FFFF. 4.7 Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, PowerDown Modes, for the procedure for stopping SQ functions. 4.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store queues can be set independently. Page 142 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7] 4B 4B 4B 4B 4B 4B 4B 4B Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 4.7.3 111000 Don't care 0/1 LW specification 00 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off. • When MMU is on The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have no meaning. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 143 of 1076 Section 4 Caches SH7750, SH7750S, SH7750R Group When a prefetch instruction is issued for the SQ area, address translation is performed and external memory address bits [28:10] are generated in accordance with the SZ bit specification. For external memory address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0. Transfer from the SQs to external memory is performed to this address. • When MMU is off The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address to issue a PREF instruction. The meaning of address bits [31:0] is as follows: [31:26]: [25:6]: [5]: 111000 Address 0/1 [4:2]: [1:0] Don't care 00 Store queue specification External memory address bits [25:6] 0: SQ0 specification 1: SQ1 specification and external memory address bit [5] No meaning in a prefetch Fixed at 0 External memory address bits [28:26], which cannot be generated from the above address, are generated from the QACR0/1 registers. QACR0 [4:2]: QACR1 [4:2]: External memory address bits [28:26] corresponding to SQ0 External memory address bits [28:26] corresponding to SQ1 External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register. Page 144 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 4.7.4 Section 4 Caches SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted. • When MMU is on Operation is in accordance with the address translation information recorded in the UTLB, and MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read type for transfer from the SQs to external memory (PREF instruction), and a TLB miss exception, protection violation exception, or initial page write exception is generated. However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address error will be flagged in user mode even if address translation is successful. • When MMU is off Operation is in accordance with MMUCR.SQMD. 0: Privileged/user access possible 1: Privileged access possible If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will be flagged. 4.7.5 Reading the SQs (SH7750R Only) In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword access is possible. [31:6] [5] [4:2] [1:0] : H'FF001000 : 0/1 : LW specification : 00 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 : Store queue specification : 0: SQ0 specification, 1: SQ1 specification : Specification of longword position in SQ0 or SQ1 : Fixed at 0 Page 145 of 1076 Section 4 Caches 4.7.6 SH7750, SH7750S, SH7750R Group SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below. (1) When SQ data is transferred to external memory within a normal program If a PREF instruction for transfer from an SQ to external memory is included in the three instructions preceding an SQ store instruction, the SQ is updated because the SQ write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed, so that erroneous data may be transferred to external memory. (2) When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction ; PREF instruction for transfer from SQ to external memory ; Address of this instruction is saved to SPC when exception occurs. ; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine. Instruction 1 ; May be executed if an SQ store instruction. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; Not executed even if an SQ store instruction. Page 146 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 4 Caches Example 2: When an instruction that generates an exception branches using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ. Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 (branch destination of instruction 1) ; May be executed if an SQ access instruction. Instruction 8 ; May be executed if an SQ store instruction. Example 3: When an instruction that generates an exception does not branch using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; May be executed if an SQ store instruction. Instruction 5 To recover from this problem it is necessary that conditions A and B be satisfied. A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external memory, a store instruction for the same store queue must be executed, and conditions (1) and (2) below must be satisfied. (1) Three NOP instructions*1 must be inserted between the above two instructions. (2) There must not be a PREF instruction to transfer data from the store queue to external memory in the delay slot of the branch instruction. B: There must be no PREF instruction to transfer data from the store queue to external memory executed in the exception handling routine. If such an instruction is executed, and if there is a store to the store queue instruction among the four instructions*2 at the address referred to by SPC, the data transferred to external memory by the PREF instruction may indicate that execution of the store instruction has completed. Notes: 1. If there are other instructions between the above two instructions, the problem can be avoided if the other instructions and NOP instructions together total three or more instructions. 2. If the instruction at the address referred to by SPC is a branch instruction the two instructions at the branch destination may be affected. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 147 of 1076 Section 4 Caches Page 148 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions Section 5 Exceptions 5.1 Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control to a user-written exception handling routine, in order to support such functions, is given the generic name of exception handling. SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1. Table 5.1 Exception-Related Registers Abbreviation R/W P4 Initial Value*1 Address*2 TRAPA exception register TRA R/W Undefined Exception event register EXPEVT R/W H'0000 0000/ H'FF00 0024 H'1F00 0024 32 H'0000 0020*1 Interrupt event register INTEVT R/W Undefined Name Area 7 Address*2 Access Size H'FF00 0020 H'1F00 0020 32 H'FF00 0028 H'1F00 0028 32 Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset. 2. This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 149 of 1076 Section 5 Exceptions 5.2 SH7750, SH7750S, SH7750R Group Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12bit exception code. The exception code set in INTEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1. EXPEVT and INTEVT 31 0 12 11 0 Exception code 0 TRA 31 0 10 9 0 2 1 0 imm 0 0 Legend: 0: Reserved bits. These bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the TRAPA instruction Figure 5.1 Register Bit Configurations Page 150 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 5.3 Exception Handling Functions 5.3.1 Exception Handling Flow Section 5 Exceptions In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 by an RTE instruction. The basic processing flow is as follows. See section 2, Programming Model, for the meaning of the individual SR bits. 1. 2. 3. 4. 5. 6. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR. The block bit (BL) in SR is set to 1. The mode bit (MD) in SR is set to 1. The register bank bit (RB) in SR is set to 1. In a reset, the FPU disable bit (FD) in SR is cleared to 0. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A000 0000. General exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (P1, P2) should be specified for vector addresses. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 151 of 1076 Section 5 Exceptions 5.4 SH7750, SH7750S, SH7750R Group Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Category Mode Exception Priority Priority Vector Level Order Address Reset 1 1 H'A000 0000 — H'000 Manual reset 1 2 H'A000 0000 — H'020 H-UDI reset 1 1 H'A000 0000 — H'000 Instruction TLB multiple-hit exception 1 3 H'A000 0000 — H'140 Data TLB multiple-hit exception 1 4 H'A000 0000 — H'140 User break before instruction 1 execution* 2 0 (VBR/DBR) H'100/ — H'1E0 Instruction address error 2 1 (VBR) H'100 H'0E0 Instruction TLB miss exception 2 2 (VBR) H'400 H'040 Instruction TLB protection violation exception 2 3 (VBR) H'100 H'0A0 General illegal instruction exception 2 4 (VBR) H'100 H'180 Slot illegal instruction exception 2 4 (VBR) H'100 H'1A0 Abort type Power-on reset General Reexception execution type Exception Code General FPU disable exception 2 4 (VBR) H'100 H'800 Slot FPU disable exception 2 4 (VBR) H'100 H'820 Data address error (read) 2 5 (VBR) H'100 H'0E0 Data address error (write) 2 5 (VBR) H'100 H'100 Data TLB miss exception (read) 2 6 (VBR) H'400 H'040 Data TLB miss exception (write) 2 6 (VBR) H'400 H'060 Data TLB protection violation exception (read) 2 7 (VBR) H'100 H'0A0 Data TLB protection violation exception (write) 2 7 (VBR) H'100 H'0C0 FPU exception 2 8 (VBR) H'100 H'120 Initial page write exception 2 9 (VBR) H'100 H'080 2 4 (VBR) H'100 H'160 2 10 (VBR/DBR) H'100/ — H'1E0 Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* Page 152 of 1076 Offset R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Exception Execution Category Mode Interrupt Section 5 Exceptions Exception Completion Nonmaskable interrupt type External IRL3–IRL0 interrupts 0 Priority Level Priority Vector Order Address Offset Exception Code 3 — (VBR) H'600 H'1C0 4 2 (VBR) H'600 H'200 * 1 H'220 2 H'240 3 H'260 4 H'280 5 H'2A0 6 H'2C0 7 H'2E0 8 H'300 9 H'320 A H'340 B H'360 C H'380 D H'3A0 E Peripheral TMU0 module TMU1 interrupt (module/ TMU2 source) (VBR) H'600 H'400 H'420 TUNI2 H'440 TICPI2 H'460 TMU3 TUNI3 H'B00 TMU4 TUNI4 H'B80 RTC ATI H'480 PRI H'4A0 CUI H'4C0 WDT REF Sep 24, 2013 H'3C0 2 * TUNI1 SCI R01UH0456EJ0702 Rev. 7.02 TUNI0 4 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 ITI H'560 RCMI H'580 ROVI H'5A0 H-UDI H-UDI H'600 GPIO GPIOI H'620 Page 153 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group Exception Category Execution Mode Exception Interrupt Completion Peripheral module type DMAC DMTE0 interrupt (module/ source) Priority Order 4 * 2 Vector Address Offset Exception Code (VBR) H'600 H'640 DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0 3 H'780 3 DMTE5* H'7A0 3 DMTE6* H'7C0 DMTE7* 3 H'7E0 DMAE H'6C0 ERI H'700 RXI H'720 BRI H'740 TXI H'760 DMTE4* SCIF Priority Level Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL: Interrupt request level (pins IRL3–IRL0). Module/source: See the sections on the relevant peripheral modules. Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100. 2. The priority order of external interrupts and peripheral module interrupts can be set by software. 3. SH7750R only. Page 154 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 5.5 Exception Flow 5.5.1 Exception Flow Section 5 Exceptions Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed. Yes Reset requested? No Execute next instruction General exception requested? Yes No Interrupt requested? No Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 PC ← (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT ← exception code SR. {MD, RB, BL, FD, IMASK} ← 11101111 PC ← H'A000 0000 Figure 5.2 Instruction Execution and Exception Handling R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 155 of 1076 Section 5 Exceptions 5.5.2 SH7750, SH7750S, SH7750R Group Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3. Page 156 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions Pipeline flow: Instruction n Instruction n+1 IF ID EX TLB miss (data access) MA WB IF ID EX MA WB General illegal instruction exception Instruction n+2 TLB miss (instruction access) IF ID EX MA WB Instruction n+3 IF ID EX MA Order of detection: WB Legend: IF: Instruction fetch ID: Instruction decode EX: Instruction execution MA: Memory access WB: Write-back General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: Program order TLB miss (instruction n) 1 Re-execution of instruction n General illegal instruction exception (instruction n+1) 2 Re-execution of instruction n+1 TLB miss (instruction n+2) 3 Re-execution of instruction n+2 Execution of instruction n+3 4 Figure 5.3 Example of General Exception Acceptance Order R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 157 of 1076 Section 5 Exceptions 5.5.3 SH7750, SH7750S, SH7750R Group Exception Requests and BL Bit When the BL bit in SR is 0, general exception and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 20, User Break Controller (UBC). If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction. 5.6 Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. Page 158 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 5.6.1 Section 5 Exceptions Resets (1) Power-On Reset • Sources: ⎯ SCK2 pin high level and RESET pin low level ⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin must be driven low. It is therefore essential to execute a power-on reset and drive the TRST pin low when powering on. If the SCK2 pin is changed to the low level while the RESET pin is low, a manual reset may occur after the power-on reset operation. Do not drive the SCK2 pin low during this interval (see figure 22.3). Power_on_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 159 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group (2) Manual Reset • Sources: ⎯ SCK2 pin low level and RESET pin low level ⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR ⎯ When the watchdog timer overflows while the WT/IT bit and RSTS bit are both set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. Manual_reset() { EXPEVT = H'00000020; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Page 160 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Table 5.3 Section 5 Exceptions Types of Reset Reset State Transition Conditions Internal States Type SCK2 RESET CPU On-Chip Peripheral Modules Power-on reset High Low Initialized Manual reset Low Low Initialized See Register Configuration in each section (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. H-UDI_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 161 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Page 162 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 163 of 1076 Section 5 Exceptions 5.6.2 SH7750, SH7750S, SH7750R Group General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'00000040 : H'00000060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Page 164 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 165 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 166 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode User Mode 00 Only read access possible Access not possible 01 Read/write access possible Access not possible 10 Only read access possible Only read access possible 11 Read/write access possible Read/write access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'000000A0 : H'000000C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 167 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode User Mode 0 Access possible Access not possible 1 Access possible Access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 168 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions (6) Data Address Error • Sources: ⎯ Word data access from other than a word boundary (2n +1) ⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ⎯ Access to area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'000000E0: H'00000100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 169 of 1076 Section 5 Exceptions SH7750, SH7750S, SH7750R Group (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 170 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 5 Exceptions (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm Rm (unsigned), 1→T Otherwise, 0 → T 0011nnnnmmmm0110 — Comparison result CMP/GT Rm,Rn When Rn > Rm (signed), 1 → T 0011nnnnmmmm0111 — Otherwise, 0 → T Comparison result CMP/PZ Rn When Rn ≥ 0, 1 → T Otherwise, 0 → T 0100nnnn00010001 — Comparison result CMP/PL Rn When Rn > 0, 1 → T Otherwise, 0 → T 0100nnnn00010101 — Comparison result CMP/STR Rm,Rn When any bytes are equal, 1→T Otherwise, 0 → T 0010nnnnmmmm1100 — Comparison result DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation result DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^Q → T 0010nnnnmmmm0111 — Calculation result 0 → M/Q/T 0000000000011001 — 0 Signed, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm1101 — — DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm0101 — — DT Rn – 1 → Rn; when Rn = 0, 1→T When Rn ≠ 0, 0 → T 0100nnnn00010000 — Comparison result DIV0U DMULS.L Rm,Rn Rn Page 218 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Instruction Section 7 Instruction Set Operation Instruction Code Privileged T Bit EXTS.B Rm,Rn Rm sign-extended from byte → Rn 0110nnnnmmmm1110 — — EXTS.W Rm,Rn Rm sign-extended from word → Rn 0110nnnnmmmm1111 — — EXTU.B Rm,Rn Rm zero-extended from byte → Rn 0110nnnnmmmm1100 — — EXTU.W Rm,Rn Rm zero-extended from word → Rn 0110nnnnmmmm1101 — — MAC.L @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits 0000nnnnmmmm1111 — — MAC.W @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits 0100nnnnmmmm1111 — — MUL.L Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits 0000nnnnmmmm0111 — — MULS.W Rm,Rn Signed, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1111 — — MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1110 — — NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — — SUBC Rm,Rn Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — Borrow SUBV Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Underflow Page 219 of 1076 Section 7 Instruction Set Table 7.5 SH7750, SH7750S, SH7750R Group Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — — AND #imm,R0 R0 & imm → R0 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) 11001001iiiiiiii — — 11001101iiiiiiii — — NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — — OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — — OR #imm,R0 R0 | imm → R0 — OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR) TAS.B 11001011iiiiiiii — 11001111iiiiiiii — @Rn When (Rn) = 0, 1 → T 0100nnnn00011011 Otherwise, 0 → T In both cases, 1 → MSB of (Rn) — Test result TST Rm,Rn Rn & Rm; when result = 0, 1→T Otherwise, 0 → T 0010nnnnmmmm1000 — Test result TST #imm,R0 R0 & imm; when result = 0, 1→T Otherwise, 0 → T 11001000iiiiiiii — Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii = 0, 1 → T Otherwise, 0 → T — Test result XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — — XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — — 11001110iiiiiiii — — XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 + GBR) Page 220 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Table 7.6 Section 7 Instruction Set Shift Instructions Instruction Operation Instruction Code Privileged T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — MSB ROTR Rn LSB → Rn → T 0100nnnn00000101 — LSB ROTCL Rn T ← Rn ← T 0100nnnn00100100 — MSB ROTCR Rn T → Rn → T 0100nnnn00100101 — LSB SHAD Rm,Rn When Rn ≥ 0, Rn > Rm → [MSB → Rn] — SHAL Rn T ← Rn ← 0 0100nnnn00100000 — MSB 0100nnnn00100001 — SHAR Rn MSB → Rn → T SHLD Rm,Rn When Rn ≥ 0, Rn > Rm → [0 → Rn] — SHLL Rn T ← Rn ← 0 MSB SHLR Rn 0 → Rn → T 0100nnnn00000001 — LSB SHLL2 Rn Rn > 2 → Rn 0100nnnn00001001 — — SHLL8 Rn Rn > 8 → Rn 0100nnnn00011001 — — SHLL16 Rn Rn > 16 → Rn 0100nnnn00101001 — — R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 0100nnnn00000000 — LSB Page 221 of 1076 Section 7 Instruction Set Table 7.7 SH7750, SH7750S, SH7750R Group Branch Instructions Instruction Operation Instruction Code Privileged T Bit BF label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001011dddddddd — — BF/S label Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001111dddddddd — — BT label When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001001dddddddd — — BT/S label Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001101dddddddd — — BRA label Delayed branch, disp × 2 + PC + 4 → PC 1010dddddddddddd — — BRAF Rn Delayed branch, Rn + PC + 4 → PC 0000nnnn00100011 — — BSR label Delayed branch, PC + 4 → PR, 1011dddddddddddd — disp × 2 + PC + 4 → PC — BSRF Rn Delayed branch, PC + 4 → PR, 0000nnnn00000011 — Rn + PC + 4 → PC — JMP @Rn Delayed branch, Rn → PC 0100nnnn00101011 — — JSR @Rn Delayed branch, PC + 4 → PR, 0100nnnn00001011 — Rn → PC — Delayed branch, PR → PC — RTS Page 222 of 1076 0000000000001011 — R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Table 7.8 Section 7 Instruction Set System Control Instructions Instruction Operation Instruction Code Privileged T Bit CLRMAC 0 → MACH, MACL 0000000000101000 — — CLRS 0→S 0000000001001000 — — CLRT 0→T 0000000000001000 — 0 LSB LDC Rm,SR Rm → SR 0100mmmm00001110 Privileged LDC Rm,GBR Rm → GBR 0100mmmm00011110 — — LDC Rm,VBR Rm → VBR 0100mmmm00101110 Privileged — LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged — LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged — LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged — LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — — LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged — LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged — LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged — LDC.L @Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged — LDC.L @Rm+,Rn_BANK (Rm) → Rn_BANK, Rm + 4 → Rm 0100mmmm1nnn0111 Privileged — LDS Rm,MACH Rm → MACH 0100mmmm00001010 — — LDS Rm,MACL Rm → MACL 0100mmmm00011010 — — LDS Rm,PR Rm → PR 0100mmmm00101010 — — LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — — LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — — LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — — PTEH/PTEL → TLB 0000000000111000 Privileged — R0,@Rn R0 → (Rn) (without fetching cache block) 0000nnnn11000011 — — No operation 0000000000001001 — — OCBI @Rn Invalidates operand cache block 0000nnnn10010011 — — OCBP @Rn Writes back and invalidates operand cache block 0000nnnn10100011 — — OCBWB @Rn Writes back operand cache block 0000nnnn10110011 — — PREF @Rn (Rn) → operand cache 0000nnnn10000011 — — LDTLB MOVCA. L NOP R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 223 of 1076 Section 7 Instruction Set SH7750, SH7750S, SH7750R Group Instruction Operation Instruction Code Privileged T Bit RTE Delayed branch, SSR/SPC → SR/PC 0000000000101011 Privileged — SETS 1→S 0000000001011000 — — SETT 1→T 0000000000011000 — 1 SLEEP Sleep or standby 0000000000011011 Privileged — STC SR,Rn SR → Rn 0000nnnn00000010 Privileged — STC GBR,Rn GBR → Rn 0000nnnn00010010 — — STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged — STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged — STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged — STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged — STC DBR,Rn DBR → Rn 0000nnnn11111010 Privileged — STC Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) 0000nnnn1mmm0010 Privileged — STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Privileged — STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 — — STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn) 0100nnnn00100011 Privileged — STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn) 0100nnnn00110011 Privileged — STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn) 0100nnnn01000011 Privileged — STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged — STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged — STC.L Rm_BANK,@-Rn Rn – 4 → Rn, 0100nnnn1mmm0011 Privileged Rm_BANK → (Rn) (m = 0 to 7) — STS MACH,Rn MACH → Rn 0000nnnn00001010 — — STS MACL,Rn MACL → Rn 0000nnnn00011010 — — STS PR,Rn PR → Rn 0000nnnn00101010 — — STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 — — STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 — — STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 — — TRAPA #imm PC + 2 → SPC, SR → SSR, #imm CH1 > CH2 > CH3 1 CH0 > CH2 > CH3 > CH1 0 CH2 > CH0 > CH1 > CH3 1 Round robin mode 1 (Initial value) Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0. Bit 4 (SH7750S)—Check Overrun for DREQ (COD): When this bit is set to 1, cancellation of an accepted DREQ acceptance flag is enabled. When cancellation of an accepted DREQ acceptance flag is enabled by setting COD to 1, clear CHCRn.DS to 0 and then negate DREQ (to the high level). For details, see External Request Mode in section 14.3.2, DMA Transfer Requests. Bit 4: COD Description 0 DREQ acceptance flag cancellation disabled 1 DREQ acceptance flag cancellation enabled (Initial value) Note: When external request mode is used in the SH7750S, recommend setting COD to 1 permanently. Bit 4 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 565 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description 0 No address error, DMA transfer enabled (Initial value) [Clearing condition] When 0 is written to AE after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] When an address error is caused by the DMAC Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. Bit 1: NMIF 0 Description No NMI input, DMA transfer enabled (Initial value) [Clearing condition] When 0 is written to NMIF after reading NMIF = 1 1 NMI input, DMA transfer disabled [Setting condition] When an NMI interrupt is generated Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. Bit 0: DME Description 0 Operation disabled on all channels 1 Operation enabled on all channels Page 566 of 1076 (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.3 Section 14 Direct Memory Access Controller (DMAC) Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. There are two modes for DMA transfer: single address mode and dual address mode. Either burst mode or cycle steal mode can be selected as the bus mode. 14.3.1 DMA Transfer Procedure After the desired transfer conditions have been set in the DMA source address register (SAR), DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one transfer unit of data (determined by the setting of TS2–TS0). In auto-request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is decremented by 1 for each transfer. The actual transfer flow depends on the address mode and bus mode. 3. When the specified number of transfers have been completed (when the DMATCR value reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE interrupt request is sent to the CPU. 4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event of an address error, a DMAE interrupt request is forcibly sent to the CPU. Figure 14.2 shows a flowchart of this procedure. Note: If transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 567 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) No DE, DME = 1? Yes *4 Illegal address check (reflected in AE bit) No NMIF, AE, TE = 0? Yes *2 Transfer request issued? *1 No *3 Yes Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR DMATCR = 0? NMIF or AE = 1 or DE = 0 or DME = 0? No Yes No Yes DMTE interrupt request (when IE = 1) NMIF or AE = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, DREQ detection method Transfer suspended No Yes End of transfer Normal end Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE and DME bits are set to 1. 2. DREQ level detection (external request) in burst mode, or cycle steal mode. 3. DREQ edge detection (external request) in burst mode, or auto-request mode in burst mode. 4. An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn. Figure 14.2 DMAC Transfer Flowchart Page 568 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.3.2 Section 14 Direct Memory Access Controller (DMAC) DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The transfer request mode is selected by means of bits RS3–RS0 in DMA channel control registers 0–3 (CHCR0–CHCR3). Auto Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bit in CHCR0–CHCR3 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in CHCR0–CHCR3 and the NMIF and AE bits in DMAOR are all 0). External Request Mode: In this mode a transfer is performed in response to a transfer request signal (DREQ) from an external device. One of the modes shown in table 14.4 should be chosen according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when DREQ is input. The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the DREQ signal (level detection when DS = 0, edge detection when DS = 1). DREQ is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0). In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 569 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.4 Selecting External Request Mode with RS Bits RS3 0 RS2 0 RS1 RS0 Address Mode Transfer Source Transfer Destination 0 0 Dual address mode External memory or memory-mapped external device, or external device with DACK External memory or memory-mapped external device, or external device with DACK 1 0 Single address mode External memory or memory-mapped external device External device with DACK 1 Single address mode External device with DACK External memory or memory-mapped external device • External Request Acceptance Conditions 1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, if an external request (DREQ: edge-detected) is input it will be held inside the DMAC until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0). 2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0), if an external request (DREQ) is input, DMA transfer is started. 3. An external request (DREQ) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF = 1, or DMAOR.AE = 1, or during a power-on reset or manual reset, in deep sleep mode or standby mode, or while the DMAC is in the module standby state. 4. A previously input external request will be canceled by the occurrence of an NMI interrupt (DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or manual reset. In the SH7750S, it is possible to cancel a previously input external request (DREQ). With DMAOR.COD set to 1, clear CHCRn.DS to 0 and then drive the DREQ pin high. On the SH7750R, it is possible to cancel an external request that has been accepted by external request (DREQ) edge detection by first negating DREQ and then clearing CHCR.DS from 1 to 0. Afterwards CHCR.DS should be reset to 1 and DREQ asserted. (The SH7750R has no DMAOR.COD bit, but it is possible to cancel an external request that has been accepted by external request (DREQ) edge detection, as is the case when the DMAOR.COD bit of the SH7750S is set to 1.) Page 570 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) • Usage Notes An external request (DREQ) is detected by a low level or falling edge. Ensure that the external request (DREQ) signal is held high when there is no DMA transfer request from an external device after a power-on reset or manual reset. When DMA transfer is restarted, check whether a DMA transfer request is being held. On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input. The source of the transfer request does not have to be the data transfer source or destination. However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2). When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty interrupt), the transfer destination must be the SCI/SCIF's transmit data register (SCTDR1/SCFTDR2). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 571 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer RS3 RS2 RS1 RS0 Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode 1 0 0 1 1 0 1 0 SCI transmitter SCTDR1 (SCI transmit-dataempty transfer request) External* SCTDR1 Cycle steal mode 1 SCI receiver SCRDR1 (SCI receive-data-full transfer request) SCRDR1 External* Cycle steal mode 0 SCIF transmitter SCFTDR2 (SCIF transmit-dataempty transfer request) External* SCFTDR2 Cycle steal mode 1 SCIF receiver SCFRDR2 (SCIF receive-data-full transfer request) SCFRDR2 External* Cycle steal mode 0 TMU channel 2 Input capture occurrence External* External* Burst/cycle steal mode 1 TMU channel 2 Input capture occurrence External* On-chip peripheral Burst/cycle steal mode 0 TMU channel 2 Input capture occurrence On-chip External* peripheral Burst/cycle steal mode Legend: TMU: Timer unit SCI: Serial communication interface SCIF: Serial communication interface with FIFO Notes: 1. SCI/SCIF burst transfer setting is prohibited. 2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. A DMA transfer request by means of an input capture interrupt can be canceled by setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU. * External memory or memory-mapped external device To output a transfer request from an on-chip peripheral module, set the DMA transfer request enable bit for that module and output a transfer request signal. For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and 16, Serial Communication Interface with FIFO (SCIF). Page 572 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority orders are available in fixed mode: • CH0 > CH1 > CH2 > CH3 • CH0 > CH2 > CH3 > CH1 • CH2 > CH0 > CH1 > CH3 The priority order is selected with bits PR1 and PR0 in DMAOR. Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. This is illustrated in figure 14.3. The order of priority in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3. Note: In round robin mode, if no transfer request is accepted for any channel during DMA transfer, the priority order becomes CH0 > CH1 > CH2 > CH3. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 573 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Transfer on channel 0 Initial priority order CH0 > CH1 > CH2 > CH3 Channel 0 is given the lowest priority. Priority order after transfer CH1 > CH2 > CH3 > CH0 Transfer on channel 1 Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH2 > CH3 > CH0 > CH1 When channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously. Transfer on channel 2 Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer Priority after transfer due to issuance of a transfer request for channel 1 only. CH3 > CH0 > CH1 > CH2 When channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. If there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. CH2 > CH3 > CH0 > CH1 Transfer on channel 3 Initial priority order CH0 > CH1 > CH2 > CH3 No change in priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 Figure 14.3 Round Robin Mode Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The operation of the DMAC in this case is as follows. Page 574 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. The channel 3 transfer is started. 8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. Transfer request 1. Issued for channels 0 and 3 3. Issued for channel 1 Channel waiting 3 DMAC operation Channel priority order 2. Start of channel 0 transfer 0>1>2>3 Change of priority order 1, 3 4. End of channel 0 transfer 1>2>3>0 5. Start of channel 1 transfer 3 6. End of channel 1 transfer Change of priority order 2>3>0>1 7. Start of channel 3 transfer None Change of priority order 8. End of channel 3 transfer 0>1>2>3 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 575 of 1076 Section 14 Direct Memory Access Controller (DMAC) 14.3.4 SH7750, SH7750S, SH7750R Group Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. The actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. Table 14.6 Supported DMA Transfers Transfer Destination External Device with DACK External Memory Memory-Mapped External Device On-Chip Peripheral Module External device with DACK Not available Single address mode Single address mode Not available External memory Single address mode Dual address mode Dual address mode Dual address mode Memory-mapped external device Single address mode Dual address mode Dual address mode Dual address mode On-chip peripheral module Not available Dual address mode Dual address mode Not available Transfer Source Page 576 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows an example of a transfer between external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External address bus External data bus SH7750, SH7750S, SH7750R External memory DMAC External device with DACK DACK DREQ Legend: : Data flow Figure 14.5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. Only the external request signal (DREQ) is used in both these cases. Figure 14.6 shows the DMA transfer timing for single address mode. The access timing depends on the type of external memory. For details, see the descriptions of the memory interfaces in section 13, Bus State Controller (BSC). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 577 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CKIO A28–A0 Address output to external memory space CSn D63–D0 DACK WE Data output from external device with DACK DACK signal to external device with DACK WE signal to external memory space (a) From external device with DACK to external memory space CKIO A28–A0 Address output to external memory space CSn D63–D0 RD DACK Data output from external memory space RD signal to external memory space DACK signal to external device with DACK (b) From external memory space to external device with DACK Figure 14.6 DMA Transfer Timing in Single Address Mode Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either onchip peripheral module or external address. Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or transfer destination. Page 578 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus cycles in order to write in the transfer destination the data corresponding to the size specified by CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the BSC's data buffer in the read cycle, then written to the other external memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output timing is the same as that of CSn in a read or write cycle specified by the CHCRn.AM bit. SAR BSC Data bus DAR Memory Address bus DMAC Transfer source module Transfer destination module Data buffer Taking the SAR value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (BSC). 1st bus cycle SAR BSC Data bus DAR Memory Address bus DMAC Transfer source module Transfer destination module Data buffer Taking the DAR value as the address, the data stored in the BSC's data buffer is written to the transfer destination module. 2nd bus cycle Figure 14.7 Operation in Dual Address Mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 579 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CKIO Transfer source address A26–A0 Transfer destination address CSn D63–D0 RD WE DACK Data read cycle (1st cycle) Data write cycle (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0– CHCR3. Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end condition is satisfied. Cycle steal mode can be used with all categories of transfer request source, transfer source, and transfer destination. Page 580 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and DREQ level detection. DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC Read Write CPU CPU Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied. With DREQ low level detection in external request mode, however, when DREQ is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted, even if the transfer end condition has not been satisfied. Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in this example are single address mode and DREQ level detection (CHCRn.DS = 0, CHCRn.TM = 1). DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.10 Example of DMA Transfer in Burst Mode Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode setting can also be made. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 581 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Mode Single Dual Legend: 32B: B: C: External: Internal: Request Mode Bus Mode Transfer Size Usable (Bits) Channels External device with DACK and external memory External B/C 8/16/32/64/32B 0, 1 (2, 3)* External device with DACK and memory-mapped external device External B/C 8/16/32/64/32B 0, 1 (2, 3)*6 External memory and external memory Internal*1 7 External* B/C 8/16/32/64/32B 0 to 3*5 *6 External memory and memory-mapped external device Internal*1 External*7 B/C 8/16/32/64/32B 0 to 3*5 *6 Memory-mapped external device and memory-mapped external device Internal*1 External*7 B/C 8/16/32/64/32B 0 to 3*5 *6 External memory and on-chip peripheral module Internal*2 B/C*3 8/16/32/64*4 0 to 3*5 *6 Memory-mapped external device and on-chip peripheral module Internal*2 B/C*3 8/16/32/64*4 0 to 3*5 *6 Type of Transfer 6 32-byte burst transfer Burst Cycle steal External request Auto-request or on-chip peripheral module request Notes: 1. External request, auto-request, or on-chip peripheral module request (TMU input capture interrupt request) possible. In the case of an on-chip peripheral module request, it is not possible to specify external memory data transfer with the SCI (SCIF) as the transfer request source. 2. Auto-request, or on-chip peripheral module request possible. If the transfer request source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or the transfer destination must be SCTDR1 (SCFTDR2). 3. When the transfer request source is the SCI (SCIF), only cycle steal mode can be used. Page 582 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 4. Access size permitted for the on-chip peripheral module register that is the transfer source or transfer destination. 5. When the transfer request is an external request, only channels 0 and 1 can be used. 6. In DDT mode, transfer requests can be accepted for all channels from external devices capable of DTR format output. 7. See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA transfer by means of an external request. (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode Transfer Source Transfer Destination Usable Address DMAC Mode Channels 1 Synchronous DRAM External device with DACK Single 0, 1 2 External device with DACK Synchronous DRAM Single 0, 1 3 SRAM-type, DRAM External device with DACK Single 0, 1 4 External device with DACK SRAM-type, DRAM Single 0, 1 5 Synchronous DRAM SRAM-type, MPX, PCMCIA Dual 0, 1 6 SRAM-type, MPX, PCMCIA Dual 0, 1 7 SRAM-type, DRAM, PCMCIA, MPX Dual 0, 1 8 SRAM-type, MPX, PCMCIA Dual 0, 1 Transfer Direction (Settable Memory Interface) * Synchronous DRAM SRAM-type, MPX, PCMCIA * * SRAM-type, DRAM, PCMCIA, MPX * "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: Memory interfaces on which transfer is possible in single address mode are SRAM, byte control SRAM, burst ROM, DRAM, and synchronous DRAM. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. * DACK output setting in dual address mode transfer (b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in DDT mode. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 583 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Transfer Destination Usable Address DMAC Mode Channels Single 0 to 3 Single 0 to 3 Dual 0 to 3 Transfer Direction (Settable Memory Interface) Transfer Source 1 1 Synchronous DRAM* External device with DACK 2 External device with DACK Synchronous DRAM 3 4 Synchronous DRAM SRAM-type, MPX, PCMCIA 5 SRAM-type, DRAM, PCMCIA, MPX 6 SRAM-type, MPX, PCMCIA SRAM-type, MPX, PCMCIA *2 Synchronous DRAM SRAM-type, MPX, PCMCIA *2 SRAM-type, DRAM, PCMCIA, MPX 2 * Dual 0 to 3 *2 Dual 0 to 3 Dual 0 to 3 "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. 1. In SH7750, the bus width must be 64 bits 2. DACK output setting in dual address mode transfer Bus Mode and Channel Priority Order When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set for channel 0. If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. Channel execution alternates in the order: channel 1 → channel 0 → channel 1 → channel 0. An example of round robin mode operation is shown in figure 14.11. Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends. Page 584 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group CPU DMAC CH1 DMAC CH1 DMAC channel 1 burst mode CPU Section 14 Direct Memory Access Controller (DMAC) DMAC CH0 DMAC CH1 DMAC CH0 CH0 CH1 CH0 DMAC channel 0 and channel 1 round robin mode DMAC CH1 DMAC CH1 DMAC channel 1 burst mode CPU CPU Legend: Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing) Figure 14.11 Bus Handling with Two DMAC Channels Operating Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the CPU during a break in requests. 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. See section 13, Bus State Controller (BSC), for details. DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest. When falling edge detection is selected for DREQ, the DMAC will recognize DREQ two cycles (CKIO) later because the signal must pass through the asynchronous input synchronization circuit. (There is a 1-cycle (CKIO) delay when low-level detection is selected.) The second and subsequent DREQ sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of single address mode). DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in the first cycle only, and so DRAK is output in the first cycle only . R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 585 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Operation: Figures 14.12 to 14.22 show the timing in each mode. 1. Cycle Steal Mode In cycle steal mode, The DREQ sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of DREQ. For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. For details of the timing for various kinds of memory access, see section 13, Bus State Controller (BSC). Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after the first DREQ sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle. Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the first DREQ sampling operation. The second sampling begins one cycle after the first assertion of DRAK. In single address mode, the DACK signal is output every DMAC transfer cycle. 2. Burst Mode, Dual Address Mode, Level Detection DREQ sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 3. Burst Mode, Single Address Mode, Level Detection DREQ sampling timing in burst mode using single address mode and level detection is shown in figure 14.20. Page 586 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle. In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. 4. Burst Mode, Dual Address Mode, Edge Detection In burst mode using dual address mode and edge detection, DREQ sampling is performed in the first cycle only. For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 5. Burst Mode, Single Address Mode, Edge Detection In burst mode using single address mode and edge detection, DREQ sampling is performed only in the first cycle. For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In single address mode, the DACK signal is output every DMAC transfer cycle. Suspension of DMA Transfer in Case of DREQ Level Detection With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which DMA transfer is being executed can judge from the rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating DREQ. In this case, the next DARK signal is not output. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 587 of 1076 Page 588 of 1076 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[63:0] A[25:0] CKIO 2nd acceptance Write Destination address DMAC : DREQ sampling and determination of channel priority Legend: CPU 1st acceptance Read Source address Bus locked CPU Read Source address DMAC Write Destination address Bus locked CPU Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[63:0] A[25:0] CKIO DMAC Write CPU Destination address 2nd acceptance : DREQ sampling and determination of channel priority Legend: CPU 1st acceptance Read Source address Bus locked DMAC Write CPU Destination address 3rd acceptance Read Source address Bus locked DMAC 4th acceptance Read Source address SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) Page 589 of 1076 Page 590 of 1076 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[63:0] A[25:0] CKIO 2nd acceptance Write Destination address DMAC-1 : DREQ sampling and determination of channel priority Legend: CPU 1st acceptance Read Source address Bus locked Read Write Destination address DMAC-2 Source address Bus locked CPU Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[63:0] A[25:0] CKIO Legend: : DREQ sampling and determination of channel priority CPU 1st acceptance Read Read DMAC-2 Write Destination address Bus locked Source address TE bit: transfer end Write Destination address DMAC-1 Source address Bus locked CPU SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) Page 591 of 1076 Page 592 of 1076 Bus cycle D[63:0] A[25:0] On-chip peripheral data bus On-chip peripheral address bus CKIO (Bcyc:Pcyc = 1:1) CPU Read Source address DMAC Write Destination address CPU Read Source address DMAC Write Destination address CPU Read Source address DMAC Write CPU Destination address Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 Bus cycle On-chip peripheral data bus On-chip peripheral address bus D[63:0] A[25:0] CKIO (Bcyc:Pcyc = 1:1) CPU Read T1 T2 Write CPU Destination address DMAC Source address Read T1 T2 Write CPU Destination address DMAC Source address Read T1 T2 Write Destination address DMAC Source address SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection) Page 593 of 1076 Page 594 of 1076 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[63:0] A[25:0] CKIO DMAC 2nd acceptance CPU Legend: : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC 3rd acceptance Read Source address CPU DMAC 4th acceptance Read Source address CPU DMAC Read Source address CPU Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[63:0] A[25:0] CKIO DMAC 2nd acceptance Legend: : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address CPU DMAC 3rd acceptance Read Source address CPU DMAC Read Source address CPU SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection) Page 595 of 1076 Page 596 of 1076 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[63:0] A[25:0] CKIO DMAC-1 2nd acceptance Legend: : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC-2 3rd acceptance Read Source address DMAC-3 Read Source address CPU 4th acceptance DMAC-4 Read Source address Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 DACK0 Bus cycle DRAK0 DREQ0 (edge detection) D[63:0] A[25:0] CKIO DMAC-1 Legend: : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC-2 DMAC-3 Read Source address TE bit: transfer end Read Source address DMAC-4 Read Source address CPU SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection) Page 597 of 1076 Page 598 of 1076 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[63:0] A[25:0] CKIO CPU Asserted 2 cycles before start of bus cycle 2nd acceptance D3 DMAC-1 D2 Legend: : DREQ sampling and determination of channel priority 1st acceptance D1 Destination address 3rd acceptance D1 Asserted 2 cycles before start of bus cycle D4 D3 DMAC-2 D2 Destination address D1 Asserted 2 cycles before start of bus cycle D4 D3 DMAC-3 D2 Destination address D4 CPU Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.3.6 Section 14 Direct Memory Access Controller (DMAC) Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer. 1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request) When a transfer end condition is satisfied, acceptance of DMAC transfer requests is suspended. The DMAC completes transfer for the transfer requests accepted up to the point at which the transfer end condition was satisfied, then stops. In cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, AutoRequest) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge detection, only the first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14.3.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 3. Burst Mode, Level Detection (External Request) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation in section 14.3.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 4. Transfer Suspension Bus Timing Transfer suspension is executed on completion of processing for one transfer unit. In dual address mode transfer, write cycle processing is executed even if a transfer end condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 599 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0. • The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1. End of transfer when DMATCR = 0 When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an interrupt (DMTE) request is sent to the CPU. Transfer ending when DMATCR = 0 does not follow the procedures described in 1 to 4 in section 14.3.6, Ending DMA Transfer. 2. End of transfer when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows the procedures described in 1 to 4 in section 14.3.6, Ending DMA Transfer. Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all channels simultaneously when either of the following conditions is satisfied: • The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is set to 1. • The DMA master enable bit (DME) in DMAOR is cleared to 0. 1. End of transfer when AE = 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. Therefore, when AE is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the AE bit after first reading 1 from it. Acceptance of external requests is suspended while AE is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. Page 600 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1 from it. As in the case of AE being set to 1, acceptance of external requests is suspended while NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. End of transfer when DME = 0 in DMAOR If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. When resuming transfer, DME must be set to 1. Operation will then be resumed from the next transfer. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 601 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group 14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions Register Set Value Transfer source: external memory SAR1 H'0C000000 Transfer source: external device with DACK DAR1 (Accessed by DACK) Number of transfers: 32 DMATCR1 H'00000020 Transfer source address: decremented CHCR1 H'000022A5 DMAOR H'00000201 Transfer destination address: (setting invalid) Transfer request source: external pin (DREQ1) edge detection Bus mode: burst Transfer unit: word No interrupt request at end of transfer Channel priority order: 2 > 0 > 1 > 3 Page 602 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC. Figure 14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins). DMAC DDT Memory SAR0 DAR0 DREQ0–3 ddtmode tdack id[1:0] Request ddtmode controller bavl TR BAVL DBREQ BSC Data buffer Address bus CHCR0 Data bus Data buffer DMATCR0 External device (with DTR DBREQ, BAVL, TR, TDACK, and ID [1:0]) TDACK ID[1:0] FIFO or memory Figure 14.23 On-Demand Transfer Mode Block Diagram For channels 0 to 3, after making the settings for normal DMA transfer using the CPU, a transfer request can be issued from an external device using the DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR signals (handshake protocol using the data bus). A transfer request can also be issued simply by asserting TR, without using the external bus (handshake protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a transfer request can be issued directly from an external device (with DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins) by asserting DBREQ and TR simultaneously. Note: DTR format = Data transfer request format In DDT mode, there is a choice of five modes for performing DMA transfer. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 603 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group 1. Normal data transfer mode (channel 0) BAVL (the data bus available signal) is asserted in response to DBREQ (the data bus request signal) from an external device. Two CKIO-synchronous cycles after BAVL is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with TR (the transfer request signal). The initial settings are then made in the DMAC channel 0 control register, and the DMA transfer is processed. 2. Normal data transfer mode (channels 1 to 3) In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA transfer requests only are performed from the external device. As in 1 above, DBREQ is asserted from the external device and the external bus is secured, then the DTR format is driven. The transfer request channel can be specified by means of the two ID bits in the DTR format. 3. Handshake protocol using the data bus (valid for channel 0 only) This mode is only valid for channel 0. After the initial settings have been made in the DMAC channel 0 control register by means of normal data transfer mode (channel 0) in the SH7750, or after the initial settings have been made in the DMAC channel 0 control register from the CPU or by means of normal data transfer mode (channel 0) in the SH7750S, the DDT module asserts a data transfer request for the DMAC by setting DTR format ID = 00, MD = 00, and SZ ≠ 101 or 110, and driving the DTR format. 4. Handshake protocol without use of the data bus The DDT module includes a function for recording the previously asserted request channel. By using this function, it is possible to assert a transfer request for the channel for which a request was asserted immediately before, by asserting TR only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the DMAC control register (DTR format and data transfer setting by the CPU in the DMAC). 5. Direct data transfer mode (valid for channel 2 only) A data transfer request can be asserted for channel 2 by asserting DBREQ and TR simultaneously from an external device after the initial settings have been made in the DMAC channel 2 control register. Page 604 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.5.2 Section 14 Direct Memory Access Controller (DMAC) Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. DBREQ/DREQ0 BAVL/DRAK0 TR/DREQ1 TDACK/DACK0 SH7750, SH7750S, SH7750R ID1, ID0/DRAK1, DACK1 External device CKIO D63–D0=DTR A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode • DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR format) or a DMA request from an external device to the DMAC If there is a wait for release of the data bus, an external device can have the data bus released by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL. • BAVL: Data bus D63–D0 release signal Assertion of BAVL means that the data bus will be released two cycles later. This LSI does not switch the data pins to output status for a total of three cycles: the cycle in which the data bus is released and the cycles preceding and following it. • TR: Transfer request signal Assertion of TR has the following different meanings. ⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same time the DTR format is output, two cycles after BAVL is asserted. ⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a transfer request to be issued for the channel for which a transfer request was made immediately before. This function can be used only when BAVL is not asserted two cycles earlier. ⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request can be made to channel 2 by asserting DBREQ and TR simultaneously. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 605 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group • TDACK: Reply strobe signal for external device from DMAC The assert timing of this signal is the same as the DACKn assert timing of the memory interfaces. Note that it is a low active signal. • ID1, ID0: Channel number notification signals ⎯ 00: Channel 0 (means demand data transfer) ⎯ 01: Channel 1 ⎯ 10: Channel 2 ⎯ 11: Channel 3 Data Transfer Request Format 63 61 60 59 SZ ID 57 MD 55 48 COUNT (Reserved) 31 0 ADDRESS R/W Figure 14.25 Data Transfer Request Format The data transfer request format (DTR format) consists of 64 bits, with connection to D[63:0]. In the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, the transfer data size, read/write access, channel number, transfer request mode, number of transfers, and transfer source or transfer destination address are specified. A specification in bits 47–32 is invalid. In the SH7750, only single address mode can be set in normal data transfer mode (channel 0). With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01, SM[1:0] = 01, RS[3:0] = (0010: R/W = 0, 0011: R/W = 1), TM = (0: MD = 11, 1: MD = 01, 10), TS[2:0] = (SZ), and IE = 0 settings are made in DMA channel control register 0, COUNT is set in transfer count register 0, and ADDRESS is set in source/destination address register 0. Therefore, in DDT mode, the above control registers cannot be written to by the CPU, but can be read. In the SH7750S, DMAC control registers CHCR0, SAR0, DAR0, and DMATCR0 can be written to and read by the CPU even in normal data transfer mode (channel 0). Caution is necessary in this case, as a DMAC control register written to by the CPU will be overwritten by a subsequent transfer request (MD[1:0] = 01, 10, or 11) using the DTR format. Page 606 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Bits 63 to 61: Transmit Size (SZ2–SZ0) • 000: Byte size (8-bit) specification • 001: Word size (16-bit) specification • 010: Longword size (32-bit) specification • 011: Quadword size (64-bit) specification • 100: 32-byte block transfer specification • 101: Setting prohibited • 110: Request queue clear specification • 111: Transfer end specification Bit 60: Read/Write (R/W) • 0: Memory read specification • 1: Memory write specification Bits 59 and 58: Channel Number (ID1, ID0) • 00: Channel 0 (demand data transfer) • 01: Channel 1 • 10: Channel 2 • 11: Channel 3 Bits 57 and 56: Transfer Request Mode (MD1, MD0) • 00: Handshake protocol (data bus used) • 01: Burst mode (edge detection) specification • 10: Burst mode (level detection) specification • 11: Cycle steal mode specification Bits 55 to 48: Transfer Count (COUNT7–COUNT0) • Transfer count: 1 to 255 • 00000000: Maximum number of transfers (16M) Bits 47 to 32: Reserved Bits 31 to 0: Address (ADDRESS31–ADDRESS0) • R/W = 0: Transfer source address specification • R/W = 1: Transfer destination address specification Notes: 1. Only the ID field is valid for channels 1 to 3. 2. To start DMA transfer by means of demand data transfer on channel 0, the initial value of MD in the DTR format must be 01, 10, or 11. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 607 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group 3. The COUNT field is ignored if MD = 00. 4. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst mode and cycle steal mode, a handshake protocol is used to transfer each unit of data. 5. The maximum number of transfers can be specified by setting COUNT = 0 as DTR format initialization data. If the amount of data to be transferred is unknown, set COUNT = 0, start DMA transfer, and transfer the DTR format (ID = 00, MD ≠ 00, SZ = 111) when the required amount of data has been transferred. This will terminate DMA transfer on channel 0. In this case, the TE bit in DMA channel control register 0 is not set, but transfer cannot be restarted. 6. When port functions are used (BCR2.PORTEN = 1) and DDT mode is selected, input the DTR format for D[63:52] and D[31:0]. In this case, if ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110. 7. For DTR format transfer when ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110. 14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer. On channels 1 to 3, output a transfer request from an external device by means of the DTR format (ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains in the request queue and a transfer is completed, the request queue retains it. When another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant. Page 608 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 Tb Tg tRASD Tj Tk Tl tAD Tm Tn R01UH0456EJ0702 Rev. 7.02 ID1–ID0 TDACK TR BAVL DBREQ BS D63–D0 (READ) DQMn CASn RAS RD/WR CSn tBAVD tTRS tBAVD tRASD tTRH To Tp tRDS tIDD tTDAD tBSD tCASD2 tDQMD [2CKIO cycle - tDTRS] ( 18ns F100MHz) DTR 1CKIO cycle (10ns F100MHz) tCASD2 tRWD tCSD c1 tDTRH Ti Row Th Address tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Ta BANK CKIO tBSD tRDH c2 Ts c3 tDQMD Tr DMAC Channel c1 Tq c4 Tu tIDD tTDAD tCSD tAD Tt Tv Tw SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001) Page 609 of 1076 Page 610 of 1076 Tb Tg tRASD Tj Tk Tl tAD Tm Tn ID1–ID0 TDACK TR BAVL DBREQ BS D63–D0 (READ) DQMn CASn RAS RD/WR CSn tBAVD tTRS tBAVD tBSD tTRH tIDD tCASD2 tBSD tWDD c2 DMAC Channel tTDAD c1 To tRWD tDQMD [2CKIO cycle - tDTRS] (18ns F100MHz) DTR 1CKIO cycle (10ns 100MHz) tWDD tCASD2 tRASD tRWD tCSD c1 tDTRH Ti Row Th Address tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Ta BANK CKIO c4 tIDD tTDAD c3 Tp Tr tDQMD tCSD tAD Tq Ts Tt Tu Tv Tw Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 Tg tRASD Tj Tk Tl tAD Tm Tn R01UH0456EJ0702 Rev. 7.02 ID1-ID0 TDACK TR BAVL DBREQ BS D63-D0 (READ) DQMn CASn RAS RD/WR CSn tBAVD tTRS tBAVD tRASD tTRH To Tp tRDS tBSD tCASD2 tDQMD [2CKIO cycles - tDTRS] (= 18ns: 100MHz) DTR= 1CKIO cycle (= 10ns: 100MHz) tCASD2 tRWD tCSD c1 tDTRH Ti Row Th Addr tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Tb BANK CKIO Ta tBSD tRDH c2 Ts c3 tDQMD Tr DMAC Channel c1 Tq c4 tCSD tAD Tt DMAC Channel tTDAD tTDAD SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer Page 611 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ BAVL TR A25–A0 D63–D0 RAS, CAS, WE RA CA D0 DTR BA D1 D2 D3 RD TDACK ID1, ID0 00 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Page 612 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR RA A25–A0 D63–D0 RAS, CAS, WE CA D0 DTR BA D1 D2 D3 D4 D5 WT TDACK ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 613 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK A25–A0 D63–D0 RAS, CAS, WE RA CA DTR CA D0 BA RD CA D1 RD RD DQMn ID1, ID0 00 00 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Page 614 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR RA A25–A0 D63–D0 RAS, CAS, WE DTR BA CA CA D0 D1 WT WT DQMn TDACK ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 615 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ BAVL TR A25–A0 D63–D0 CA DTR MD = 10 or 11 CMD D0 CA D1 D2 D3 DTR MD = 00 WT D0 D1 WT TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Page 616 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 D63–D0 CA DTR MD = 10 or 11 CMD D0 CA D1 D2 D3 D0 WT D1 D2 D3 WT TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 617 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ BAVL TR RA A25–A0 CA D0 D63–D0 RAS, CAS, WE BA D1 D2 D3 RD Figure 14.35 Read from Synchronous DRAM Precharge Bank CLK DBREQ Transfer requests can be accepted BAVL TR RA A25–A0 CA D63–D0 RAS, CAS, WE D0 PCH BA D1 D2 D3 RD Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Page 618 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA D0 D63–D0 RAS, CAS, WE D1 D2 D3 RD Figure 14.37 Read from Synchronous DRAM (Row Hit) CLK DBREQ BAVL TR A25–A0 RA D0 D63–D0 RAS, CAS, WE CA BA D1 D2 D3 WT Figure 14.38 Write to Synchronous DRAM Precharge Bank R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 619 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ Transfer requests can be accepted BAVL TR RA A25–A0 CA D63–D0 RAS, CAS, WE D0 BA PCH D1 D2 D3 WT Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CLK A25–A0 CA D63–D0 D0 RAS, CAS, WE WT D1 D2 D3 Figure 14.40 Write to Synchronous DRAM (Row Hit) Page 620 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR RA A25–A0 D63–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 621 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group DMA Operation Register (DMAOR) 31 15 9 8 2 4 PR[1:0] DDT AE NMIF COD (SH7750S) DDT: 0: Normal DMA mode 1: On-demand data transfer mode 1 0 DME Figure 14.42 DDT Mode Setting CLK DBREQ BAVL No DMA request sampling TR A25–A0 CA DTR MD = 01 D63–D0 CMD D0 WT CA D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT TDACK ID1, ID0 Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device → External Bus Data Transfer Page 622 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL Wait for next DMA request TR CA A25–A0 D63–D0 DTR MD = 10 CMD CA D0 RD D1 D2 D3 D0 D1 D2 D3 RD TDACK ID1, ID0 Start of data transfer Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus → External Device Data Transfer R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 623 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ BAVL TR A25–A0 D63–D0 CMD CA CA D0 DTR MD = 01 RD CA Idle cycle RD D2 Idle cycle D3 Idle cycle RD DQMn TDACK ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer Page 624 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 D63–D0 CA DTR MD = 01 CMD DQMn CA CA D0 D1 D3 WT WT WT Idle cycle Idle cycle Idle cycle TDACK ID1, ID0 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 625 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group CLK DBREQ BAVL TR A25–A0 D63–D0 RA CA DTR D0 D1 D2 D3 ID = 1, 2, or 3 RAS, CAS, WE BA RD TDACK ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus Page 626 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 D0 RAS, CAS, WE BA D1 D2 D3 D4 D5 D6 D7 RD TDACK ID1, ID0 10 No DTR cycle, so requests can be made at any time Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 627 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 5th 4th No more requests A25–A0 RA CA D0 D63–D0 RAS, CAS, WE BA RD CA CA D1 RD D2 D3 D0 D1 D2 D3 D0 RD D1 D2 NOP ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Page 628 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 5th 4th DBREQ BAVL TR A25–A0 RA D0 D63–D0 RAS, CAS, WE CA BA WT CA CA D1 D2 D3 D0 WT D1 D2 D3 D0 WT CA D1 D2 D3 WT TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 629 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Handshaking is necessary to send additional requests Four requests can be queued CLK 1st 2nd 3rd 5th 4th DBREQ BAVL TR A25–A0 CA D0 D63–D0 RAS, CAS, WE CA RD D1 RD CA D2 D3 D0 D1 RD CA D2 D3 D0 D1 D2 RD TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Page 630 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th DBREQ BAVL TR A25–A0 CA D63–D0 D0 RAS, CAS, WE WT CA CA D1 D2 D3 D0 WT D1 D2 D3 D0 WT CA D1 D2 D3 WT TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 14.5.4 Notes on Use of DDT Module 1. Normal data transfer mode (channel 0) Initial settings for channel 0 demand transfer must be DTR.ID = 00 and DTR.MD = 01, 10, or 11. In this case, only single address mode can be set for channel 0. 2. Normal data transfer mode (channels 1 to 3) If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored. 3. Handshake protocol using the data bus (valid on channel 0 only) a. The handshake protocol using the data bus can be executed only on channel 0. (Set DTR.ID = 00, DTR.MD = 00, DTR.SZ ≠ 101 or 110. Operation is not guaranteed if settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ = 101 or 110 are made.) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 631 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group b. If, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that DMA transfer is executed settings of DTR.ID = 00, DTR.MD = 00, and DTR, SZ ≠ 101.110 are input in the handshake protocol using the data bus, a transfer request will be asserted for channel 0. c. In the SH7750S and SH7750R, initial settings can be made in the DMAC channel 0 control register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101 or 110 are subsequently input, a transfer request to channel 0 will be asserted. 4. Handshake protocol without use of the data bus a. With the handshake protocol without use of the data bus, a DMA transfer request can be input to the DMAC again for the channel for which transfer was requested immediately before by asserting TR only. b. When using the handshake protocol without use of the data bus, first make the necessary settings in the DMAC control registers. c. When not using the handshake protocol without use of the data bus, if TR only is asserted without outputting DTR, a request will be issued for the channel for which DMA transfer was requested immediately before. Also, if the first DMA transfer request after a power-on reset is input by asserting TR only, it will be ignored and the DMAC will not operate. d. If TR only is asserted by means of the handshake protocol without use of the data bus and a DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE = 1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1. 5. Direct data transfer mode (valid on channel 2 only) a. If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and TR during DMA transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is space in the DDT channel 2 request queue. b. In direct data transfer mode (with DBREQ and TR asserted simultaneously), DBREQ is not interpreted as a bus arbitration signal, and therefore the BAVL signal is never asserted. 6. Request queue transfer request acceptance a. The DDT has four request queues for each of channels 1 to 3. When these request queues are full, a DMA transfer request from an external device will be ignored. b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished (burst mode) or that a DMA bus cycle is not in progress (cycle steal mode). Page 632 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 7. DTR format a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows. When DTR.ID= 00 • MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus • MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request) • MD ≠ 10, SZ = 110: DDT request queue clear When DTR.ID ≠ 00 • Transfer request to channels 1—3 (items other than ID ignored) 8. Data transfer end request a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set in CHCR0, SAR0, DAR0, and DMATCR0 are retained. With the SH7750, execution cannot be restarted from an external device in this case. To restart execution in the SH7750S and SH7750R, set CHCR0.DE = 1 with an MOV instruction. 9. Request queue clearance a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are all cleared. All external requests held on the DMAC side are also cleared. b. In case 4-d, the DMAC freeze state can be cleared. c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in case 11, the DMAC freeze state can be cleared. 10. DBREQ assertion a. After DBREQ is asserted, do not assert DBREQ again until BAVL is asserted, as this will result in a discrepancy between the number of DBREQ and BAVL assertions. b. The BAVL assertion period due to DBREQ assertion is one cycle. If a row address miss occurs in a read or write in the non-precharged bank during synchronous DRAM access, BAVL is asserted for a number of cycles in accordance with the RAS precharge interval set in BSC.MCR.TCP. c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an external device. If a row address miss occurs at this time in a read or write in the nonprecharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ signal asserted by the external device is ignored. Therefore, BAVL is not asserted again due to this signal. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 633 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group 11. Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode, the DMAC will freeze. This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT mode. 12. Confirming DMA transfer requests and number of transfers executed The channel associated with a DMA bus cycle being executed in response to a DMA transfer request can be confirmed by determining the level of external pins ID1 and ID0 at the rising edge of the CKIO clock while TDACK is asserted. (ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3) 14.6 Configuration of the DMAC (SH7750R) 14.6.1 Block Diagram of the DMAC Figure 14.53 is a block diagram of the DMAC in the SH7750R. Page 634 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) On-chip peripheral module Internal bus Peripheral bus DMAC module Count control SARn Registr control DARn DMATCRn Activation control CHCRn DMAOR TMU SCI, SCIF Request priority control queclr0–7 Bus interface DACK0, DACK1 DRAK0, DRAK1 External address/on-chip peripheral module address dmaqueclr0-7 DREQ0, DREQ1 32B data buffer BAVL/ID2 D[63:0] Bus state controller External bus 8 SAR0, DAR0, DMATCR0, CHCR0 only Request DDT module DTR command buffer Request controller CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 TR DBREQ DBREQ DDTMODE BAVL DDTD ID[1:0] 48 bits TDACK id[2:0] Legend: DMAORn: SARn: DARn: DMATCRn: CHCRn: Note: DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register tdack n = 0 to 7 Figure 14.53 Block Diagram of the DMAC R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 635 of 1076 Section 14 Direct Memory Access Controller (DMAC) 14.6.2 SH7750, SH7750S, SH7750R Group Pin Configuration (SH7750R) Tables 14.11 and 14.12 show the pin configuration of the DMAC. Table 14.11 DMAC Pins Channel Pin Name Abbreviation I/O Function 0 DMA transfer request DREQ0 Input DMA transfer request input from external device to channel 0 DREQ acceptance confirmation DRAK0 Output Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution 1 DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification Page 636 of 1076 DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Table 14.12 DMAC Pins in DDT Mode Pin Name Abbreviation I/O Function Data bus request DBREQ (DREQ0) Input Data bus release request from external device for DTR format input Data bus available BAVL/ID2 (DRAK0) Output Data bus release notification Data bus can be used 2 cycles after BAVL is asserted Notification of channel number to external device at same time as TDACK output Transfer request signal TR (DREQ1) Input If asserted 2 cycles after BAVL assertion, DTR format is sent Only TR asserted: DMA request DBREQ and TR asserted simultaneously: Direct request to channel 2 DMAC strobe TDACK (DACK0) Output Reply strobe signal for external device from DMAC Channel number notification ID[1:0] (DRAK1, DACK1) Output Notification of channel number to external device at same time as TDACK output (ID [1] = DRAK1, ID [0] = DACK1) Requests for DMA transfer from external devices are normally accepted only on channel 0 (DREQ0) and channel 1 (DREQ1). In DDT mode, the BAVL pin functions as both the data-busavailable pin and channel-number-notification (ID2) pin. 14.6.3 Register Configuration (SH7750R) Table 14.13 shows the configuration of the DMAC's registers. The DMAC of the SH7750R has a total of 33 registers: four registers are assigned to each channel, and there is a control register for the overall control of the DMAC. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 637 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.13 Register Configuration Channel Name 0 1 2 3 Common Abbreviation Read/ Write Initial Value P4 Address Area 7 Address Access Size 2 Undefined H'FFA00000 H'1FA00000 32 2 Undefined H'FFA00004 H'1FA00004 32 2 Undefined H'FFA00008 H'1FA00008 32 1 2 DMA source address SAR0 register 0 R/W* DMA destination address register 0 DAR0 R/W* DMA transfer count register 0 DMATCR0 R/W* DMA channel control register 0 CHCR0 R/W* * H'00000000 H'FFA0000C H'1FA0000C 32 DMA source address SAR1 register 1 R/W Undefined H'FFA00010 H'1FA00010 32 DMA destination address register 1 DAR1 R/W Undefined H'FFA00014 H'1FA00014 32 DMA transfer count register 1 DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32 DMA channel control register 1 CHCR1 R/W* H'00000000 H'FFA0001C H'1FA0001C 32 DMA source address SAR2 register 2 R/W Undefined H'FFA00020 H'1FA00020 32 DMA destination address register 2 DAR2 R/W Undefined H'FFA00024 H'1FA00024 32 DMA transfer count register 2 DMATCR2 R/W Undefined H'FFA00028 H'1FA00028 32 DMA channel control register 2 CHCR2 R/W* H'00000000 H'FFA0002C H'1FA0002C 32 DMA source address SAR3 register 3 R/W Undefined H'FFA00030 H'1FA00030 32 DMA destination address register 3 DAR3 R/W Undefined H'FFA00034 H'1FA00034 32 DMA transfer count register 3 DMATCR3 R/W Undefined H'FFA00038 H'1FA00038 32 DMA channel control register 3 CHCR3 R/W* 1 H'00000000 H'FFA0003C H'1FA0003C 32 DMA operation register DMAOR R/W* 1 H'00000000 H'FFA00040 H'1FA00040 32 Page 638 of 1076 1 1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Channel Name 4 5 6 7 Abbreviation Section 14 Direct Memory Access Controller (DMAC) Read/ Write Initial Value P4 Address Area 7 Address Access Size DMA source address SAR4 register 4 R/W Undefined H'FFA00050 H'1FA00050 32 DMA destination address register 4 DAR4 R/W Undefined H'FFA00054 H'1FA00054 32 DMA transfer count register 4 DMATCR4 R/W Undefined H'FFA00058 H'1FA00058 32 DMA channel control register 4 CHCR4 R/W* H'00000000 H'FFA0005C H'1FA0005C 32 DMA source address SAR5 register 5 R/W Undefined H'FFA00060 H'1FA00060 32 DMA destination address register 5 DAR5 R/W Undefined H'FFA00064 H'1FA00064 32 DMA transfer count register 5 DMATCR5 R/W Undefined H'FFA00068 H'1FA00068 32 DMA channel control register 5 CHCR5 R/W* H'00000000 H'FFA0006C H'1FA0006C 32 DMA source address SAR6 register 6 R/W Undefined H'FFA00070 H'1FA00070 32 DMA destination address register 6 DAR6 R/W Undefined H'FFA00074 H'1FA00074 32 DMA transfer count register 6 DMATCR6 R/W Undefined H'FFA00078 H'1FA00078 32 DMA channel control register 6 CHCR6 R/W* H'00000000 H'FFA0007C H'1FA0007C 32 DMA source address SAR7 register 7 R/W Undefined H'FFA00080 H'1FA00080 32 DMA destination address register 7 DAR7 R/W Undefined H'FFA00084 H'1FA00084 32 DMA transfer count register 7 DMATCR7 R/W Undefined H'FFA00088 H'1FA00088 32 DMA channel control register 7 CHCR7 R/W* H'00000000 H'FFA0008C H'1FA0008C 32 1 1 1 1 Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. 1. Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. 2. In the SH7750R, writes from the CPU and writes from external I/O devices using the DTR format are possible in DDT mode. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 639 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group 14.7 Register Descriptions (SH7750R) 14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA source address registers 0−7 (SAR0−SAR7) are 32-bit readable/writable registers that specify the source address for a DMA transfer. The functions of these registers are the same as on the SH7750 or SH7750S. For more information, see section 14.2.1, DMA Source Address Registers 0−3 (SAR0−SAR3). 14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA destination address registers 0−7 (DAR0−DAR7) are 32-bit readable/writable registers that specify the destination address for a DMA transfer. The functions of these registers are the same as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination Address Registers 0−3 (DAR0−DAR3). Page 640 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.7.3 Section 14 Direct Memory Access Controller (DMAC) DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA transfer count registers 0−7 (DMATCR0−DMATCR7) are 32-bit readable/writable registers that specify the number of transfers in transfer operations for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Functions of these registers are the same as the transfer-count registers of the SH7750 or SH7750S. For more information, see section 14.2.3, DMA Transfer Count Registers 0−3 (DMATCR0−DMATCR3). 14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) Bit: 31 30 29 28 27 26 25 24 SSA SSA SSA STC DSA DSA DSA DTC 2 1 0 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 — — — — DS RL AM AL 0 0 0 0 0 0 0 0 R R R R 6 5 4 7 TM 0 R/W (R/W) R/W (R/W) 3 2 1 0 IE TE DE 0 0 0 0 R/( W) R/W R/( W) R/W TS2 TS1 TS0 QCL 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA channel control registers 0−7(CHCR0−CHCR7) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31−28 and 27−24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 641 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group about the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller (BSC). No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should always be 0. These bits are always read as 0. These registers are initialized to H'00000000 by a power-on or manual reset. Their values are retained in standby, sleep, and deep-sleep modes. Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2SSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the DSA2−DSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0. Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of DREQ) is an active-high or active-low output. Page 642 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. (DDT mode: TDACK) For details of the settings, see the description of the AM bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For details of the settings, see the description of the DM1 and DM0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. For details of the settings, see the description of the RS3−RS0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size (access size). For details of the settings, see the description of the TS2−TS0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 643 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Bit 3⎯Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. This bit is only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1. CHCR Bit 3 QCL 0 Description This bit is always read as 0. (Initial value) Writing a 0 to this bit is invalid. 1 When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the DDT side and any external requests stored in the DMAC. The written value is not retained. Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). For details of the settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Page 644 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.7.5 Section 14 Direct Memory Access Controller (DMAC) DMA Operation Register (DMAOR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — 0 0 0 0 R R R R DDT DBL Initial value: 0 0 R/W: R/W R/W PR1 PR0 0 0 R/W R/W 7 6 5 4 3 2 1 0 — — — — — AE NMIF DME 0 0 0 0 0 0 0 0 R R R R R R/(W) R/(W) R/W DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0. Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 14⎯Number of DDT-Mode Channels (DBL): Selects the number of channels that are able to accept external requests in DDT mode. Bit 14: DBL Description 0 Four DDT-mode channels 1 Eight DDT-mode channels (Initial value) Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests. When DMAOR.DBL = 1, one channel can be selected from among channels 0−7 by the combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the channel selection by DTR format in the DDT mode. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 645 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1) DTR.ID[1:0] DTR.SZ[2:0] ≠ 101 DTR.SZ[2:0] = 101 00 CH0 CH4 01 CH1 CH5 10 CH2 CH6 11 CH3 CH7 63 61 60 59 58 57 56 55 SZ R/W ID MD 4847 COUNT 32 31 (Reserved) 0 ADDRESS Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. DMAOR Bit 9 DMAOR Bit 8 PR1 PR0 Description 0 0 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 0 1 CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 1 0 CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 1 1 Round robin mode (Initial value) Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR) Page 646 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the DME bit in section 14.2.5, DMA Operation Register (DMAOR) 14.8 Operation (SH7750R) Operation specific to the SH7750R is described here. For details of operation, see section 14.3, Operation. 14.8.1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode, the DMAC always operates with eight channels, and external requests are only accepted on channel 0 (DREQ) and channel 1 (DREQ1). After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR, DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends when the transfer-end condition is satisfied. There are three modes for transfer requests: autorequest, external request, and on-chip peripheral module request. The addressing modes for DMA transfer are the single-address mode and the dual-address mode. Bus mode is selectable between burst mode and cycle steal mode. 14.8.2 Channel Specification for DDT-Mode DMA Transfer For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels. External requests are accepted on channels 0−3 when DMAOR.DBL = 0, and on channels 0−7 when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in section 14.7.5, DMA Operation Register (DMAOR). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 647 of 1076 Section 14 Direct Memory Access Controller (DMAC) 14.8.3 SH7750, SH7750S, SH7750R Group Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode (DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion) assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.15). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), it is important to note that the BAVL pin has the two functions as shown in table 14.16. Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode BAVL/ID2 ID[1:0] Transfer Channel 1 00 CH0 01 CH1 10 CH2 11 CH3 0 00 CH4 01 CH5 10 CH6 11 CH7 Table 14.16 Function of BAVL Function of BAVL TDACK = High Bus available TDACK = Low Notification of channel number (ID2) Page 648 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 14.8.4 Section 14 Direct Memory Access Controller (DMAC) Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1. Table 14.17 shows the DTR format settings for clearing request queues. Table 14.17 DTR Format for Clearing Request Queues DMAOR.DBL DTR.ID DTR.MD DTR.SZ DTR.COUNT[7:4] Description 0 10 110 * Clear the request queues of all channels (1−7). 00 Clear the CH0 request-accepted flag 11 1 00 10 Setting prohibited 110 * Clear the request queues of all channels (1−7). Clear the CH0 request-accepted flag. 11 0001 Clear the CH0 request-accepted flag 0010 Clear the CH1 request queues. 0011 Clear the CH2 request queues. 0100 Clear the CH3 request queues. 0101 Clear the CH4 request queues. 0110 Clear the CH5 request queues. 0111 Clear the CH6 request queues. 1000 Clear the CH7 request queues. Note: (SH7750R) DTR.SZ = DTR[63:61], DTR.ID = DTR[59:58], DTR.MD = DTR[57:56], DTR.COUNT[7:4] = DTR[55:52] 14.8.5 Interrupt-Request Codes When the number of transfers specified in DMATCR has been finished and the interrupt request is enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each channel. Table 14.18 lists the interrupt-request codes that are associated with these transfer-end interrupts. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 649 of 1076 Section 14 Direct Memory Access Controller (DMAC) SH7750, SH7750S, SH7750R Group Table 14.18 DMAC Interrupt-Request Codes Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer-end interrupt H'640 High DMTE1 CH1 transfer-end interrupt H'660 DMTE2 CH2 transfer-end interrupt H'680 DMTE3 CH3 transfer-end interrupt H'6A0 DMTE4 CH4 transfer-end interrupt H'780 DMTE5 CH5 transfer-end interrupt H'7A0 DMTE6 CH6 transfer-end interrupt H'7C0 DMTE7 CH7 transfer-end interrupt H'7E0 DMAE Address error interrupt H'6C0 Low Note: DMTE4−DMTE7: These codes are not used in the SH7750 or SH7750S. CKIO DBREQ BAVL/ID2 TR RA A25–A0 D63–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Page 650 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL/ID2 TR RA A25–A0 D63–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 651 of 1076 Section 14 Direct Memory Access Controller (DMAC) 14.9 SH7750, SH7750S, SH7750R Group Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7750 or SH7750S or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0–DMATCR7, and CHCR0–CHCR7 in the SH7750R, first clear the DE bit for the relevant channel. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating. Confirmation method when DMA transfer is not executed correctly: With the SH7750 and SH7750S, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR3, and DMATCR0–DMATCR3. With the SH7750R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR7, and DMATCR0–DMATCR7. If NMIF was set before the transfer, the DMATCR transfer count will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR0–CHCR3 in the SH7750 or SH7750S or CHCR0–CHCR7 in the SH7750R, the DMATCR value will indicate the remaining number of transfers. Also, the next addresses to be accessed can be found by reading SAR0–SAR3 and DAR0– DAR3 in the SH7750 or SH7750S or SAR0–SAR7 and DAR0–DAR7 in the SH7750R. If the AE bit has been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. Either check that TE = 1 in the SH7750 or SH7750S's CHCR0–CHCR3 or in the SH7750R's CHCR0–CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, CCN, BSC, or UBC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the relevant channel before setting DE to 1 in CHCR, or make the register settings with DE cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1 in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. Page 652 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 14 Direct Memory Access Controller (DMAC) 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set. 9. In external request (DREQ) edge detection in the SH7750R, an external request that has been accepted can be cancelled in the following way. Firstly, negate DREQ and change the value of CHCR.DS from 1 to 0. After that, set the CHCR.DS bit back to 1, then assert DREQ. (Though the SH7750R does not have a DMAOR.COD bit, similar to when the DMAOR.COD bit is 1 in the SH7750S, external requests that have once been accepted can be cancelled when the external request (DREQ) edge is detected.) 10. SH7750 Only: When a DMA transfer is performed between an on-chip peripheral module and external memory, the data may not be transferred correctly if the following conditions apply. To work around this problem, use the CPU to transfer the data. ⎯ Conditions Under which Problem Occurs a. Big endian is selected. b. The external memory bus width is 32 bits. c. Data is being transferred from an on-chip peripheral module*1 to external memory. d. The transmit size*2 of the data to be transferred is 32 bits. Conditions a. to d. must all be satisfied. ⎯ Description of Problem When transferring data from an on-chip peripheral module, bits 15 to 8 of the 32-bit data become misaligned. As a result, the data is not transferred correctly. Data that should be transferred: 12 34 56 78 Data actually transferred to external memory: 12 34 12 78 Notes: 1. The registers corresponding to the above conditions are the following. TMU.TCOR0 TMU.TCNT0 TMU.TCOR1 TMU.TCNT1 TMU.TCOR2 TMU.TCNT2 TMU.TCPR2 H-UDI.SDDR 2. Set by the transmit size bits in the DMA channel control register. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 653 of 1076 Section 14 Direct Memory Access Controller (DMAC) Page 654 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI is equipped with a single-channel serial communication interface (SCI) and a singlechannel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. The SCI supports a smart card interface. This is a serial communication function supporting a subset of the ISO/IEC 7816-3 (identification cards) standard. For details, see section 17, Smart Card Interface. The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO registers for both transmission and reception. For details, see section 16, Serial Communication Interface with FIFO (SCIF). 15.1.1 Features SCI features are listed below. • Choice of synchronous or asynchronous serial communication mode ⎯ Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: A break can be detected by reading the RxD pin level directly from the serial port register (SCSPTR1) when a framing error occurs. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 655 of 1076 Section 15 Serial Communication Interface (SCI) • • • • • SH7750, SH7750S, SH7750R Group ⎯ Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. On-chip baud rate generator allows any bit rate to be selected. Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive-error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer. When not in use, the SCI can be stopped by halting its clock supply to reduce power consumption. Page 656 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 15.1.2 Section 15 Serial Communication Interface (SCI) Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 TxD Parity generation SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control Internal data bus SCBRR1 Pck Baud rate generator Pck/4 Pck/16 Pck/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI Legend: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 15.1 Block Diagram of SCI R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 657 of 1076 Section 15 Serial Communication Interface (SCI) 15.1.3 SH7750, SH7750S, SH7750R Group Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation I/O Function Serial clock pin Receive data pin MD0/SCK I/O Clock input/output RxD Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection, can be set in the SCI's SCSPTR1 register. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. With the exception of the serial port register, the SCI registers are initialized in standby mode and in the module standby state as well as after a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Page 658 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Table 15.2 SCI Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 1 Serial status register SCSSR1 R/(W)* H'84 H'FFE00010 H'1FE00010 8 Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 R/W H'00*2 H'FFE0001C H'1FE0001C 8 Serial port register SCSPTR1 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined. 15.2 Register Descriptions 15.2.1 Receive Shift Register (SCRSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCRDR1 automatically. SCRSR1 cannot be directly read or written to by the CPU. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 659 of 1076 Section 15 Serial Communication Interface (SCI) 15.2.2 SH7750, SH7750S, SH7750R Group Receive Data Register (SCRDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for reception. Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data continuously. SCRDR1 is a read-only register, and cannot be written to by the CPU. SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.3 Transmit Shift Register (SCTSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1. SCTSR1 cannot be directly read or written to by the CPU. Page 660 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 15.2.4 Section 15 Serial Communication Interface (SCI) Transmit Data Register (SCTDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1. SCTDR1 can be read or written to by the CPU at all times. SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.5 erial Mode Register (SCSMR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7: C/A Description 0 Asynchronous mode 1 Synchronous mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 (Initial value) Page 661 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR Description 0 8-bit data 1 7-bit data* Note: * (Initial value) When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted. Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * (Initial value) When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/E Description 0 Even parity*1 1 Odd parity*2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Page 662 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP Description 0 1 stop bit*1 1 2 stop bits*2 (Initial value) Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function including notes on use, see section 15.3.3, Multiprocessor Communication Function. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 663 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pck clock 1 Pck/4 clock 0 Pck/16 clock 1 Pck/64 clock 1 (Initial value) Note: Pck: Peripheral clock 15.2.6 Serial Control Register (SCSCR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE Description 0 Transmit-data-empty interrupt (TXI) request disabled* 1 Note: (Initial value) Transmit-data-empty interrupt (TXI) request enabled * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Page 664 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5: TE Description 0 Transmission disabled* 1 2 1 (Initial value) Transmission enabled* Notes: 1. The TDRE flag in SCSSR1 is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to SCTDR1 and the TDRE flag in SCSSR1 is cleared to 0. SCSMR1 setting must be performed to decide the transmit format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE Description 0 Reception disabled*1 1 Reception enabled*2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR1 setting must be performed to decide the receive format before setting the RE bit to 1. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 665 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] 1 Note: • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled* * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data transmission. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) request disabled* 1 Transmit-end interrupt (TEI) request enabled* Note: * (Initial value) TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCI's operating mode with SCSMR1. For details of clock source selection, see table 15.9 in section 15.3, Operation. Page 666 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as input pin (input signal ignored)*1 Synchronous mode Internal clock/SCK pin functions as serial clock output*1 Asynchronous mode Internal clock/SCK pin functions as 2 clock output* Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock input*3 Synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as clock input*3 Synchronous mode External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 15.2.7 Serial Status Register (SCSSR1) Bit: Initial value: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 R/W: R/(W)* Note: * 0 0 0 0 1 — 0 R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 667 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE Description 0 Valid transmit data has been written to SCTDR1 [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When data is written to SCTDR1 by the DMAC There is no valid transmit data in SCTDR1 (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 • When data is transferred from SCTDR1 to SCTSR1 and data can be written to SCTDR1 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF 0 Description There is no valid receive data in SCRDR1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to RDRF after reading RDRF = 1 • When data in SCRDR1 is read by the DMAC There is valid receive data in SCRDR1 [Setting condition] When serial reception ends normally and receive data is transferred from SCRSR1 to SCRDR1 Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCSCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Page 668 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR1, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued either. Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to FER after reading FER = 1 A framing error occurred during reception [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0*2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 669 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to PER after reading PER = 1 A parity error occurred during reception*2 [Setting condition] When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND 0 Description Transmission is in progress [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When data is written to SCTDR1 by the DMAC Transmission has been ended (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 • When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB)*: This bit is read-only and cannot be written to. The read value is undefined. Page 670 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Note: * This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode. This bit does not function correctly in this LSI. However, do not use the read value from this bit. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether transmission has been completed before changing its value. Bit 0: MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted 15.2.8 (Initial value) Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 EIO — — — 3 2 1 SPB1IO SPB1DT SPB0IO 0 SPB0DT 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 671 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Bit 7: EIO Description 0 When the RIE bit is 1, RXI and ERI interrupts are sent to INTC (Initial value) 1 When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin (Initial value) Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined. Page 672 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level Section 15 Serial Communication Interface (SCI) SCI I/O port block diagrams are shown in figures 15.2 to 15.4. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 673 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Reset R Q D SPB1IO C SPTRW Internal data bus Reset MD0/SCK Q R D SPB1DT C SPTRW Mode setting register SCI Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 15.2 MD0/SCK Pin Page 674 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Reset R Q D SPB0IO C Internal data bus SPTRW Reset MD7/TxD R Q D SPB0DT C SPTRW SCI Transmit enable signal Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 15.3 MD7/TxD Pin SCI RxD Serial receive data Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 15.4 RxD Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 675 of 1076 Section 15 Serial Communication Interface (SCI) 15.2.9 SH7750, SH7750S, SH7750R Group Bit Rate Register (SCBRR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. The SCBRR1 setting is found from the following equations. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Synchronous mode: N= Pck 8 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR1 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR1 Setting n Clock CKS1 CKS0 0 Pck 0 0 1 Pck/4 0 1 2 Pck/16 1 0 3 Pck/64 1 1 Page 676 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) The bit rate error in asynchronous mode is found from the following equation: Pck × 106 Error (%) = (N + 1) × B × 64 × 22n – 1 – 1 × 100 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode. Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode Pck (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 –18.62 0 1 –14.67 0 1 0.00 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 677 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Pck (MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 Pck (MHz) 6 6.144 7.37288 8 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99 Page 678 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Pck (MHz) 9.8304 10 12 12.288 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00 Pck (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 31250 0 14 –1.70 0 15 0.00 0 19 –1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 679 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Pck (MHz) 24 24.576 28.7 30 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 106 –0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 –0.35 300 2 155 0.16 2 159 0.00 2 186 –0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 –0.35 1200 1 155 0.16 1 159 0.00 1 186 –0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 –0.35 4800 0 155 0.16 0 159 0.00 0 186 –0.08 0 194 –1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 –0.35 19200 0 38 0.16 0 39 0.00 0 46 –0.61 0 48 –0.35 31250 0 23 0.00 0 24 –1.70 0 28 –1.03 0 29 0.00 38400 0 19 –2.34 0 19 0.00 0 22 1.55 0 23 1.73 Legend: Blank: No setting is available. —: A setting is available but error occurs. Page 680 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pck (MHz) 4 Bit Rate (bits/s) n 8 16 28.7 30 N n N n N n N n N 10 — — — — — — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 — — 0 29 500k 0 1 0 3 0 7 — — 0 14 1M 0 0* 0 1 0 3 — — — — 0 0* 0 1 — — — — 2M Legend: Blank: No setting is available. —: A setting is available but error occurs. * Continuous transmission/reception is not possible. Note: As far as possible, the setting should be made so that the error is within 1%. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 681 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pck (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0 Page 682 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 683 of 1076 Section 15 Serial Communication Interface (SCI) 15.3 Operation 15.3.1 Overview SH7750, SH7750S, SH7750R Group The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9. • Asynchronous mode ⎯ Data length: Choice of 7 or 8 bits ⎯ Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ⎯ Detection of framing, parity, and overrun errors, and breaks, during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). • Synchronous mode ⎯ Transfer format: Fixed 8-bit data ⎯ Detection of overrun errors during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip. When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock. Page 684 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/A CHR MP PE STOP Mode Data Length Multiprocessor Parity Bit Bit Stop Bit Length 0 8-bit data No 1 bit 0 0 0 0 1 1 Asynchronous mode No 2 bits 0 Yes 1 1 0 2 bits 0 7-bit data No 1 1 1 * 0 0 1 1 0 Yes * * * * 1 bit 2 bits Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No 1 bit 2 bits 1 bit 1 1 1 bit 2 bits 1 0 1 bit 2 bits Synchronous mode 8-bit data No None Note: An asterisk in the table means “Don't care.” R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 685 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting Bit 7: C/A Bit 1: CKE1 Bit 0: CKE0 0 0 0 1 1 SCI Transmit/Receive Clock Mode Asynchronous mode 0 Clock Source SCK Pin Function Internal SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 1 1 Synchronous mode 0 1 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Page 686 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Idle state (mark state) 1 Serial data (LSB) 0 D0 1 (MSB) D1 Start bit D2 D3 D4 D5 D6 D7 Transmit/receive data 1 bit 7 or 8 bits 0/1 1 1 Parity bit Stop bit(s) 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR1 setting. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 687 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 * 1 0 S 8-bit data MPB STOP 0 * 1 1 S 8-bit data MPB STOP STOP 1 * 1 0 S 7-bit data MPB STOP 1 * 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note: An asterisk in the table means “Don't care.” Page 688 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 15.7 shows a sample SCI initialization flowchart. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 689 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR1 to 0 When clock output is selected in asynchronous mode, it is output immediately after SCSCR1 settings are made. Set CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 2. Set the transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set transmit/receive format in SCSMR1 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Set value in SCBRR1 Wait 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits No Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCI will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 15.7 Sample SCI Initialization Flowchart Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Page 690 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes Read TEND flag in SCSSR1 TEND = 1? No 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR1 to 0. Yes Break output? No Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR1 to 0 End of transmission Figure 15.8 Sample Serial Transmission Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 691 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 15.9 shows an example of the operation for transmission in asynchronous mode. Page 692 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Start bit 1 Serial data 0 Section 15 Serial Communication Interface (SCI) Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler TEI interrupt request One frame Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 693 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Start of reception Read ORER, PER, and FER flags in SCSSR1 PER or FER or ORER = 1? No Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 Yes Error handling 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 2. SCI status check and receive data read : Read SCSSR1 and check that RDRF = 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. 3. Serial reception continuation procedure: To continue serial reception, complete zeroclearing of the RDRF flag before the stop bit for the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by an RXI interrupt and the SCRDR1 value is read.) End of reception Figure 15.10 Sample Serial Reception Flowchart (1) Page 694 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling No Clear RE bit in SCSCR1 to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 End Figure 15.10 Sample Serial Reception Flowchart (2) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 695 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SCSMR1. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Note: No further receive operations can be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. A receive-data-full request is always output to the DMAC when the RDRF flag changes to 1. Table 15.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Reception of next data is completed while RDRF flag in SCSSR1 is set to 1 Receive data is not transferred from SCRSR1 to SCRDR1 Framing error FER Stop bit is 0 Receive data is transferred from SCRSR1 to SCRDR1 Parity error PER Received data parity differs from that (even or odd) set in SCSMR1 Receive data is transferred from SCRSR1 to SCRDR1 Page 696 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Figure 15.11 shows an example of the operation for reception in asynchronous mode. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 0/1 RDRF FER RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 697 of 1076 Section 15 Serial Communication Interface (SCI) 15.3.3 SH7750, SH7750S, SH7750R Group Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent*. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received*. In this way, data communication is carried out among a number of processors. Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Note: * With this LSI, the RDRF flag in SCSSR1 is also set to 1 when data with a 0 multiprocessor bit transmitted to another station is received. When the RDRF flag in SCSSR1 is set to 1, check the state of the MPIE bit in SCSCR1 with the exception handling routine, and if the MPIE bit is 1, skip the data. That is to say, data skipping is implemented in cooperation with the exception handling routine. Page 698 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: Receiving station specification (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2, Operation in Asynchronous Mode. Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 699 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Start of transmission Read TEND flag in SCSSR1 TEND = 1? No 2. Preparation for data transfer: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1. Yes Set MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 3. Serial data transmission: Write the first transmit data to SCTDR1, then clear the TDRE flag to 0. Clear TDRE flag to 0 Read TEND flag in SCSSR1 TEND = 1? 1. SCI status check and ID data write: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0. No Yes Clear MPBT bit in SCSSR1 to 0 To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Write data to SCTDR1 Clear TDRE flag to 0 Read TDRE flag in SCSSR1 TDRE = 1? No Yes No All data transmitted? Yes End of transmission Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart Page 700 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The order of transmission is the same as in step 2. Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 701 of 1076 Section 15 Serial Communication Interface (SCI) 1 Serial data Start bit 0 Multiproces- Stop sor bit bit Data D0 D1 D7 1 1 SH7750, SH7750S, SH7750R Group Start bit 0 Data D0 D1 Multiproces- Stop Start bit sor bit bit D7 0 1 0 Data D0 D1 Multiproces- Stop sor bit bit D7 0 1 Idle state (mark state) TDRE TEND One frame Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler TXI interrupt request TEI interrupt request MPBT bit cleared to 0, data written to SCTDR1, and TDRE flag cleared to 0 by TEI interrupt handler Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCI for reception. 1. Method for determining whether an interrupt generated during receive operation is a multiprocessor interrupt When an interrupt such as RXI occurs during receive operation using the on-chip SCI multiprocessor communication function, check the state of the MPIE bit in the SCSCR1 register as part of the interrupt handling routine. a. If the MPIE bit in the SCSCR1 register is set to 1 Ignore the received data. Data with the multiprocessor bit (MPB) set to 0 and intended for another station was received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the RDRF bit in the SCSCR1 register to 0. Page 702 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) b. If the MPIE bit in the SCSCR1 register is cleared to 0 A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set to 1 was received, or a receive data full interrupt (RXI) occurred when data with the multiprocessor bit (MPB) set to 0 and intended for this station was received. 2. Method for determining whether received data is ID or data Do not use the MPB bit in the SCSSR1 register for software processing. When using software processing to determine whether received data is ID (MPB = 1) or data (MPB = 0), use a procedure such as saving a user-defined flag in memory to indicate receive start. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 703 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Start of reception Set MPIE bit to 1 RXI = 1? No Yes Yes User-defined receive start flag = 1? No Read ORER and FER flags in SCSSR1 FER or ORER = 1? Yes No Read RDRF flag in SCSSR1 No MPIE = 0? Yes Read receive data in SCRDR1 No This station's ID? Yes Set user-defined receive start flag to 1 Set RDRF = 0 and MPIE = 1 End of ID reception handling Read ORER and FER flags in SCSSR1 FER or ORER = 1? Yes No Read receive data in SCRDR1 No All data received? Yes Clear user-defined receive start flag to 0 RTE End of data reception Error handling Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Page 704 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 705 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Figure 15.16 shows an example of SCI operation for multiprocessor format reception. 1 Start Data (ID1) bit Serial data 0 D0 D1 Data (Data1) Stop Start MPB bit bit D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 Idle state (mark state) 1 MPIE RDRF SCRDR1 value ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data is not this RXI interrupt station's ID, MPIE request bit is set to 1 again MPIE = 1 The RDRF flag is cleared to 0 by the RXI interrupt handler. (a) Data does not match station's ID 1 Start Data (ID2) bit Serial data 0 D0 D1 Stop Start MPB bit bit D7 1 1 0 Data (Data2) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF SCRDR1 value RXI interrupt request (multiprocessor interrupt) MPIE = 0 Data2 ID2 ID1 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station's ID, reception continues and data is received by RXI interrupt handler MPIE bit set to 1 again (b) Data matches station's ID Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Page 706 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit position. If the multiprocessor bit is 0, the MPIE bit is not changed. 4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1. 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.17 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don't care Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transmission/reception Figure 15.17 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 707 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before the end of bit 7. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. Page 708 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Figure 15.18 shows a sample SCI initialization flowchart. 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Initialization Clear TE and RE bits in SCSCR1 to 0 2. Set transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set transmit/receive format in SCSMR1 Set value in SCBRR1 Wait 1-bit interval elapsed? No Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.18 Sample SCI Initialization Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 709 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes 2. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Read TEND flag in SCSSR1 TEND = 1? No Yes Clear TE bit in SCSCR1 to 0 End Figure 15.19 Sample Serial Transmission Flowchart Page 710 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 15.20 shows an example of SCI operation in transmission. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 711 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Transfer direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Data written to SCTDR1 and TDRE flag cleared to 0 in TXI interrupt handler TXI interrupt request TEI interrupt request One frame Figure 15.20 Example of SCI Transmit Operation Page 712 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Start of reception Read ORER flag in SCSSR1 Yes ORER = 1? No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception 1. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. 2. SCI status check and receive data read: Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Figure 15.21 Sample Serial Reception Flowchart (1) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 713 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR1 to 0 End Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Page 714 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Figure 15.22 shows an example of SCI operation in reception. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Data read from SCRDR1 and RDRF flag cleared to 0 in RXI interrupt handler RXI interrupt request ERI interrupt request due to overrun error One frame Figure 15.22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for transmission and reception. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 715 of 1076 Section 15 Serial Communication Interface (SCI) Start of transmission/reception Read TDRE flag in SCSSR1 No TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 SH7750, SH7750S, SH7750R Group 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. 3. SCI status check and receive data read: Read ORER flag in SCSSR1 Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the Yes ORER = 1? RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Error handling No Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data transferred? Yes Clear TE and RE bits in SCRSR1 to 0 End of transmission/reception 4. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1 and clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the DMAC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1. Similarly, the RDRF flag is cleared automatically when the DMAC is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1. Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception Page 716 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 15.4 Section 15 Serial Communication Interface (SCI) SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is generated separately from the interrupt request. A TDR-empty request can activate the direct memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0 automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC. When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the interrupt request. An RDR-full request can activate the DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is performed by the DMAC. When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated. The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be generated even during normal data reception. When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC cannot be activated by a TEI interrupt request. A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the transmit operation has ended. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 717 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Table 15.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Receive error (ORER, FER, or PER) Not possible High RXI Receive data register full (RDRF) Possible TXI Transmit data register empty (TDRE) Possible TEI Transmit end (TEND) Not possible Low See section 5, Exceptions, for the priority order and relation to non-SCI interrupts. 15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1. Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to SCTDR1. Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is not transferred from SCRSR1 to SCRDR1, and the receive data is lost. Page 718 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors RDRF ORER FER PER Receive Data Transfer SCRSR1 → SCRDR1 Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X Legend: O: Receive data is transferred from SCRSR1 to SCRDR1. X: Receive data is not transferred from SCRSR1 to SCRDR1. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of its current state, and the TxD pin becomes an output port outputting the value 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 719 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND flag was set, transmission may not complete properly because stop bit transmission processing is still underway. Therefore, wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits are used) after confirming that the TEND flag was set before clearing the TE bit. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.24. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode Page 720 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ................ (1) 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using the DMAC: • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated. (See figure 15.25) SCK t TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4. Figure 15.25 Example of Synchronous Transmission by DMAC • When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as the activation source with bits RS3 to RS0 in CHCR. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 721 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group • When using the DMAC for transmission/reception, making a setting to disable RXI and TXI interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. When Using Synchronous External Clock Mode: • Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. • Only set both TE and RE to 1 when external clock SCK is 1. • In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using DMAC: When using the DMAC for transmission/reception, make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. SH7750 Only: When the following conditions are satisfied, the same data may be transmitted multiple times. • Conditions Under which Problem Occurs a. External SCK clock input mode is selected (SCSCR1.CKE1 = 1). b. Synchronous mode is selected (SCSMR1C/A = 1). c. Transmit or receive is in progress (SCSCR1.TE = 1). Conditions a. to c. must all be satisfied. • Workarounds Workaround 1 ⎯ PLL2 on As shown in figure 15.26, after synchronizing asynchronous input external clock SCK with CKIO, input it to the SCK pin of the SH7750. In this case the SCK clock cycle minimum value will be: peripheral clock cycle (Pck) × 8. Note that this workaround will reduce the timing margins of the TxD and RxD pins synchronized with the SCK pin. ⎯ PLL2 off Operation cannot be guaranteed. (Usage prohibited.) Page 722 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 15 Serial Communication Interface (SCI) Workaround 2 Do not select settings a., b., and c. at the same time. Multiplexer (switches between clock mode and SCK input) SH7750 Mode setting signal MD0/SCK Edge trigger FF D Q B A CKIO Figure 15.26 Example Countermeasure on SH7750 • Clock Timing Make sure that the timing of the clock input to the SCK pin, including the delay from edge trigger FF and the multiplexer in figure 15.26, conforms to that shown below. CKIO tSCKH tSCKS tSCKH tSCKS SCK Figure 15.27 Clock Input Timing of SCK Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 723 of 1076 Section 15 Serial Communication Interface (SCI) SH7750, SH7750S, SH7750R Group Table 15.14 Peripheral Module Signal Timing tSCKS Product tSCKH Min Max Min Max Unit HD6417750BP200 5 ⎯ 0 ⎯ ns HD6417750BP200M 5 ⎯ 0 ⎯ ns HD6417750F167 5 ⎯ 0 ⎯ ns HD6417750F167I 5 ⎯ 0 ⎯ ns HD6417750VF128 8 ⎯ 0 ⎯ ns Page 724 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview This LSI is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 Features SCIF features are listed below. • Asynchronous serial communication Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. ⎯ Data length: 7 or 8 bits ⎯ Stop bit length: 1 or 2 bits ⎯ Parity: Even/odd/none ⎯ Receive error detection: Parity, framing, and overrun errors ⎯ Break detection: If the receive data following that in which a framing error occurred is also at the space “0” level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RxD2 pin level directly from the serial port register (SCSPTR2). • Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. • On-chip baud rate generator allows any bit rate to be selected. • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 725 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. • The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. • When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. • Modem control functions (RTS2 and CTS2) are provided. • The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. • A timeout error (DR) can be detected during reception. Page 726 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 16.1.2 Section 16 Serial Communication Interface with FIFO (SCIF) Block Diagram Bus interface Figure 16.1 shows a block diagram of the SCIF. Module data bus RxD2 SCFRDR2 (16-stage) SCFTDR2 (16-stage) SCRSR2 SCTSR2 SCSMR2 SCLSR2 SCFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 SCBRR2 Pck Baud rate generator Parity generation Pck/4 Pck/16 Transmission/ reception control TxD2 Internal data bus Pck/64 Clock Parity check External clock SCK2 TXI RXI ERI BRI CTS2 RTS2 SCIF Legend: SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR2: SCBRR2: SCSPTR2: SCFCR2: SCFDR2: SCLSR2: Serial status register Bit rate register Serial port register FIFO control register FIFO data count register Line status register Figure 16.1 Block Diagram of SCIF R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 727 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.3 SH7750, SH7750S, SH7750R Group Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation I/O Function Serial clock pin SCK2/MRESET Input Clock input Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin CTS2 I/O Transmission enabled Modem control pin MD8/RTS2 I/O Transmission request Note: After a power-on reset, these pins function as mode input pins MD1, MD2, and MD8. These pins can function as serial pins by setting the SCIF operation with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Page 728 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 16.1.4 Section 16 Serial Communication Interface with FIFO (SCIF) Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Name Abbreviation R/W Initial Value Serial mode register SCSMR2 R/W H'0000 H'FFE80000 H'1FE80000 16 Bit rate register SCBRR2 R/W H'FF H'FFE80004 H'1FE80004 8 Serial control register SCSCR2 R/W H'0000 H'FFE80008 H'1FE80008 16 Transmit FIFO data register SCFTDR2 W Serial status register SCFSR2 P4 Address Area 7 Address Access Size Undefined H'FFE8000C H'1FE8000C 8 1 R/(W)* H'0060 H'FFE80010 H'1FE80010 16 Receive FIFO data register SCFRDR2 R Undefined H'FFE80014 H'1FE80014 8 FIFO control register SCFCR2 R/W H'0000 H'FFE80018 H'1FE80018 16 FIFO data count register SCFDR2 R H'0000 H'FFE8001C H'1FE8001C 16 Serial port register SCSPTR2 R/W Line status register SCLSR2 H'0000*2 H'FFE80020 H'1FE80020 16 R/(W)*3 H'0000 H'FFE80024 H'1FE80024 16 Notes: 1. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified. 2. The value of bits 6, 4, and 0 is undefined. 3. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified. 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO register, SCFRDR2, automatically. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 729 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group SCRSR2 cannot be directly read or written to by the CPU. 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes). SCFRDR2 is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive data, subsequent serial data is lost. The contents of SCFRDR2 are undefined after a power-on reset or manual reset. 16.2.3 Transmit Shift Register (SCTSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2 to SCTSR2, and transmission started, automatically. SCTSR2 cannot be directly read or written to by the CPU. Page 730 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 16.2.4 Section 16 Serial Communication Interface with FIFO (SCIF) Transmit FIFO Data Register (SCFTDR2) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W SCFTDR2 is an 8-bit 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR2 are undefined after a power-on reset or manual reset. 16.2.5 Serial Mode Register (SCSMR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — CHR PE O/E STOP — CKS1 CKS0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R R/W R/W SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR2 can be read or written to by the CPU at all times. SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 731 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR Description 0 8-bit data 1 7-bit data* Note: * (Initial value) When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Note: (Initial value) Parity bit addition and checking enabled* * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/E bit setting is invalid when parity addition and checking is disabled. Bit 4: O/E Description 0 Even parity*1 1 (Initial value) 2 Odd parity* Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Page 732 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP Description 0 1 stop bit*1 (Initial value) 2 2 stop bits* 1 Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Reserved: This bit is always read as 0, and should only be written with 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register (SCBRR2). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pck clock 1 Pck/4 clock 0 Pck/16 clock 1 Pck/64 clock 1 (Initial value) Note: Pck: Peripheral clock R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 733 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.6 SH7750, SH7750S, SH7750R Group Serial Control Register (SCSCR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE REIE — CKE1 — Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R The SCSCR2 register performs enabling or disabling of SCIF transfer operations, and interrupt requests, and selection of the serial clock source. SCSCR2 can be read or written to by the CPU at all times. SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 8, 2, and 0—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1. Bit 7: TIE Description 0 Transmit-FIFO-data-empty interrupt (TXI) request disabled* 1 Transmit-FIFO-data-empty interrupt (TXI) request enabled Note: * (Initial value) TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. Page 734 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE Description 0 Transmission disabled 1 Transmission enabled* Note: * (Initial value) Serial transmission is started when transmit data is written to SCFTDR2 in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description 0 Reception disabled*1 1 (Initial value) 2 Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. 2. Serial transmission is started when a start bit is detected in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 735 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE Description 0 Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled* (Initial value) 1 Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. Bit 1—Clock Enable 1 (CKE1): Selects the SCIF clock source. The CKE1 bit must be set before determining the SCIF's operating mode with SCSMR2. Bit 1: CKE1 Description 0 Internal clock/SCK2 pin functions as port 1 External clock/SCK2 pin functions as clock input* Note: * (Initial value) Inputs a clock with a frequency 16 times the bit rate. Page 736 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 16.2.7 Serial Status Register (SCFSR2) Bit: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR 0 1 1 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R R R/(W)* R/(W)* Initial value: R/W: R/(W)* Note: Section 16 Serial Communication Interface with FIFO (SCIF) * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified. SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 12—Number of Parity Errors (PER3–PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to PER0 will be 0. Bits 11 to 8—Number of Framing Errors (FER3–FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 737 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2, and reception continues. The FER and PER bits in SCFSR2 can be used to determine whether there is a receive error that is to be from SCFRDR2. Bit 7: ER Description 0 No framing error or parity error occurred during reception (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When 0 is written to ER after reading ER = 1 A framing error or parity error occurred during reception [Setting conditions] Note: * • When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0* • When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Page 738 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description 0 Transmission is in progress [Clearing conditions] 1 • When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1 • When data is written to SCFTDR2 by the DMAC Transmission has been ended (Initial value) [Setting conditions] • Power-on reset or manual reset • When the TE bit in SCSCR2 is 0 • When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1-byte serial transmit character R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 739 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2. Bit 5: TDFE Description 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR2 [Clearing conditions] 1 • When transmit data exceeding the transmit trigger set number is written to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE • When transmit data exceeding the transmit trigger set number is written to SCFTDR2 by the DMAC The number of transmit data bytes in SCFTDR2 does not exceed the transmit trigger set number (Initial value) [Setting conditions] Note: * • Power-on reset or manual reset • When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2. Page 740 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK Description 0 A break signal has not been received (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When 0 is written to BRK after reading BRK = 1 A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space “0” level (low level ) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed. Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR2. Bit 3: FER 0 Description There is no framing error that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When there is no framing error in the data that is to be read next from SCFRDR2 There is a framing error that is to be read from SCFRDR2 [Setting condition] When there is a framing error in the data that is to be read next from SCFRDR2 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 741 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 2—Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR2. Bit 2: PER Description 0 There is no parity error that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When there is no parity error in the data that is to be read next from SCFRDR2 There is a parity error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a parity error in the data that is to be read next from SCFRDR2 Page 742 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). Bit 1: RDF Description 0 The number of receive data bytes in SCFRDR2 is less than the receive trigger set number (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF • When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR2 contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR2 is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR2 is indicated by the lower bits of SCFDR2. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 743 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR Description 0 Reception is in progress or has ended normally and there is no receive data left in SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When all the receive data in SCFRDR2 has been read after reading DR = 1, and 0 is written to DR • When all the receive data in SCFRDR2 has been read by the DMAC No further receive data has arrived [Setting condition] When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: 16.2.8 * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: Elementary time unit (time for transfer of 1 bit) Bit Rate Register (SCBRR2) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR2. SCBRR2 can be read or written to by the CPU at all times. SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Page 744 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) The SCBRR2 setting is found from the following equation. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR2 Setting n Clock CKS1 CKS0 0 Pck 0 0 1 Pck/4 0 1 2 Pck/16 1 0 3 Pck/64 1 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = 16.2.9 Pck × 106 (N + 1) × B × 64 × 22n – 1 – 1 × 100 FIFO Control Register (SCFCR2) Bit: 15 14 13 12 11 — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Note: * 10 9 8 RSTRG2* RSTRG1* RSTRG0* Reserved bit in the SH7750. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 745 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750S, SH7750R)—RTS2 Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits output the high level to the RTS2 signal when the number of received data stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below. Bit 10: RSTRG2 Bit 9: RSTRG1 Bit 8: RSTRG0 RTS2 Output Active Trigger 0 0 0 15 1 1 0 4 1 6 0 8 1 10 0 12 1 14 1 1 0 1 Page 746 of 1076 (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2). The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 0 1 Bit 6: RTRG0 Receive Trigger Number 0 1 1 4 0 8 1 14 (Initial value) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table. • SH7750 Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number 0 0 7 (9) 1 3 (13) 0 1 (15) 1 0 (16) 1 (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. • SH7750S/SH7750R Bit 5: TTRG1 0 1 Bit 4: TTRG0 Transmit Trigger Number 0 8 (8) 1 4 (12) 0 2 (14) 1 1 (15) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 747 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals. Bit 3: MCE Description 0 Modem signals disabled* 1 Modem signals enabled Note: * (Initial value) CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST Description 0 Reset operation disabled* 1 Reset operation enabled Note: * (Initial value) A reset operation is performed in the event of a power-on reset or manual reset. Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST Description 0 Reset operation disabled* 1 Reset operation enabled Note: * (Initial value) A reset operation is performed in the event of a power-on reset or manual reset. Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing. Bit 0: LOOP Description 0 Loopback test disabled 1 Loopback test enabled Page 748 of 1076 (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2. SCFDR2 can be read by the CPU at all times. Bit: 15 14 13 12 11 10 9 8 — — — T4 T3 T2 T1 T0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data. Bit: 7 6 5 4 3 2 1 0 — — — R4 R3 R2 R1 R0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 749 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group 16.2.11 Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT — — Initial value: R/W: SPB2IO SPB2DT 0 — 0 — 0 — 0 — R/W R/W R/W R/W R R R/W R/W SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the CTS2 pin by means of bits 5 and 4. Data can be read from, and output data written to, the RTS2 pin by means of bits 6 and 7. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies the serial port RTS2 pin input/output condition. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to RTS2 pin 1 RTSDT bit value is output to RTS2 pin Page 750 of 1076 (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies the serial port CTS2 pin input/output condition. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to CTS2 pin 1 CTSDT bit value is output to CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Reserved: The value of this bit is undefined when read. The write value should always be 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 751 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level Page 752 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) SCIF I/O port block diagrams are shown in figures 16.2 to 16.5. Reset R D7 Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R D6 Q D RTSDT C SPTRW SCIF Modem control enable signal* RTS2 signal Mode setting register SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.2 MD8/RTS2 Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 753 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Reset R Q D CTSIO C D5 Internal data bus SPTRW Reset CTS2 R Q D CTSDT C D4 SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 CTS2 Pin Page 754 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Reset R Q D SPB2IO C D1 Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C D0 SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register D0 Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 16.5 MD2/RxD2 Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 755 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group 16.2.12 Line Status Register (SCLSR2) Bit: Note: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — ORER Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R (R/W)* * Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while the receive FIFO is full Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR2, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Page 756 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 16.3 Operation 16.3.1 Overview Section 16 Serial Communication Interface with FIFO (SCIF) The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. RTS2 and CTS2 signals are also provided as modem control signals. The transmission format is selected using the serial mode register (SCSMR2), as shown in table 16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register (SCSCR2), as shown in table 16.4. • Data length: Choice of 7 or 8 bits • Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception • Indication of the number of data bytes stored in the transmit and receive FIFO registers • Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock, and can output a clock with a frequency of 16 times the bit rate. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 757 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings SCIF Transfer Format Bit 6: CHR Bit 5: PE Bit 3: STOP Mode Data Length Multiprocessor Parity Bit Bit 0 0 0 Asynchronous mode 8-bit data No Stop Bit Length No 1 bit 1 1 2 bits 0 Yes 1 bit 1 1 0 2 bits 0 7-bit data No 1 bit 1 1 2 bits 0 Yes 1 bit 1 2 bits Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting SCIF Transmit/Receive Clock Bit 1: CKE1 Mode Clock Source SCK2 Pin Function 0 Asynchronous mode Internal SCIF does not use SCK2 pin External Inputs clock with frequency of 16 times the bit rate 1 16.3.2 Serial Operation Transmit/Receive Format Table 16.5 shows the transmit/receive formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings. Page 758 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.5 Serial Transmit/Receive Formats SCSMR2 Settings Serial Transmit/Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8-bit data STOP 0 0 1 S 8-bit data STOP STOP 0 1 0 S 8-bit data P STOP 0 1 1 S 8-bit data P STOP STOP 1 0 0 S 7-bit data STOP 1 0 1 S 7-bit data STOP STOP 1 1 0 S 7-bit data P STOP 1 1 1 S 7-bit data P STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in SCSCR2. For details of SCIF clock source selection, see table 16.4. When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit rate used. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 759 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Page 760 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.6 shows a sample SCIF initialization flowchart. 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR2 to 0 2. Set the transmit/receive format in SCSMR2. 3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.) Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 bit in SCSCR2 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Set transmit/receive format in SCSMR2 Set value in SCBRR2 Wait 1-bit interval elapsed? No Yes Set RTRG1–0, TTRG1–0, and MCE bits in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits End Figure 16.6 Sample SCIF Initialization Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 761 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Serial Data Transmission: Figure 16.7 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Start of transmission Read TDFE flag in SCFSR2 TDFE = 1? No The number of transmit data bytes that can be written is 16 - (transmit trigger set number). Yes Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0 All data transmitted? 2. Serial transmission continuation procedure: No Yes No Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: Read TEND flag in SCFSR2 TEND = 1? Read SCFSR2 and check that the TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR2, then clear the TE bit in SCSCR2 to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of SCFDR2. Clear TE bit in SCSCR2 to 0 End of transmission Figure 16.7 Sample Serial Transmission Flowchart Page 762 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is at least 16 - transmit trigger setting. 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls to or below the transmit trigger number set in the FIFO control register (SCFCR2), the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 763 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Figure 16.8 shows an example of the operation for transmission in asynchronous mode. Start bit 1 Serial data Data 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 Idle state (mark state) 1 TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS2 input value. When CTS2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS2 is set to 0, the next transmit data is output starting from the start bit. Figure 16.9 shows an example of the operation when modem control is used. Start bit Serial data TxD2 0 Parity Stop bit bit D0 D1 D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS2 Drive high before stop bit Figure 16.9 Example of Operation Using Modem Control (CTS2) Page 764 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR2 and ORER flag in SCLSR2 ER or DR or BRK or ORER = 1? No Read RDF flag in SCFSR2 No RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCFSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End of reception Yes Error handling 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Figure 16.10 Sample Serial Reception Flowchart (1) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 765 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling No SH7750, SH7750S, SH7750R Group 1. Whether a framing error or parity error has occurred that is to be read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 (the break data in which a framing error occurred is stored). ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0 End Figure 16.10 Sample Serial Reception Flowchart (2) Page 766 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred. d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If b, c, and d checks are passed, the receive data is stored in SCFRDR2. Note: Reception continues when parity error, framing error occurs. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 767 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Figure 16.11 shows an example of the operation for reception in asynchronous mode. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 0/1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When RTS2 is 0, reception is possible. SH7750: When RTS2 is 1, this indicates that SCFRDR2 contains 15 or more bytes of data. SH7750S, SH7750R: When RTS2 is 1, this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the RTS2 output active trigger set number. The RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR2), described in section 16.2.9, FIFO control register (SCFCR2). RTS2 also becomes 1 when bit 4 (RE) in SCSCR2 is 0. Page 768 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.12 shows an example of the operation when modem control is used. Start bit Serial data RxD2 0 Parity Stop bit bit D0 D1 D2 D7 0/1 1 Start bit 0 RTS2 Figure 16.12 Example of Operation Using Modem Control (RTS2) 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When transmission/reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests. When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is generated separately from the interrupt request. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 769 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 16.6 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Interrupt initiated by receive error flag (ER) Not possible High RXI Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR) Possible BRI Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) TXI Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count register (SCFDR2). SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the Page 770 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive operation continues. Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.13. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 771 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD2) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ...................... (1) 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1 / (2 × 16)) × 100% = 46.875% ................................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Page 772 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 16 Serial Communication Interface with FIFO (SCIF) SCK2/MRESET: As the manual reset pin is multiplexed with the SCK2 pin, a manual reset must not be executed while the SCIF is operating in external clock mode. When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler. Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. Overrun Error Flag (SH7750): SCIF overrun error flag is not set in the case that overrun error and flaming error occurred simultaneously in receiving data, that means 17th byte data which overrun was accompanying with flaming error. In such case, only SCFSR2. ER flag which shows occurrence of flaming error is set. Receive FIFO stores data received before the overrun and does not store (i. e. lose) overrun data. SCIF has no bit which corresponds to SCFSR2. FER for the lost data. In addition to the overrun error handling software routine, exception handler should check cooccurrence of overrun error when a flaming error is occurred and when a co-occurrence is found, it should handle also overrun error (When (i) a overrun error solely occurred without accompanying with other receive error and (ii) when a parity error is accompanied with overrun error, usual overrun error handling can be used. Overrun error handling should rather be done primarily). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 773 of 1076 Section 16 Serial Communication Interface with FIFO (SCIF) SH7750, SH7750S, SH7750R Group Flow chart: Framing error occurrence When flaming error (SCFSR.ER=1) is occurred, bit7 to Bits 7 to 0 in SCFDR2 = H'10? bit0 should be read out from SCFDR2. If bit7 to bit0 No equals H'10, contents of the receive FIFO should be read. When the data received last is not accompanied Yes with flaming error (SCFSR2.FER=0) both overrun error Normal error handling handling and flaming error handling shoud be PER or FER bit in SCFSR2 set to 1? Yes conducted. No Error handling Read receive FIFO No Last data? Yes Overrun error handling + framing error handling Figure 16.14 Overrun Error Flag Page 774 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 Features Features of the smart card interface are listed below. • Asynchronous mode ⎯ Data length: 8 bits ⎯ Parity bit generation and checking ⎯ Transmission of error signal (parity error) in receive mode ⎯ Error signal detection and automatic data retransmission in transmit mode ⎯ Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources There are three interrupt sources—transmit-data-empty, receive-data-full, and transmit/receive error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 775 of 1076 Section 17 Smart Card Interface 17.1.2 SH7750, SH7750S, SH7750R Group Block Diagram Bus interface Figure 17.1 shows a block diagram of the smart card interface. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 SCSCMR1 SCSSR1 SCSCR1 SCSMR1 SCSPTR1 SCBRR1 Pck Baud rate generator Parity generation Pck/4 Pck/16 Transmission/ reception control TxD Internal data bus Pck/64 Clock Parity check External clock SCK TXI RXI ERI SCI Legend: SCSCMR1: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 17.1 Block Diagram of Smart Card Interface Page 776 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 17.1.3 Section 17 Smart Card Interface Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin Receive data pin MD0/SCK I/O Clock input/output RxD Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset. 17.1.4 Register Configuration The smart card interface has the internal registers shown in table 17.2. Details of the SCBRR1, SCTDR1, SCRDR1, and SCSPTR1 registers are the same as for the normal SCI function: see the register descriptions in section 15, Serial Communication Interface (SCI). With the exception of the serial port register, the smart card interface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 17.2 Smart Card Interface Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 1 Serial status register SCSSR1 R/(W)* H'84 H'FFE00010 H'1FE00010 8 Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 Smart card mode register SCSCMR1 R/W H'00 H'FFE00018 H'1FE00018 8 Serial port register SCSPTR1 R/W H'00*2 H'FFE0001C H'1FE0001C 8 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 777 of 1076 Section 17 Smart Card Interface 17.2 SH7750, SH7750S, SH7750R Group Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit: 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value: — — — — 0 0 — 0 R/W: — — — — R/W R/W — R/W Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 Description SCTDR1 contents are transmitted LSB-first (Initial value) Receive data is stored in SCRDR1 LSB-first 1 SCTDR1 contents are transmitted MSB-first Receive data is stored in SCRDR1 MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the bit 3 function for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2: SINV Description 0 SCTDR1 contents are transmitted as they are (Initial value) Receive data is stored in SCRDR1 as it is 1 SCTDR1 contents are inverted before being transmitted Receive data is stored in SCRDR1 in inverted form Page 778 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description 0 Smart card interface function is disabled 1 Smart card interface function is enabled 17.2.2 (Initial value) Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: 7 6 5 4 3 2 1 0 GM(C/A) CHR PE O/E STOP MP CKS1 CKS0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are made by CKE1 and CKE0. Bit 7: GM 0 1 Description Normal smart card interface mode operation (Initial value) • The TEND flag is set 12.5 etu after the beginning of the start bit • Clock output on/off control only GSM mode smart card interface mode operation • The TEND flag is set 11.0 etu after the beginning of the start bit • Clock output on/off and fixed-high/fixed-low control (set in SCSCR1) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 779 of 1076 Section 17 Smart Card Interface 17.2.3 SH7750, SH7750S, SH7750R Group Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE — — CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bits 3 and 2—Reserved: Not used with the smart card interface. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits specify the function of the SCK pin. In smart card interface mode, an internal clock is always used as the clock source. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. GM CKE1 CKE0 SCK Pin Function 0 0 0 Port I/O pin 1 Clock output as SCK output pin 0 Invalid setting: must not be used 1 Invalid setting: must not be used 0 Output pin with output fixed low 1 Clock output as output pin 0 Output pin with output fixed high 1 Clock output as output pin 1 1 0 1 Page 780 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 17.2.4 Section 17 Smart Card Interface Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ ERS PER TEND — — 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Initial value: R/W: R/(W)* Note: * Only 0 can be written, to clear the flag. Bits 7 to 5: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4: ERS Description 0 Normal reception, no error signal (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to ERS after reading ERS = 1 An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] When the low level of the error signal is detected Note: Clearing the TE bit in SCSCR1 to 0 does not affect the ERS flag, which retains its previous state. Bit 3—Parity Error (PER): Operates in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 781 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description 0 Transmission in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 Transmission has been ended (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0 • When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character • When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character Note: etu: Elementary Time Unit (time for transfer for 1 bit) Bits 1 and 0—Reserved: Not used with the smart card interface. 17.3 Operation 17.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. • If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. • Only asynchronous communication is supported; there is no synchronous communication function. Page 782 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 17.3.2 Section 17 Smart Card Interface Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the VCC power supply side with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Note: If an IC card is not connected, and both TE and RE are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. VCC TxD IO Data line RxD SH7750 SH7750S SH7750R SCK Clock line Px (port) Reset line Connected equipment CLK RST IC card Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 783 of 1076 Section 17 Smart Card Interface 17.3.3 SH7750, SH7750S, SH7750R Group Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. If an error signal is detected during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output Ds: D0–D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 17.3 Smart Card Interface Data Format The operation sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting station starts transmission of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. Page 784 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O/E 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER/ERS PER TEND 0 0 SCRDR1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCSCMR1 — — — — SDIR SINV — SMIF SCSPTR1 — — — SPB1IO SPB1DT SPB0IO EIO SPB0DT Note: A dash indicates an unused bit. Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to select the clock output state. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 785 of 1076 Section 17 Smart Card Interface I/O data Ds Da SH7750, SH7750S, SH7750R Group Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 Note: etu: Elementary Time Unit (time for transfer for 1 bit) Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details. Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Figure 17.5 shows examples of register settings and the waveform of the start character for the two types of IC card (direct convention and inverse convention). With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. Page 786 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception). (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State (Z) State (a) Direct convention (SDIR = SINV = O/E = 0) (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (b) Inverse convention (SDIR = SINV = O/E = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for calculating the bit rate is shown below. Table 17.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= Pck × 106 1488 × 22n – 1 × (N + 1) Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255) B = Bit rate (bits/s) Pck = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 787 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pck (MHz) N 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 0 9600.0 13440.9 14400.0 19200.0 33602.2 44354.8 67204.3 1 4800.0 6720.4 7200.0 9600.0 16801.1 22177.4 33602.2 2 3200.0 4480.3 4800.0 6400.0 11200.7 14784.9 22401.4 Note: Bit rates are rounded to one decimal place. The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral module operating frequency and bit rate is shown below. Here, N is an integer in the range 0 ≤ N ≤ 255, and the smaller error is specified. N= Pck × 106 – 1 1488 × 22n – 1 × B Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) Pck (MHz) 7.1424 10.00 10.7136 14.2848 25.00 33.00 50.00 Bits/s N Error N Error N Error N Error N Error N Error N Error 9600 0 0.00 1 30.00 1 25.00 1 8.99 3 14.27 4 8.22 6 0.01 Page 788 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) Pck (MHz) Maximum Bit Rate (bits/s) N n 7.1424 19200 0 0 10.00 26882 0 0 10.7136 28800 0 0 16.00 43010 0 0 20.00 53763 0 0 25.0 67204 0 0 30.0 80645 0 0 33.0 88710 0 0 50.0 67204 0 0 The bit rate error is given by the following equation: Pck Error (%) = 1488 × 22n – 1 × B × (N + 1) × 106 – 1 × 100 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state. Table 17.8 Register Settings and SCK Pin State Register Values SCK Pin Setting SMIF GM CKE1 CKE0 Output State 1*1 1 0 0 0 Port Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 2* 2 3* 2 SCK (serial clock) output state Low output Low-level output state SCK (serial clock) output state High output High-level output state SCK (serial clock) output state Notes: 1. The SCK output state changes as soon as the CKE0 bit setting is changed. Clear the CKE1 bit to 0. 2. Stopping and starting the clock by changing the CKE0 bit setting does not affect the clock duty cycle. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 789 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Width is undefined Port value Width is undefined Port value SCK (a) When GM = 0 CKE1 value Specified width Specified width CKE1 value SCK (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting 17.3.6 Data Transmit/Receive Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set the GM bit, parity bit (O/E), and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SCSMR1). Clear the CHR and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR1). When the SMIF bit is set to 1, the TxD pin and RxD pin both go to the high-impedance state. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR1). 6. Set the clock source select bits (CKE1 and CKE0) in SCSCR1. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCSCR1. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Page 790 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Initialization Clear TE and RE bits in SCSCR1 to 0 1 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 2 In SCSMR1, set parity in O/E bit, clock in CKS1 and CKS0 bits, and set GM 3 Set SMIF, SDIR, and SINV bits in SCSCMR1 4 Set value in SCBRR1 5 In SCSCR1, set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. 6 Wait 1-bit interval elapsed? No Yes Set TIE, RIE, TE, and RE bits in SCSCR1 7 End Figure 17.7 Sample Initialization Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 791 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. 2. 3. 4. Perform smart card interface mode initialization as described in Initialization above. Check that the FER/ERS error flag in SCSSR1 is cleared to 0. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. With the above processing, interrupt handling is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. Page 792 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Start Initialization 1 Start of transmission 2 FER/ERS = 0? No Yes Error handling No TEND = 1? 3 Yes Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 4 All data transmitted? 5 No Yes FER/ERS = 0? No Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 6 End of transmission Figure 17.8 Sample Transmission Processing Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 793 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from SCRDR1. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. With the above processing, interrupt handling is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. If a parity error occurs during reception and the PER flag is set to 1, the received data is still transferred to SCRDR1, and therefore this data can be read. Page 794 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface Start 1 Initialization Start of reception 2 ORER = 0 and PER = 0? No Yes Error handling No RDRF = 1? 3 Yes Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 4 All data received? 5 No Yes Clear RE bit in SCSCR1 to 0 6 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 795 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.9. Table 17.9 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit mode Receive mode Flag Mask Bit Interrupt Source Normal operation TEND TIE TXI Error FER/ERS RIE ERI Normal operation RDRF RIE RXI Error PER, ORER RIE ERI Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to 1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically, including retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. The error flag must therefore be cleared. Page 796 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 17.10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 797 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group The receive margin in smart card mode can therefore be expressed as shown in the following equation. M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (D = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 – 1/2 × 372) × 100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred. 3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to 1. 4. If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated. 5. When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Page 798 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface nth transfer frame Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n+1 (DE) 5 Ds D0 D1 D2 D3 D4 RDRF 2 4 1 3 PER Figure 17.11 Retransfer Operation in SCI Receive Mode Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received. 3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not set. 4. If an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated. nth transfer frame Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 Transfer from SCTDR1 to SCTSR1 Transfer from SCTDR1 to SCTSR1 TDRE Transfer from SCTDR1 to SCTSR1 TEND 2 4 FER/ERS 1 3 Figure 17.12 Retransfer Operation in SCI Transmit Mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 799 of 1076 Section 17 Smart Card Interface SH7750, SH7750S, SH7750R Group (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode. 2. Write 0 to the TE and RE bits in the serial control register (SCSCR1) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in standby mode. 3. Write 0 to the CKE0 bit in SCSCR1 to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 to the serial mode register (SCSMR1) and smart card mode register (SCSMR1). 6. Make the transition to the standby state. Returning from Standby Mode to Smart Card Interface Mode: 7. Clear the standby state. 8. Set the CKE1 bit in SCSCR1 to the value for the fixed output state at the start of standby (the current SCK pin state). 9. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Standby mode Normal operation 123 4 56 Normal operation 7 89 Figure 17.13 Procedure for Stopping and Restarting the Clock Page 800 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 17 Smart Card Interface (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3. Set the serial mode register (SCSMR1) and smart card mode register (SCSCMR1), and switch to smart card mode operation. 4. Set the CKE0 bit in SCSCR1 to 1 to start clock output. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 801 of 1076 Section 17 Smart Card Interface Page 802 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Section 18 I/O Ports 18.1 Overview This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: • • • • 20-bit I/O port with input/output direction independently specifiable for each bit Pull-up can be specified independently for each bit. Interrupt input is possible for 16 of the 20 I/O port bits. Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2 (BCR2). The features of the SCI I/O port are as follows: • Data can be output when the I/O port is designated for output and SCI enabling has not been set. This allows break function transmission. • The RxD pin value can be read at all times, allowing break state detection. • SCK pin control is possible when the I/O port is designated for output and SCI enabling has not been set. • The SCK pin value can be read at all times. The features of the SCIF I/O port are as follows: • Data can be output when the I/O port is designated for output and SCIF enabling has not been set. This allows break function transmission. • The RxD2 pin value can be read at all times, allowing break state detection. • CTS2 and RTS2 pin control is possible when the I/O port is designated for output and SCIF enabling has not been set. • The CTS2 and RTS2 pin values can be read at all times. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 803 of 1076 Section 18 I/O Ports 18.1.2 SH7750, SH7750S, SH7750R Group Block Diagrams Figure 18.1 shows a block diagram of the 16-bit general-purpose I/O port. PBnPUP PORTEN Pull-up resistor Internal bus PDTRW Port 15 (input/ output)/D47 to Port 0 (input/ output)/D32 1 D Q C MPX 0 Dn output data BCK 0 1 MPX DnDIR PBnIO MPX 0 Interrupt controller PTIRENn PORTEN PBnPuP DnDIR PBnIO PTIRENn 0: Port not available 0: Pull-up 0: Input 0: Input 0: Interrupt input disabled Data input strobe 1 Q C D BCK Dn input data 1: Port available 1: Pull-up off 1: Output 1: Output 1: Interrupt input enabled Figure 18.1 16-Bit Port Page 804 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Figure 18.2 shows a block diagram of the 4-bit general-purpose I/O port. PBnPUP Pull-up resistor PORTEN Internal bus PDTRW Port 19 (input/ output)/D51 to Port 16 (input/ output)/D48 1 D Q C MPX 0 Dn output data BCK 0 1 PBnIO Data input strobe 0 MPX MPX DnDIR 1 C Q D BCK Dn input data PORTEN PBnPuP DnDIR PBnIO 0: Port not available 0: Pull-up 0: Input 0: Input 1: Port available 1: Pull-up off 1: Output 1: Output Figure 18.2 4-Bit Port R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 805 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset R Q D SPB1IO C Internal data bus SPTRW Reset MD0/SCK Q R D SPB1DT C SPTRW Mode setting register SCI Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 18.3 MD0/SCK Pin Page 806 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Reset R Q D SPB0IO C Internal data bus SPTRW Reset MD7/TxD R Q D SPB0DT C SPTRW SCI Transmit enable signal Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.4 MD7/TxD Pin SCI RxD Serial receive data Internal data bus SPTRR Legend: Read SPTR Figure 18.5 RxD Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 807 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group SCIF I/O port block diagrams are shown in figures 18.6 to 18.9. Reset R Q D SPB2IO C Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 18.7 MD2/RxD2 Pin Page 808 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Reset R Q D CTSIO C Internal data bus SPTRW Reset CTS2 R Q D CTSDT C SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.8 CTS2 Pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 809 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group Reset R Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R Q D RTSDT C SPTRW Mode setting register SCIF Modem control enable signal* RTS2 signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. Figure 18.9 MD8/RTS2 Pin Page 810 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 18.1.3 Section 18 I/O Ports Pin Configuration Table 18.1 shows the 20-bit general-purpose I/O port pin configuration. Table 18.1 20-Bit General-Purpose I/O Port Pins Pin Name Signal I/O Function Port 19 pin PORT19/D51 I/O I/O port Port 18 pin PORT18/D50 I/O I/O port Port 17 pin PORT17/D49 I/O I/O port Port 16 pin PORT16/D48 I/O I/O port Port 15 pin PORT15/D47 I/O* I/O port / GPIO interrupt Port 14 pin PORT14/D46 I/O* I/O port / GPIO interrupt Port 13 pin PORT13/D45 I/O* I/O port / GPIO interrupt Port 12 pin PORT12/D44 I/O* I/O port / GPIO interrupt Port 11 pin PORT11/D43 I/O* I/O port / GPIO interrupt Port 10 pin PORT10/D42 I/O* I/O port / GPIO interrupt Port 9 pin PORT9/D41 I/O* I/O port / GPIO interrupt Port 8 pin PORT8/D40 I/O* I/O port / GPIO interrupt Port 7 pin PORT7/D39 I/O* I/O port / GPIO interrupt Port 6 pin PORT6/D38 I/O* I/O port / GPIO interrupt Port 5 pin PORT5/D37 I/O* I/O port / GPIO interrupt Port 4 pin PORT4/D36 I/O* I/O port / GPIO interrupt Port 3 pin PORT3/D35 I/O* I/O port / GPIO interrupt Port 2 pin PORT2/D34 I/O* I/O port / GPIO interrupt Port 1 pin PORT1/D33 I/O* I/O port / GPIO interrupt Port 0 pin PORT0/D32 I/O* I/O port / GPIO interrupt Note: * When port pins are used as GPIO interrupts, they must be set to input mode. The input setting can be made in the PCTRA register. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 811 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin MD0/SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection can be performed by means of a setting in the SCI's SCSPTR1 register. Table 18.3 shows the SCIF I/O port pin configuration. Table 18.3 SCIF I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin MRESET/SCK2 Input Clock input Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin CTS2 I/O Transmission enabled Modem control pin MD8/RTS2 I/O Transmission request Note: The MRESET/SCK2 pin functions as the MRESET manual reset pin when a manual reset is executed. The MD1/TxD2, MD2/RxD2, and MD8/RTS2 pins function as the MD1, MD2, and MD8 mode input pins after a power-on reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE and RE bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Page 812 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 18.1.4 Section 18 I/O Ports Register Configuration The 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Name Abbreviation R/W Initial Value* P4 Address Port control register A PCTRA R/W H'00000000 H'FF80002C H'1F80002C 32 Port data register A PDTRA R/W Undefined H'FF800030 H'1F800030 16 Port control register B PCTRB R/W H'00000000 H'FF800040 H'1F800040 32 Port data register B PDTRB R/W Undefined H'FF800044 H'1F800044 16 GPIO interrupt control register GPIOIC R/W H'00000000 H'FF800048 H'1F800048 16 Serial port register SCSPTR1 R/W Undefined H'FFE0001C H'1FE0001C 8 Serial port register SCSPTR2 R/W Undefined H'FFE80020 H'1FE80020 16 Note: * Area 7 Address Access Size Initialized by a power-on reset. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 813 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group 18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port should be set to output with PCTRA after writing a value to the PDTRA register. PCTRA is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Page 814 of 1076 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PB7PUP PB7IO PB6PUP PB6IO PB5PUP PB5IO PB4PUP PB4IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB3PUP PB3IO PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 0–15) of 16-bit port is pulled up 1 Bit m (m = 0–15) of 16-bit port is not pulled up (Initial value) Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 0–15) of 16-bit port is an input 1 Bit m (m = 0–15) of 16-bit port is an output 18.2.2 (Initial value) Port Data Register A (PDTRA) Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port. When a bit is set as an output, the value written to the PDTRA register is output from the external pin. When a value is read from the PDTRA register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRA register is read. PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT Initial value: R/W: Bit: Initial value: R/W: PB8DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 8 Page 815 of 1076 Section 18 I/O Ports 18.2.3 SH7750, SH7750S, SH7750R Group Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 4-bit port should be set to output with PCTRB after writing a value to the PDTRB register. PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PB19PUP PB19IO PB18PUP PB18IO PB17PUP PB17IO PB16PUP PB16IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Page 816 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Bit 2n + 1 (n = 0–3)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 4-bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 16–19) of 4-bit port is pulled up 1 Bit m (m = 16–19) of 4-bit port is not pulled up (Initial value) Bit 2n (n = 0–3)—Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 16–19) of 4-bit port is an input 1 Bit m (m = 16–19) of 4-bit port is an output 18.2.4 (Initial value) Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit in the 4-bit port. When a bit is set as an output, the value written to the PDTRB register is output from the external pin. When a value is read from the PDTRB register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRB register is read. PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — PB19DT PB18DT PB17DT PB16DT Initial value: 0 0 0 0 — — — — R/W: R R R R R/W R/W R/W R/W R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 817 of 1076 Section 18 I/O Ports 18.2.5 SH7750, SH7750S, SH7750R Group GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can be identified by reading the PDTRA register. Bit: 15 14 13 12 11 10 9 8 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 PTIREN8 Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit n (n = 0–15)—Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn Description 0 Port m (m = 0–15) of 16-bit port is used as a normal I/O port (Initial value) 1 Port m (m = 0–15) of 16-bit port is used as a GPIO interrupt* Note: * When using an interrupt, set the corresponding port to input in the PCTRA register before making the PTIRENn setting. Page 818 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 18.2.6 Section 18 I/O Ports Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 EIO — — — 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SPB1IO SPB1DT SPB0IO SPB0DT The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): See section 15.2.8, Serial Port Register (SCSPTR1). Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 (Initial value) Page 819 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level Page 820 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 18.2.7 Section 18 I/O Ports Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT — — Initial value: R/W: SPB2IO SPB2DT 0 — 0 — 0 0 0 — R/W R/W R/W R/W R R R/W R/W The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. CTS2 pin data reading and output data writing can be performed by means of bits 5 and 4, and RTS2 pin data reading and output data writing by means of bits 7 and 6. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies serial port RTS2 pin input/output. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to the RTS2 pin 1 RTSDT bit value is output to the RTS2 pin R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 (Initial value) Page 821 of 1076 Section 18 I/O Ports SH7750, SH7750S, SH7750R Group Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the RTS2 pin is designated as an output, the value of the RTSDT bit is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies serial port CTS2 pin input/output. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to the CTS2 pin 1 CTSDT bit value is output to the CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO pin (see the description of bit 5, CTSIO, for details). When the CTS2 pin is designated as an output, the value of the CTSDT bit is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bits 3 and 2—Reserved: These bits are always read as 0, and should only be written with 0. Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin Page 822 of 1076 (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 18 I/O Ports Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 823 of 1076 Section 18 I/O Ports Page 824 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 19 Interrupt Controller (INTC) Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features. • Fifteen interrupt priority levels can be set By setting the three interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. • NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception service routine, enabling it to be used as a noise canceler. • NMI request masking when SR.BL bit is set to 1 It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set to 1. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the INTC. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 825 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group NMI Input control IRL3– IRL0 4 4 TMU (Interrupt request) RTC (Interrupt request) SCI (Interrupt request) SCIF (Interrupt request) SR WDT (Interrupt request) IMASK REF (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request) GPIO (Interrupt request) Interrupt request Comparator Priority identifier CPU IPR IPRA–IPRD*1 INTPRI00*2 Bus interface Internal bus ICR INTC Legend: TMU: Timer unit RTC: Realtime clock unit SCI: Serial communication interface SCIF: Serial communication interface with FIFO WDT: Watchdog timer REF: Memory refresh controller section of the bus state controller DMAC: Direct memory access controller H-UDI: High-performance user debug interface GPIO: I/O port ICR: Interrupt control register IPRA–IPRD: Interrupt priority registers A–D*1 INTPRI00: Interrupt priority level setting register 00*2 SR: Status register Notes: 1. IPRD is provided only in the SH7750S and SH7750R. 2. INTPRI00 is provided only in the SH7750R. Figure 19.1 Block Diagram of INTC Page 826 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.1.3 Section 19 Interrupt Controller (INTC) Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Abbreviation I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt input pins IRL3–IRL0 Input Input of interrupt request signals (maskable by IMASK in SR) 19.1.4 Register Configuration The INTC has the registers shown in table 19.2. Table 19.2 INTC Registers Name Abbreviation R/W Initial Value*1 P4 Address Area 7 Address Access Size Interrupt control register ICR R/W *2 H'FFD00000 H'1FD00000 16 Interrupt priority register A IPRA R/W H'0000 H'FFD00004 H'1FD00004 16 Interrupt priority register B IPRB R/W H'0000 H'FFD00008 H'1FD00008 16 Interrupt priority register C IPRC R/W H'0000 H'FFD0000C H'1FD0000C 16 Interrupt priority register D*3 IPRD R/W H'DA74 H'FFD00010 H'1FD00010 16 Interrupt priority level setting 4 register 00* INTPRI00 R/W H'00000000 H'FE080000 H'1E080000 32 Interrupt source register 00*4 INTREQ00 R H'00000000 H'FE080020 H'1E080020 32 Interrupt mask register 00*4 INTMSK00 R/W H'00000300 H'FE080040 H'1E080040 32 R — H'FE080060 H'1E080060 32 Interrupt mask INTMSKCLR clear register 00*4 00 Notes: 1. Initialized by a power-on reset or manual reset. 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 827 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group 3. SH7750S and SH7750R only 4. SH7750R only 19.2 Interrupt Sources There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK) in the status register (SR). Page 828 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.2.2 Section 19 Interrupt Controller (INTC) IRL Interrupts IRL interrupts are input by level at pins IRL3–IRL0. The priority level is the level indicated by pins IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7750 SH7750S SH7750R Priority encoder Interrupt requests 4 IRL3 to IRL0 IRL3 to IRL0 Figure 19.2 Example of IRL Interrupt Connection R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 829 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group Table 19.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 IRL2 IRL1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 IRL0 Interrupt Priority Level Interrupt Request 0 15 Level 15 interrupt request 1 14 Level 14 interrupt request 0 13 Level 13 interrupt request 1 12 Level 12 interrupt request 0 11 Level 11 interrupt request 1 10 Level 10 interrupt request 0 9 Level 9 interrupt request 1 8 Level 8 interrupt request 0 7 Level 7 interrupt request 1 6 Level 6 interrupt request 0 5 Level 5 interrupt request 1 4 Level 4 interrupt request 0 3 Level 3 interrupt request 1 2 Level 2 interrupt request 0 1 Level 1 interrupt request 1 0 No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the IRL pin change is detected. In standby mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt handling. Pins IRL0–IRL3 can be used for four independent interrupt requests by setting the IRLM bit to 1 in the ICR register. When independent interrupt requests are used in the SH7750, the interrupt priority levels are fixed (table 19.4). When independent interrupt requests are used in the SH7750S or SH7750R, the interrupt priority levels can be set in interrupt priority register D (IPRD). Page 830 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 19 Interrupt Controller (INTC) Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1) IRL3 IRL2 IRL1 IRL0 Interrupt Priority Level Interrupt Request 1/0 1/0 1/0 0 13 IRL0 1/0 1/0 0 1 10 IRL1 1/0 0 1 1 7 IRL2 0 1 1 1 4 IRL3 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following nine modules: • • • • • • • • • High-performance user debug interface (H-UDI) Direct memory access controller (DMAC) Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Serial communication interface with FIFO (SCIF) Bus state controller (BSC) Watchdog timer (WDT) I/O port (GPIO) Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D (IPRA–IPRD), 00 (INTPRI00). The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. In the case of interrupts on channel 3 or 4 of the TMU, also read from the interrupt source register 00 (INTREQ00). This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 831 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. 19.2.4 Interrupt Exception Handling and Priority Table 19.5 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. The order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD). The order of priority of the on-chip peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.5. Updating of interrupt priority registers A to D, 00 should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing internally. Page 832 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 19 Interrupt Controller (INTC) Table 19.5 Interrupt Exception Handling Sources and Priority Order Interrupt Source INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within IPR Setting Unit Default Priority NMI H'1C0 16 — — IRL IRL3–IRL0 = 0 H'200 15 — — IRL3–IRL0 = 1 H'220 14 — — IRL3–IRL0 = 2 H'240 13 — — IRL3–IRL0 = 3 H'260 12 — — IRL3–IRL0 = 4 H'280 11 — — IRL3–IRL0 = 5 H'2A0 10 — — High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low IRL3–IRL0 = 6 H'2C0 9 — — IRL3–IRL0 = 7 H'2E0 8 — — IRL3–IRL0 = 8 H'300 7 — — IRL3–IRL0 = 9 H'320 6 — — IRL3–IRL0 = A H'340 5 — — IRL3–IRL0 = B H'360 4 — — IRL3–IRL0 = C H'380 3 — — IRL3–IRL0 = D H'3A0 2 — — IRL3–IRL0 = E H'3C0 1 — — IPRD (15– 1 12)* — 1 IRL0 H'240 15–0 (13)* IRL1 H'2A0 15–0 (10)*1 IPRD (11–8)*1 — IRL2 H'300 15–0 (7)*1 IPRD (7–4)*1 — IRL3 H'360 1 15–0 (4)* IPRD (3–0)*1 — H-UDI H-UDI H'600 15–0 (0) IPRC (3–0) — GPIO GPIOI H'620 15–0 (0) IPRC (15–12) — DMAC DMTE0 H'640 15–0 (0) IPRC (11–8) DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0 DMTE4*2 H'780 2 DMTE5* H'7A0 DMTE6*2 H'7C0 DMTE7*2 H'7E0 DMAE H'6C0 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low Page 833 of 1076 Section 19 Interrupt Controller (INTC) Interrupt Source SH7750, SH7750S, SH7750R Group INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within IPR Setting Unit Default Priority High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low TMU3 TUNI3*2 H'B00 15–0 (0) INTPRI00 (11–8) — TMU4 TUNI4*2 H'B80 15–0 (0) INTPRI00 (15–12) — TMU0 TUNI0 H'400 15–0 (0) IPRA (15–12) — TMU1 TUNI1 H'420 15–0 (0) IPRA (11–8) — TMU2 TUNI2 H'440 15–0 (0) IPRA (7–4) High TICPI2 H'460 ATI H'480 PRI H'4A0 RTC Low 15–0 (0) IPRA (3–0) High ↑ ⏐ ↓ Low 15–0 (0) IPRB (7–4) High ↑ ⏐ ⏐ ↓ Low 15–0 (0) IPRC (7–4) High ↑ ⏐ ⏐ ↓ Low CUI H'4C0 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 ERI H'700 RXI H'720 BRI H'740 TXI H'760 WDT ITI H'560 15–0 (0) IPRB (15–12) — REF RCMI H'580 15–0 (0) IPRB (11–8) ROVI H'5A0 SCI SCIF High Low Legend: TUNI0–TUNI4: Underflow interrupts TICPI2: Input capture interrupt ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt Page 834 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 19 Interrupt Controller (INTC) RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: High-performance use debug interface GPIOI: I/O port interrupt DMTE0–DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt Notes: 1. Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the SH7750, the initial values cannot be changed. 2. SH7750R only 19.3 Register Descriptions 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 835 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group IPRD (SH7750S and SH7750R only) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 1 1 0 1 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 1 1 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 19.6 shows the relationship between the interrupt request sources and the IPRA–IPRD register bits. Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12 11–8 Interrupt priority register A TMU0 TMU1 1 7–4 3–0 TMU2 RTC Interrupt priority register B WDT REF* SCI Reserved*2 Interrupt priority register C GPIO DMAC SCIF H-UDI Interrupt priority register D*3 IRL0 IRL1 IRL2 IRL3 Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus State Controller (BSC), for details. 2. Reserved bits: These bits are always read as 0 and should always be written with 0. 3. SH7750S and SH7750R only As shown in table 19.6, four on-chip peripheral modules are assigned to each register. Interrupt priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the fourbit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). Page 836 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.3.2 Section 19 Interrupt Controller (INTC) Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode. Bit: 15 14 13 12 11 10 9 8 Bit name: NMIL MAI — — — — NMIB NMIE Initial value: 0/1* 0 0 0 0 0 0 0 R/W: R R/W — — — — R/W R/W Bit: 7 6 5 4 3 2 1 0 IRLM — — — — — — — 0 0 0 0 0 0 0 0 R/W — — — — — — — Bit name: Initial value: R/W: Note: * 1 when NMI pin input is high, 0 when low. Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. Bit 15: NMIL Description 0 NMI pin input level is low 1 NMI pin input level is high Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU's SR.BL bit. Bit 14: MAI Description 0 Interrupts enabled even while NMI pin is low 1 Note: (Initial value) Interrupts disabled while NMI pin is low* * NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 837 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB Description 0 NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) 1 NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information will be lost, and so must be saved beforehand. 2. This bit is cleared automatically by NMI acceptance. Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. Bit 8: NMIE Description 0 Interrupt request detected on falling edge of NMI input 1 Interrupt request detected on rising edge of NMI input (Initial value) Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as levelencoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM Description 0 IRL pins used as level-encoded interrupt requests 1 IRL pins used as four independent interrupt requests (level-sense IRQ mode) (Initial value) Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written with 0. Page 838 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.3.3 Section 19 Interrupt Controller (INTC) Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only) The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15−0) for the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R Initial value: 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00. Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register Bit Register 31 to 28 InterruptReserved priority-level setting register 00 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0 Reserved Reserved Reserved TMU ch4 TMU ch3 Reserved Reserved Note: As shown in the table above, levels for all eight on-chip peripheral modules are assigned in a single register. The interrupt priority level for the interrupt source that corresponds to each set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that interrupt requests from that source are masked. Reserved bits are always read as 0. When writing, only 0s should be written to these bits. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 839 of 1076 Section 19 Interrupt Controller (INTC) 19.3.4 SH7750, SH7750S, SH7750R Group Interrupt Source Register 00 (INTREQ00) (SH7750R Only) The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has been sent to the INTC. The states of the bits in this register is not affected by masking of the corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register. INTREQ00 is a 32-bit read-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit 31 to 0—Interrupt Request: Each of the non-reserved bits in this register indicates that there is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 Description 0 There is no interrupt request that corresponds to this bit 1 There is an interrupt request that corresponds to this bit. Page 840 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.3.5 Section 19 Interrupt Controller (INTC) Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) The interrupt mask register 00 (INTMSK00) sets the masking of individual interrupt requests. INTMSK00 is a 32-bit register. It is initialized to H'000003FF by a reset, and retains this value in standby mode. To cancel masking of an interrupt, write a 1 to the corresponding bit in the INTMSKCLR00 register. Note that writing a 0 to a bit in INTMSK00 does not change its value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 Initial value: 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 31 to 0—Interrupt Mask: Sets the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 Description 0 Interrupt requests from the source that corresponds to this bit are accepted 1 Interrupt requests from the source that corresponds to this bit are masked (Initial value) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 841 of 1076 Section 19 Interrupt Controller (INTC) 19.3.6 SH7750, SH7750S, SH7750R Group Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt requests. INTMSKCLR00 is a 32-bit write-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — W W W W W W W W W W W W W W W W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — W W W W W W W W W W W W W W W R/W: R/W: W Bit 31 to 0⎯Interrupt Mask Clear: Each bit selects whether or not to clear the masking of the interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 Description 0 Masking of interrupt requests from the source that corresponds to the bit is not changed 1 Masking of interrupt requests from the source that corresponds to the bit is cleared 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) The relationship between the bits in these registers and interrupt sources is as shown below. Table 19.8 Bit Assignments Bit number Module Interrupt 31 to 10, 7 to 0 Reserved Reserved 9 TMU TUNI4 8 TMU TUNI3 Page 842 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence Section 19 Interrupt Controller (INTC) The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers A to C (IPRA–IPRC). Lowerpriority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.5, Interrupt Exception Handling Sources and Priority Order, is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. The R15 contents at this time are saved in SGR. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the particular interrupt source. Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.9 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. 3. For some interrupt sources, their interrupt masks (INTMSK00) must e cleared using the INTMSKCLR00 register. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 843 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group Program execution state Interrupt generated? No Yes (BL bit in SR = 0) or (sleep or standby mode)? No NMIB in ICR = 1 and NMI? Yes No No NMI? Yes Yes No Level 15 interrupt? Yes Yes IMASK* = level 14 or lower? No Set interrupt source in INTEVT Yes Level 14 interrupt? Yes IMASK = level 13 or lower? No Yes Save SR to SSR; save PC to SPC No Level 1 interrupt? No Yes IMASK = level 0? No Set BL, MD, RB bits in SR to 1 Branch to exception handler Note: * IMASK: Interrupt mask bits in status register (SR) Figure 19.3 Interrupt Operation Flowchart Page 844 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.4.2 Section 19 Interrupt Controller (INTC) Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the interrupt source in the corresponding interrupt handler. 3. Save SPC and SSR to the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be shortened for urgent processing. 19.4.3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin is low, irrespective of the BL and IMASK bits in the SR register. • In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin. • In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the MAI bit is set to 1. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 845 of 1076 Section 19 Interrupt Controller (INTC) 19.5 SH7750, SH7750S, SH7750R Group Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 19.9. Table 19.9 Interrupt Response Time Number of States Item NMI RL Peripheral Modules Time for priority decision and SR mask bit comparison* 1Icyc + 4Bcyc 1Icyc + 7Bcyc 1Icyc + 2Bcyc Wait time until end of sequence being executed by CPU S – 1 (≥ 0) × Icyc S – 1 (≥ 0) × Icyc S – 1 (≥ 0) × Icyc Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started 4 × Icyc 4 × Icyc 4 × Icyc Response time Total 5Icyc + 4Bcyc + (S – 1)Icyc 5Icyc + 7Bcyc + (S – 1)Icyc 5Icyc + 2Bcyc + (S – 1)Icyc Minimum case 13Icyc 19Icyc 9Icyc When Icyc: Bcyc = 2:1 Maximum case 36 + S Icyc 60 + S Icyc 20 + S Icyc When Icyc: Bcyc = 8:1 Notes Legend: Icyc: One cycle of internal clock supplied to CPU, etc. Bcyc: One CKIO cycle S: Latency of instruction Note: * In the SH7750 and SH7750S including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is generated. Page 846 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 19.6 Usage Notes 19.6.1 NMI Interrupts (SH7750 and SH7750S Only) Section 19 Interrupt Controller (INTC) When multiple NMI interrupts are input to the NMI pin within a set period of time (which is dependent on the internal state of the CPU and the external bus state), subsequent interrupts may not be accepted. Note that this problem does not occur when sufficient time*1 is provided between NMI interrupt inputs or with non-NMI interrupts such as IRL interrupts. Workarounds: Methods 1, 2, or 3 below may be used to avoid the above problem. 1. Allow sufficient time between NMI interrupt inputs, as described in note 1, below. Note that it may not be possible to assure the above interval between NMI interrupt inputs if hazard is input to NMI, and that this may cause the device to malfunction. Design the external circuits so that no hazard is input via NMI.*2 2. Do not use NMI interrupts. Use IRL interrupts instead. 3. Workaround using software The above problem can be avoided by inserting the following lines of code*3*4 into the NMI exception handling routine. Notes: 1. If SR.BL is cleared to 0 so that one or more instructions may be executed between the handling of two NMI interrupts. 2. When changing the level of the NMI input, ensure that the high and low durations are at least 5 CKIO cycles. Also ensure that no noise pulses occur before or after level changes. 3. If the NMI exception handling routine contains code that changes the value of the SR.BL bit, the code listed below should be inserted before the point at which the change is made. 4. Registers R0 to R3 in the code sample can be changed to any general register. Also, the necessary register save and restore instructions should be inserted before and after the code listed below, as appropriate. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 847 of 1076 Section 19 Interrupt Controller (INTC) SH7750, SH7750S, SH7750R Group ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; R0 : tmp ;; R1 : Original SR ;; R2 : Original ICR ;; R3 : ICR Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH: ; (1) Set SR.IMASK = H'F stc SR, R1 ; mov R1,R0 or #H'F0,R0 ldc R0, SR Store SR ; (2) Reverse ICR.NMIE mov.l #ICR, R3 mov.w @R3, R2 mov.w #H'0100, R0 xor R2, R0 mov.w R0, @R3 bra NMIH1 ; Store ICR ; Write ICR.NMIE inverted (dummy) @R3, R0 ; dummy read ; Write ICR.NMIE nop .pool .align 4 NMIH2: ; mov.w mov.w R2, @R3 stc SR, R0 ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R1, SR ; bra NMIH3 Page 848 of 1076 Restore SR R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 19 Interrupt Controller (INTC) nop NMIH1: bra NMIH2 nop NMIH3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 849 of 1076 Section 19 Interrupt Controller (INTC) Page 850 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective selfmonitoring debugger, enabling programs to be debugged with the chip alone, without using an incircuit emulator. 20.1.1 Features The UBC has the following features. • Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions (sequential break setting: channel A → channel B). • The following can be set as break compare conditions: ⎯ Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked ⎯ Data (channel B only, 32-bit mask capability) ⎯ Bus cycle: Instruction access/operand access ⎯ Read/write ⎯ Operand size: Byte/word/longword/quadword • An instruction access cycle break can be effected before or after the instruction is executed. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 851 of 1076 Section 20 User Break Controller (UBC) 20.1.2 SH7750, SH7750S, SH7750R Group Block Diagram Figure 20.1 shows a block diagram of the UBC. Access control Address bus Data bus Channel A Access comparator BBRA BARA Address comparator BASRA BAMRA Channel B Access comparator BBRB BARB Address comparator BASRB BAMRB Data comparator BDRB BDMRB Legend: BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register Control BRCR User break trap request Figure 20.1 Block Diagram of User Break Controller Page 852 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Break address register A BARA R/W Undefined H'FF200000 H'1F200000 32 Break address mask register A BAMRA R/W Undefined H'FF200004 H'1F200004 8 Break bus cycle register A BBRA R/W H'0000 H'FF200008 H'1F200008 16 Break ASID register A BASRA R/W Undefined H'FF000014 H'1F000014 8 Break address register B BARB R/W Undefined H'FF20000C H'1F20000C 32 Break address mask register B BAMRB R/W Undefined H'FF200010 H'1F200010 8 Break bus cycle register B BBRB R/W H'0000 H'FF200014 H'1F200014 16 Break ASID register B BASRB R/W Undefined H'FF000018 H'1F000018 8 Break data register B BDRB R/W Undefined H'FF200018 H'1F200018 32 Break data mask register B BDMRB R/W Undefined H'FF20001C H'1F20001C 32 Break control register BRCR R/W H'0000* H'FF200020 H'1F200020 16 Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for details. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 853 of 1076 Section 20 User Break Controller (UBC) 20.2 Register Descriptions 20.2.1 Access to UBC Control Registers SH7750, SH7750S, SH7750R Group The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC control register contents cannot be transferred to a floating-point register using a floating-point memory load instruction. When a UBC control register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Page 854 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 20.2.2 Section 20 User Break Controller (UBC) Break Address Register A (BARA) Bit: 31 30 29 28 27 26 25 24 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W: Bit: Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 R/W: Bit: Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bit: Initial value: R/W: Legend: *: Undefined Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual address used in the channel A break conditions. BARA is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address (bits 31–0) used in the channel A break conditions. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 855 of 1076 Section 20 User Break Controller (UBC) 20.2.3 SH7750, SH7750S, SH7750R Group Break ASID Register A (BASRA) Bit: 7 6 5 4 3 2 1 0 BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Legend: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset. Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used in the channel A break conditions. 20.2.4 Break Address Mask Register A (BAMRA) Bit: 7 6 5 4 — — — — 3 2 1 0 BAMA2 BASMA BAMA1 BAMA0 Initial value: 0 0 0 0 * * * * R/W: R R R R R/W R/W R/W R/W Legend: *: Undefined Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA. BAMRA is not initialized by a power-on reset or manual reset. Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID7 to ASID0 (BASA7–BASA0) are to be masked. Bit 2: BASMA Description 0 All BASRA bits are included in break conditions 1 No BASRA bits are included in break conditions Page 856 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address 31 to 0 (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0 Description 0 0 0 All BARA bits are included in break conditions 1 Lower 10 bits of BARA are masked, and not included in break conditions 0 Lower 12 bits of BARA are masked, and not included in break conditions 1 All BARA bits are masked, and not included in break conditions 0 Lower 16 bits of BARA are masked, and not included in break conditions 1 Lower 20 bits of BARA are masked, and not included in break conditions * Reserved (cannot be set) 1 1 0 1 Legend: *: Don't care 20.2.5 Break Bus Cycle Register A (BBRA) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from among the channel A break conditions. BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 857 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 Bit 4: IDA0 0 1 Description 0 Condition comparison is not performed 1 Instruction access cycle is used as break condition (Initial value) 0 Operand access cycle is used as break condition 1 Instruction access cycle or operand access cycle is used as break condition Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. Bit 3: RWA1 Bit 2: RWA0 Description 0 0 Condition comparison is not performed 1 Read cycle is used as break condition 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition 1 (Initial value) Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of the bus cycle used as a channel A break condition. Bit 6: SZA2 Bit 1: SZA1 Bit 0: SZA0 Description 0 0 0 Operand size is not included in break conditions (Initial value) 1 Byte access is used as break condition 1 1 0 1 0 Word access is used as break condition 1 Longword access is used as break condition 0 Quadword access is used as break condition 1 Reserved (cannot be set) * Reserved (cannot be set) Legend: *: Don't care Page 858 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 20.2.6 Section 20 User Break Controller (UBC) Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register. The bit configuration is the same as for BAMRA. 20.2.9 Break Data Register B (BDRB) Bit: 31 30 29 28 27 26 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Legend: *: Undefined R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 859 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDMB2 BDMB2 BDMB2 BDMB2 BDMB1 BDMB1 BDMB1 BDMB1 3 2 1 0 9 8 7 6 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BDMB1 BDMB1 BDMB1 BDMB1 BDMB1 BDMB1 BDMB9 BDMB8 5 4 3 2 1 0 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value: R/W: Legend: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on reset or manual reset. Page 860 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data B31 to B0 (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn Description 0 Channel B break data bit BDBn is included in break conditions 1 Channel B break data bit BDBn is masked, and not included in break conditions n = 31 to 0 Note: When the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and BDMRB. 20.2.11 Break Bus Cycle Register B (BBRB) BBRB is the channel B bus break register. The bit configuration is the same as for BBRA. 20.2.12 Break Control Register (BRCR) Bit: 15 14 13 12 11 10 9 8 CMFA CMFB — — — PCBA — — Initial value: R/W: 0 0 0 0 0 * 0 0 R/W R/W R R R R/W R R 7 6 5 4 3 2 1 0 DBEB PCBB — — SEQ — — UBDE Bit: Initial value: R/W: Legend: * * 0 0 * 0 0 0 R/W R/W R R R/W R R R/W *: Undefined The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 861 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 15: CMFA Description 0 Channel A break condition is not matched 1 Channel A break condition match has occurred (Initial value) Bit 14—Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 14: CMFB Description 0 Channel B break condition is not matched 1 Channel B break condition match has occurred (Initial value) Bits 13 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bit 10—Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 10: PCBA Description 0 Channel A PC break is effected before instruction execution 1 Channel A PC break is effected after instruction execution Bits 9 and 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB Description 0 Data bus condition is not included in channel B conditions 1 Data bus condition is included in channel B conditions Note: When the data bus is included in the break conditions, bits IDB1–0 in break bus cycle register B (BBRB) should be set to 10 or 11. Page 862 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB Description 0 Channel B PC break is effected before instruction execution 1 Channel B PC break is effected after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset. Bit 3: SEQ Description 0 Channel A and B comparisons are performed as independent conditions 1 Channel A and B comparisons are performed as sequential conditions (channel A → channel B) Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see section 20.4, User Break Debug Support Function) is to be used. Bit 0: UBDE Description 0 User break debug function is not used 1 User break debug function is used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 (Initial value) Page 863 of 1076 Section 20 User Break Controller (UBC) 20.3 Operation 20.3.1 Explanation of Terms Relating to Accesses SH7750, SH7750S, SH7750R Group An instruction access is an access that obtains an instruction. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+disp×2+4 in the instruction MOV.W @(disp,PC), Rn (an access very close to the program counter) is an operand access. The fetching of an instruction from the branch destination when a branch instruction is executed is also an instruction access. As the term “data” is used to distinguish data from an address, the term “operand access” is used in this section. In this LSI, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention: • PREF, OCBP, and OCBWB instructions: Treated as read accesses. • MOVCA.L and OCBI instructions: Treated as write accesses. • TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. This LSI handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword. 20.3.2 Explanation of Terms Relating to Instruction Intervals In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions. • Example of sequence of instructions with no branch: 100 Instruction A (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A) 104 Instruction C (2 instructions after instruction A) 106 Instruction D (3 instructions after instruction A) Page 864 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) • Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) 20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR). Set the break addresses in the break address registers for each channel (BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers (BASRA, BASRB), and the address and ASID masking methods in the break address mask registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions, also set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups (RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit (in the CPU's SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not automatically cleared. Therefore, a memory store instruction should be used on the BRCR R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 865 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group register to clear the flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for Sequential Conditions, for the operation when the channel A condition match and channel B condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register. 20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a pre-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). Page 866 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. 20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Address Bits Compared Quadword (100) Address bits A31–A3 Longword (011) Address bits A31–A2 Word (010) Address bits A31–A1 Byte (001) Address bits A31–A0 Not included in condition (000) In quadword access, address bits A31–A3 In longword access, address bits A31–A2 In word access, address bits A31–A1 In byte access, address bits A31–A0 2. When data value is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions—address, ASID, and data—are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition. Set the IDB1–0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is specified, the same data should be set in the two bytes comprising bits 15–8 and bits 7–0 in break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored. 3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 867 of 1076 Section 20 User Break Controller (UBC) 20.3.6 SH7750, SH7750S, SH7750R Group Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A) → flag not set Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A) → flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. Example 1: 110 Instruction (pre-execution break on channel A) → flag set 112 Instruction (pre-execution break on channel B) → flag not set Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss) → flag set 20.3.7 Program Counter (PC) Value Saved 1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). In this case, the PC Page 868 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. The instruction at which the condition match occurred is executed, and a user break interrupt occurs before the following instruction is executed. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, the fact that memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 20.3.8 Contiguous A and B Settings for Sequential Conditions When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B Instruction B is 0 instructions after instruction A Equivalent to setting the same address. Do not use this setting. Instruction B is 1 instruction after instruction A Sequential operation is not guaranteed. Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 869 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after instruction A Sequential operation is not guaranteed. Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed. 3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after instruction A Sequential operation is not guaranteed. Instruction B is 4 or more instructions after instruction A Sequential operation is guaranteed. 4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn. 20.3.9 Usage Notes 1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. a. Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. b. Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. c. Operand access break (address/data): The BL bit value after the executed instruction is referenced. d. In the case of an instruction that modifies the BL bit Page 870 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) SL.BL PreExecution Instruction Access PostExecution Instruction Access PreExecution Instruction Access PostExecution Instruction Access Operand Access (Address/Data) 0→0 A A A A A 1→0 M M M M A 0→1 A M A M M 1→1 M M M M M Legend: A: Accepted M: Masked e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is invalid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A → A → B (user break generated) → B (no break generated) 7. In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completion type exception. Consequently, in the event of contention between a completion type exception and a post-execution break, the postexecution break is suppressed in accordance with the priorities of the two events. For example, R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 871 of 1076 Section 20 User Break Controller (UBC) SH7750, SH7750S, SH7750R Group in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition. 20.4 User Break Debug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the BRCR register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break debug support function is shown in figure 20.2. Page 872 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Exception/ interrupt/trap? Trap Interrupt EXPEVT ← exception code INTEVT ← interrupt code EXPEVT ← H'160 TRA ← TRAPA (imm) SGR ← R15 No Yes Reset exception? (BRCR.UBDE == 1) && (user break exception)? Yes No PC ← DBR PC ← VBR + vector offset Debug program Exception service routine PC ← H'A0000000 R15 ← SGR (STC instruction) Execute RTE instruction PC ← SPC SR ← SSR End of exception operations Figure 20.2 User Break Debug Support Function Flowchart R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 873 of 1076 Section 20 User Break Controller (UBC) 20.5 SH7750, SH7750S, SH7750R Group Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'00000404 with ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 Conditions set: Channel A → channel B sequential mode ⎯ Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word ⎯ Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003722E with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000 Page 874 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 20 User Break Controller (UBC) Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word ⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. Operand Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02 Data: H'0000A512 / data mask: H'00000000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000AB000 to H'000ABFFE with ASID = H'70. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 875 of 1076 Section 20 User Break Controller (UBC) 20.6 SH7750, SH7750S, SH7750R Group User Break Controller Stop Function In the SH7750S, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller. This function is not provided in the SH7750. 20.6.1 Transition to User Break Controller Stopped State Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit to 1 and enter the stopped state. (1) Initialize BBRA and BBRB to 0; (2) Initialize BRCR to 0; (3) Make a dummy read of BRCR; (4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back. (5) Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. Do not read or write the following registers while the user break controller clock is stopped: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these registers are read or written, the value cannot be guaranteed. 20.6.2 Cancelling the User Break Controller Stopped State The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps (6) and (7) below to clear the MSTP5 bit to 0 to cancel the stopped state. (6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data back; (7) Make two dummy reads of STBCR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine. Page 876 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 20.6.3 Section 20 User Break Controller (UBC) Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov #0, R0 mov.l #BBRA, R1 mov.w R0, @R1 mov.l #BBRB, R1 mov.w R0, @R1 ; (2) Initialize BRCR to 0. mov.l #BRCR, R1 mov.w R0, @R1 ; (3) Dummy read BRCR. mov.w @R1, R0 ; (4) Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 or #H'1, R0 mov.b R0, @R1 ; (5) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 ; Canceling user break controller stopped state ; (6) Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 and #H'FE, R0 mov.b R0, @R1 ; (7) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 877 of 1076 Section 20 User Break Controller (UBC) Page 878 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 21 High-performance User Debug Interface (H-UDI) Section 21 High-performance User Debug Interface (H-UDI) 21.1 Overview 21.1.1 Features The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7750R's H-UDI supports boundary-scan, but is used for emulator connection as well. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK). The pin functions and serial transfer protocol conform to the JTAG specifications. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and control registers are reset independently of the chip reset pin by driving the TRST pin low or setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and initialized in an ordinary reset. The H-UDI circuit has four internal registers: SDBPR, SDIR, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR register supports the JTAG bypass mode, SDIR is the command register, and SDDR is the data register. SDIR can be accessed directly from the TDI and TDO pins. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 879 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group Break control ASEBRK/BRKACK Interrupt/reset etc. TCK TAP controller TMS Decoder TDI SDBSR SDBPR Shift register SDIR * * SDINT SDDRH SDDRL TDO Peripheral module bus TRST MUX Note: * Provided only in the SH7750R. Figure 21.1 Block Diagram of H-UDI Circuit Page 880 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 21.1.3 Section 21 High-performance User Debug Interface (H-UDI) Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins When Not Used Pin Name Abbreviation I/O Function Clock pin TCK Input Same as the JTAG serial clock input pin. Data Open*1 is transferred from data input pin TDI to the HUDI circuit, and data is read from data output pin TDO, in synchronization with this signal. Mode pin TMS Input The mode select input pin. Changing this Open*1 signal in synchronization with TCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification. Reset pin TRST Input The input pin that resets the H-UDI. This signal *2 *3 is received asynchronously with respect to TCK, and effects a reset of the JTAG interface circuit when low. TRST must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification. Data input pin TDI Input The data input pin. Data is sent to the H-UDI circuit by changing this signal in synchronization with TCK. Data output pin TDO Output The data output pin. Data is sent to the H-UDI Open circuit by reading this signal in synchronization with TCK. Emulator pin ASEBRK/ BRKACK Input/ output Dedicated emulator pin Open*1 Open*1 Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the H-UDI, there is no problem in connecting a pullup resistance externally. 2. When designing a board that enables the use of an emulator, or when using interrupts and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on, and also provide for control by TRST alone. 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by the rating of the pull-up resistor. Although this current has no effect on the chip's operation, unnecessary current will be dissipated. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 881 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or CPG setting of this LSI such that the TCK frequency is lower than that of this LSI’s on-chip peripheral module clock. 21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side H-UDI Side R/W Access Initial 1 Size Value* H'FFFF R/W 32 H'FFFFFFFD (Fixed 2 value* ) SDDR/ R/W H'FFF00008 H'1FF00008 32/16 SDDRH Undefined — — — Data register L SDDRL R/W H'FFF0000A H'1FF0000A 16 Undefined — — — Bypass register SDBPR — Undefined R/W 1 — Interrupt source 4 register* SDINT H'0000 W* 32 H'00000000 Boundary scan 4 register* SDBSR — Undefined R/W — Undefined Abbreviation P4 R/W Address Instruction register SDIR R Data register H Name Area 7 Address Access Initial 1 Size Value* H'FFF00000 H'1FF00000 16 — — — R/W H'FFF00014 H'1FF00014 16 — — — 3 Notes: 1. Initialized when the TRST pin goes low or when the TAP is in the Test-Logic-Reset state. 2. The value read from H-UDI is fixed (H'FFFFFFFD). 3. Using the H-UDI interrupt command, a 1 can be written to the least significant bit. 4. SH7750R only Page 882 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 21 High-performance User Debug Interface (H-UDI) 21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed by the CPU while writing is in progress, it may not be possible to read the correct value. In this case, SDIR should be read twice, and then read again if the read values do not match. Operation is undefined if a reserved command is set in this register. SH7750, SH7750S: Bit: 15 14 13 12 11 10 9 8 TI3 TI2 TI1 TI0 — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bits 15 to 12—Test Instruction Bits (TI3−TI0) Bit 15: TI3 Bit 14: TI2 Bit 13: TI1 Bit 12: TI0 Description 0 0 — — Reserved 1 0 — Reserved 1 1 0 1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 0 H-UDI reset negate 1 H-UDI reset assert 0 — Reserved 1 — H-UDI interrupt 0 — Reserved 1 0 Reserved 1 Bypass mode (Initial value) Page 883 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group Bits 11 to 0—Reserved: These bits are always read as 1, and should only be written with 1. SH7750R: Bit: 15 14 13 12 11 10 9 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bits 15 to 8—Test Instruction Bits (TI7–TI0) Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TI7 TI6 TI5 TI4 TI3 TI2 TI1 Bit 8: TI0 Description 0 0 0 0 0 0 0 0 EXTEST 0 0 0 0 0 1 0 0 SAMPLE/PRELOAD 0 1 1 0 — — — — H-UDI reset negate 0 1 1 1 — — — — H-UDI reset assert 1 0 1 — — — — — H-UDI interrupt 1 1 1 1 1 1 1 1 Bypass mode (Initial value) Other than above Reserved Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1. Page 884 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 21.2.2 Section 21 High-performance User Debug Interface (H-UDI) Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by a TRST or CPU reset. Bit: 31 Initial value: 30 29 28 27 26 25 24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: R/W: Legend: *: Undefined Bits 31 to 0—DR Data: These bits store the SDDR value. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 885 of 1076 Section 21 High-performance User Debug Interface (H-UDI) 21.2.3 SH7750, SH7750S, SH7750R Group Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the H-UDI. 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by the CPU. From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the SDIR register (Update-IR). While SDIR is holding a H-UDI interrupt command, the SDINT register is connected between the TDI and TDO pins of the H-UDI, allowing it to be read as a 32bit register. In this case, the upper 16 bits will all be 0, and the lower 16 bits will represent SDINT. From the CPU, only writing a 0 to the INTREQ bit is possible. While this bit holds a 1, the interrupt requests continue to be issued, so this bit should always be cleared in the interrupt handler. This register is initialized in the Test-Logic-Reset state of TRST or TAP. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — INTREQ Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bits 15 to 1—Reserved: These bits are always read as 0. When writing, only 0s should be written here. Bit 0⎯Interrupt Request (INTREQ): Indicates whether or not an interrupt request has been issued by an H-UDI interrupt command. From the CPU, the interrupt request can be cleared by writing a 0 to this bit. If a 1 is written to this bit, it retains the value it had before the write operation. Page 886 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 21.2.5 Section 21 High-performance User Debug Interface (H-UDI) Boundary Scan Register (SDBSR) (SH7750R Only) The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the relationship between the SH7750R's pins and the boundary scan register. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 887 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group Table 21.3 Configuration of the Boundary Scan Register No. Pin Name Type to TDO No. Pin Name Type No. Pin Name Type 309 A19 OUT 272 D48 OUT 345 CKIO2ENB IN 308 A18 CTL 271 D62 IN 344 MD6/IOIS16 IN 307 A18 OUT 270 D62 CTL OUT 343 STATUS1 CTL 306 SCK2/MRESET IN 269 D62 342 STATUS1 OUT 305 SCK2/MRESET CTL 268 D49 IN 341 STATUS0 CTL 304 SCK2/MRESET OUT 267 D49 CTL 340 STATUS0 OUT 303 MD7/TXD IN 266 D49 OUT 339 A1 CTL 302 MD7/TXD CTL 265 D61 IN 338 A1 OUT 301 MD7/TXD OUT 264 D61 CTL 337 A0 CTL 300 MD8/RTS2 IN 263 D61 OUT 336 A0 OUT 299 MD8/RTS2 CTL 262 D50 IN 335 DACK1 CTL 298 MD8/RTS2 OUT 261 D50 CTL 334 DACK1 OUT 297 TCLK IN 260 D50 OUT 333 DACK0 CTL 296 TCLK CTL 259 D60 IN 332 DACK0 OUT 295 TCLK OUT 258 D60 CTL 331 MD5/RAS2 IN 294 CTS2 IN 257 D60 OUT 330 MD5/RAS2 CTL 293 CTS2 CTL 256 D51 IN 329 MD5/RAS2 OUT 292 CTS2 OUT 255 D51 CTL 328 MD4/CE2B IN 291 NMI IN 254 D51 OUT 327 MD4/CE2B CTL 290 IRL3 IN 253 D59 IN 326 MD4/CE2B OUT 289 IRL2 IN 252 D59 CTL OUT 325 MD3/CE2A IN 288 IRL1 IN 251 D59 324 MD3/CE2A CTL 287 IRL0 IN 250 D52 IN 323 MD3/CE2A OUT 286 MD2/RXD2 IN 249 D52 CTL 322 A25 CTL 285 MD1/TXD2 IN 248 D52 OUT 321 A25 OUT 284 MD1/TXD2 CTL 247 D58 IN 320 A24 CTL 283 MD1/TXD2 OUT 246 D58 CTL 319 A24 OUT 282 MD0/SCK IN 245 D58 OUT 318 A23 CTL 281 MD0/SCK CTL 244 D53 IN 317 A23 OUT 280 MD0/SCK OUT 243 D53 CTL OUT 316 A22 CTL 279 RD/WR2 CTL 242 D53 315 A22 OUT 278 RD/WR2 OUT 241 D57 IN 314 A21 CTL 277 D63 IN 240 D57 CTL 313 A21 OUT 276 D63 CTL 239 D57 OUT 312 A20 CTL 275 D63 OUT 238 D54 IN 311 A20 OUT 274 D48 IN 237 D54 CTL 310 A19 CTL 273 D48 CTL 236 D54 OUT Page 888 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin Name Type No. Pin Name Type No. Pin Name Type 235 D56 IN 196 D21 IN 157 DRAK1 OUT 234 D56 CTL 195 D21 CTL 156 A2 CTL 233 D56 OUT 194 D21 OUT 155 A2 OUT CTL 232 D55 IN 193 D25 IN 154 A3 231 D55 CTL 192 D25 CTL 153 A3 OUT 230 D55 OUT 191 D25 OUT 152 A4 CTL OUT 229 D31 IN 190 DREQ1 IN 151 A4 228 D31 CTL 189 DREQ0 IN 150 A5 CTL 227 D31 OUT 188 RXD IN 149 A5 OUT 226 D16 IN 187 D22 IN 148 A6 CTL 225 D16 CTL 186 D22 CTL 147 A6 OUT 224 D16 OUT 185 D22 OUT 146 A7 CTL 223 D30 IN 184 D24 IN 145 A7 OUT 222 D30 CTL 183 D24 CTL 144 A8 CTL 221 D30 OUT 182 D24 OUT 143 A8 OUT CTL 220 D17 IN 181 D23 IN 142 A9 219 D17 CTL 180 D23 CTL 141 A9 OUT 218 D17 OUT 179 D23 OUT 140 A10 CTL 217 D29 IN 178 WE7/CAS7/DQM7/REG CTL 139 A10 OUT 216 D29 CTL 177 WE7/CAS7/DQM7/REG OUT 138 A11 CTL 215 D29 OUT 176 WE6/CAS6/DQM6 CTL 137 A11 OUT CTL 214 D18 IN 175 WE6/CAS6/DQM6 OUT 136 A12 213 D18 CTL 174 WE3/CAS3/DQM3/ICIOWR CTL 135 A12 OUT 212 D18 OUT 173 WE3/CAS3/DQM3/ICIOWR OUT 134 A13 CTL 211 D28 IN 172 WE2/CAS2/DQM2/ICIORD CTL 133 A13 OUT 210 D28 CTL 171 WE2/CAS2/DQM2/ICIORD OUT 132 A14 CTL 209 D28 OUT 170 RD/WR CTL 131 A14 OUT 208 D19 IN 169 RD/WR OUT 130 A15 CTL 207 D19 CTL 168 RD/CASS/FRAME CTL 129 A15 OUT 206 D19 OUT 167 RD/CASS/FRAME OUT 128 A16 CTL 205 D27 IN 166 RAS CTL 127 A16 OUT 204 D27 CTL 165 RAS OUT 126 A17 CTL 203 D27 OUT 164 CS2 CTL 125 A17 OUT 202 D20 IN 163 CS2 OUT 124 WE0/CAS0/DQM0 CTL 201 D20 CTL 162 CS3 CTL 123 WE0/CAS0/DQM0 OUT 200 D20 OUT 161 CS3 OUT 122 WE1/CAS1/DQM1 CTL 199 D26 IN 160 DRAK0 CTL 121 WE1/CAS1/DQM1 OUT 198 D26 CTL 159 DRAK0 OUT 120 WE4/CAS4/DQM4 CTL 197 D26 OUT 158 DRAK1 CTL 119 WE4/CAS4/DQM4 OUT R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 889 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group No. Pin Name Type No. Pin Name Type No. Pin Name Type 118 WE5/CAS5/DQM5 CTL 78 D13 IN 38 D35 CTL 117 WE5/CAS5/DQM5 OUT 77 D13 CTL 37 D35 OUT 116 CKE CTL 76 D13 OUT 36 D44 IN 115 CKE OUT 75 D1 IN 35 D44 CTL 114 D7 IN 74 D1 CTL 34 D44 OUT 113 D7 CTL 73 D1 OUT 33 D34 IN 112 D7 OUT 72 D14 IN 32 D34 CTL 111 D8 IN 71 D14 CTL 31 D34 OUT 110 D8 CTL 70 D14 OUT 30 D45 IN 109 D8 OUT 69 D0 IN 29 D45 CTL 108 BREQ/BSACK IN 68 D0 CTL 28 D45 OUT 107 BACK/BSREQ CTL 67 D0 OUT 27 D33 IN 106 BACK/BSREQ OUT 66 D15 IN 26 D33 CTL 105 D6 IN 65 D15 CTL 25 D33 OUT 104 D6 CTL 64 D15 OUT 24 D46 IN 103 D6 OUT 63 D39 IN 23 D46 CTL 102 D9 IN 62 D39 CTL 22 D46 OUT 101 D9 CTL 61 D39 OUT 21 D32 IN 100 D9 OUT 60 D40 IN 20 D32 CTL 99 D5 IN 59 D40 CTL 19 D32 OUT 98 D5 CTL 58 D40 OUT 18 D47 IN 97 D5 OUT 57 D38 IN 17 D47 CTL 96 D10 IN 56 D38 CTL 16 D47 OUT 95 D10 CTL 55 D38 OUT 15 RD2 CTL 94 D10 OUT 54 D41 IN 14 RD2 OUT 93 D4 IN 53 D41 CTL 13 BS CTL 92 D4 CTL 52 D41 OUT 12 BS OUT 91 D4 OUT 51 D37 IN 11 CS6 CTL OUT 90 D11 IN 50 D37 CTL 10 CS6 89 D11 CTL 49 D37 OUT 9 CS5 CTL 88 D11 OUT 48 D42 IN 8 CS5 OUT 87 D3 IN 47 D42 CTL 7 CS4 CTL 86 D3 CTL 46 D42 OUT 6 CS4 OUT 85 D3 OUT 45 D36 IN 5 CS1 CTL 84 D12 IN 44 D36 CTL 4 CS1 OUT 83 D12 CTL 43 D36 OUT 3 CS0 CTL 82 D12 OUT 42 D43 IN 2 CS0 OUT 81 D2 IN 41 D43 CTL 1 RDY IN 80 D2 CTL 40 D43 OUT from TDI 79 D2 OUT 39 D35 IN Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW. Page 890 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 21.3 Operation 21.3.1 TAP Control Section 21 High-performance User Debug Interface (H-UDI) Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK. • The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. • The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO is in the high-impedance state. • In a transition to TRST = 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to TCK. 1 Test-Logic-Reset 0 Run-Test/Idle 0 1 Select-DR-Scan 1 Select-IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 Figure 21.2 TAP Control State Transition Diagram R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 891 of 1076 Section 21 High-performance User Debug Interface (H-UDI) 21.3.2 SH7750, SH7750S, SH7750R Group H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. H-UDI reset assert H-UDI pin H-UDI reset negate Chip internal reset CPU state Normal Reset Reset processing Figure 21.3 H-UDI Reset 21.3.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an RTE instruction. The exception code stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be controlled with bits 3 to 0 of control register IPRC. In the SH7750 or SH7750S, the H-UDI interrupt request signal is asserted for about eight cycles of the LSI's on-chip peripheral clock after the command is set. The number of cycles for assertion is determined by the ratio of TCK to the frequency of the on-chip peripheral clock. Since the period of assertion is limited, the CPU may miss a request. In the SH7750R, the H-UDI interrupt request signal is asserted when the INTREQ bit in the SDINT register is set to 1 after the command is set (Update-IR). The interrupt request signal will not be negated unless a 0 is written to the INTREQ bit by software; therefore, the CPU will not miss a request. As long as the H-UDI interrupt command is set in SDIR, the SDINT register is connected between the TDI and TDO pins. Note that, in the SH7750 or SH7750S, the H-UDI interrupt command automatically becomes a bypass command immediately after it has been set. In the SH7750R, the command is not changed Page 892 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 21 High-performance User Debug Interface (H-UDI) except by the following operations: update in the Update-IR state, initialization in the Test-LogicReset state, and initialization by assertion of TRST. 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) In the SH7750R, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode. However, the following limitations apply. 1. Boundary scan does not cover clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, and CKIO). 2. Boundary scan does not cover reset-related signals (RESET, CA) 3. Boundary scan does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. With EXTEST, assert the MRESET pin (low), the RESET pin (low), and CA pin (high). With SAMPLE/PRELOAD, assert the CA pin (high). 5. To perform boundary scan, supply a clock to the EXTAL pin, and wait for the power-on oscillation settling time to elapse before starting boundary scan. The frequency range of the input clock is from 1 to 33.3 MHz. Note that after the power-on oscillation settling time has elapsed, a clock does not need to be supplied to the EXTAL pin any longer. For details on the power-on oscillation settling time, see section 22, Electrical Characteristics. 21.4 Usage Notes 1. SDIR Command Once an SDIR command has been set, it remains unchanged until initialization by asserting TRST or placing the TAP in the Test-Logic-Reset state, or until another command (other than an H-UDI interrupt command) is written from the H-UDI. 2. SDIR Commands in Sleep Mode Sleep mode is cleared by an H-UDI interrupt or H-UDI reset, and these exception requests are accepted in this mode. In standby mode, neither an H-UDI interrupt nor an H-UDI reset is accepted. 3. In standby mode, the H-UDI function cannot be used. Furthermore, TCK must be retained at a high level when entering the standby mode in order to retain the TAP state before and after standby mode. 4. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. 5. The H-UDI pins of the SH7750 and SH7750S must not be connected to a boundary-scan signal loop on the board. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 893 of 1076 Section 21 High-performance User Debug Interface (H-UDI) SH7750, SH7750S, SH7750R Group 6. In BYPASS mode on the SH7750 or SH7750S, the contents of the bypass register (SDBPR) are undefined in the Capture-DR state. On the SH7750R, SDBPR has a value of 0. Page 894 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit 1 I/O, PLL, RTC, CPG power supply voltage VDDQ VDD-PLL1/2 VDD-RTC VDD-CPG –0.3 to 4.2, –0.3 to 4.6* V Internal power supply voltage VDD –0.3 to 2.5, –0.3 to 2.1*1 V Input voltage Vin –0.3 to VDDQ +0.3 V Operating temperature Topr –20 to 75, –40 to 85* Storage temperature Tstg –55 to 125 2 °C °C Notes: Permanent damage to the chip may result if the maximum ratings are exceeded. Permanent damage to the chip may result if all VSS pins are not connected to GND. For information on the power-on and power-off procedures, refer to appendix H, Power-On and Power-Off Procedures. 1. HD6417750R only 2. HD6417750RBA240HV only R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 895 of 1076 Section 22 Electrical Characteristics 22.2 SH7750, SH7750S, SH7750R Group DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) Ta = –20 to +75°C*3 Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.4 1.5 1.6 IDD — 230 580 Sleep mode — — 120 Standby mode — — 400 — — 800 — 170 215 Sleep mode — 35 40 Standby mode — — 440 — — 880 — 15 25 3 5 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 — — 1 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current Standby dissipation mode IDD-RTC Input voltage RESET, NMI, TRST VIH Other input pins RESET, NMI, TRST VIL Other input pins Input leakage current All input pins Page 896 of 1076 |Iin| Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 240 MHz μA Ta = 25°C* 1 Ta > 50°C*1 mA Ick = 240 MHz, Bck = 120 MHz μA Ta = 25°C*1 1 Ta > 50°C* μA RTC on*2 RTC off V μA VIN = 0.5 to VDDQ –0.5 V R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions Three-state leakage current I/O, all output pins (off state) |Isti| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Output voltage All output pins VOH 2.4 — — V IOH = –2 mA VOL — — 0.55 Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. 3. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 897 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.3 DC Characteristics (HD6417750RF240 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.4 1.5 1.6 IDD — 230 580 Sleep mode — — 120 Standby mode — — 400 — — 800 — 140 180 Sleep mode — 35 40 Standby mode — — 440 — — 880 — 15 25 3 5 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current Standby dissipation mode IDD-RTC Input voltage RESET, NMI, TRST VIH Other input pins RESET, NMI, TRST VIL Other input pins Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 240 MHz μA Ta = 25°C*1 1 Ta > 50°C* mA Ick = 240 MHz, Bck = 80 MHz μA Ta = 25°C*1 1 Ta > 50°C* μA RTC on*2 RTC off V Input leakage current All input pins |Iin| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Three-state leakage current I/O, all output pins (off state) |Isti| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Page 898 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOH 2.4 — — V IOH = –2 mA VOL — — 0.55 Output voltage All output pins Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 899 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*3) Ta = –20 to +75°C*4 Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.35 1.5 1.6 IDD — 190 480 Sleep mode — — 100 Standby mode — — 400 — — 800 — 140 180 Sleep mode — 30 35 Standby mode — — 440 — — 880 — 15 25 3 5 VDDQ × 0.9 — VDDQ + 0.3 Other input pins 2.0 — VDDQ + 0.3 RESET, VIL NMI, TRST –0.3 — VDDQ × 0.1 Other input pins –0.3 — VDDQ × 0.2 Current dissipation Current dissipation RTC current dissipation Normal operation Normal operation Standby mode IDDQ IDD-RTC Input voltage RESET, VIH NMI, TRST Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz μA Ta = 25°C*1 1 Ta > 50°C* mA Ick = 200 MHz, Bck = 100 MHz μA Ta = 25°C*1 Ta > 50°C*1 μA RTC on*2 RTC off V Input leakage All input current pins |Iin| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Three-state leakage current |Isti| — — 1 μA VIN = 0.5 to VDDQ –0.5 V I/O, all output pins (off state) Page 900 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOH 2.4 — — V IOH = –2 mA VOL — — 0.55 Output voltage All output pins Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG 3.3 V system currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. 3. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 901 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.5 DC Characteristics (HD6417750RF200 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.35 1.5 1.6 IDD — 190 480 Sleep mode — — 100 Standby mode — — 400 — — 800 — 140 180 Sleep mode — 30 35 Standby mode — — 440 — — 880 — 15 25 3 5 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current Standby dissipation mode IDD-RTC Input voltage RESET, NMI, TRST VIH Other input pins RESET, NMI, TRST VIL Other input pins Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz μA Ta = 25°C*1 1 Ta > 50°C* mA Ick = 200 MHz, Bck = 67 MHz μA Ta = 25°C*1 1 Ta > 50°C* μA RTC on*2 RTC off V Input leakage current All input pins |Iin| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Three-state leakage current I/O, all output pins (off state) |Isti| — — 1 μA VIN = 0.5 to VDDQ –0.5 V Page 902 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOH 2.4 — — V IOH = –2 mA VOL — — 0.55 Output voltage All output pins Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 903 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.6 DC Characteristics (HD6417750SBP200 (V), HD6417750SBA200V) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.8 1.95 2.07 IDD — 410 780 Sleep mode — 165 210 Standby mode — — 2000 — — 5000 — 140 180 Sleep mode — 40 50 Standby mode — — 2200 — — 5500 — 15 25 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current During RTC IDD-RTC dissipation operation Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 200 MHz, Bck = 100 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST VIH VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Other input pins RESET, NMI, TRST VIL Other input pins Output voltage All output pins Page 904 of 1076 V V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 905 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.7 DC Characteristics (HD6417750SF200 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.8 1.95 2.07 IDD — 410 780 Sleep mode — 165 210 Standby mode — — 2000 — — 5000 — 140 180 Sleep mode — 40 50 Standby mode — — 2200 — — 5500 — 15 25 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current During RTC IDD-RTC dissipation operation Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 200 MHz, Bck = 67 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST VIH VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Other input pins RESET, NMI, TRST VIL Other input pins Output voltage All output pins Page 906 of 1076 V V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 907 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.8 DC Characteristics (HD6417750BP200M (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.8 1.95 2.07 IDD — 1000 1200 Sleep mode — 165 — Standby mode — — 2000 — — 5000 — 160 200 Sleep mode — 40 — Standby mode — — 2200 — — 5500 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Current dissipation Current dissipation Normal operation Normal operation Input voltage RESET, NMI, TRST IDDQ VIH Other input pins RESET, NMI, TRST VIL Other input pins Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 200 MHz, Bck = 100 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) V Output voltage All output pins Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Page 908 of 1076 V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 909 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.9 DC Characteristics (HD6417750SF167 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.6 1.8 2.0 IDD — 320 650 Sleep mode — 120 150 Standby mode — 50 400 — 100 800 — 140 180 Sleep mode — 40 50 Standby mode — 110 440 — 220 880 — 15 45 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current During RTC IDD-RTC dissipation operation Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 167 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA μA Ick = 167 MHz, Bck = 84 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST VIH VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Other input pins RESET, NMI, TRST VIL Other input pins Output voltage All output pins Page 910 of 1076 V V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 911 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.10 DC Characteristics (HD6417750F167 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.6 1.8 2.0 IDD — 630 700 Sleep mode — 120 — Standby mode — — 400 — — 800 — 160 200 Sleep mode — 40 — Standby mode — — 440 — — 880 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Current dissipation Current dissipation Normal operation Normal operation Input voltage RESET, NMI, TRST IDDQ VIH Other input pins RESET, NMI, TRST VIL Other input pins Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 167 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) V Output voltage All output pins Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Page 912 of 1076 Ick = 167 MHz, Bck = 84 MHz V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 913 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.11 DC Characteristics (HD6417750SVF133 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.4 1.5 1.7 IDD — 210 520 Sleep mode — 50 60 Standby mode — — 100 — — 200 — 80 160 Sleep mode — 35 40 Standby mode — — 110 — — 220 — 15 25 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current During RTC IDD-RTC dissipation operation Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 133 MHz, Bck = 67 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA μA Ick = 133 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST VIH VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Other input pins RESET, NMI, TRST VIL Other input pins Output voltage All output pins Page 914 of 1076 V V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 915 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.12 DC Characteristics (HD6417750SVBT133 (V)) Ta = –30 to +70°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.4 1.5 1.7 IDD — 210 520 Sleep mode — 50 60 Standby mode — — 100 — — 200 — 80 160 Sleep mode — 35 40 Standby mode — — 110 — — 220 — 15 45 Current dissipation Current dissipation Normal operation Normal operation IDDQ RTC current During RTC IDD-RTC dissipation operation Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 133 MHz, Bck = 66 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA μA Ick = 133 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST VIH VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 VOH 2.4 — — VOL — — 0.55 Other input pins RESET, NMI, TRST VIL Other input pins Output voltage All output pins Page 916 of 1076 V V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics Symbol Min Typ Max Unit Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 917 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.13 DC Characteristics (HD6417750VF128 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, deep sleep mode, standby mode VDD 1.4 1.5 1.7 IDD — — 520 Sleep mode — — 60 Standby mode — — 100 — — 200 — — 160 Sleep mode — — 40 Standby mode — — 110 — — 220 VDDQ × 0.9 — VDDQ + 0.3 2.0 — VDDQ + 0.3 –0.3 — VDDQ × 0.1 –0.3 — VDDQ × 0.2 Current dissipation Current dissipation Normal operation Normal operation Input voltage RESET, NMI, TRST IDDQ VIH Other input pins RESET, NMI, TRST VIL Other input pins Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 128 MHz, Bck = 64 MHz μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) V Output voltage All output pins VOH 2.4 — — VOL — — 0.55 Pull-up resistance All pull-up resistance Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Page 918 of 1076 Ick = 128 MHz, Bck = 64 MHz V IOH = –2 mA IOL = 2 mA R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Table 22.14 Permissible Output Currents Ta = –20 to +75°C Item Symbol Min Typ Max Unit Permissible output low current (per pin) IOL — — 2 mA Permissible output low current (total) ΣIOL — — 120 Permissible output high current (per pin) –IOH — — 2 Permissible output high current (total) Σ(–IOH) — — 40 Note: To protect chip reliability, do not exceed the output current values in table 22.14. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 919 of 1076 Section 22 Electrical Characteristics 22.3 SH7750, SH7750S, SH7750R Group AC Characteristics In principle, this LSI input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) Item Operating frequency Symbol Min Typ Max Unit f 1 — 240 MHz External bus 1 — 120 Peripheral modules 1 — 60 Symbol Min Typ Max Unit f 1 — 240 MHz External bus 1 — 84 Peripheral modules 1 — 60 CPU, FPU, cache, TLB Table 22.16 Clock Timing (HD6417750RF240 (V)) Item Operating frequency CPU, FPU, cache, TLB Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V*, HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*) Item Operating frequency Note: * Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 100 Peripheral modules 1 — 50 CPU, FPU, cache, TLB This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. Table 22.18 Clock Timing (HD6417750RF200 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 84 Peripheral modules 1 — 50 CPU, FPU, cache, TLB Page 920 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Table 22.19 Clock Timing (HD6417750SF200 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 67 Peripheral modules 1 — 50 CPU, FPU, cache, TLB Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 167 MHz External bus 1 — 84 Peripheral modules 1 — 42 CPU, FPU, cache, TLB Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) Item Operating frequency Table 22.22 Symbol Min Typ Max Unit f 1 — 134 MHz External bus 1 — 67 Peripheral modules 1 — 34 CPU, FPU, cache, TLB Clock Timing (HD6417750VF128 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 128 MHz External bus 1 — 64 Peripheral modules 1 — 32 CPU, FPU, cache, TLB R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 921 of 1076 Section 22 Electrical Characteristics 22.3.1 SH7750, SH7750S, SH7750R Group Clock and Control Signal Timing Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V), HD6417750RBA240HV) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*2, CL = 30 pF Item Symbol Min Max Unit PLL1 6-times/PLL2 operation fEX 16 34 MHz PLL1 12-times/PLL2 operation fEX 14 20 PLL1/PLL2 not operating fEX 1 34 EXTAL clock input cycle time tEXcyc 30 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL1/PLL2 operating fOP 25 120 MHz PLL1/PLL2 not operating fOP 1 34 MHz CKIO clock output cycle time tcyc 8.3 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) EXTAL clock input frequency Figure CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 Page 922 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 3 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 3 — ms 22.7 22.8 Standby return oscillation settling time 3 tOSC4 3 — ms 1 Standby return oscillation settling time 1* tOSC2 2 — ms 1 2 — ms Standby return oscillation settling time 2* tOSC3 1 Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. 1. When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 923 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit PLL1 6-times/PLL2 operation fEX 16 34 MHz PLL1 12-times/PLL2 operation fEX 14 20 PLL1/PLL2 not operating Figure fEX 1 34 EXTAL clock input cycle time tEXcyc 30 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL1/PLL2 operating fOP 25 84 MHz PLL1/PLL2 not operating fOP 1 34 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 22.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2(1) CKIO clock output rise time tCKOr — 3 ns 22.2(1) CKIO clock output fall time tCKOf — 3 ns 22.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2(2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 3 — ms 22.4, 22.6 Page 924 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure Standby return oscillation settling time 2 tOSC3 3 — ms 22.7 Standby return oscillation settling time 3 tOSC4 3 — ms 22.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 925 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V), HD6417750RBA240HV*2) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*3, CL = 30 pF Item Symbol Min Max Unit PLL1 6-times/PLL2 operation fEX 16 34 MHz PLL1 12-times/PLL2 operation fEX 14 17 PLL1/PLL2 not operating fEX 1 34 EXTAL clock input cycle time tEXcyc 30 1000 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL1/PLL2 operating fOP 25 100 MHz PLL1/PLL2 not operating fOP 1 100 MHz CKIO clock output cycle time tcyc 10 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 5 — ms 22.4, 22.6 EXTAL clock input frequency Page 926 of 1076 ns Figure 22.1 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 22.8 Standby return oscillation settling time 3 tOSC4 5 — ms 1 Standby return oscillation settling time 1* tOSC2 2 — ms 1 2 — ms 1 Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Standby return oscillation settling time 2* tOSC3 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. 1. When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 927 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit PLL1 6-times/PLL2 operation fEX 16 34 MHz PLL1 12-times/PLL2 operation fEX 14 17 PLL1/PLL2 not operating Figure fEX 1 34 EXTAL clock input cycle time tEXcyc 30 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL1/PLL2 operating fOP 25 84 MHz PLL1/PLL2 not operating fOP 1 34 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 5 — ms 22.4, 22.6 Page 928 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 tOSC4 5 — ms 22.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 929 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750SBA200V) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating PLL2 not operating Symbol Min Max Unit fEX 16 67 MHz 1/2 divider not fEX operating 8 34 1/2 divider operating fEX 2 67 1/2 divider not fEX operating 1 34 1/2 divider operating Figure EXTAL clock input cycle time tEXcyc 15 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL2 operating fOP 25 100 MHz PLL2 not operating fOP 1 100 MHz CKIO clock output cycle time tcyc 10 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 Page 930 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 10 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 22.8 tOSC4 5 — ms Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 931 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating PLL2 not operating Symbol Min Max Unit fEX 16 67 MHz 1/2 divider not fEX operating 8 34 1/2 divider operating fEX 2 67 1/2 divider not fEX operating 1 34 1/2 divider operating Figure EXTAL clock input cycle time tEXcyc 15 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL2 operating fOP 25 67 MHz PLL2 not operating fOP 1 67 MHz CKIO clock output cycle time tcyc 10 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 Page 932 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 10 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 tOSC4 5 — ms 22.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 933 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V), HD6417750SF167 (V)) HD6417750SF167 (V), HD6417750F167 (V): Item EXTAL clock input frequency PLL2 operating PLL2 not operating VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Symbol Min Max Unit fEX 16 56 MHz 1/2 divider not fEX operating 8 28 1/2 divider operating fEX 2 56 1/2 divider not fEX operating 1 28 1/2 divider operating Figure EXTAL clock input cycle time tEXcyc 18 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL2 operating fOP 25 84 MHz PLL2 not operating fOP 1 84 MHz CKIO clock output cycle time tcyc 12 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 Page 934 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 10 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 22.8 tOSC4 5 — ms Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 935 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) HD6417750SVBT133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –30 to +70°C, CL = 30 pF HD6417750SVF133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating PLL2 not operating Symbol Min Max Unit fEX 16 45 MHz 1/2 divider not fEX operating 8 23 1/2 divider operating fEX 2 45 1/2 divider not fEX operating 1 23 1/2 divider operating Figure EXTAL clock input cycle time tEXcyc 22 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL2 operating fOP 25 67 MHz PLL2 not operating fOP 1 67 MHz CKIO clock output cycle time tcyc 14 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 Page 936 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 10 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 22.8 tOSC4 5 — ms Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 937 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating PLL2 not operating Symbol Min Max Unit fEX 16 43 MHz 1/2 divider not fEX operating 8 22 1/2 divider operating fEX 2 43 1/2 divider not fEX operating 1 22 1/2 divider operating Figure EXTAL clock input cycle time tEXcyc 23 1000 ns 22.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 22.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 22.1 EXTAL clock input rise time tEXr — 4 ns 22.1 EXTAL clock input fall time tEXf — 4 ns 22.1 CKIO clock output PLL2 operating fOP 25 64 MHz PLL2 not operating fOP 1 64 MHz CKIO clock output cycle time tcyc 15 1000 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 22.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 22.2 (1) CKIO clock output rise time tCKOr — 3 ns 22.2 (1) CKIO clock output fall time tCKOf — 3 ns 22.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 22.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 22.2 (2) Power-on oscillation settling time tOSC1 10 — ms 22.3, 22.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 22.3, 22.5 SCK2 reset setup time tSCK2RS 20 — ns 22.11 SCK2 reset hold time tSCK2RH 20 — ns 22.3, 22.5, 22.11 MD reset setup time tMDRS 3 — tcyc 22.12 MD reset hold time tMDRH 20 — ns 22.3, 22.5, 22.12 RESET assert time tRESW 20 — tcyc 22.3, 22.4, 22.5, 22.6, 22.11 Page 938 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Item Symbol Min Max Unit Figure PLL synchronization settling time tPLL 200 — μs 22.9, 22.10 Standby return oscillation settling time 1 tOSC2 10 — ms 22.4, 22.6 Standby return oscillation settling time 2 tOSC3 5 — ms 22.7 Standby return oscillation settling time 3 tOSC4 5 — ms 22.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 22.10 TRST reset hold time tTRSTRH 0 — ns 22.3, 22.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 939 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group tEXcyc tEXL tEXH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tEXf tEXr Note: When the clock is input from the EXTAL pin Figure 22.1 EXTAL Clock Input Timing tcyc tCKOL1 tCKOH1 VOH VOH VOH 1/2VDDQ 1/2VDDQ VOL VOL tCKOf tCKOr Figure 22.2 (1) CKIO Clock Output Timing tCKOH2 1.5 V tCKOL2 1.5 V 1.5 V Figure 22.2 (2) CKIO Clock Output Timing Page 940 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Stable oscillation CKIO, internal clock VDD min VDD tRESW tOSC1 RESET tSCK2RH SCK2 tOSCMD tMDRH MD8, MD7, MD2–MD0 tTRSTRH TRST Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 not operating Figure 22.3 Power-On Oscillation Settling Time Standby Stable oscillation CKIO, internal clock tRESW tOSC2 RESET Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 not operating Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 941 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Stable oscillation Internal clock VDD min VDD tRESW tOSC1 RESET tSCK2RH SCK2 tOSCMD tMDRH MD8, MD7, MD2–MD0 tTRSTRH TRST CKIO Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 operating Figure 22.5 Power-On Oscillation Settling Time Stable oscillation Standby Internal clock tRESW tOSC2 RESET CKIO Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 operating Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET) Page 942 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Standby Stable oscillation CKIO, internal clock tOSC3 NMI Note: Oscillation settling time when on-chip oscillator is used Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI) Stable oscillation Standby CKIO, internal clock tOSC4 IRL3 to IRL0 Note: Oscillation settling time when on-chip oscillator is used Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 943 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input tPLL × 2 PLL synchronization PLL synchronization PLL output, CKIO output Internal clock STATUS1, STATUS0 Normal Normal Standby Note: When external clock from EXTAL is input Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt IRL3–IRL0 interrupt request Stable input clock Stable input clock EXTAL input PLL synchronization tIRLSTB tPLL × 2 PLL synchronization PLL output, CKIO output Internal clock STATUS1, STATUS0 Normal Standby Normal Note: When external clock from EXTAL is input Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt Page 944 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Bus idle CKIO tRESW RESET tSCK2RS tSCK2RH SCK2 Figure 22.11 Manual Reset Input Timing RESET tMDRS tMDRH MD6–MD3 Figure 22.12 Mode Input Timing R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 945 of 1076 Section 22 Electrical Characteristics 22.3.2 SH7750, SH7750S, SH7750R Group Control Signal Timing Table 22.32 Control Signal Timing HD6417750R BP240 (V) HD6417750R BP200 (V) HD6417750R BG240 (V) HD6417750R BG200 (V) HD6417750R BA240HV HD6417750R 5 BA240HV* 1 HD6417750R F240 (V) 1 1 * * HD6417750R F200 (V) 1 * * Item Symbol Min Max Min Max Min Max Min Max Unit Figure BREQ setup time tBREQS 2 — 2.5 — 3.5 — 3.5 — ns 22.13 BREQ hold time tBREQH 1.5 — 1.5 — 1.5 — 1.5 — ns 22.13 BACK delay time tBACKD — 5.3 — 6 — 6 — 6 ns 22.13 Bus tri-state delay time tBOFF1 — 12 — 12 — 12 — 12 ns 22.13 Bus tri-state delay time to standby mode tBOFF2 — 2 — 2 — 2 — 2 tcyc 22.14 (2) Bus buffer on time tBON1 — 12 — 12 — 12 — 12 ns 22.13 Bus buffer on time from standby tBON2 — 2 — 2 — 2 — 2 tcyc 22.14 (2) STATUS0/1 delay time tSTD1 — 6 — 6 — 6 — 6 ns 22.14 (1) tSTD2 — 2 — 2 — 2 — 2 tcyc 22.14 (1), (2) tSTD3 — 2 — 2 — 2 — 2 tcyc 22.14 (2) Page 946 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Table 22.33 Control Signal Timing HD6417750V F128 (V) HD6417750 SVF133 (V) HD6417750S VBT133 (V) HD6417750F 167 (V) HD6417750S F167 (V) HD6417750S F200 (V) *2 *2 *3 HD6417750B P200M (V) HD6417750S BP200 (V) HD6417750S BA200V *4 Item Symbol Min Max Min Max Min Max Min Max Unit Figure BREQ setup time tBREQS 3.5 — 3.5 — 3.5 — 3 — ns 22.13 BREQ hold time tBREQH 1.5 — 1.5 — 1.5 — 1.5 — ns 22.13 BACK delay time tBACKD — 10 — 10 — 8 — 6 ns 22.13 Bus tri-state delay time tBOFF1 — 15 — 15 — 12 — 10 ns 22.13 Bus tri-state delay time to standby mode tBOFF2 — 2 — 2 — 2 — 2 tcyc 22.14 (2) Bus buffer on time tBON1 — 12 — 12 — 12 — 12 ns 22.13 Bus buffer on time from standby tBON2 — 2 — 2 — 2 — 2 tcyc 22.14 (2) STATUS0/1 delay time tSTD1 — 6 — 6 — 6 — 6 ns 22.14 (1) tSTD2 — 2 — 2 — 2 — 2 tcyc 22.14 (1), (2) tSTD3 — 2 — 2 — 2 — 2 tcyc 22.14 (2) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*6, CL = 30 pF, PLL2 on VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 6. Ta = –40 to 85°C for the HD6417750RBA240HV. Notes: 1. 2. 3. 4. 5. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 947 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group CKIO tBREQH tBREQS tBREQH tBREQS tBACKD tBACKD BREQ BACK A[25-0], CSn, BS, RD/WR, CE2A, CE2B, RD/WR2, RAS, RAS2, WEn, RD RD2 tBOFF1 tBON1 Figure 22.13 Control Signal Timing Normal operation Reset or sleep mode Normal operation CKIO STATUS1, STATUS0 normal reset or sleep tSTD2 normal tSTD1 Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode Page 948 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Normal operation Software standby mode Normal operation CKIO STATUS1, STATUS0 normal software standby tSTD2 CSn, RD, RD/WR, WEn, BS, RAS, CE2A, CE2B, CASn normal tSTD3 tBOFF2 tBON2 A25−A0, D31−D0 * DACKn, DRAKn, SCK, TXD, TXD2, CTS2, RTS2 Note: * These pins can be put into the state od high-impedance with STBCR. Figure 22.14 (2) Pin Drive Timing for Software Standby Mode R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 949 of 1076 Section 22 Electrical Characteristics 22.3.3 SH7750, SH7750S, SH7750R Group Bus Timing Table 22.34 Bus Timing (1) HD6417750R BP240 (V) HD6417750R BP200 (V) HD6417750R BG240 (V) HD6417750R BG200 (V) HD6417750R BA240HV HD6417750R 2 BA240HV* 1 HD6417750R F240 (V) 1 1 * * HD6417750R F200 (V) 1 * * Item Symbol Min Max Min Max Min Max Min Max Unit Notes Address delay time tAD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns BS delay time tBSD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns CS delay time tCSD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns RW delay time tRWD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns RD delay time tRSD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns Read data setup time tRDS 2 — 2.5 — 3.5 — 3.5 — ns Read data hold time tRDH 1.5 — 1.5 — 1.5 — 1.5 — ns WE delay time (falling edge) tWEDF — 5.3 — 6 — 6 — 6 ns WE delay time tWED1 1.5 5.3 1.5 6 1.5 6 1.5 6 ns Write data delay time tWDD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns RDY setup time tRDYS 2 — 2.5 — 3.5 — 3.5 — ns RDY hold time tRDYH 1.5 — 1.5 — 1.5 — 1.5 — ns RAS delay time tRASD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns CAS delay time 1 tCASD1 1.5 5.3 1.5 6 1.5 6 1.5 6 ns CAS delay time 2 tCASD2 1.5 5.3 1.5 6 1.5 6 1.5 6 ns SDRAM CKE delay time tCKED 1.5 5.3 1.5 6 1.5 6 1.5 6 ns SDRAM DQM delay time tDQMD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns SDRAM Relative to CKIO falling edge DRAM FRAME delay time tFMD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns MPX IOIS16 setup time tIO16S 2 — 2.5 — 3.5 — 3.5 — ns PCMCIA IOIS16 hold time tIO16H 1.5 — 1.5 — 1.5 — 1.5 — ns PCMCIA 1.5 5.3 1.5 6 1.5 6 1.5 6 ns PCMCIA ICIOWR delay time tICWSDF (falling edge) Page 950 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics HD6417750R BP240 (V) HD6417750R BP200 (V) HD6417750R BG240 (V) HD6417750R BG200 (V) HD6417750R BA240HV HD6417750R 2 BA240HV* 1 1 Max Min Max HD6417750R F200 (V) 1 * * Item HD6417750R F240 (V) 1 * Min Max * Symbol Min Min Max Unit Notes ICIORD delay time tICRSD 1.5 5.3 1.5 6 1.5 6 1.5 DACK delay time tDACD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns PCMCIA 6 ns DACK delay time (falling edge) tDACDF 1.5 5.3 1.5 6 1.5 6 1.5 6 ns DTR setup time tDTRS 2.0 — 2.5 — 3.5 — 3.5 — ns DTR hold time tDTRH 1.5 — 1.5 — 1.5 — 1.5 — ns DBREQ setup time tDBQS 2.0 — 2.5 — 3.5 — 3.5 — ns DBREQ hold time tDBQH 1.5 — 1.5 — 1.5 — 1.5 — ns TR setup time tTRS 2.0 — 2.5 — 3.5 — 3.5 — ns TR hold time tTRH 1.5 — 1.5 — 1.5 — 1.5 — ns BAVL delay time tBAVD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns TDACK delay time tTDAD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns ID1, ID0 delay time tIDD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns Relative to CKIO falling edge 3 Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C* , CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417750RBA240HV. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 951 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.35 Bus Timing (2) HD6417750 SVF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750 SVBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *1 *2 *3 Item Symbol Min Max Min Max Min Max Unit Address delay time tAD 1.5 10 1.5 8 1.5 6 ns BS delay time tBSD 1.5 10 1.5 8 1.5 6 ns CS delay time tCSD 1.5 10 1.5 8 1.5 6 ns RW delay time tRWD 1.5 10 1.5 8 1.5 6 ns RD delay time tRSD 1.5 10 1.5 8 1.5 6 ns Read data setup time tRDS 3.5 — 3.5 — 3 — ns Read data hold time tRDH 1.5 — 1.5 — 1.5 — ns WE delay time (falling edge) tWEDF — 10 — 8 — 6 ns WE delay time tWED1 1.5 10 1.5 8 1.5 6 ns Write data delay time tWDD 1.5 10 1.5 8 1.5 6 ns RDY setup time tRDYS 3.5 — 3.5 — 3 — ns RDY hold time tRDYH 1.5 — 1.5 — 1.5 — ns RAS delay time tRASD 1.5 10 1.5 8 1.5 6 ns CAS delay time 1 tCASD1 1.5 10 1.5 8 1.5 6 ns DRAM CAS delay time 2 tCASD2 1.5 10 1.5 8 1.5 6 ns SDRAM CKE delay time tCKED 1.5 10 1.5 8 1.5 6 ns SDRAM DQM delay time tDQMD 1.5 10 1.5 8 1.5 6 ns SDRAM FRAME delay time tFMD 1.5 10 1.5 8 1.5 6 ns MPX IOIS16 setup time tIO16S 3.5 — 3.5 — 3 — ns PCMCIA IOIS16 hold time tIO16H 1.5 — 1.5 — 1.5 — ns PCMCIA ICIOWR delay time (falling edge) tICWSDF 1.5 10 1.5 8 1.5 6 ns PCMCIA ICIORD delay time tICRSD 1.5 10 1.5 8 1.5 6 ns PCMCIA DACK delay time tDACD 1.5 10 1.5 8 1.5 6 ns DACK delay time (falling edge) tDACDF 1.5 10 1.5 8 1.5 6 ns Page 952 of 1076 Notes Relative to CKIO falling edge Relative to CKIO falling edge R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics HD6417750 SVF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750 SVBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *1 *2 *3 Item Symbol Min Max Min Max Min Max Unit DTR setup time tDTRS 3.5 — 3.5 — 3 — ns DTR hold time tDTRH 1.5 — 1.5 — 1.5 — ns DBREQ setup time tDBQS 3.5 — 3.5 — 3 — ns DBREQ hold time tDBQH 1.5 — 1.5 — 1.5 — ns TR setup time tTRS 3.5 — 3.5 — 3 — ns TR hold time tTRH 1.5 — 1.5 — 1.5 — ns BAVL delay time tBAVD 1.5 10 1.5 8 1.5 6 ns TDACK delay time tTDAD 1.5 10 1.5 8 1.5 6 ns ID1, ID0 delay time tIDD 1.5 10 1.5 8 1.5 6 ns Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 953 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.36 Bus Timing (3) HD6417750 VF128 (V) HD6417750 F167 (V) HD6417750 BP200M (V) *1 *2 *3 Item Symbol Min Max Min Max Min Max Unit Notes Address delay time tAD 1.3 10 1.3 8 1.2 6 ns BS delay time tBSD 1.3 10 1.3 8 1.2 6 ns CS delay time tCSD 1.3 10 1.3 8 1.2 6 ns RW delay time tRWD 1.3 10 1.3 8 1.2 6 ns RD delay time tRSD 1.3 10 1.3 8 1.2 6 ns Read data setup time tRDS 3.5 — 3.5 — 3 — ns Read data hold time tRDH 1.5 — 1.5 — 1.5 — ns WE delay time (falling edge) tWEDF — 10 — 8 — 6 ns WE delay time tWED1 1.3 10 1.3 8 1.2 6 ns Write data delay time tWDD 1.3 10 1.3 8 1.2 6 ns RDY setup time tRDYS 3.5 — 3.5 — 3 — ns RDY hold time tRDYH 1.5 — 1.5 — 1.5 — ns RAS delay time tRASD 1.3 10 1.3 8 1.2 6 ns CAS delay time 1 tCASD1 1.3 10 1.3 8 1.2 6 ns CAS delay time 2 tCASD2 1.3 10 1.3 8 1.2 6 ns SDRAM CKE delay time tCKED 0.5 10 0.5 8 0.5 6 ns SDRAM DQM delay time tDQMD 1.3 10 1.3 8 1.2 6 ns SDRAM Relative to CKIO falling edge DRAM FRAME delay time tFMD 1.3 10 1.3 8 1.2 6 ns MPX IOIS16 setup time tIO16S 3.5 — 3.5 — 3 — ns PCMCIA IOIS16 hold time tIO16H 1.5 — 1.5 — 1.5 — ns PCMCIA ICIOWR delay time (falling edge) tICWSDF 1.3 10 1.3 8 1.2 6 ns PCMCIA ICIORD delay time tICRSD 1.3 10 1.3 8 1.2 6 ns PCMCIA DACK delay time tDACD 1.3 10 1.3 8 1.2 6 ns DACK delay time (falling edge) tDACDF 1.3 10 1.3 8 1.2 6 ns Page 954 of 1076 Relative to CKIO falling edge R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Item Section 22 Electrical Characteristics HD6417750 VF128 (V) HD6417750 F167 (V) HD6417750 BP200M (V) *1 *2 *3 Symbol Min Max Min Max Min Max Unit DTR setup time tDTRS 3.5 — 3.5 — 3 — ns DTR hold time tDTRH 1.5 — 1.5 — 1.5 — ns DBREQ setup time tDBQS 3.5 — 3.5 — 3 — ns DBREQ hold time tDBQH 1.5 — 1.5 — 1.5 — ns TR setup time tTRS 3.5 — 3.5 — 3 — ns TR hold time tTRH 1.5 — 1.5 — 1.5 — ns BAVL delay time tBAVD 1.3 10 1.3 8 1.2 6 ns TDACK delay time tTDAD 1.3 10 1.3 8 1.2 6 ns ID1, ID0 delay time tIDD 1.3 10 1.3 8 1.2 6 ns Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 955 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group T1 T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D63–D0 (read) tWED1 tWEDF tRDH tWEDF WEn tWDD tWDD tWDD D63–D0 (write) tBSD tBSD BS RDY tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACD tDACD tDACDF tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Page 956 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics T1 Tw T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D63–D0 tRDH (read) tWED1 tWEDF tWEDF WEn tWDD tWDD tWDD D63–D0 (write) tBSD tBSD BS tRDYS tRDYH RDY tDACD tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACDF tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 957 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group T1 Tw Twe T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D63–D0 (read) tWED1 tWEDF tRDH tWEDF WEn tWDD tWDD tWDD D63–D0 (write) tBSD tBSD BS tRDYS tRDYH RDY tDACD DACKn (SA: IO ← memory) tDACDF tRDYS tDACD tRDYH tDACD tDACDF DACKn (SA: IO → memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Page 958 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD RD tRDS D63–D0 (read) tWED1 tWEDF WEn tWDD tRSD * tRDH tWEDF tWDD tWDD D63–D0 (write) tBSD tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD DACKn (DA) tDACD tDACDF tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: * SH7750R only Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 959 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group TB2 T1 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD tAD A25–A5 tAD A4–A0 tCSD tCSD tRWD tRWD CSn RD/WR tRSD tRSD tRSD RD tRDS D63–D0 (read) tBSD tRDH tRDS tRDH tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.19 Burst ROM Bus Cycle (No Wait) Page 960 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tDACD tDACD Twb tRDH tAD TB1 tRDYH TB2 tRDS tRDYH Twe tRDYS tRSD tRDYS tBSD tRWD tCSD tAD Tw Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS D63–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO T1 TB2 TB1 Twb TB2 Twb tRDYS TB1 tRDH tRWD tAD tRDYH tDACD tRDS tRSD tCSD T2 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) Page 961 of 1076 Page 962 of 1076 tDACD tDACD tBSD tRWD tCSD tAD IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Legend: DACKn (DA) DACKn (SA: IO ← memory) RDY BS D63–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO TS1 tRDS tRSD TB2 tDACD tBSD T1 tDACD tAD TS1 tRDH TH1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 tRDS T2 tDACD tRDH TH1 tRSD tRWD tCSD tAD Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tBSD tRSD Tw tDACD tDACD TB2 tDACD tRDH tAD TB1 tRDYH tRDS tRDYH Twe tRDYS tDACD tRDYS tBSD tRSD tRWD tCSD tAD T1 IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Legend: DACKn (DA) DACKn (SA: IO ← memory) RDY BS D63–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO Twb Twbe TB2 TB1 Twb Twbe TB2 tBSD Twb tRDYS tBSD TB1 tRDYS T2 tRDS tRDH tRSD tRWD tCSD tAD tRDYH tDACD tRDYH Twbe SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) Page 963 of 1076 Page 964 of 1076 Row Address tDACD tWDD tCASD2 tRASD tRWD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D63–D0 (write) D63–D0 (read) DQMn CASS RAS RD/WR CSn Row Precharge-sel tCSD Row tAD Tr BANK CKIO tRASD Trw Tc2 tDQMD tCASD2 tCASD2 column H/L tAD Tc1 Tc3 d0 tBSD tRDH Td2 tDACD tDACD tBSD tRDS Tc4/Td1 tDQMD Td3 Td4 tRWD tCSD tAD Tpc Tpc Tpc tWDD Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tWDD tCASD2 tRASD tRWD tCSD Row Row Row tAD Tr Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D63–D0 (write) D63–D0 (read) DQMn CASS RAS RD/WR CSn Address Precharge-sel BANK CKIO tRASD Trw Tc2 tDQMD tCASD2 tCASD2 c0 H/L tAD Tc1 Tc3 d0 tDACD tBSD tRDS Tc4/Td1 tBSD d1 tRDH Td2 d2 tDQMD Td3 Td4 d3 tDACD tRWD tCSD tAD Tpc Tpc Tpc tWDD SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) Page 965 of 1076 Section 22 Electrical Characteristics Tr Trw SH7750, SH7750S, SH7750R Group Tc1 Tc2 Tc3 Tc4/Td1 Td3 Td2 Td4 CKIO tAD tAD BANK Row tAD tRWD Precharge-sel Row H/L tRWD Address CSn Row c0 tCSD tCSD tRWD tRWD RD/WR tRASD tRASD RAS tCASD2 tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tRDS D63–D0 (read) D63–D0 (write) tRDH d0 d1 d2 d3 tWDD tWDD tBSD tBSD BS CKE tDACD tDACD tDACD DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) Page 966 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Tpr Tpc Section 22 Electrical Characteristics Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td4 Td3 Td2 CKIO tAD tAD tAD BANK Row Precharge-sel Row H/L Address Row c0 tAD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD tRASD RAS tCASD2 tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tRDS D63–D0 (read) D63–D0 (write) tRDH d1 d0 d2 d3 tWDD tWDD tBSD tBSD BS CKE DACKn (SA: IO ← memory) tDACD tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 967 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Tc1 Tc2 Tc3 Tc4/Td1 Td4 Td3 Td2 CKIO tAD tAD BANK Row Precharge-sel Address H/L c0 tCSD tCSD tRWD tRWD tRASD tRASD CSn RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tRDS D63–D0 (read) D63–D0 (write) tRDH d1 d0 d2 d3 tWDD tWDD tBSD tBSD BS CKE tDACD tDACD tDACD DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst ((RASD = 1, CAS Latency = 3) Page 968 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Tr Trw Section 22 Electrical Characteristics Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc CKIO tAD BANK Row Precharge-sel Row Address Row tAD tAD H/L Column tCSD tCSD CSn tRWD tRWD tCASD2 tCASD2 RD/WR tRASD tRASD RAS tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD D63–D0 (write) tWDD c0 tBSD BS tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 969 of 1076 Section 22 Electrical Characteristics Tr Trw SH7750, SH7750S, SH7750R Group Tc1 Tc2 Tc3 Trwl Tc4 Trwl Tpc CKIO tAD tAD BANK Row Precharge-sel Row H/L Address Row c0 tAD tCSD tCSD CSn tRWD tRWD tCASD2 tCASD2 RD/WR tRASD tRASD RAS tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD D63–D0 (write) tWDD d0 tBSD BS d1 d2 d3 tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Page 970 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Tr Section 22 Electrical Characteristics Trw Tc1 Tc2 Tc3 Trwl Tc4 Trwl CKIO tAD tAD BANK Row Precharge-sel Row H/L Address Row c0 tAD tCSD tCSD CSn tRWD tRWD tCASD2 tCASD2 RD/WR tRASD tRASD RAS tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD D63–D0 (write) tWDD d0 tBSD BS d1 d2 d3 tBSD CKE tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 971 of 1076 Section 22 Electrical Characteristics Tpr Tpc SH7750, SH7750S, SH7750R Group Tr Trw Tc1 Tc2 Tc3 Trwl Tc4 Trwl CKIO tAD tAD tAD BANK Row Row Precharge-sel H/L Row H/L Row c0 tAD Address tCSD tCSD CSn tRWD tRWD tRASD tRASD tRWD tRWD RD/WR tRASD tRASD RAS tCASD2 tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD D63–D0 (write) tWDD d0 tBSD BS d1 d2 d3 tBSD CKE tDACD tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Page 972 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Tnop Section 22 Electrical Characteristics (Tnop) Tc1 Tc2 Tc3 Trwl Tc4 Trwl CKIO tAD BANK tAD Row Precharge-sel H/L Address c0 tCSD tCSD CSn tRWD tRWD RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD tWDD D63–D0 (write) d1 d0 tBSD d2 d3 tBSD BS CKE tDACD SA-DMA tDACD DACKn (SA: IO → memory) Normal write Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 973 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Tpr Tpc CKIO tAD tAD BANK Row Precharge-sel H/L Address tCSD tCSD CSn tRWD tRWD tRASD tRASD RD/WR RAS tCASD2 tCASD2 tDQMD tDQMD tWDD tWDD CASS DQMn D63–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (RASD = 1, TPC[2:0] = 001) Page 974 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group TRr1 TRr2 Section 22 Electrical Characteristics TRr3 TRr4 TRrw TRr5 Trc Trc Trc CKIO tAD tAD BANK Precharge-sel Address tCSD tCSD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD tCASD2 tCASD2 tCASD2 tRASD RAS tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D63–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 975 of 1076 Section 22 Electrical Characteristics TRs1 TRs2 SH7750, SH7750S, SH7750R Group TRs3 TRs4 TRs5 Trc Trc Trc CKIO tAD tAD BANK Precharge-sel Address tCSD tCSD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD tRASD RAS tCASD2 tCASD2 tCASD2 tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D63–D0 (write) tBSD BS tCKED tCKED CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001) Page 976 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group TRp1 TRp2 Section 22 Electrical Characteristics TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD BANK Precharge-sel Address tCSD tCSD tCSD CSn tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D63–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 977 of 1076 Section 22 Electrical Characteristics TRp1 TRp2 SH7750, SH7750S, SH7750R Group TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD BANK Precharge-sel Address tCSD tCSD tCSD tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 CSn RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D63–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET) Page 978 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tDACD tDACD tWDD tRASD Tr2 tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tr1 tBSD (1) tCASD1 Tc2 tBSD tRDS column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Tr1 tDACD tDACD tWDD tRASD Tr2 Trw tBSD tBSD Tc2 tRDS tCASD1 Tcw (2) column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Tpc SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 Page 979 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group T1r Tr2 Tc1 Tc2 Tce Tpc CKIO tAD tAD Row A25–A0 tAD Column tCSD tCSD tRWD tRWD CSn RD/WR RAS CASn tRASD tRASD tCASD1 tRASD tCASD1 tCASD1 tRDS D63–D0 (read) tRDH tWDD D63–D0 (write) tBSD tBSD BS DACKn (SA: IO ← memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) Page 980 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tWDD tRWD tRASD tRWD tCSD Row tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO T1r tDACD tRASD Tr2 tBSD tAD Tc1 tBSD tCASD1 c0 Tc2 tRDS tDACD tRDH Tc2 c1 d0 tCASD1 tAD Tc1 Tc1 d1 c2 tBSD Tc2 Tc1 d2 tBSD tCASD1 c3 Tc2 tRDS Tce d3 tRDH tCASD1 tRASD tRWD tCSD tAD Tpc SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) Page 981 of 1076 Page 982 of 1076 tRASD Row Tr2 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO tBSD Trw tAD Tc1 tBSD tCASD1 c0 Tcw Tc2 tRDS tCASD1 Tc1 tRDH tDACD d0 tCASD1 c1 Tcw Tc2 Tc1 d1 c2 Tcw Tc2 Tc1 d2 Tc2 c3 tCASD1 Tcw tRDS Tce d3 tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 c0 Tcw Tc2 Tc1 tCASD1 Tcnw c1 Tc2 tRDH Tcw Tcnw Tc1 c2 Tcw Tc2 Tc1 tCASD1 Tcnw d2 Tcw c3 Tc2 Tcnw tRDS Tce tAD Tpc tRASD tDACD t DACD tWDD tCASD1 tRASD tBSD tCASD1 tRDS tDACD d0 d1 d3 tRDH tCASD1 tRASD tRWD tAD Tc1 tRWD tBSD Trw tCSD Row Tr2 tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) Page 983 of 1076 Page 984 of 1076 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tpc tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Tr1 tDACD tBSD tRASD Row Tr2 tCASD1 tAD Tc1 tBSD c0 Tc2 tRDS Tc2 tRDH tDACD c1 d0 tCASD1 tAD Tc1 Tc1 d1 c2 Tc2 tBSD Tc1 d2 tBSD tCASD1 c3 Tc2 tRDS Tce d3 tRDH tCASD1 tRWD tCSD tAD Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tBSD tWDD tCASD1 tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tr1 tBSD tCASD1 c0 Tr2 tRDS tCASD1 tAD Tc1 tRDH tDACD d0 c1 Tc2 Tc1 d1 c2 Tc2 tBSD Tc1 d2 c3 tBSD tCASD1 Tc2 tRDS tRASD Tce d3 RAS-down mode ended tRDH tCASD1 tRWD tCSD tAD SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) Page 985 of 1076 Page 986 of 1076 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tr1 tDACD tDACD tWDD tRASD Row Tr2 tBSD d0 tAD Tc1 tCASD1 tDACD tBSD tRDS c0 Tc2 d0 tDACD tWDD tRDH tCASD1 Tc1 d1 c1 Tc2 d1 Tc1 d2 c2 Tc2 d2 Tc1 d3 tRDS tCASD1 c3 Tc2 d3 tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO tDACD tDACD tWDD tRASD Row Tr2 Trw tBSD tAD Tc1 tBSD d0 Tc2 tWDD tRDH tCASD1 Tc1 tDACD d0 tDACD tRDS tCASD1 c0 Tcw d1 c1 Tcw Tc2 Tc1 d1 d2 c2 Tcw Tc2 Tc1 d2 d3 Tc2 tRDS tCASD1 c3 Tcw tRDH tWDD d3 tCASD1 tRASD tRWD tCSD tAD Tpc SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) Page 987 of 1076 Page 988 of 1076 c0 Tcw Tc2 Tc1 tCASD1 Tcnw c1 Tcw Tc2 d1 Tcnw d2 Tc1 c2 Tcw Tc2 d2 Tcnw d3 Tc1 c3 Tcw Tc2 tAD Tcnw tDACD tDACD tWDD tWDD tRASD tDACD tDACD tCASD1 tRASD tBSD tBSD d0 tWDD tRDH tDACD d0 tDACD tRDS tCASD1 d1 tRDS tCASD1 Tpc tRDH tWDD d3 tCASD1 tRASD tRWD tAD Tc1 tRWD Trw tCSD Row Tr2 tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tpc tRWD tCSD tAD Tr1 tDACD tDACD tAD Tc1 tBSD d0 tCASD1 tWDD tRASD Row Tr2 tDACD tBSD tRDS c0 Tc2 d0 c1 tDACD Tc2 d1 tWDD tRDH tCASD1 Tc1 d1 Tc1 d2 c2 Tc2 d2 tCASD1 Tc1 d3 tRDS c3 Tc2 tRDH tWDD d3 tCASD1 tRWD tCSD tAD SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) Page 989 of 1076 Page 990 of 1076 tDACD tDACD tWDD tRDS tBSD d0 tDACD tDACD tDACD tBSD Tc2 Tc1 d0 c1 tDACD Tc2 d1 tWDD tRDH tCASD1 tCASD1 c0 tWDD tRWD tRWD tCASD1 tCSD Tc1 tCSD tAD Tnop Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D63–D0 (write) D63–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO d1 Tc1 d2 c2 Tc1 c3 Tc2 d2 tRASD tRWD tCSD tAD d3 tRDS tRDH tWDD d3 tCASD1 tCASD1 RAS down mode ended Tc2 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group TRr1 TRr2 Section 22 Electrical Characteristics TRr3 TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 991 of 1076 Section 22 Electrical Characteristics TRr1 TRr2 SH7750, SH7750S, SH7750R Group TRr3 TRr4 TRr4w TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) Page 992 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group TRr1 TRr2 TRr3 Section 22 Electrical Characteristics TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 993 of 1076 Page 994 of 1076 tDACD tBSD Note: tRDS *: SH7750S and SH7750R (1) tBSD tWDD tDACD tWDD tRDH tRSD tRWD tCSD tAD tWEDF tRSD Tpcm2 tWEDF tWDD tWED1 tRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RDY BS D15–D0 (write) WE1 D15–D0 (read) RD RD/WR CExx REG (WE7) A25–A0 CKIO Tpcm1 TED tDACD tBSD tWDD tWED1 tRSD tRWD tCSD tAD Tpcm0 tBSD tWDD Tpcm1 tRDYS tWEDF tRSD Tpcm1w (2) tRDYS tWDD tRSD tRWD tCSD tAD tDACD tRDH TEH tWEDF * Tpcm2w tRDYH tRDS Tpcm2 tRDYH Tpcm1w Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 Tpci2 tDACD tIO16S tBSD (1) tWDD tDACD tIO16H tBSD tWDD tICWSDF tICWSDF tRDS tRDH tRWD tCSD tAD tICRSD tICRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) IOIS16 RDY BS D15–D0 (write) ICIOWR (WE3) D15–D0 (read) ICIORD (WE2) RD/WR CExx REG (WE7) A25–A0 CKIO Tpci1 tDACD tBSD tWDD tICWSDF tICRSD tRWD tCSD tAD Tpci0 tBSD tWDD Tpci1 tRDYS tICWSDF tRDYH Tpci1w (2) tIO16S tRDYS tICRSD Tpci1w tICWSDF tIO16H tWDD tRWD tCSD tAD tDACD tRDH tICRSD Tpci2w tRDYH tRDS Tpci2 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait Page 995 of 1076 Page 996 of 1076 Tpci1 tBSD tWDD tBSD tWDD tICWSDF tICWSDF tICRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high IOIS16 RDY BS D15–D0 (write) ICIOWR (WE3) D15–D0 (read) ICIORD (WE2) RD/WR CExx REG (WE7) A0 A25–A1 CKIO Tpci0 tICWSDF tRDS Tpci2 tIO16S tIO16H tRDYS tRDYH tICRSD Tpci1w tRDH tICRSD Tpci2w tWDD tCSD tAD Tpci0 tWDD tICWSDF Tpci1 tICWSDF Tpci2 tRDYS tRDYH Tpci1w Tpci2w tWDD tRWD tCSD tAD Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 (1) tBSD tWED1 tDACD tRDYH tRDH tCSD tRWD D0 tRDS Tmd1 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD tRDYS tWED1 tRWD tCSD A tFMD Tmd1w Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 tWDD RD/FRAME CKIO Tm1 tWDD tDACD tBSD tWDD tFMD Tmd1w (2) tRDYS tRDYH Tmd1w tDACD tWED1 tRWD tRDYH tRDH tCSD D0 tRDS Tmd1 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tBSD tRDYS tWED1 tRWD tCSD A tFMD Tm0 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) Page 997 of 1076 Page 998 of 1076 tBSD (1) tWED1 tRWD tCSD tWDD tDACD tRDYH D0 tWDD tFMD 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 RD/FRAME CKIO Tm1 (2) tBSD D0 tWED1 tRWD tCSD tWDD tDACD tRDYH Tmd1 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 (3) tRDYS tBSD D0 tRDYH Tmd1w tCSD tWDD tDACD tWED1 tRWD tRDYH Tmd1 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tBSD Tmd1 (1) D1 tRDH Tmd3 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tBSD D0 Tmd2 tRDYH tWDD tRDS tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1w Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 RD/FRAME CKIO Tm1 D2 tWED1 tRWD tCSD tDACD D3 tFMD Tmd4 tDACD tBSD Tmd1 D0 tBSD Tmd2 D1 Tmd3 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (2) tRDYH tRDH Tmd2w tRDYH tRDYS tWDD tRDS Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 D2 tFMD Tmd4w tWED1 tRWD tCSD tDACD D3 Tmd4 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait) Page 999 of 1076 Page 1000 of 1076 tDACD tBSD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 (1) D2 Tmd3 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tBSD D1 Tmd2 tRDYH D0 tWDD Tmd1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 RD/FRAME CKIO D3 tFMD Tmd4 tDACD tWED1 tRWD tCSD tDACD tBSD D0 Tmd1 tBSD D1 Tmd2 D2 Tmd3 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (2) tRDYH Tmd2w tRDYH tRDYS tWDD Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 tFMD Tmd4w D3 Tmd4 tDACD tWED1 tRWD tCSD Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Sep 24, 2013 R01UH0456EJ0702 Rev. 7.02 tDACD tDACD tBSD tWED1 tRDS tRSD T2 (1) tDACD tBSD tWEDF tRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS WEn D63–D0 (read) RD RD/WR CSn A25–A0 CKIO T1 tDACD tDACD tWED1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tBSD tWED1 tRSD Tw (2) tDACD tRDYS tBSD tWEDF tRSD tRWD tCSD tAD T1 tWED1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tRDYH tRDS T2 tDACD tRSD Tw (3) tRDYH Twe tRDYS tDACD tRDYS tBSD tWEDF tDACD tBSD tWED1 tRSD tRWD tCSD tAD T1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tWED1 tRDYH tRDS T2 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) Page 1001 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD D63–D0 (read) tRDS tWED1 tRDH tWED1 tWEDF WEn tBSD tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) Page 1002 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 22.3.4 Section 22 Electrical Characteristics Peripheral Module Signal Timing Table 22.37 Peripheral Module Signal Timing (1) HD6417750 RBP240 (V) HD6417750 RBP200 (V) HD6417750 RBG240 (V) HD6417750R BG200 (V) HD6417750 RBA240HV HD6417750 3 RBA240HV* *2 HD6417750 F240 (V) *2 HD6417750 RF200 (V) *2 *2 Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — 4 — 4 — 4 — Pcyc*1 22.61 Timer clock pulse width (low) tTCLKWL 4 — 4 — 4 — 4 — Pcyc*1 22.61 Timer clock rise time tTCLKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Timer clock fall time tTCLKf — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Oscillation settling time tROSC — 3 — 3 — 3 — 3 s 22.62 Input clock cycle (asynchronous) tScyc 4 — 4 — 4 — 4 — Pcyc*1 22.63 Input clock cycle (synchronous) tScyc 6 — 6 — 6 — 6 — Pcyc*1 22.63 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tScyc 22.63 Input clock rise time tSCKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Input clock fall time tSCKf — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Transfer data delay time tTXD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.64 Receive data tRXS setup time (synchronous) 16 — 16 — 16 — 16 — ns 22.64 Receive data tRXH hold time (synchronous) 16 — 16 — 16 — 16 — ns 22.64 Output data delay time tPORTD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.65 Input data setup time tPORTS 2 — 2.5 — 3.5 — 3.5 — ns 22.65 Input data hold time tPORTH 1.5 — 1.5 — 1.5 — 1.5 — ns 22.65 SCI I/O ports R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1003 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group HD6417750 RBP240 (V) HD6417750 RBP200 (V) HD6417750 RBG240 (V) HD6417750R BG200 (V) HD6417750 RBA240HV HD6417750 3 RBA240HV* *2 HD6417750 F240 (V) *2 HD6417750 RF200 (V) *2 *2 Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure DMAC DREQn setup time tDRQS 2 — 2.5 — 3.5 — 3.5 — ns 22.66 DREQn hold time tDRQH 1.5 — 1.5 — 1.5 — 1.5 — ns 22.66 DRAKn delay time tDRAKD 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.66 NMI pulse width (high) tNMIH 5 — 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — 30 — ns 22.71 Standby mode 5 — 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — 30 — ns 22.71 Standby mode INTC NMI pulse width (low) H-UDI Notes: tNMIL Input clock cycle tTCKcyc 50 — 50 — 50 — 50 — ns 22.67 Input clock pulse width (high) tTCKH 15 — 15 — 15 — 15 — ns 22.67 Input clock pulse width (low) tTCKL 15 — 15 — 15 — 15 — ns 22.67 Input clock rise time tTCKr — 10 — 10 — 10 — 10 ns 22.67 Input clock fall tTCKf time — 10 — 10 — 10 — 10 ns 22.67 ASEBRK setup time tASEBRKS 10 — 10 — 10 — 10 — tcyc 22.68 ASEBRK hold tASEBRKH time 10 — 10 — 10 — 10 — tcyc 22.68 TDI/TMS setup time tTDIS 15 — 15 — 15 — 15 — ns 22.69 TDI/TMS hold tTDIH time 15 — 15 — 15 — 15 — ns 22.69 TDO delay time tTDO 0 10 0 10 0 10 0 10 ns 22.69 ASE-PINBRK pulse width tPINBRK 2 — 2 — 2 — 2 — Pcyc*1 22.70 1. Pcyc: P clock cycles 4 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF* , PLL2 on Page 1004 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics 3. This is the case when the device in use is an HD6417750RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417750RBA240HV. Table 22.38 Peripheral Module Signal Timing (2) HD6417750S VF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750S VBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *2 *3 *4 Module Item Symbol Min Max Min Max Min Max Unit Figure TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — 4 — 4 — Pcyc*1 22.61 Timer clock pulse width (low) tTCLKWL 4 — 4 — 4 — Pcyc*1 22.61 Timer clock rise time tTCLKr — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Timer clock fall time tTCLKf — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Oscillation settling time tROSC — 3 — 3 — 3 s 22.62 Input clock cycle (asynchronous) tScyc 4 — 4 — 4 — Pcyc*1 22.63 Input clock cycle (synchronous) tScyc 6 — 6 — 6 — Pcyc*1 22.63 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc 22.63 Input clock rise time tSCKr — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Input clock fall tSCKf time — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Transfer data delay time tTXD 1.5 10 1.5 8 1.5 6 ns 22.64 Receive data tRXS setup time (synchronous) 16 — 16 — 16 — ns 22.64 Receive data tRXH hold time (synchronous) 16 — 16 — 16 — ns 22.64 SCI R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1005 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group HD6417750S VF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750S VBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *2 *3 *4 Module Item Symbol Min Max Min Max Min Max Unit Figure I/O ports Output data delay time tPORTD 1.5 10 1.5 8 1.5 6 ns 22.65 Input data setup time tPORTS 3.5 — 3.5 — 3 — ns 22.65 Input data hold tPORTH time 1.5 — 1.5 — 1.5 — ns 22.65 DREQn setup tDRQS time 3.5 — 3.5 — 3 — ns 22.66 DREQn hold time tDRQH 1.5 — 1.5 — 1.5 — ns 22.66 DRAKn delay time tDRAKD 1.5 10 1.5 8 1.5 6 ns 22.66 DMAC Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Page 1006 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics Table 22.39 Peripheral Module Signal Timing (3) HD6417750S VF133 (V) HD6417750 SF167 (V) HD6417750 SBP200 (V) HD6417750S VBT133 (V) HD6417750 SF200 (V) HD6417750 SBA200V *2 *3 *4 Module Item Symbol Min Max Min Max Min Max Unit Figure INTC NMI pulse width (high) tNMIH 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — ns 22.71 Standby mode NMI pulse width (low) tNMIL 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — ns 22.71 Standby mode Input clock cycle tTCKcyc 50 — 50 — 50 — ns 22.67 Input clock pulse width (high) tTCKH 15 — 15 — 15 — ns 22.67 Input clock pulse width (low) tTCKL 15 — 15 — 15 — ns 22.67 Input clock rise time tTCKr — 10 — 10 — 10 ns 22.67 Input clock fall tTCKf time — 10 — 10 — 10 ns 22.67 ASEBRK setup time tASEBRKS 10 — 10 — 10 — tcyc 22.68 ASEBRK hold tASEBRKH time 10 — 10 — 10 — tcyc 22.68 TDI/TMS setup time tTDIS 15 — 15 — 15 — ns 22.69 TDI/TMS hold tTDIH time 15 — 15 — 15 — ns 22.69 TDO delay time tTDO 0 10 0 10 0 10 ns 22.69 ASE-PINBRK pulse width tPINBRK 2 — 2 — 2 — Pcyc*1 22.70 H-UDI Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1007 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.40 Peripheral Module Signal Timing (4) HD6417750 VF128 (V) HD6417750 F167 (V) HD6417750 BP200M (V) *2 *3 *4 Module Item Symbol Min Max Min Max Min Max Unit Figure TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — 4 — 4 — Pcyc*1 22.61 Timer clock pulse width (low) tTCLKWL 4 — 4 — 4 — Pcyc*1 22.61 Timer clock rise time tTCLKr — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Timer clock fall time tTCLKf — 0.8 — 0.8 — 0.8 Pcyc*1 22.61 Oscillation settling time tROSC — 3 — 3 — 3 s 22.62 Input clock cycle (asynchronous) tScyc 4 — 4 — 4 — Pcyc*1 22.63 Input clock cycle (synchronous) tScyc 6 — 6 — 6 — Pcyc*1 22.63 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc 22.63 Input clock rise time tSCKr — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Input clock fall tSCKf time — 0.8 — 0.8 — 0.8 Pcyc*1 22.63 Transfer data delay time tTXD 1.3 10 1.3 8 1.2 6 ns 22.64 Receive data tRXS setup time (synchronous) 16 — 16 — 16 — ns 22.64 Receive data tRXH hold time (synchronous) 16 — 16 — 16 — ns 22.64 Output data delay time tPORTD 0.5 10 0.5 8 0.5 6 ns 22.65 Input data setup time tPORTS 3.5 — 3.5 — 3 — ns 22.65 Input data hold tPORTH time 1.5 — 1.5 — 1.5 — ns 22.65 SCI I/O ports Page 1008 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Symbol Section 22 Electrical Characteristics HD6417750 VF128 (V) HD6417750 F167 (V) HD6417750 BP200M (V) *2 *3 *4 Module Item Min Max Min Max Min Max Unit Figure DMAC DREQn setup tDRQS time 3.5 — 3.5 — 3 — ns 22.66 DREQn hold time tDRQH 1.5 — 1.5 — 1.5 — ns 22.66 DRAKn delay time tDRAKD 1.0 10 1.0 8 1.0 6 ns 22.66 Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1009 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group Table 22.41 Peripheral Module Signal Timing (5) HD6417750 VF128 (V) HD6417750 F167 (V) HD6417750 BP200M (V) *2 *3 *4 Module Item Symbol Min Max Min Max Min Max Unit Figure INTC NMI pulse width (high) tNMIH 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — ns 22.71 Standby mode NMI pulse width (low) tNMIL 5 — 5 — 5 — tcyc 22.71 Normal or sleep mode 30 — 30 — 30 — ns 22.71 Standby mode Input clock cycle tTCKcyc 50 — 50 — 50 — ns 22.67 Input clock pulse width (high) tTCKH 15 — 15 — 15 — ns 22.67 Input clock pulse width (low) tTCKL 15 — 15 — 15 — ns 22.67 Input clock rise time tTCKr — 10 — 10 — 10 ns 22.67 Input clock fall tTCKf time — 10 — 10 — 10 ns 22.67 ASEBRK setup time tASEBRKS 10 — 10 — 10 — tcyc 22.68 ASEBRK hold time tASEBRKH 10 — 10 — 10 — tcyc 22.68 TDI/TMS setup time tTDIS 15 — 15 — 15 — ns 22.69 TDI/TMS hold tTDIH time 15 — 15 — 15 — ns 22.69 TDO delay time tTDO 0 10 0 10 0 10 ns 22.69 ASE-PINBRK pulse width tPINBRK 2 — 2 — 2 — Pcyc*1 22.70 H-UDI Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Page 1010 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 22.61 TCLK Input Timing Stable oscillation RTC internal clock VDD-RTC VDD-RTC min tROSC Figure 22.62 RTC Oscillation Settling Time at Power-On tSCKW SCK, SCK2 tScyc tSCKf tSCKr Figure 22.63 SCK Input Clock Timing R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1011 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group tScyc SCK tTXD tTXD TXD RXD tRXS tRXH Figure 22.64 SCI I/O Synchronous Mode Clock Timing CKIO Ports 19–0 (read) tPORTS tPORTH Ports 19–0 (write) tPORTD tPORTD Figure 22.65 I/O Port Input/Output Timing CKIO tDRQH tDRQH DREQn tDRQS DRAKn tDRQS tDRAKD Figure 22.66 (a) DREQ/DRAK Timing Page 1012 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Section 22 Electrical Characteristics CKIO tDBQS tDBQH DBREQ tBAVD tBAVD BAVL tTRH tTRS TR tDTRS D63 to D0 (READ) (1) tDTRH (2) (1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz) (2): DTR = 1CKIO cycle (= 10 ns: 100 MHz) (tDTRS + tDTRH) < DTR < 10 ns Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing tTCKcyc tTCKL tTCKH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tTCKf tTCKr Note: When clock is input from TCK pin Figure 22.67 TCK Input Timing R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1013 of 1076 Section 22 Electrical Characteristics SH7750, SH7750S, SH7750R Group RESET SCK2/ MRESET (Low) (High) tASEBRKS tASEBRKH tASEBRKS tASEBRKH ASEBRK/ BRKACK Figure 22.68 RESET Hold Timing tTCKcyc TCK tTDIS TDI TMS tTDIH tTDO TDO Figure 22.69 H-UDI Data Transfer Timing tPINBRK ASEBRK Figure 22.70 Pin Break Timing tNMIH tNMIL NMI Figure 22.71 NMI Input Timing Page 1014 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group 22.3.5 Section 22 Electrical Characteristics AC Characteristic Test Conditions The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (VDDQ = 3.3 ±0.3 V) • Input pulse level: VSSQ to 3.0 V (VSSQ to VDDQ for RESET, TRST, NMI, and ASEBRK/BRKACK) • Input rise/fall time: 1 ns The output load circuit is shown in figure 22.72. IOL DUT output LSI output pin VREF CL IOH Notes: CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is set to 30 pF. IOL and IOH values are as shown in table 22.16, Permissible Output Currents. Figure 22.72 Output Load Circuit R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1015 of 1076 Section 22 Electrical Characteristics 22.3.6 SH7750, SH7750S, SH7750R Group Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI' pins is shown below. The graph shown in figure 22.73 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device. The graph will not be linear if the connected load capacitance exceeds the range shown in figure 22.73. +4.0 ns Delay Time +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF +50 pF Load Capacitance Figure 22.73 Load Capacitance vs. Delay Time Page 1016 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix A Address List Appendix A Address List Table A.1 Address List Module Register P4 Address Area 7 1 Address* Size Power-On Reset Manual Reset Synchronization Sleep Standby Clock CCN PTEH H'FF00 0000 H'1F00 0000 32 Undefined Undefined Held Held Ick CCN PTEL H'FF00 0004 H'1F00 0004 32 Undefined Undefined Held Held Ick CCN TTB H'FF00 0008 H'1F00 0008 32 Undefined Undefined Held Held Ick CCN TEA H'FF00 000C H'1F00 000C 32 Undefined Held Held Held Ick CCN MMUCR H'FF00 0010 H'1F00 0010 32 H'0000 0000 H'0000 0000 Held Held Ick CCN BASRA H'FF00 0014 H'1F00 0014 8 Undefined Held Held Held Ick CCN BASRB H'FF00 0018 H'1F00 0018 8 Undefined Held Held Held Ick CCN CCR H'FF00 001C H'1F00 001C 32 H'0000 0000 H'0000 0000 Held Held Ick CCN TRA H'FF00 0020 H'1F00 0020 32 Undefined Undefined Held Held Ick CCN EXPEVT H'FF00 0024 H'1F00 0024 32 H'0000 0000 H'0000 0020 Held Held Ick CCN INTEVT H'FF00 0028 H'1F00 0028 32 Undefined Undefined Held Held Ick CCN PTEA H'FF00 0034 H'1F00 0034 32 Undefined Undefined Held Held Ick CCN QACR0 H'FF00 0038 H'1F00 0038 32 Undefined Undefined Held Held Ick CCN QACR1 H'FF00 003C H'1F00 003C 32 Undefined Undefined Held Held Ick UBC BARA H'FF20 0000 H'1F20 0000 32 Undefined Held Held Held Ick UBC BAMRA H'FF20 0004 H'1F20 0004 8 Undefined Held Held Held Ick UBC BBRA H'FF20 0008 H'1F20 0008 16 H'0000 Held Held Held Ick UBC BARB H'FF20 000C H'1F20 000C 32 Undefined Held Held Held Ick UBC BAMRB H'FF20 0010 H'1F20 0010 8 Undefined Held Held Held Ick UBC BBRB H'FF20 0014 H'1F20 0014 16 H'0000 Held Held Held Ick UBC BDRB H'FF20 0018 H'1F20 0018 32 Undefined Held Held Held Ick UBC BDMRB H'FF20 001C H'1F20 001C 32 Undefined Held Held Held Ick Held Held Held Ick 2 UBC BRCR H'FF20 0020 H'1F20 0020 16 H'0000* BSC BCR1 H'FF80 0000 H'1F80 0000 32 H'0000 2 0000* Held Held Held Bck BSC BCR2 H'FF80 0004 H'1F80 0004 16 2 H'3FFC* Held Held Held Bck BSC BCR3* 5 H'FF80 0050 H'1F80 0050 16 H'0000 Held Held Held Bck BSC 5 BCR4* H'FE0A00F0 H'1E0A00F0 32 H'0000 0000 Held Held Held Bck R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1017 of 1076 Appendix A Address List Module Register SH7750, SH7750S, SH7750R Group P4 Address Area 7 1 Address* Size H'1F80 0008 32 Power-On Reset Manual Reset H'7777 7777 Synchronization Sleep Standby Clock BSC WCR1 H'FF80 0008 Held Held Held Bck BSC WCR2 H'FF80 000C H'1F80 000C 32 H'FFFE EFFF Held Held Held Bck BSC WCR3 H'FF80 0010 H'0777 7777 Held Held Held Bck BSC MCR H'FF80 0014 H'1F80 0014 32 H'0000 0000 Held Held Held Bck BSC PCR H'FF80 0018 H'1F80 0018 16 H'0000 Held Held Held Bck BSC RTCSR H'FF80 001C H'1F80 001C 16 H'0000 Held Held Held Bck BSC RTCNT H'FF80 0020 H'1F80 0020 16 H'0000 Held Held Held Bck BSC RTCOR H'FF80 0024 H'1F80 0024 16 H'0000 Held Held Held Bck BSC RFCR H'FF80 0028 H'1F80 0028 16 H'0000 Held Held Held Bck BSC PCTRA H'FF80 002C H'1F80 002C 32 H'0000 0000 Held Held Held Bck BSC PDTRA H'FF80 0030 H'1F80 0030 16 Undefined Held Held Held Bck BSC PCTRB H'FF80 0040 H'1F80 0040 32 H'0000 0000 Held Held Held Bck BSC PDTRB H'FF80 0044 H'1F80 0044 16 Undefined Held Held Held Bck BSC GPIOIC H'FF80 0048 H'1F80 0048 16 H'0000 0000 Held Held Held Bck BSC SDMR2 H'FF90 xxxx H'1F90 xxxx 8 Write-only BSC SDMR3 H'FF94 xxxx H'1F94 xxxx 8 DMAC SAR0 H'FFA0 0000 H'1FA0 0000 32 Undefined Undefined Held Held Bck DMAC DAR0 H'FFA0 0004 H'1FA0 0004 32 Undefined Undefined Held Held Bck DMAC DMATCR0 H'FFA0 0008 H'1FA0 0008 32 Undefined Undefined Held Held Bck DMAC CHCR0 H'FFA0 000C H'1FA0 000C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR1 H'FFA0 0010 H'1FA0 0010 Undefined Undefined Held Bck DMAC DAR1 H'FFA0 0014 H'1FA0 0014 32 Undefined Undefined Held Held Bck DMAC DMATCR1 H'FFA0 0018 H'1FA0 0018 32 Undefined Undefined Held Held Bck H'1F80 0010 32 32 Bck Bck Held DMAC CHCR1 H'FFA0 001C H'1FA0 001C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR2 H'FFA0 0020 H'1FA0 0020 32 Undefined Undefined Held Held Bck DMAC DAR2 H'FFA0 0024 H'1FA0 0024 32 Undefined Undefined Held Held Bck DMAC DMATCR2 H'FFA0 0028 H'1FA0 0028 32 Undefined Undefined Held Held Bck DMAC CHCR2 H'FFA0 002C H'1FA0 002C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR3 H'FFA0 0030 H'1FA0 0030 Undefined Undefined Held Bck DMAC DAR3 H'FFA0 0034 H'1FA0 0034 32 Undefined Undefined Held Held Bck DMAC DMATCR3 H'FFA0 0038 H'1FA0 0038 32 Undefined Undefined Held Held Bck DMAC CHCR3 H'0000 0000 H'0000 0000 Held Held Bck Page 1018 of 1076 32 H'FFA0 003C H'1FA0 003C 32 Held R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Module Register DMAC DMAOR DMAC SAR4* P4 Address Area 7 1 Address* Appendix A Address List Size Power-On Reset Manual Reset Synchronization Sleep Standby Clock H'FFA0 0040 H'1FA0 0040 32 H'0000 0000 H'0000 0000 Held Held Bck 5 H'FFA0 0050 H'1FA0 0050 32 Undefined Undefined Held Held Bck 5 H'FFA0 0054 H'1FA0 0054 32 Undefined Undefined Held Held Bck DMAC DAR4* DMAC 5 DMATCR4* H'FFA0 0058 DMAC CHCR4* DMAC SAR5* DMAC 5 DAR5* DMAC DMATCR5* 5 5 5 DMAC CHCR5* DMAC SAR6* 5 Undefined Undefined Held Held Bck H'FFA0 005C H'1FA0 005C 32 H'1FA0 0058 32 H'0000 0000 H'0000 0000 Held Held Bck H'FFA0 0060 H'1FA0 0060 32 Undefined Undefined Held Held Bck H'FFA0 0064 H'1FA0 0064 32 Undefined Undefined Held Held Bck H'FFA0 0068 H'1FA0 0068 32 Undefined Undefined Held Held Bck H'FFA0 006C H'1FA0 006C 32 H'0000 0000 H'0000 0000 Held Held Bck 5 H'FFA0 0070 H'1FA0 0070 32 Undefined Undefined Held Held Bck 5 H'FFA0 0074 H'1FA0 0074 32 Undefined Undefined Held Held Bck DMAC DAR6* DMAC 5 DMATCR6* H'FFA0 0078 DMAC CHCR6* DMAC SAR7* DMAC 5 DAR7* DMAC DMATCR7* 5 5 5 5 Undefined Undefined Held Held Bck H'FFA0 007C H'1FA0 007C 32 H'1FA0 0078 32 H'0000 0000 H'0000 0000 Held Held Bck H'FFA0 0080 H'1FA0 0080 32 Undefined Undefined Held Held Bck H'FFA0 0084 H'1FA0 0084 32 Undefined Undefined Held Held Bck H'FFA0 0088 H'1FA0 0088 32 Undefined Undefined Held Held Bck H'FFA0 008C H'1FA0 008C 32 H'0000 0000 H'0000 0000 Held Held Bck H'FFC0 0000 H'1FC0 0000 16 *2 Held Held Held Pck DMAC CHCR7* CPG FRQCR 6 CPG* STBCR H'FFC0 0004 H'1FC0 0004 8 H'00 Held Held Held Pck 6 CPG* WTCNT H'FFC0 0008 H'1FC0 0008 8/16*3 H'00 Held Held Held Pck CPG* 6 3 WTCSR H'FFC0 000C H'1FC0 000C 8/16* H'00 Held Held Held Pck 6 CPG* STBCR2 H'FFC0 0010 H'1FC0 0010 8 H'00 Held Held Held Pck RTC R64CNT H'FFC8 0000 H'1FC8 0000 8 Held Held Held Held Pck RTC RSECCNT H'FFC8 0004 H'1FC8 0004 8 Held Held Held Held Pck RTC RMINCNT H'FFC8 0008 H'1FC8 0008 8 Held Held Held Held Pck RTC RHRCNT H'FFC8 000C H'1FC8 000C 8 Held Held Held Held Pck RTC RWKCNT H'FFC8 0010 H'1FC8 0010 8 Held Held Held Held Pck RTC RDAYCNT H'FFC8 0014 H'1FC8 0014 8 Held Held Held Held Pck RTC RMONCNT H'FFC8 0018 H'1FC8 0018 Held Held Held Held Pck RTC RYRCNT H'FFC8 001C H'1FC8 001C 16 Held Held Held Held Pck RTC RSECAR H'FFC8 0020 H'1FC8 0020 8 Held * Held Held Held Pck R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 8 2 Page 1019 of 1076 Appendix A Address List SH7750, SH7750S, SH7750R Group Area 7 1 Address* Manual Reset Synchronization Sleep Standby Clock Module Register P4 Address RTC RMINAR H'FFC8 0024 H'1FC8 0024 8 Held * 2 Held Held Held Pck RTC RHRAR H'FFC8 0028 H'1FC8 0028 8 Held * 2 Held Held Held Pck H'FFC8 002C H'1FC8 002C 8 Held * 2 Held Held Held Pck Held Held Held Pck 2 Held Held Held Pck Held Held Pck RTC RWKAR Size Power-On Reset RTC RDAYAR H'FFC8 0030 H'1FC8 0030 8 2 Held * RTC RMONAR H'FFC8 0034 H'1FC8 0034 8 Held * H'FFC8 0038 H'1FC8 0038 8 H'00* 2 H'FFC8 003C H'1FC8 003C 8 2 H'09* 2 H'00* Held Held Pck H'FFC8 0050 H'1FC8 0050 8 H'00 Held Held Held Pck Held Held Held Pck Held Held Pck RTC RCR1 H'00* 2 RTC RCR2 RTC RCR3* RTC 5 RYRAR* H'FFC8 0054 H'1FC8 0054 16 Undefined INTC ICR H'FFD0 0000 H'1FD0 0000 16 H'0000* INTC IPRA H'FFD0 0004 H'1FD0 0004 16 H'0000 H'0000 Held Held Pck INTC IPRB H'FFD0 0008 H'1FD0 0008 16 H'0000 H'0000 Held Held Pck INTC IPRC H'FFD0 000C H'1FD0 000C 16 H'0000 H'0000 Held Held Pck INTC 4 IPRD* H'FFD00010 H'1F000010 16 H'DA74 H'DA74 Held Held Pck INTC INTPRI00 *5 H'FE08 0000 H'1E08 0000 32 H'0000 0000 Held Held Held Pck INTC INTREQ00 H'FE08 0020 *5 H'1E08 0020 32 H'0000 0000 Held Held Held Pck INTC INTMSK00 H'FE08 0040 *5 H'1E08 0040 32 H'0000 0300 Held Held Held Pck INTC INTMSKC 5 LR00* H'FE08 0060 H'1E08 0060 32 Write-only 6 CPG* CLKSTP 5 00* H'FE0A 0000 H'1E0A 0000 32 6 CPG* CLKSTPC H'FE0A 0008 H'1E0A 0008 32 5 LR00* TMU TSTR2* 5 5 TMU TCOR3* TMU TCNT3* 5 5 5 TMU TCR3* TMU 5 TCOR4* TMU TCNT4* 5 Page 1020 of 1076 2 H'0000 0000 H'0000* 2 Pck Held Held Held Write-only Pck Pck H'FE10 0004 H'1E10 0004 8 H'00 Held Held Held Pck H'FE10 0008 H'1E10 0008 32 H'FFFF FFFF Held Held Held Pck H'FE10 000C H'1E10 000C 32 H'FFFF FFFF Held Held Held Pck H'FE10 0010 H'1E10 0010 16 H'0000 Held Held Held Pck H'FE10 0014 H'1E10 0014 32 H'FFFF FFFF Held Held Held Pck H'FE10 0018 H'1E10 0018 32 H'FFFF FFFF Held Held Held Pck R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Module Register 5 P4 Address Area 7 1 Address* Appendix A Address List Size Power-On Reset Manual Reset Synchronization Sleep Standby Clock TMU TCR4* H'FE10 001C H'1E10 001C 16 H'0000 Held Held Held Pck TMU TOCR H'FFD8 0000 H'1FD8 0000 8 H'00 H'00 Held Held Pck TMU TSTR H'FFD8 0004 H'1FD8 0004 8 H'00 H'00 Held 2 H'00* Pck TMU TCOR0 H'FFD8 0008 H'1FD8 0008 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCNT0 H'FFD8 000C H'1FD8 000C 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCR0 H'FFD8 0010 H'1FD8 0010 16 H'0000 Held Held Pck TMU TCOR1 H'FFD8 0014 H'1FD8 0014 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCNT1 H'FFD8 0018 H'1FD8 0018 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCR1 H'FFD8 001C H'1FD8 001C 16 H'0000 Held Held Pck TMU TCOR2 H'FFD8 0020 H'1FD8 0020 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCNT2 H'FFD8 0024 H'1FD8 0024 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck H'0000 H'0000 TMU TCR2 H'FFD8 0028 H'1FD8 0028 16 H'0000 H'0000 Held Held Pck TMU TCPR2 H'FFD8 002C H'1FD8 002C 32 Held Held Held Held Pck SCI SCSMR1 H'FFE0 0000 H'1FE0 0000 8 H'00 H'00 Held H'00 Pck SCI SCBRR1 H'FFE0 0004 H'1FE0 0004 8 H'FF H'FF Held H'FF Pck SCI SCSCR1 H'FFE0 0008 H'1FE0 0008 8 H'00 H'00 Held H'00 Pck SCI SCTDR1 H'FFE0 000C H'1FE0 000C 8 H'FF H'FF Held H'FF Pck SCI SCSSR1 H'FFE0 0010 H'1FE0 0010 H'84 H'84 Held H'84 Pck SCI SCRDR1 H'FFE0 0014 H'1FE0 0014 8 H'00 H'00 Held H'00 Pck SCI SCSCMR1 H'FFE0 0018 H'1FE0 0018 8 H'00 H'00 Held H'00 Pck SCI SCSPTR1 H'FFE0 001C H'1FE0 001C 8 2 H'00* H'00* Held H'00* SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16 H'0000 H'0000 Held Held Pck SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8 H'FF H'FF Held Held Pck SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16 H'0000 H'0000 Held Held Pck SCIF SCFTDR2 H'FFE8 000C H'1FE8 000C 8 Undefined Undefined Held Held Pck SCIF SCFSR2 16 H'0060 H'0060 Held Held Pck SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 Undefined Undefined Held Held Pck SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16 H'0000 H'0000 Held Held Pck SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16 H'0000 H'0000 Held Held Pck SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 2 H'0000* H'0000* Held Held Pck SCIF SCLSR2 16 H'0000 H'0000 Held Held Pck H'FFE8 0010 H'1FE8 0010 H'FFE8 0024 H'1FE8 0024 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 8 2 2 2 Pck Page 1021 of 1076 Appendix A Address List SH7750, SH7750S, SH7750R Group Synchronization Sleep Standby Clock Module Register P4 Address H-UDI SDIR H'FFF0 0000 H'1FF0 0000 16 H'FFFF* Held Held Held Pck H-UDI SDDR H'FFF0 0008 H'1FF0 0008 32 Undefined Held Held Held Pck H'FFF0 0014 H'1FF0 0014 16 H'0000 Held Held Held Pck H-UDI SDINT* 5 Size Power-On Reset Manual Reset Area 7 1 Address* 2 Notes: 1. With control registers, the above addresses in the physical page number field can be accessed by means of a TLB setting. When these addresses are referenced directly without using the TLB, operations are limited. 2. Includes undefined bits. See the descriptions of the individual modules. 3. Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. 4. SH7750S, SH7750R only 5. SH7750R only 6. Includes power-down states Page 1022 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix B Package Dimensions Appendix B Package Dimensions JEITA Package Code P-BGA256-27x27-1.27 RENESAS Code PRBG0256DE-B Previous Code BP-256A/BP-256AV MASS[Typ.] 3.0g D A E B ×4 v y1 S y A1 A S S SD e e Y W V U T Reference Symbol R P SE N M L Dimension in Millimeters Min Nom D 27.0 E 27.0 0.20 v K Max w J H A G A1 F 2.5 0.5 e E 0.6 0.7 1.27 0.60 0.75 0.90 D b C x 0.30 B y 0.20 A y1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 φ b φ× M S A B φ0.10 M S 0.35 SD 0.635 SE 0.635 ZD ZE Figure B.1 Package Dimensions (256-Pin BGA: Devices Other than HD6417750RBA240HV and HD6417750SBA200V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1023 of 1076 Appendix B Package Dimensions JEITA Package Code P-HQFP208-28x28-0.50 RENESAS Code PRQP0208KE-B SH7750, SH7750S, SH7750R Group Previous Code FP-208E/FP-208EV MASS[Typ.] 5.3g HD *1 D 156 105 157 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 104 HE b1 c c1 *2 E bp ZE Reference Symbol Terminal cross section 53 208 1 52 ZD Index mark c A2 A F θ L A1 e y *3 bp L1 x M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 28 28 3.20 30.4 30.6 30.8 30.4 30.6 30.8 3.56 0.00 0.15 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 8° 0° 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.3 Figure B.2 Package Dimensions (208-Pin QFP) Page 1024 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group JEITA Package Code P-LFBGA264-15x15-0.80 Appendix B Package Dimensions RENESAS Code PLBG0264GA-A Previous Code BP-264/BP-264V MASS[Typ.] 0.6g D w S B E w S A ×4 v y1 S y A1 A S S ZD e A e U T R P Reference Symbol N M B L K J H Dimension in Millimeters Min Nom D 15.00 E 15.00 Max G v 0.15 F w 0.20 E 1.40 A ZE D C B A1 0.35 0.40 0.45 0.50 0.80 e A b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 φ b φ ×M S A B 0.45 0.55 x 0.08 y 0.10 y1 0.2 SD SE ZD 1.10 ZE 1.10 Figure B.3 Package Dimensions (264-Pin CSP) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1025 of 1076 Appendix B Package Dimensions JEITA Package Code P-FBGA292-17x17-0.80 SH7750, SH7750S, SH7750R Group RENESAS Code PRBG0292GA-A MASS[Typ.] 0.9g Previous Code — E w S A D w S B 4× v y1 S y A1 A S S e ZE B SE e Y W V U T R Reference Symbol P A N Dimension in Millimeters Min Nom D 17.00 K E 17.00 J v M SD L H G F Max 0.15 w 0.20 A 2.00 E A1 ZD D C b A 1 2 3 4 5 6 7 8 0.35 0.40 0.45 0.80 e B 0.45 0.50 0.55 x 0.08 y 0.10 9 10 11 12 13 14 15 16 17 18 19 20 φ b φ ×M S A B y1 0.20 SD 0.40 SE 0.40 ZD 0.9 ZE 0.9 Figure B.4 Package Dimensions (292-Pin BGA) Page 1026 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group RENESAS Code PRBG0256DM-A Previous Code ⎯ MASS[Typ.] 2.8g w S B JEITA Package Code P-BGA256-27x27-1.27 Appendix B Package Dimensions D w S A ×4 y1 S E E1 D1 v e φb A A1 S y S φ× M S A B Y W V U T R P B N M Dimension in Millimeters L K Reference Symbol J D 27.0 G E 27.0 F v 0.20 E D w 0.30 C A Min Nom Max e H ZE B A1 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A ZD 2.6 0.50 e b 0.60 0.70 1.27 0.65 0.75 0.85 x 0.15 y 0.20 y1 0.35 ZD 1.435 ZE 1.435 D1 24.0 E1 24.0 Figure B.5 Package Dimensions (256-Pin BGA: HD6417750RBA240HV and HD6417750SBA200V) R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1027 of 1076 Appendix B Package Dimensions Page 1028 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix C Mode Pin Settings Appendix C Mode Pin Settings The MD8–MD0 pin values are input in the event of a power-on reset via the RESET or SCK2/MRESET pin. (1) Clock Modes • Clock Operating Modes (SH7750, SH7750S) External Pin Combination Frequency (vs. Input Clock) Clock 1/2 Peripheral FRQCR Operating Frequency CPU Bus Module Initial Mode MD2 MD1 MD0 Divider Value PLL1 PLL2 Clock Clock Clock 0 0 0 1 1 2 3 4 5 1 0 0 Off On On 6 3/2 3/2 H'0E1A 1 Off On On 6 1 1 H'0E23 0 On On On 3 1 1/2 H'0E13 1 Off On On 6 2 1 H'0E13 0 On On On 3 3/2 3/4 H'0E0A 1 Off On On 6 3 3/2 H'0E0A Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1029 of 1076 Appendix C Mode Pin Settings SH7750, SH7750S, SH7750R Group • Clock Operating Modes (SH7750R) External Pin Combination Clock Operating Mode MD2 0 0 MD1 0 1 1 2 3 4 1 0 5 6 1 MD0 Frequency (vs. Input Clock) CPU PLL2 Clock PLL1 Bus Clock Peripheral FRQCR Module Clock Initial Value 0 On (×12) On 12 3 3 H'0E1A 1 On (×12) On 12 3/2 3/2 H'0E2C 0 On (×6) 6 2 1 H'0E13 1 On (×12) On 12 4 2 H'0E13 0 On (×6) 6 3 3/2 H'0E0A 1 On (×12) On 12 6 3 H'0E0A 0 Off (×6) 1 1/2 1/2 H'0808 On On Off Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. (2) Area 0 Bus Width Pin Value MD6 MD4 MD3 Bus Width Memory Type 0 0 0 64 bits MPX interface 1 8 bits Reserved (setting prohibited) 0 16 bits Reserved 1 32 bits MPX interface 1 1 0 1 Page 1030 of 1076 0 64 bits SRAM interface 1 8 bits SRAM interface 0 16 bits SRAM interface 1 32 bits SRAM interface R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix C Mode Pin Settings (3) Endian Pin Value MD5 Endian 0 Big endian 1 Little endian (4) Master/Slave Pin Value MD7 Master/Slave 0 Slave 1 Master (5) Clock Input Pin Value MD8 Clock Input 0 External input clock 1 Crystal resonator R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1031 of 1076 Appendix C Mode Pin Settings Page 1032 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Appendix D CKIO2ENB Pin Configuration SH7750, SH7750S, SH7750R Group Appendix D CKIO2ENB Pin Configuration SH7750 SH7750S SH7750R rd_pullup_control VDDQ RD/CASS/FRAME rd_dt_ rd_hiz_control VDDQ RD2 VDDQ rdwr_pullup_control rdwr_dt_ RD/WR rdwr_hiz_control VDDQ RD/WR2 PLL2 Bus clock CKIO ckio_hiz_control CKIO2 VDDQ VSSQ CKIO2ENB Figure D.1 CKIO2ENB Pin Configuration R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1033 of 1076 Appendix D CKIO2ENB Pin Configuration SH7750, SH7750S, SH7750R Group CKIO2ENB Description 0 RD2, RD/WR2, and CKIO2 have the same pin states as RD, RD/WR, and CKIO, respectively 1 RD2, RD/WR2, and CKIO2 are in the high-impedance state Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases. However, CKIO2 is not fed back. Page 1034 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix E Pin Functions Appendix E Pin Functions E.1 Pin States Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State Reset (Power-On) Reset (Manual) Slave Standby Bus Hardware Released Standby 19 19 Z* 19 Z* 19 Z* Z 19 19 19 19 Z 19 Signal Name I/O Master Slave Master D0–D7 I/O Z Z Z* D8–D15 D16–D23 D24–D31 I/O I/O I/O Z Z Z Z Z* Z* 19 19 Z* Z* 19 Z Z* Z* Z* Z* Z Z 19 Z* 19 Z* 19 Z* 19 Z* Z 19 18 Z* K* 19 18 Z* K* 19 18 Z* K* Z D32–D51 I/O Z Z 19 18 Z* K* D52–D55 I/O Z Z 19 Z* 19 Z* 19 Z* 19 Z* Z D56–D63 I/O Z Z 19 Z* 19 Z* 19 Z* 19 Z* Z P 13 15 Z* O* 13 13 6 Z* O* 13 Z 13 8 13 13 6 13 A0, A1, A18–A25 O P Z* Z* A2–A17 O P P Z* O* Z* Z* O* Z* Z RESET I I I I I I I I BACK/BSREQ O H H H H H O Z P 12 I* 12 I* 12 I* 12 I* Z 13 6 Z* H* 13 Z* Z L O Z BREQ/BSACK I P BS O H PZ H 13 Z* CKE O H H O O CS6–CS0 RAS RD/CASS/FRAME RD/WR RDY WE7/CAS7/DQM7 O O O O I O H H H H PI H PZ PZ PZ PZ PI PZ 13 13 6 Z* H* 13 13 4 Z* O* 13 4 Z* O* Z 13 13 4 Z* O* 13 4 Z* O* Z 13 13 6 13 Z Z* H O O Z* Z* Z* H 12 12 Z* H* 12 13 Z* Z Z* 12 I* I* Z* I* Z O 13 Z* 13 4 Z* O* 13 4 Z* O* Z 13 4 Z* O* 13 4 Z* O* Z 13 4 Z* O* 13 4 Z* O* Z WE6/CAS6/DQM6 O H PZ O 13 Z* WE5/CAS5/DQM5 O H PZ O 13 Z* O 13 13 4 Z* O* 13 4 Z* O* Z 13 13 4 Z* O* 13 4 Z* O* Z 13 13 4 13 4 Z WE4/CAS4/DQM4 WE3/CAS3/DQM3 WE2/CAS2/DQM2 O O O R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 H H H PZ PZ PZ O O Z* Z* Z* Z* O* Z* O* Page 1035 of 1076 Appendix E Pin Functions SH7750, SH7750S, SH7750R Group Reset (Power-On) Reset (Manual) Signal Name I/O Master Slave Master Slave Standby Bus Hardware Released Standby WE1/CAS1/DQM1 O H PZ O 13 Z* 13 4 Z* O* 13 4 Z* O* O 13 WE0/CAS0/DQM0 O H PZ Z* 13 Z 13 4 Z* O* Z 11 7 O Z Z* O* 4 O L L L L Z* O* MD7/TXD I/O 14 PI* 14 PI* 11 Z* 11 Z* 11 18 7 11 18 7 Z* K* O* Z* K* O* Z MD6/IOIS16 I 14 PI* PI* DACK1–DACK0 MD5/RAS2 MD4/CE2B MD3/CE2A 1 I/O* 3 I/O* 2 I/O* 14 PI* 14 PI* 14 PI* 14 12 12 I* 13 5 Z* O* 14 13 6 Z* H* 14 13 6 PI* PI* PI* Z* H* 10 12 Z* I* 14 10 12 I* 13 13 4 Z* O* 13 13 6 Z* H* 13 13 6 Z* Z* Z* 10 Z 13 Z* Z 13 Z* H* 10 Z 13 4 Z* O* Z* Z 10 10 CKIO O O O O* Z* O* Z* PZ O* Z* Z STATUS1–STATUS0 O O O O O O O ZO* IRL3–IRL0 I PI PI I* I* I* I* 12 I PI 12 I* 12 I* 12 I* 12 I* I 11 I* 11 Z* 11 I* I L 11 7 Z* O* O NMI I PI 12 DREQ1–DREQ0 I PI PI 11 I* DRAK1–DRAK0 O L L L MD0/SCK RXD SCK2/MRESET MD1/TXD2 MD2/RXD2 CTS2 I/O I I I/O I 14 PI* PI 14 PI* I* 11 I* PI 14 PI* 14 PI* I* 11 PI PI 11 14 PI* 14 11 Z* 11 12 11 I* 11 I* 11 I* 11 Z* 11 12 11 18 7 16 Z 11 18 Z* K* O* I* OK* 11 Z* I* 11 Z 11 I* 11 Z 11 I* 18 7 Z 11 18 7 Z* K* O* Z* K* O* Z PI* I* I* 11 Z* I* 11 Z 11 I* 11 18 Z* K* 11 18 I* K * Z 11 I* 11 18 Z* K* 11 18 I* K * I/O PI PI 11 I* MD8/RTS2 I/O 14 PI* 14 PI* 11 I* TCLK I/O PI PI I* I* K* O * I* O * Z TDO O O O O O O O Z TMS I PI PI PI PI PZ PI Z TCK I PI PI PI PI PZ PI Z TDI I PI PI PI PI PZ PI Z TRST I PI PI PI PI PZ PI Z O 20 9 20 9 PZ* O* PZ* O* 20 PZ* 9 20 O* * 20 PZ* 9 20 O* * PZ 20 PZ* 9 20 O* * Z 21 CKIO2* Page 1036 of 1076 11 11 11 17 11 17 Z R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix E Pin Functions Reset (Power-On) Reset (Manual) Signal Name I/O Master Slave Master Slave Standby Bus Hardware Released Standby RD2* O 20 Z* 9 20 H* * 20 9 Z* PZ* 13 20 Z* * 9 O* 9 13 Z* * 9 13 4 Z* * O* 9 13 4 Z* * O* Z RD/WR2* O 20 Z* 9 20 H* * 20 9 Z* PZ* 13 20 Z* * 9 H* 9 13 Z* * 9 13 4 Z* * H* 9 13 Z* * Z CKIO2ENB I PI PI PI PI PI PI Z CA I I 21 21 ASEBRK/BRKACK I/O I 22 22 PI* O* I 22 22 PI* O* I 22 22 PI* O* I 22 22 PI* O* I 22 22 PI* O* I 22 22 PI* O* Z Legend: I: Input (not Pulled Up) O: Output Z: High-impedance (not Pulled Up) H: High-level output L: Low-level output K: Output state held PI: Input (Pulled Up) PZ: High-impedance (Pulled Up) Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Output when area 2 is used as DRAM. Output when area 5 is used as PCMCIA. Output when area 6 is used as PCMCIA. Z (I) or O on refresh operations, depending on register setting (BCR1.HIZCNT). Depends on refresh operations. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). Z or O, depending on register setting (STBCR.PHZ). Output when refreshing is set. Operation in respective state when CKIO2ENB = 0 (SH7750/SH7750S) (High-level outputs as SH7750R). PZ or O, depending on register setting (FRQCR.CKOEN). Pulled up or not pulled up, depending on register setting (STBCR.PPU). Pulled up or not pulled up, depending on register setting (BCR1.IPUP). Pulled up or not pulled up, depending on register setting (BCR1.OPUP). Pulled up with a built-in pull-up resistance. However it, cannot use for fixation of an input MD pin at the time of power-on reset. Pull up or down outside this LSI. Output when refreshing is set (SH7750R only). Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only). Z or O, depending on register setting (TOCR, TCOE) Output state held when used as port. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1037 of 1076 Appendix E Pin Functions SH7750, SH7750S, SH7750R Group 19. Pulled up or not pulled up, depending on register setting (BCR1.DPUP) (SH7750R only). 20. Z when CKIO2ENB = 1 21. BGA Package only. 22. Depends on Emulator operations. E.2 Handling of Unused Pins • When RTC is not used ⎯ EXTAL2: Pull up to 3.3 V ⎯ XTAL2: Leave unconnected ⎯ VDD-RTC: Power supply (3.3 V) ⎯ VSS-RTC: Power supply (0 V) • When PLL1 is not used ⎯ VDD-PLL1: Power supply (3.3 V) ⎯ VSS-PLL1: Power supply (0 V) • When PLL2 is not used ⎯ VDD-PLL2: Power supply (3.3 V) ⎯ VSS-PLL2: Power supply (0 V) • When on-chip crystal oscillator is not used ⎯ XTAL: Leave unconnected ⎯ VDD-CPG: Power supply (3.3 V) ⎯ VSS-CPG: Power supply (0 V) Note: To prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins. Page 1038 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix F Synchronous DRAM Address Multiplexing Tables Appendix F Synchronous DRAM Address Multiplexing Tables (1) BUS 64 AMX 0 (16M: 512k × 16b × 2) × 4 * AMXEXT 0 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A22 A22 A11 BANK selects bank address A13 A21 H/L A10 Address precharge setting A12 A20 0 A9 Address A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1039 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (2) BUS 32 AMX 0 SH7750, SH7750S, SH7750R Group (16M: 512k × 16b × 2) × 2 * AMXEXT 0 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1040 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (3) BUS 64 AMX 0 Appendix F Synchronous DRAM Address Multiplexing Tables (16M: 512k × 16b × 2) × 4 * AMXEXT 1 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A21 A21 A11 BANK selects bank address A13 A22 H/L A10 Address precharge setting A12 A20 0 A9 Address A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1041 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (4) BUS 32 AMX 0 SH7750, SH7750S, SH7750R Group (16M: 512k × 16b × 2) × 2 * AMXEXT 1 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1042 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (5) BUS 64 AMX 1 Appendix F Synchronous DRAM Address Multiplexing Tables (16M: 1M × 8b × 2) × 8 * AMXEXT 0 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function A14 A23 A23 A11 BANK selects bank address A13 A22 H/L A10 Address precharge setting A12 A21 0 A9 Address A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1043 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (6) BUS 32 AMX 1 SH7750, SH7750S, SH7750R Group (16M: 1M × 8b × 2) × 4 * AMXEXT 0 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1044 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (7) BUS 64 AMX 1 Appendix F Synchronous DRAM Address Multiplexing Tables (16M: 1M × 8b × 2) × 8 * AMXEXT 1 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function A14 A22 A22 A11 BANK selects bank address A13 A23 H/L A10 Address precharge setting A12 A21 0 A9 Address A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1045 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (8) BUS 32 AMX 1 SH7750, SH7750S, SH7750R Group (16M: 1M × 8b × 2) × 4 * AMXEXT 1 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1046 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (9) BUS 64 AMX 2 Appendix F Synchronous DRAM Address Multiplexing Tables (64M: 1M × 16b × 4) × 4 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins A16 A24 A24 A13 A15 A23 A23 A12 A14 A22 0 A11 A13 A21 H/L A10 A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 32MB Function BANK selects bank address Address precharge setting Address Page 1047 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (10) BUS 32 AMX 2 (64M: 1M × 16b × 4) × 2 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7750, SH7750S, SH7750R Group 16MB Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 A13 A21 0 A11 A12 A20 H/L A10 A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1048 of 1076 BANK selects bank address Address precharge setting Address R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (11) BUS 64 Appendix F Synchronous DRAM Address Multiplexing Tables (64M: 2M × 8b × 4) × 8 * (128M: 2M × 16b × 4) × 4 * 64M, column-addr-9bit AMX 3 LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins A16 A25 A25 A13 A15 A24 A24 A12 A14 A23 0 A11 A13 A22 H/L A10 A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 64MB Function BANK selects bank address Address precharge setting Address Page 1049 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (12) BUS 32 (64M: 2M × 8b × 4) × 4 * (128M: 2M × 16b × 4) × 2 64M, column-addr-9bit AMX 3 LSI Address Pins RAS Cycle CAS Cycle SH7750, SH7750S, SH7750R Group 32MB Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 A13 A22 0 A11 A12 A21 H/L A10 A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1050 of 1076 BANK selects bank address Address precharge setting Address R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (13) BUS 64 AMX 4 Appendix F Synchronous DRAM Address Multiplexing Tables (64M: 512k × 32b × 4) × 2 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function BANK selects bank address A15 A23 A23 A12 A14 A22 A22 A11 A13 A21 H/L A10 Address precharge setting A12 A20 0 A9 Address A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1051 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (14) BUS 32 AMX 4 (64M: 512k × 32b × 4) × 1 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7750, SH7750S, SH7750R Group 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1052 of 1076 BANK selects bank address R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (15) BUS 64 AMX 5 Appendix F Synchronous DRAM Address Multiplexing Tables (64M: 1M × 32b × 2) × 2 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function BANK selects bank address A15 A23 A23 A12 A14 A22 0 A11 A13 A21 H/L A10 Address precharge setting A12 A20 0 A9 Address A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1053 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (16) BUS 32 AMX 5 (64M: 1M × 32b × 2) × 1 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7750, SH7750S, SH7750R Group 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 0 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1054 of 1076 BANK selects bank address R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (17) Appendix F Synchronous DRAM Address Multiplexing Tables BUS 64 (128M: 4M × 8b × 4) × 8* (SH7750R only) AMX 6 128M, column-addr-10bit 128MB AMXEXT0 LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function BANK selects bank address A16 A26 A26 A13 A15 A25 A25 A12 A14 A24 0 A11 A13 A23 H/L A10 Address precharge setting A12 A22 A12 A9 Address A11 A21 A11 A8 A10 A20 A10 A7 A9 A19 A9 A6 A8 A18 A8 A5 A7 A17 A7 A4 A6 A16 A6 A3 A5 A15 A5 A2 A4 A14 A4 A1 A3 A13 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1055 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (18) SH7750, SH7750S, SH7750R Group BUS 64 (256M: 4M × 16b × 4) × 4 (SH7750R only) * AMX 6 256M, column-addr-9bit 128MB AMXEXT1 LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function BANK selects bank address A17 A26 A26 A14 A16 A25 A25 A13 A15 A24 0 A12 A14 A23 0 A11 A13 A22 H/L A10 Address precharge setting A12 A21 0 A9 Address A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 A2 Not used A1 Not used A0 Not used Page 1056 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (19) Appendix F Synchronous DRAM Address Multiplexing Tables BUS 32 (128M: 4M × 8b × 4) × 4 (SH7750S and SH7750R only) * AMX 6 column-addr-10bit 64MB AMXEXT 0 LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function BANK selects bank address A15 A25 A25 A13 A14 A24 A24 A12 A13 A23 0 A11 Address precharge setting A12 A22 H/L A10 Address A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1057 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (20) SH7750, SH7750S, SH7750R Group BUS 32 (256M: 4M × 16b × 4) × 2 (SH7750S and SH7750R only) * AMX 6 256M, column-addr-9bit 64MB AMXEXT 1 LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function BANK selects bank address A16 A25 A25 A14 A15 A24 A24 A13 A14 A23 0 A12 A13 A22 0 A11 A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1058 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group (21) BUS 64 AMX 7 Appendix F Synchronous DRAM Address Multiplexing Tables (16M: 256k × 32b × 2) × 2 * 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A13 A21 A21 A10 BANK selects bank address A12 A20 H/L A9 Address precharge setting A11 A19 0 A8 Address A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 A2 Not used A1 Not used A0 Not used R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1059 of 1076 Appendix F Synchronous DRAM Address Multiplexing Tables (22) BUS 32 AMX 7 (16M: 256k × 32b × 2) × 1 * 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7750, SH7750S, SH7750R Group 2MB Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H/L A9 Address precharge setting A10 A18 0 A8 Address A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Note: * Example of a synchronous DRAM configuration Page 1060 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix G Prefetching of Instructions and its Side Effects Appendix G Prefetching of Instructions and its Side Effects This LSI incorporates an on-chip buffer for holding instructions that have been read ahead of their execution (prefetching of instructions). Therefore, do not allocate programs to memory in such a way that instructions are in the last 20 bytes of any memory space. If a program is allocated in such a way, the prefetching of instructions may lead to a bus access for reading an instruction from beyond the memory space. The following shows a case in which such bus access is a problem. Address Area 0 Area 1 H'03FFFFF8 H'03FFFFFA H'03FFFFFC H'03FFFFFE H'04000000 H'04000002 . . . . . . ADD R1,R4 JMP @R2 NOP NOP PC (Program counter) Address of instruction for prefetching Figure G.1 Instruction Prefetch Figure G.1 depicts a case in which the instruction (ADD) indicated by the program counter and the instruction at the address H'04000002 are fetched simultaneously. The program is assumed to branch to a region other than area 1 after the subsequent JMP instruction and delay slot instruction have been executed. In this case, a bus access to area 1 (instruction prefetch), which is not visible in the program flow, may occur. 1. Side effects of the prefetching of instructions a. An external bus access caused by an instruction prefetch may cause malfunctions in external devices, such as FIFOs, that are connected to the region accessed. b. If no device responds to an external bus request that is triggered by an instruction prefetch, execution may hang. 2. Methods of preventing the invalid prefetching of instructions a. Use an MMU. b. Do not allocate programs so that they run into the last 20-byte region of any memory space. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1061 of 1076 Appendix G Prefetching of Instructions and its Side Effects Page 1062 of 1076 SH7750, SH7750S, SH7750R Group R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group Appendix H Power-On and Power-Off Procedures Appendix H Power-On and Power-Off Procedures H.1 Power-On Stipulations 1. Supply power to power supply VDDQ and to I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. Perform input to the signal lines (RESET, MRESET, MD0 to MD10, external clock, etc.) after or at the same time power is supplied to VDDQ. Applying input to signal lines before power is supplied to VDDQ could damage the product. ⎯ Drive the RESET signal low when power is first supplied to VDDQ. ⎯ Input a high-level MRESET signal in the same sequence as power supply VDDQ when power is first supplied to VDDQ. 3. It is recommended to apply power first to power supply VDDQ and then to power supply VDD. 4. In addition to 1., 2., and 3. above, also observe the stipulations in H.3. Furthermore: ⎯ There are no time restrictions on the power-on sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure H.1. Nevertheless, it is recommended that the power-on sequence be completed in as short a time as possible. ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the rise of power supply VDDQ and power supply VDD from GND (0 V) to above the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) is 100 ms (max.), as shown in figure H.2. The product may be damaged if this time limit is exceeded. It is recommended that the power-on sequence be completed in as short a time as possible. H.2 Power-Off Stipulations 1. Power off power supply VDDQ and I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. There are no timing restrictions for the RESET and MRESET signal lines at power-off. 3. Cut off the input signal level for signal lines other than RESET and MRESET in the same sequence as power supply VDDQ. 4. It is recommended to first power off power supply VDD and then power supply VDDQ. 5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in H.3. Furthermore: ⎯ There are no time restrictions on the power-off sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure H.1. Nevertheless, it is recommended that the power-off sequence be completed in as short a time as possible. R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 Page 1063 of 1076 Appendix H Power-On and Power-Off Procedures SH7750, SH7750S, SH7750R Group ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the fall of power supply VDDQ and power supply VDD from the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) to GND (0 V) is 150 ms (max.), as shown in figure H.2. The product may be damaged if this time limit is exceeded. It is recommended that the power-off sequence be completed in as short a time as possible. H.3 Common Stipulations for Power-On and Power-Off 1. Always ensure that VDDQ = VDD−CPG = VDD−RTC = VDD−PLL1/2. Refer to 9.8.5, Hardware Standby Mode Timing (SH7750S, SH7750R Only), regarding VDD−RTC in hardware standby mode on the SH7750S and SH7750R. 2. Ensure that −0.3 V < VDD < VDDQ + 0.3 V. 3. Ensure that VSS = VSSQ = VSS−PLL1/2 = VSS−CPG = VSS−RTC = GND (0 V). The product may be damaged if conditions 1., 2., and 3. above are not satisfied. [V] Power supply VDDQ Power-on Power supply VDD Power-off 0.3 V (max) 0.3 V (max) GND [t] Figure H.1 Power-On Procedure 1 Page 1064 of 1076 R01UH0456EJ0702 Rev. 7.02 Sep 24, 2013 SH7750, SH7750S, SH7750R Group [V] Power-on Appendix H Power-On and Power-Off Procedures Power supply VDDQ Power-off VDDQ(min) Power supply VDD VDD(min) GND tpwu tpwd tpwu