NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
HI5741
DATASHEET
14-Bit, 100MSPS, High Speed D/A Converter
The HI5741 is a 14-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 14-bit linearity is maintained along the
entire transfer curve.
Ordering Information
PART
NUMBER
PART
MARKING
HI5741BIB
HI5741BIB
HI5741BIB-T
HI5741BIB
HI5741BIBZ
(Note)
HI5741BIBZ
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . . 1 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
TEMP.
RANGE (°C)
-40 to +85
PKG.
PACKAGE DWG. #
• Cellular Base Stations
28 Ld SOIC M28.3
• Wireless Communications
28 Ld SOIC Tape and Reel M28.3
-40 to +85
28 Ld SOIC M28.3
(Pb-free)
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Equipment
HI5741BIBZ-T HI5741BIBZ 28 Ld SOIC Tape and Reel M28.3
(Note)
(Pb-free)
• High Resolution Imaging Systems
HI5741-EVS
• Arbitrary Waveform Generators
+25
Evaluation Board
(SOIC)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
HI5741
(28 LD SOIC)
TOP VIEW
D13 (MSB) 1
28 DGND
D12 2
27 AGND
D11
3
D10 4
26 REF OUT
25 CTRL AMP OUT
D9 5
24 CTRL AMP IN
D8 6
23 RSET
D7 7
22 AVEE
D6 8
21 IOUT
D5 9
20 IOUT
D4 10
19 ARTN
D3 11
18 DVEE
D2 12
17 DGND
D1 13
16 DVCC
D0 (LSB) 14
FN4071 Rev 12.00
September 20, 2006
FN4071
Rev 12.00
September 20, 2006
15 CLOCK
Page 1 of 13
HI5741
Typical Application Circuit
+5V
HI5741
0.01F
DVCC (16)
D13
D13 (MSB) (1)
D12
D12 (2)
D11
D11 (3)
D10
D10 (4)
D9
D9 (5)
D8
D8 (6)
D7
D7 (7)
D6
D6 (8)
D5
D5 (9)
D4
D4 (10)
D3
D3 (11)
(20) IOUT
D2
D2 (12)
D1
D1 (13)
(23) RSET
D0
D0 (LSB) (14)
CLK (15)
50
(25) CTRL AMP OUT
-5.2V (AVEE)
(26) REF OUT
D/A OUT
(21) IOUT
64
64
976
(19) ARTN
(27) AGND
DGND (17, 28)
(22) AVEE
DVEE (18)
0.1F
0.1F
(24) CTRL AMP IN
0.01F
0.01F
0.1F
-5.2V (AVEE)
-5.2V (DVEE)
Functional Block Diagram
(LSB) D0
D1
D2
D3
D4
10 LSBs
CURRENT
CELLS
D5
14-BIT
MASTER
REGISTER
D6
D7
DATA
BUFFER/
LEVEL
SHIFTER
R2R
NETWORK
ARTN
SLAVE
REGISTER
227
D8
227
D9
D10
15
D11
15
UPPER
4-BIT
DECODER
D12
15
SWITCHED
CURRENT
CELLS
IOUT
IOUT
(MSB) D13
REF CELL
CLK
+
OVERDRIVEABLE
VOLTAGE
REFERENCE
AVEE
AGND
FN4071 Rev 12.00
September 20, 2006
DVEE
DGND
DVCC
-
REF OUT
25
CTRL AMP
IN
CTRL AMP
OUT
RSET
Page 2 of 13
HI5741
Absolute Maximum ratings TA = +25°C
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . -5.5V
Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . 2.5mA
Voltage from CTRL AMP IN to AVEE . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . 2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . -3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical, Note 1)
JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVEE , DVEE = -4.94V to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal,
TA = +25°C
HI5741BI
TA = -40°C TO +85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
14
-
-
Bits
Integral Linearity Error, INL
(Note 5)
“Best Fit Straight Line”, TA = +25°C
-1.5
±1.0
1.5
LSB
“Best Fit Straight Line”, TA = -40°C to +85°C
-1.75
-
1.75
LSB
Differential Linearity Error, DNL
(Note 5) TA = +25°C
-1.0
±0.5
1.0
LSB
Offset Error, IOS
(Note 5)
-
8
75
A
Full Scale Gain Error, FSE
(Notes 3, 5)
-
3.2
10
%
Full Scale Gain Drift
With Internal Reference
-
±150
-
ppm
FSR/°C
Offset Drift Coefficient
(Note 4)
-
-
0.05
A/°C
-
-20.48
-
mA
(Note 4)
-1.25
-
0
V
Throughput Rate
(Note 4)
100
-
-
MSPS
Output Voltage Settling Time
(1/16th Scale Step Across Segment)
RL = 64(Note 4) - Settling to 0.024%
-
11
-
ns
RL = 64(Note 4) - Settling to 0.012%
-
20
-
ns
Singlet Glitch Area, GE (Peak)
RL = 64(Note 4)
-
1
-
pV•s
Output Slew Rate
RL = 64DAC Operating in Latched Mode (Note 4)
-
1,000
-
V/s
Output Rise Time
RL = 64DAC Operating in Latched Mode (Note 4)
-
675
-
ps
Output Fall Time
RL = 64DAC Operating in Latched Mode (Note 4)
-
470
-
ps
Spurious Free Dynamic Range within a Window
(Note 4)
fCLK = 10 MSPS, fOUT = 1.23MHz, 2MHz Span
-
87
-
dBc
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
FN4071 Rev 12.00
September 20, 2006
fCLK = 20 MSPS, fOUT = 5.055MHz, 2MHz Span
-
77
-
dBc
fCLK = 40 MSPS, fOUT = 16MHz, 10MHz Span
-
75
-
dBc
fCLK = 50 MSPS, fOUT = 10.1MHz, 2MHz Span
-
80
-
dBc
fCLK = 80 MSPS, fOUT = 5.1MHz, 2MHz Span
-
78
-
dBc
fCLK = 100 MSPS, fOUT = 10.1MHz, 2MHz Span
-
79
-
dBc
Page 3 of 13
HI5741
Electrical Specifications
AVEE , DVEE = -4.94V to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal,
TA = +25°C (Continued)
HI5741BI
TA = -40°C TO +85°C
PARAMETER
Spurious Free Dynamic Range to Nyquist
(Note 4)
Multi-Tone Power Ratio
(MTPR)
TEST CONDITIONS
fCLK = 10 MSPS, fOUT = 1.023MHz, 5MHz Span
MIN
TYP
MAX
UNITS
-
86
-
dBc
fCLK = 10 MSPS, fOUT = 2.02MHz, 5MHz Span
-
85
-
dBc
fCLK = 25 MSPS, fOUT = 2.02MHz, 12.5MHz Span
-
77
-
dBc
fCLK = 50 MSPS, fOUT = 5.055MHz, 25MHz Span
-
74
-
dBc
fCLK = 75 MSPS, fOUT = 7.52MHz, 37.5MHz Span
-
73
-
dBc
fCLK = 100 MSPS, fOUT = 10.1MHz, 50MHz Span
-
71
-
dBc
8 Tones, no Clipping, 110kHz Spacing, 220kHz spacing
between tones 4 and 5, fCLK = 20 MSPS (Note 7)
-
76
-
dBc
-1.27
-1.23
-1.17
V
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, VREF
(Note 5)
Internal Reference Voltage Drift
(Note 4)
-
50
-
V/°C
Internal Reference Output Current Sink/Source
Capability
(Note 4)
-500
-
+50
A
Internal Reference Load Regulation
IREF = 0 to IREF = -500A
-
100
-
V
Amplifier Input Impedance
(Note 4)
-
3
-
M
Amplifier Large Signal Bandwidth
4.0VP-P Sine Wave Input, to Slew Rate Limited (Note 4)
-
1
-
MHz
Amplifier Small Signal Bandwidth
1.0VP-P Sine Wave Input, to -3dB Loss (Note 4)
-
5
-
MHz
Reference Input Impedance (CTL IN)
(Note 4)
-
12
-
k
Reference Input Multiplying Bandwidth (CTL IN)
RL = 50, 100mV Sine Wave, to -3dB Loss at IOUT
(Note 4)
-
75
-
MHz
-
V
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH
(Note 5)
2.0
-
Input Logic Low Voltage, VIL
(Note 5)
-
-
0.8
V
Input Logic Current, IIH
(Note 5)
-
-
400
A
Input Logic Current, IIL
(Note 5)
-
-
700
A
Digital Input Capacitance, CIN
(Note 4)
-
3.0
-
pF
Data Setup Time, tSU
See Figure 1 (Note 4)
3
2.0
-
ns
Data Hold Time, tHLD
See Figure 1 (Note 4)
0.5
0.25
-
ns
Propagation Delay Time, tPD
See Figure 1 (Note 4)
-
4.5
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 1 (Note 4)
1.0
0.85
-
ns
TIMING CHARACTERISTICS
POWER SUPPLY CHARACTERISTICS
IVEEA
(Note 5)
-
42
50
mA
IVEED
(Note 5)
-
75
95
mA
IVCCD
(Note 5)
-
13
20
mA
Power Dissipation
(Note 5)
-
650
-
mW
Power Supply Rejection Ratio
VCC 5%, VEE 5%
-
5
-
A/V
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the
ratio should be 16.
4. Parameter guaranteed by design or characterization and not production tested.
5. All devices are 100% tested at +25°C.
6. Dynamic Range must be limited to a 1V swing within the compliance range.
7. In testing MTPR, tone frequencies ranged from 1.95MHz to 3.05MHz. The ratio is measured as the range from peak power to peak distortion in
the region of removed tones.
FN4071 Rev 12.00
September 20, 2006
Page 4 of 13
HI5741
Timing Diagrams
50%
CLK
D13-D0
GLITCH AREA = 1/2 (H x W)
V
ERROR BAND
HEIGHT (H)
IOUT
tPD
t(ps)
WIDTH (W)
tSETT
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
tPW1
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D13-D0
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN4071 Rev 12.00
September 20, 2006
Page 5 of 13
HI5741
Typical Performance Curves
-1.17
670
-1.18
660
-1.19
-1.20
-1.21
640
(V)
(mW)
650
630
-1.22
-1.23
-1.24
620
-1.25
NOTE: CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
610
600
-50 -40 -30 -20 -10
0
10
20
30
40
50
-1.26
60
70
-1.27
-50 -40 -30 -20 -10
80 90
TEMPERATURE (°C)
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
40
50
60
70
80 90
0.5
0.5
0.25
(LSB)
(LSB)
30
0.8
1.0
0
0
-0.5
-0.25
-1.0
-0.5
0
5000
10,000
-0.8
15,000
0
5000
CODE
10,000
15,000
CODE
FIGURE 6. TYPICAL INL PERFORMANCE
FIGURE 7. TYPICAL DNL PERFORMANCE
40
4.2
35
4.0
3.8
30
3.6
25
3.4
(%)
(A)
10 20
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
-1.5
0
TEMPERATURE (°C)
20
3.2
3.0
15
2.8
10
2.6
5
0
-50 -40 -30 -20 -10
2.4
0
10
20
30
40
50
60
TEMPERATURE (°C)
FIGURE 8. TYPICAL OFFSET CURRENT OVER
TEMPERATURE
FN4071 Rev 12.00
September 20, 2006
70
80 90
2.2
-50 -40 -30 -20 -10
0
10 20
30
40
50
60
70
80 90
TEMPERATURE (°C)
FIGURE 9. TYPICAL GAIN ERROR OVER TEMPERATURE
Page 6 of 13
HI5741
(Continued)
90
90
85
85
80
80
(dBc)
(dBc)
Typical Performance Curves
75
70
70
65
65
fOUT = (1/10) fCLK
60
75
10
fOUT = (1/5) fCLK
20
30
40
50
60
60 70 80 90 100
10
20
fCLK (MSPS)
FIGURE 10. SFDR vs CLOCK FREQUENCY
82
80
80
76
78
50
60 70 80 90100
76
74
74
72
(dBc)
(dBc)
40
FIGURE 11. SFDR vs CLOCK FREQUENCY
82
70
68
72
70
68
66
64
30
fCLK (MSPS)
66
64
fCLK = 50 MSPS
62
1
5
62
10
fOUT (MSPS)
fCLK = 75 MSPS
1
5
10
15
fOUT (MHz)
FIGURE 13. SFDR vs fOUT
FIGURE 12. SFDR vs fOUT
80
-72
fOUT = 2.03MHz
78
-74
76
72
(dBc)
(dBc)
3RD HARMONIC
-76
74
70
-78
-80
2ND HARMONIC
68
-82
66
64
62
-84
fCLK = 100 MSPS
1
5
fOUT (MHz)
FIGURE 14. SFDR vs fOUT
FN4071 Rev 12.00
September 20, 2006
10
15
20
-86
10
20
30
40
50
60 70 80 90100
fCLK (MSPS)
FIGURE 15. HARMONIC DISTORTION vs CLOCK FREQUENCY
Page 7 of 13
HI5741
Typical Performance Curves
(Continued)
10dB/
10dB/
fCLK = 20 MSPS
fCLK = 100 MSPS
fOUT = 26.6MHz
SFDR = 77.5dBc
MTPR = 75.17dBc
S
S
C
C
START 1.900MHz
STOP 3.100MHz
CENTER 26.637MHz
SPAN 2.000MHz
FIGURE 17. SFDR WITHIN A WINDOW
FIGURE 16. TYPICAL MTPR PERFORMANCE
12-BIT WINDOW
: 240V
@: -30.96mV
: 300V
@: -124.1mV
SETTLING TIME
~10ns
1
1
GLITCH = (0.5) • (300V) • (3.3ns)
= 0.495pV/s
CH1 1.00mV~
M 5.0ns CH1
-16.9mV
FIGURE 18. TYPICAL SETTLING TIME PERFORMANCE
CH1 1.00mV
M 5.0ns CH1
-109mV
FIGURE 19. TYPICAL GLITCH ENERGY
Pin Descriptions
PIN NO.
1-14
15
PIN NAME
PIN DESCRIPTION
D13 (MSB) thru D0 (LSB) Digital Data Bit 13, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit.
CLK
Data Clock Pin 100kHz to 100 MSPS.
16
DVCC
Digital Logic Supply +5V.
17, 28
DGND
Digital Ground.
18
DVEE
-5.2V Logic Supply.
23
RSET
External Resistor to set the full scale output current. IFS = 16 x (VREFOUT /RSET). Typically 976.
27
AGND
Analog Ground Supply current return pin.
19
ARTN
Analog Signal Return for the R/2R ladder.
21
IOUT
Current Output Pin.
20
IOUT
Complementary Current Output pin.
-5.2V Analog Supply.
22
AVEE
24
CTRL AMP IN
25
CTRL AMP OUT
Control amplifier out. Provides precision control of the current sources when connected to CTRL AMP IN
such that IFS = 16 x (VREFOUT /RSET).
26
REF OUT
-1.23V (typical) bandgap reference voltage output. Can sink up to 500A or be overdriven by an external
reference capable of delivering up to 2mA.
FN4071 Rev 12.00
September 20, 2006
Input to the current source base rail. Typically connected to CTRL AMP OUT and a 0.1F capacitor to AVEE.
Allows external control of the current sources.
Page 8 of 13
HI5741
Detailed Description
The HI5741 is a 14-bit, current out D/A converter. The DAC
can convert at 100 MSPS and runs on +5V and -5.2V supplies.
The architecture is an R/2R and segmented switching current
cell arrangement to reduce glitch. Laser trimming is employed
to tune linearity to true 14-bit levels. The HI5741 achieves its
low power and high speed performance from an advanced
BiCMOS process. The HI5741 consumes 650mW (typical) and
has an improved hold time of only 0.25ns (typical). The HI5741
is an excellent converter for use in communications
applications and high performance video systems.
Digital Inputs
The HI5741 is a TTL/CMOS compatible D/A. Data is latched by
a Master register. Once latched, data inputs D0 (LSB) through
D13 (MSB) are internally translated from TTL to ECL. The
internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
Decoder/Driver
The architecture employs a split R/2R ladder and segmented
current source arrangement. Bits D0 (LSB) through D9 directly
drive a typical R/2R network to create the binary weighted current
sources. Bits D10 through D13 (MSB) pass through a
“thermometer” decoder that converts the incoming data into 15
individual segmented current source enables. This split
architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
Clocks and Termination
The internal 14-bit register is updated on the rising edge of the
clock. Since the HI5741 clock rate can run to 100 MSPS, to
minimize reflections and clock noise into the part, proper
termination should be used. In PCB layout clock runs should be
kept short and have a minimum of loads. To guarantee
consistent results from board to board, controlled impedance
PCBs should be used with a characteristic line impedance ZO of
50.
To terminate the clock line, a shunt terminator to ground is the
most effective type at a 100 MSPS clock rate. A typical value
for termination can be determined by the equation:
RT = ZO
for the termination resistor. For a controlled impedance board
with a ZO of 50, the RT = 50. Shunt termination is best used
at the receiving end of the transmission line or as close to the
HI5741 CLK pin as possible.
ZO = 50
CLK
HI5741
DAC
RT = 50
FIGURE 20. HI5741 CLOCK LINE TERMINATION
FN4071 Rev 12.00
September 20, 2006
Rise and Fall times and propagation delay of the line will be
affected by the shunt terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1F and 0.01F ceramic
capacitors placed as close to the body of the HI5741 as
possible on the analog (AVEE) and digital (DVEE) supplies.
The analog and digital ground returns should be connected
together back at the device to ensure proper operation on
power up. The VCC power pin should also be decoupled with a
0.1F capacitor.
Reduction of digital noise (caused by high slew rates on the bit
inputs to the HI5741) can be accomplished through the use of
series termination resistors. The use of serial resistors, which
combine with the input capacitance of the HI5741 to induce a low
pass filter characteristic, keeps the noise generated by high slew
rate digital signals from corrupting the high accuracy analog data.
Refer to Application Note AN9619 “Optimizing setup conditions
for high accuracy measurements of the HI5741” for further details
on selecting the proper value of series termination to meet
application specific needs.
Reference
The internal reference of the HI5741 is a -1.23V (typical)
bandgap voltage reference with 50V/°C of temperature drift
(typical). The internal reference is connected to the Control
Amplifier which in turn drives the segmented current cells.
Reference Out (REF OUT) is internally connected to the Control
Amplifier. The Control Amplifier Output (CTRL OUT) should be
used to drive the Control Amplifier Input (CTRL IN) and a 0.1F
capacitor to analog VEE . This improves settling time by
providing an AC ground at the current source base node. The
Full Scale Output Current is controlled by the REF OUT pin and
the set resistor (RSET). The ratio is:
IOUT (Full Scale) = (VREF OUT /RSET) x 16.
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better performance
over temperature. Figure 21 illustrates a typical external
reference configuration.
HI5741
(26) REF OUT
-1.25V
R
-5.2V
FIGURE 21. EXTERNAL REFERENCE CONFIGURATION
Multiplying Capability
The HI5741 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal of
up to 0.6VP-P can be applied directly to the REF OUT pin as
shown in Figure 22.
Page 9 of 13
HI5741
Also, the input signal must be limited to 1VP-P to avoid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
CTRL OUT
CTRL IN
0.01F
AVEE
HI5741
REF OUT
CIN (OPTIONAL)
VIN
RSET
FIGURE 22. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The signal must have a DC value such that the peak negative
voltage equals -1.25V. Alternately, a capacitor can be placed
in series with REF OUT if a DC multiplying is not required. The
lower input bandwidth can be calculated using the following
formula:
1
C IN = ------------------------------------------ 2 1400 f IN
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 23.
HI5741
CTRL OUT
200
VIN
C1
C2
AVEE
The outputs IOUT and IOUT are complementary current outputs.
Current is steered to either IOUT or IOUT in proportion to the
digital input code. The sum of the two currents is always equal to
the full scale current minus one LSB. The current output can be
converted to a voltage by using a load resistor. Both current
outputs should have the same load resistor (64 typically). By
using a 64 load on the output, a 50 effective output resistance
(ROUT) is achieved due to the 227 (15%) parallel resistance
seen looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50 output is needed for matching
the output with a 50 line. The load resistor should be chosen so
that the effective output resistance (ROUT) matches the line
resistance. The output voltage is:
VOUT = IOUT x ROUT .
IOUT is defined in the reference section. IOUT is not trimmed to 14
bits, so it is not recommended that it be used in conjunction with
IOUT in a differential-to-single-ended application. The compliance
range of the output is from -1.25V to 0V, with a 1VP-P voltage
swing allowed within this range.
TABLE 2. INPUT CODING vs CURRENT OUTPUT
CTRL IN
50
FIGURE 23. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The nominal input/output relationship is defined as:
V IN
I OUT = -------------80
In order to prevent the full scale output current from exceeding
20.48mA, the RSET resistor must be adjusted according to the
following equation:
16V REF
R SET = -----------------------------------------------------------------------------------------V IN PEAK
I OUT Full scale – -----------------------------
80
INPUT CODE (D13-D0)
IOUT (mA)
IOUT (mA)
11 1111 1111 1111
-20.48
0
10 0000 0000 0000
-10.24
-10.24
00 0000 0000 0000
0
-20.48
Settling Time
The settling time of the HI5741 is measured as the time it takes
for the output of the DAC to settle to within a ±defined error
band of its final value during a 1/16th (code 0000... to 0001
0000.... or 1111... to 1110 1111...) scale transition. In defining
settling time specifications for the HI5741, two levels of accuracy
are considered. The accuracy levels defined for the HI5741 are
12 (or 0.024%) and 13 (0.012%) bits.
Glitch
The circuit in Figure 23 can be tuned to adjust the lower cutoff
frequency by adjusting capacitor values. Table 1 illustrates the
relationship.
TABLE 1. CAPACITOR SELECTION
fIN
C1
C2
100kHz
0.01F
1F
>1MHz
0.001F
0.1F
FN4071 Rev 12.00
September 20, 2006
Outputs
The output glitch of the HI5741 is measured by summing the
area under the switching transients after an update of the DAC.
Glitch is caused by the time skew between bits of the incoming
digital data. Typically, the switching time of digital inputs are
asymmetrical meaning that the turn off time is faster than the
turn on time (TTL designs). Unequal delay paths through the
device can also cause one current source to change before
another. In order to minimize this, the Intersil HI5741 employs
an internal register, just prior to the current sources, which is
updated on the clock edge. Lastly, the worst case glitch on
traditional D/A converters usually occurs at the major transition
(i.e., code 8191 to 8192). However, due to the split architecture
of the HI5741, the glitch is moved to the 1023 to 1024
Page 10 of 13
HI5741
transition (and every subsequent 1024 code transitions
thereafter). This split R/2R segmented current source
architecture, which decreases the amount of current switching
at any one time, makes the glitch practically constant over the
entire output range. By making the glitch a constant size over
the entire output range this effectively integrates this error out
of the end application.
In measuring the output glitch of the HI5741 the output is
terminated into a 64 load. The glitch is measured at any one
of the current cell carry (code 1023 to 1024 transition or any
multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 25 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
HI5741
(21) IOUT
64
100MHz
LOW PASS
FILTER
SCOPE
50
5k
REF OUT
(26)
-
+
-
5k
1/ CA2904
2
+
1/ CA2904
2
0.1F
240
240
HI5741
IOUT
(21)
60
50
-
VOUT
+
HFA1100
FIGURE 26. BIPOLAR OUTPUT CONFIGURATION
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 27 shows how to interface an HI5741 to
the HSP45106.
Definition of Specifications
FIGURE 24. GLITCH TEST CIRCUIT
Integral Linearity Error (INL) is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error (DNL) is the measure of the error in
step size between adjacent codes along the converter’s transfer
curve. Ideally, the step size is 1 LSB from one code to the next,
and the deviation from 1 LSB is known as DNL. A DNL
specification of greater than -1 LSB guarantees monotonicity.
a (mV)
GLITCH ENERGY = (a x t)/2
t (ns)
FIGURE 25. MEASURING GLITCH ENERGY
Applications
Bipolar Applications
To convert the output of the HI5741 to a bipolar 4V swing, the
following applications circuit is recommended. The reference
can only provide 125A of drive, so it must be buffered to
create the bipolar offset current needed to generate the -2V
output with all bits ‘off’. The output current must be converted
to a voltage and then gained up and offset to produce the
proper swing. Care must be taken to compensate for the
voltage swing and error.
Feedthru is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time is the time required
from the 50% point on the clock input for a full scale step to
settle within an 1/2 LSB error band.
Output Voltage Small Scale Settling Time is the time
required from the 50% point on the clock input for a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area (GE) is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a volt • time specification
(typically pV-s).
Differential Gain (AV) is the gain error from an ideal sine
wave with a normalized amplitude.
Differential Phase () is the phase error from an ideal sine
wave.
FN4071 Rev 12.00
September 20, 2006
Page 11 of 13
HI5741
Signal to Noise Ratio (SNR) is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics are
ignored, and an output filter of 1/2 the clock frequency is used
to eliminate alias products.
Total Harmonic Distortion (THD) is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The first
5 harmonics are included, and an output filter of 1/2 the clock
frequency is used to eliminate alias products.
Spurious Free Dynamic Range (SFDR) is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into the
D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
Multi-Tone Power Ratio (MTPR) is the amplitude difference
from peak amplitude to peak distortion (either harmonic or nonharmonic). An 8 tone pattern is loaded into the D/A. The tone
spacing of this pattern (f) is created such that tones 1 through 4
and 5 through 8 are spaced equally, with tones 4 and 5 spaced
at 2f. MTPR is measured as the dynamic range from peak
power to peak distortion in the 2f gap.
Intermodulation Distortion (IMD) is the measure of the sum
and difference products produced when a two tone input is
driven into the D/A. The distortion products created will arise at
sum and difference frequencies of the two tones. IMD can be
calculated using the following equation:
20Log (RMS of Sum and Difference Distortion Products)
IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------ RMS Amplitude of the Fundamental
U2
33 MSPS
CLK
BASEBAND
BIT
STREAM
K9
C11
B11
ENCODER
C10
A11
F10
F9
F11
H11
G11
G9
J11
G10
D10
CONTROLLER
VCC
J10
K11
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
VCC
VCC
H10
K2
J2
CLK
MOD2
MOD1
U1
MOD0
PMSEL DACSTRB
ENPOREG SIN15
ENOFREG SIN14
ENCFREG SIN13
SIN12
ENPHAC
SIN11
ENTIREG
SIN10
INHOFR
SIN9
INITPAC
SIN8
INITTAC
SIN7
SIN6
TEST
SIN5
PARSER
SIN4
BINFMT
SIN3
SIN2
SIN1
C15_MSB
SIN0
C4
C13
C12
C11
C10
COS15
C9
COS14
C8
COS13
COS12
C7
COS11
C6
COS10
C5
COS9
C4
COS8
C3
COS7
C2
COS6
C1
COS5
C0
COS4
A2
COS3
A1
COS2
A0
COS1
CS
COS0
WR
PACI
TICO
L1
VCC
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
DVCC
IOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D13 (MSB)
D12
D11
IOUT/
D10
D9
C AMP IN
D8
D7
D6 C AMP OUT
D5
D4
D3
D2
REF OUT
D1
15
RSET
D0 (LSB)
CLK
28
DGND
17
DGND
R4
50
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
16
-5.2V_D
TO RF
UP-CONVERT
STAGE
FILTER
ARET
R1
21
64
R2
20
64
24
25
C2
0.1F
C1
0.01F
-5.2V_A
-5.2V_A
26
R3
23
976
19
AVSS 27
18 DV
EE
AVEE
22
-5.2V_A
HI5741
L1
-5.2V_D
10H
-5.2V_A
L2
10H
B2
OES
OEC
HSP45106
FIGURE 27. PSK MODULATOR USING THE HI5741 AND HSP45106 16-BIT NCO
FN4071 Rev 12.00
September 20, 2006
Page 12 of 13
HI5741
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394
0.419
1.27 BSC
H
N
NOTES:
MAX
A1
e
µ
MIN
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
© Copyright Intersil Americas LLC 2000-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4071 Rev 12.00
September 20, 2006
Page 13 of 13
工商网监
湘ICP备2023018690号
