RC32365
IDTTM InterpriseTM Integrated
Communications Processor
Device Overview
–
–
–
–
–
–
–
2-way set associative
LRU replacement algorithm
4 word line size
Sub-block ordering
Byte parity
Per line cache locking
Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or
write-back algorithms
– Enhanced EJTAG and JTAG Interfaces
– Compatible with IEEE Std. 1149.1-1990
◆
Security Engine
– Dedicated DMA channels for high speed data transfers to and
from the security engine
– On-chip memory for storage of two security contexts
– Supports ECB and CBC modes for the following symmetric
encryption algorithms: DES, triple DES (both two key (k1=k3)
and three key (k1!=k3) modes), AES-128 with 128-bit blocks,
AES-192 with 128-bit blocks
– Hardware support for encryption pad generation and checking
using one of seven popular padding algorithms: supports pad
algorithm required by IPSec ESP
– Supports MD5 and SHA-1 one-way hash functions
– Programmable truncation length of computed hash and HMAC
on a security context basis
– Supports concurrent hash and encryption operations
The RC32365 device is a member of the IDT™ Interprise™ family of
integrated communications processors. This device is designed to
address a range of communications applications that require the efficient processing of IPSec algorithms. These applications include gateways, wireless access points, and virtual private network (VPN)
equipment. The key to the RC32365’s efficient processing of IPSec
algorithms is a highly progammable security engine which off-loads the
CPU core of encryption/decryption, hashing, and padding tasks.
Features List
◆
RC32300 32-bit CPU core
– 32-bit MIPS instruction set
– Supports big or little endian operation
– MMU
– 16-entry TLB
– Supports variable page sizes and enhanced write algorithm
– Supports variable number of locked entries
– 8KB Instruction Cache
– 2-way set associative
– LRU replacement algorithm
– 4 word line size
– Sub-block ordering
– Word parity
– Per line cache locking
– 2KB Data Cache
Block Diagram
MII
Security Functions
32-bit MIPS
CPU Core
EJTAG
JTAG
D. Cache
MII
Interrupt
Controller
.
.
MMU
Bus/System
Integrity
Monitor
I. Cache
2 Ethernet
10/100
Interfaces
Security
Context Storage
Hash
Unit
RNG
Encryption
Unit
DMA
Controller
Arbiter
IPBusTM
SDRAM & Device
Controllers
including PCMCIA
Support
Memory &
Peripheral Bus
(including PCMCIA)
3 Counter
Timers
GPIO
Interface
UART
(16550)
Serial Channel
GPIO Pins
SPI
Controller
SPI Bus
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
PCI Bus
Figure 1 RC32365 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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© 2005 Integrated Device Technology, Inc.
October 5, 2005
DSC 6210
RC32365
– Optimized for IPSec AH, ESP, and AH+ESP (single MAC)
tunnel and transport mode processing: initialization Vector (IV)
insertion and extraction, HMAC checking, AH mutable field
processing for both IPv4 and IPv6 packets, IPSec pad generation and checking
◆ Random Number Generator
– True hardware random number generator suitable for security
applications: may be used to generate symmetric and public
keys, initialization vectors, and nonces
– Dedicated DMA engine for transferring random numbers to
memory
– Generates random numbers at a bit rate equal to IPBus clock
frequency divided by 32
– Provides 4 word (16 byte) FIFO to queue random numbers
– Randomness tester continually verifies proper operation of
random number generator using a randomness test defined in
FIPS 140-2
◆
PCI Interface
– 32-bit PCI revision 2.2 compliant
– Supports host or satellite operation in both master and target
modes
– PCI clock: supports frequencies from 16 MHz to 66 MHz, PCI
clock may be asynchronous to master clock (CLK)
– PCI arbiter in Host mode: supports 3 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
◆
Two Ethernet Interfaces
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Two IEEE 802.3u compatible Media Independent Interfaces
(MII) with serial management interface
– MII supports IEEE 802.3u auto-negotiation speed selection
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x1997
◆
SDRAM Controller
– Supports up to 512 MB of memory
– 2 chip selects (each supports 2 or 4 banks internal SDRAM
banks)
– 32-bit data width, supports 8/16/32-bit width devices
– Supports 16Mb, 64Mb, 128Mb, and 256Mb, and 512Mb
devices
– Automatic refresh generation
◆
Memory and Peripheral Device Controller
– Provides “glueless” interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
– Provides “glueless” interface to many 16-bit PCMCIA devices
– Demultiplexed address and data buses: 32-bit data bus, 26-bit
address bus, 6 chip selects, control for external data bus
buffers
– Supports 8-bit, 16-bit, and 32-bit width devices: automatic byte
gathering and scattering
– Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/postwrite delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
when counter expires
– Supports up to 64MB of memory per chip select
◆
DMA Controller
– 9 DMA channels: two channels for each of the two Ethernet
interfaces (transmit/receive), two channels for PCI (PCI to
Memory and Memory to PCI), two channels for security engine
(input/output), one channel for the hardware random number
generator
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
address may be on any byte boundary) with arbitrary byte
length
◆
General Purpose Peripherals
– Serial port compatible with 16550 Universal Asynchronous
Receiver Transmitter (UART)
– Three general purpose 32-bit counter/timers
– Interrupt Controller
– Serial Peripheral Interface (SPI) supporting host mode
– 16 general purpose I/O (GPIO) pins which can be configured
as interrupt sources
◆ System Features
– JTAG Interface (IEEE Std. 1149.1 compatible)
– 256 pin CABGA package
– 2.5V core supply and 3.3V I/O supply
CPU Execution Core
The RC32365 is built around the RC32300 32-bit high performance
microprocessor core. The RC32300 implements the enhanced MIPS-II
ISA and helps meet the real-time goals and maximize throughput of
communications and consumer systems by providing capabilities such
as a prefetch instruction, multiple DSP instructions, and cache locking.
The instruction set is largely compatible with the MIPS32 instruction set,
allowing the customer to select from a broad range of software and
development tools. Cache locking guarantees real-time performance by
holding critical code and parameters in the cache for immediate availability. The microprocessor also implements an on-chip MMU with a
TLB, making the it fully compliant with the requirements of real time
operating systems.
Security Engine
The RC32365 incorporates an on-chip security engine that has been
designed to accelerate IPSec performance and minimize the amount of
performance required by the CPU to process secure packet traffic. The
engine includes hardware support for the DES, 3DES, and AES encryption algorithms and the MD5 and SHA1 hash functions. The engine also
supports hardware-assisted packet processing for the various modes of
IPSec, including AH, ESP, and AH+ESP tunnel and transport modes.
Two dedicated DMA channels are used to transfer data to and from the
security engine, allowing the CPU to work on other tasks during this
time.
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RC32365
Revision History
PCI Interface
The PCI interface on the RC32365 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to three external
bus masters, supporting both fixed priority and rotating priority arbitration schemes. The RC32365 can support both satellite and host PCI
configurations, enabling it to act as a slave controller for a PCI add-in
card application, or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32365 device.
PCMCIA Interface
The RC32365 provides a "glueless" connection to a single PCMCIA
I/O device via the memory and peripheral device controller. The
PCMCIA interface allows the RC32365 to connect to various types of I/O
peripherals including fax modems, storage devices, and wireless LAN
chipsets. The RC32365 implementation provides a maximum
throughput of 160 Mbps through the 16-bit wide interface as specified by
the PCMCIA 2.1 Standard.
March 17, 2003: Initial publication.
May 15, 2003: Removed “write protect capability” from features of
the SDRAM Controller.
July 9, 2003: In Table 6, changed values for RSTN (output).
Changed values in Tables 7, 8, 9, 10, and 17.
October 3, 2003: Added 180 MHz speed grade. Changed min
values in Table 7 from 1.8 to 1.2 for all signals except SDCLKINP and
SDCKENP. Changed min values for Tdo 10b and 10c in Table 10 for
PCIBEN, etc. and PCIGNTN/PCIREQN from 2.0 to 1.5.
February 25, 2004: Deleted reference to RNGCLK in Table 1
(GPIO[6]) and Table 22.
May 25, 2004: In Table 9, signals MIIxRXCLK and MIIxTXCLK, the
Min and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
October 5, 2005: Removed 180 MHz speed grade.
Ethernet Interface
The RC32365 has two Ethernet Channels supporting 10Mbps and
100Mbps speeds and provides a standard media independent interface
(MII) off-chip, allowing a wide range of external devices to be connected
efficiently.
Memory and I/O Controller
The RC32365 incorporates a flexible memory and peripheral device
controller providing direct support for SDRAM, Flash ROM, SRAM,
PCMCIA, and other I/O devices. It can interface directly to 8-bit boot
ROM for a very low cost system implementation. It also offers various
trade-offs in cost / performance for the main memory architecture. The
timers implemented on the RC32365 satisfy the requirements of most
real time operating systems.
DMA Controller
The DMA controller off-loads the CPU core from moving data among
the on-chip interfaces, external peripherals, and memory. The DMA
controller supports scatter / gather DMA with no alignment restrictions,
appropriate for communications and graphics systems.
Enhanced JTAG Interface
For system debugging, the RC32300 CPU core includes an
Enhanced JTAG (EJTAG) interface which operates in Run-Time Mode.
Thermal Considerations
The RC32365 is guaranteed in a ambient temperature range of 0° to
+70° C for commercial temperature devices and - 40° to +85° for industrial temperature devices.
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Pin Description Table
The following table lists the functions of the pins provided on the RC32365. Some of the functions listed may be multiplexed onto the same pin
(indicated as alternate functions).
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one
(high) level.
Signal
Type
Name/Description
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction. Memory and peripheral bus external data bus buffer direction control.
If the RC32365 memory and peripheral bus is connected to the A side of a transceiver such as an
IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of
the transceiver.
BOEN[1:0]
O
External Buffer Enable. These signals provide output enable control for external buffers on the
memory and peripheral data bus.
BWEN[3:0]
O
Byte Write Enables. These signals are memory and peripheral bus byte write enable signals.
BWEN[0] corresponds to byte lane MDATA[7:0]
BWEN[1] corresponds to byte lane MDATA[15:8]
BWEN[2] corresponds to byte lane MDATA[23:16]
BWEN[3] corresponds to byte lane MDATA[31:24]
CSN[5:0]
O
Chip Selects. These signals are used to select an external device on the memory and peripheral
bus.
MADDR[21:0]
O
Address Bus. 22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO[5:2] alternate functions.
MDATA[31:0]
I/O
Data Bus. 32-bit memory and peripheral data bus. During a cold reset, bits 0 through 16 of this
data bus function as inputs that are used to load the boot configuration vector.
OEN
O
Output Enable. This signal is asserted when data should be driven by an external device on the
memory and peripheral bus.
RWN
O
Read Write. This signal indicates whether the transaction on the memory and peripheral bus is a
read transaction or a write transaction. A high level indicates a read from an external device. A
low level indicates a write to an external device.
WAITACKN
I
Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer
acknowledge, this signal is asserted during a transaction to signal the completion of the transaction.
RASN
O
SDRAM Row Address Strobe. Row address strobe asserted during memory and peripheral bus
SDRAM transactions.
CASN
O
SDRAM Column Address Strobe. Column address strobe asserted during memory and peripheral bus SDRAM transactions.
SDCSN[1:0]
O
SDRAM Chip Selects. These signals are used to select SDRAM device(s) on the memory and
peripheral bus.
SDWEN
O
SDRAM Write Enable. This signal is asserted during memory and peripheral bus SDRAM write
transactions.
SDCLKOUT
O
SDRAM Clock Output. This clock is used for all SDRAM memory and peripheral bus operations.
SDCLKINP
I
SDRAM Clock Input. This clock input is typically a delayed version of SDCLKOUT. Data from the
SDRAMs is sampled using this clock.
Table 1 Pin Description (Part 1 of 6)
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RC32365
Signal
Type
Name/Description
General Purpose I/O
GPIO[0]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
GPIO[1]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
GPIO[2]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[22]
Alternate function: Memory and Peripheral bus address bit 22 (output).
GPIO[3]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[23]
Alternate function: Memory and Peripheral bus address bit 23 (output).
GPIO[4]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[24]
Alternate function: Memory and Peripheral bus address bit 24 (output).
GPIO[5]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[25]
Alternate function: Memory and Peripheral bus address bit 25 (output).
GPIO[6]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
The value of this pin may be used as a Counter Timer Clock input.
GPIO[7]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: SDCKENP
Alternate function: SDRAM clock enable output
The value of this pin may be used as a Counter Timer Clock input.
GPIO[8]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: CEN1
Alternate function: PCMCIA chip enable 1 (CE1#) (output).
GPIO[9]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: CEN2
Alternate function: PCMCIA chip enable 2 (CE2#) (output).
GPIO[10]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: REGN
Alternate function: PCMCIA Attribute Memory Select (REG#) (output).
GPIO[11]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IORDN
Alternate function: PCMCIA IO Read (IORD#) (output).
GPIO[12]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOWRN
Alternate function: PCMCIA IO Write (IOWR#) (output).
GPIO[13]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCIREQN[2]
Alternate function: PCI bus request 2 (output).
GPIO[14]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCIGNTN[2]
Alternate function: PCI bus grant 2 (output).
Table 1 Pin Description (Part 2 of 6)
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RC32365
Signal
GPIO[15]
Type
Name/Description
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCIMUINTN
Alternate function: PCI Messaging unit interrupt output.
SCK
I/O
Serial Clock. This signal is used as the serial SPI clock output. This pin may be used as a bit
input/output port.
SDI
I/O
Serial Data Input. This signal is used to shift in serial SPI data. This pin may be used as a bit
input/output port.
SDO
I/O
Serial Data Output. This signal is used to shift out serial SPI data. This pin may be used as a bit
input/output port.
PCIAD[31:0]
I/O
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during initial PCIFRAMEN assertion. Data is then driven by the bus master during writes or by the bus target during
reads.
PCICBEN[3:0]
I/O
PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the bus master during
the initial PCIFRAMEN assertion. Byte enables are driven by the bus master during subsequent
data phase(s).
Serial Interface
PCI Bus
PCICLK
I
PCI Clock. Clock used for all PCI bus transactions.
PCIDEVSELN
I/O
PCI Device Select. This signal is driven by a bus target to indicate that the target has decoded
the address as one of its own address spaces.
PCIFRAMEN
I/O
PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus transaction.
Negation indicates the last data.
PCIGNTN[1:0]
I/O
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32365 arbiter has
granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32365 that access to the PCI
bus has been granted.
PCIGNTN[1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: this signal is asserted by an external arbiter to indicate to the RC32365 that access
to the PCI bus has been granted.
PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used as a PCI Serial
EEPROM chip select.
PCIIRDYN
I/O
PCI Initiator Ready. Driven by the bus master to indicate that the current data can complete.
PCILOCKN
I/O
PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring.
PCIPAR
I/O
PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during address and
write data phases. Driven by the bus target during the read data phases.
PCIPERRN
I/O
PCI Parity Error. This signal is asserted by the receiving bus agent 2 clocks after the data is
received if a parity error is detected.
Table 1 Pin Description (Part 3 of 6)
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RC32365
Signal
Type
Name/Description
PCIREQN[1:0]
I/O
PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32365 arbiter that an agent
desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32365 to request ownership of the PCI bus.
PCIREQN[1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32365 to request ownership of the PCI bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during configuration
read and write transactions.
PCIRSTN
I/O
PCI Reset. In host mode, this signal is asserted by the RC32365 to generate a PCI reset. In satellite mode, assertion of this signal initiates a warm reset.
PCISERRN
I/O
PCI System Error. This signal is driven by an agent to indicate an address parity error, data parity error during a special cycle command, or any other system error. Requires an external pull-up.
PCISTOPN
I/O
PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indicate a retry.
PCITRDYN
I/O
PCI Target Ready. Driven by the bus target to indicate that the current data can complete.
Ethernet Interface
MII0CL
I
Ethernet 0 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision
is detected.
MII0CRS
I
Ethernet 0 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.
MII0RXCLK
I
Ethernet 0 MII Receive Clock. This clock is a continuous clock that provides a timing reference
for the reception of data.
MII0RXD[3:0]
I
Ethernet 0 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.
MII0RXDV
I
Ethernet 0 MII Receive Data Valid. The assertion of this signal indicates that valid receive data
is in the MII receive data bus.
MII0RXER
I
Ethernet 0 MII Receive Error. The assertion of this signal indicates that an error was detected
somewhere in the ethernet frame currently being sent in the MII receive data bus.
MII0TXCLK
I
Ethernet 0 MII Transmit Clock. This clock is a continuous clock that provides a timing reference
for the transfer of transmit data.
MII0TXD[3:0]
O
Ethernet 0 MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
MII0TXENP
O
Ethernet 0 MII Transmit Enable. The assertion of this signal indicates that data is present on the
MII for transmission.
MII0TXER
O
Ethernet 0 MII Transmit Coding Error. When this signal is asserted together with MIITXENP,
the ethernet PHY will transmit symbols which are not valid data or delimiters.
MII1CL
I
Ethernet 1 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision
is detected.
MII1CRS
I
Ethernet 1 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.
MII1RXCLK
I
Ethernet 1 MII Receive Clock. This clock is a continuous clock that provides a timing reference
for the reception of data.
Table 1 Pin Description (Part 4 of 6)
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RC32365
Signal
Type
Name/Description
MII1RXD[3:0]
I
Ethernet 1 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.
MII1RXDV
I
Ethernet 1 MII Receive Data Valid. The assertion of this signal indicates that valid receive data
is in the MII receive data bus.
MII1RXER
I
Ethernet 1 MII Receive Error. The assertion of this signal indicates that an error was detected
somewhere in the ethernet frame currently being sent in the MII receive data bus.
MII1TXCLK
I
Ethernet 1 MII Transmit Clock. This clock is a continuous clock that provides a timing reference
for the transfer of transmit data.
MII1TXD[3:0]
O
Ethernet 1 MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
MII1TXENP
O
Ethernet 1 MII Transmit Enable. The assertion of this signal indicates that data is present on the
MII for transmission.
MII1TXER
O
Ethernet 1 MII Transmit Coding Error. When this signal is asserted together with MIITXENP,
the ethernet PHY will transmit symbols which are not valid data or delimiters.
MIIMDC
O
MII Management Data Clock. This signal is used as a timing reference for transmission of data
on the management interface.
MIIMDIO
I/O
MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or
JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected
(since there is an internal pull-up) or driven high.
EJTAG_TMS
I
EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller.
When using the JTAG boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP
Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the system and the processor clock with a nominal 50% duty cycle.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or the
EJTAG Controller.
EJTAG / JTAG
Table 1 Pin Description (Part 5 of 6)
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RC32365
Signal
Type
Name/Description
CLK
I
Master Clock. This is the master clock input. The processor frequency is a multiple of this clock
frequency. This clock is used as the system clock for all memory and peripheral bus operations
except those associated with SDRAMs.
COLDRSTN
I
Cold Reset. The assertion of this signal initiates a cold reset. This causes the processor state to
be initialized, boot configuration to be loaded, and the internal PLL to lock onto the master clock
(CLK).
I/O
Reset. The assertion of this bidirectional signal initiates a warm reset. This signal is asserted by
the RC32365 during a warm reset. It can also be asserted by an external device to force the
RC32365 to take a warm reset exception.
Miscellaneous
RSTN
Table 1 Pin Description (Part 6 of 6)
Pin Characteristics
Pin Name
Memory and Peripheral Bus
BDIRN
BOEN[1:0]
BWEN[3:0]
CSN[5:0]
MADDR[21:0]
MDATA[31:0]
OEN
RWN
WAITACKN
RASN
CASN
SDCSN[1:0]
SDWEN
SDCLKOUT
SDCLKINP
General Purpose I/O
GPIO[15:13]
GPIO[12:0]
Serial Interface
SCK
SDI
SDO
PCI Bus Interface
PCIAD[31:0]
PCICBEN[3:0]
PCICLK
PCIDEVSELN
Internal
Resistor
Type
Buffer
I/O Type
O
O
O
O
O
I/O
O
O
I
O
O
O
O
O
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
High Drive
High Drive
High Drive
High Drive
High Drive
High Drive
High Drive
High Drive
STI2
High Drive
High Drive
High Drive
High Drive
High Drive
STI
I/O
I/O
PCI
LVTTL
PCI
Low Drive
pull-up
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
Low Drive
Low Drive
Low Drive
pull-up
pull-up
pull-up
I/O
I/O
I
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
External
Resistor1
pull-up
pull-up
pull-up on board
pull-up on board
pull-up on board
pull-up on board
Table 2 Pin Characteristics (Part 1 of 2)
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Pin Name
PCIFRAMEN
PCIGNTN[1:0]
PCIIRDYN
PCILOCKN
PCIPAR
PCIPERRN
PCIREQN[1:0]
PCIRSTN
PCISERRN
PCISTOPN
PCITRDYN
Ethernet Interfaces
MII0CL
MII0CRS
MII0RXCLK
MII0RXD[3:0]
MII0RXDV
MII0RXER
MII0TXCLK
MII0TXD[3:0]
MII0TXENP
MII0TXER
MII1CL
MII1CRS
MII1RXCLK
MII1RXD[3:0]
MII1RXDV
MII1RXER
MII1TXCLK
MII1TXD[3:0]
MII1TXENP
MII1TXER
MIIMDC
MIIMDIO
EJTAG / JTAG
JTAG_TMS
EJTAG_TMS
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TDI
Miscellaneous
CLK
COLDRSTN
RSTN
Type
Buffer
I/O Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Open Collector; PCI
PCI
PCI
I
I
I
I
I
I
I
O
O
O
I
I
I
I
I
I
I
O
O
O
O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
STI
STI
STI
STI
STI
STI
STI
Low Drive
Low Drive
Low Drive
STI
STI
STI
STI
STI
STI
STI
Low Drive
Low Drive
Low Drive
Low Drive
Low Drive
I
I
I
I
O
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
STI
STI
STI
STI
Low Drive
STI
I
I
I/O
LVTTL
LVTTL
LVTTL
STI
STI
Low Drive / STI
Internal
Resistor
External
Resistor1
pull-up on board
pull-up on board
pull-up on board
pull-up on board
pull-down on board
pull-up on board
pull-up on board
pull-up on board
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
See Chapters 22 and 23
of the RC32365 User
Reference Manual
pull-up
pull-up
pull-up on board
Table 2 Pin Characteristics (Part 2 of 2)
1.
External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table.
2. Schmidt
Trigger Input (STI).
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Boot Configuration Vector
The boot configuration vector is read into the RC32365 during cold reset. The vector defines parameters in the RC32365 that are essential to operation when cold reset is complete.
The encoding of boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4.
Signal
Name/Description
MDATA[2:0]
CPU Clock Multiplier. This field specifies the value by which the PLL multiplies the master
clock input (CLK) to obtain the processor clock frequency (PCLK).
0x0 - Multiply by 2
0x1 - 0x7 — Reserved
MDATA[3]
Endian. This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
MDATA[4]
Reserved. This pin may be driven high or low during boot configuration and its state is
recorded in the Boot Configuration Vector (BCV) field of the BCV register. This reserved bit
may be used to pass boot configuration parameters to software.
MDATA[6:5]
Boot Device Width. This field specifies the width of the boot device (i.e., Device 0).
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
0x2 - 32-bit boot device width
0x3 - reserved
MDATA[7]
Reset Mode. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles
0x1 - reserved
MDATA[8]
Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold
reset.
0x0 - Watchdog timer is enabled
0x1 - Watchdog timer is disabled
MDATA[11:9]
PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial value of the
EN bit in the PCIC register is determined by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
(EN initial value is zero)
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
(EN initial value is zero)
0x6 - reserved
0x7 - reserved
MDATA[15:12]
Reserved. These pins may be driven high or low during boot configuration and their state is
recorded in the Boot Configuration Vector (BCV) field of the BCV register. These reserved bits
may be used to pass boot configuration parameters to software.
Table 3 Boot Configuration Vector Encoding
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RC32365
Logic Diagram
The following Logic Diagram shows the primary pin functions of the RC32365.
Miscellaneous
Signals
CLK
COLDRSTN
RSTN
2
4
6
22
32
MIIMDC
MIIMDIO
Ethernet
MII0CL
MII0CRS
MII0RXCLK
MII0RXD[3:0]
MII0RXDV
MII0RXER
MII0TXCLK
MII0TXD[3:0]
MII0TXENP
MII0TXER
MII1CL
MII1CRS
MII1RXCLK
MII1RXD[3:0]
MII1RXDV
MII1RXER
MII1TXCLK
MII1TXD[3:0]
MII1TXENP
MII1TXER
PCI Bus
PCIAD[31:0]
PCICBEN[3:0]
PCICLK
PCIDEVSELN
PCIFRAMEN
PCIGNTN[1:0]
PCIIRDYN
PCILOCKN
PCIPAR
PCIPERRN
PCIREQN[1:0]
PCIRSTN
PCISERRN
PCISTOPN
PCITRDYN
2
4
BDIRN
BOEN[1:0]
BWEN[3:0]
CSN[5:0]
MADDR[21:0]
MDATA[31:0]
OEN
RWN
WAITACKN
RASN
CASN
SDCSN[1:0]
SDWEN
SDCLKOUT
SDCLKINP
Memory
and
Peripheral
Bus
4
RC32365
4
JTAG_TMS
EJTAG_TMS
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TDI
EJTAG / JTAG
Signals
GPIO[15:0]
General Purpose
I/O
4
16
32
4
SDO
SDI
SCK
Serial I/O
2
VccCore
VccI/O
Vss
VccPLL
VssPLL
2
Power/Ground
Figure 1 RC32365 Logic Diagram
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RC32365
AC Timing Definitions
Below are examples of the AC timing characteristics used throughout this document.
Tlow
Tper
Thigh
clock
Tdo
Tdo
Tzd
Tdz
Tjitter
Trise
Tfall
Output signal 1
Output signal 2
Tsu
Thld
Input Signal 1
Tpw
Signal 1
Signal 2
Tskew
Signal 3
Figure 2 AC Timing Definitions Waveform
Symbol
Definition
Tper
Clock period.
Tlow
Clock low. Amount of time the clock is low in one clock period.
Thigh
Clock high. Amount of time the clock is high in one clock period.
Trise
Rise time. Low to high transition time.
Tfall
Fall time. High to low transition time.
Tjitter
Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges.
Tdo
Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold.
The maximum time represents the earliest time the designer can use the data.
Tzd
Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid.
Tdz
Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated.
Tsu
Input set-up. Amount of time before the reference clock edge that the input must be valid.
Thld
Input hold. Amount of time after the reference clock edge that the input must remain valid.
Tpw
Pulse width. Amount of time the input or output is active for asynchronous signals.
Tslew
Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high.
X(clock)
Timing value. This notation represents a value of ‘X’ multiplied by the clock time period of the specified clock. Using 5(CLK) as an example:
X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200.
Tskew
Skew. The amount of time two signal edges deviate from one another.
Table 4 AC Timing Definitions
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Clock Parameters
15.
The values given below are based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 14 and
Parameter
Symbol
150MHz
Reference
Edge
Min
Max
Units
Timing
Diagram
Reference
See Figure 3
PCLK1
Frequency
none
100
150
MHz
CLK2,3
Frequency
none
50
75
MHz
Tper_5a
13.3
20
ns
Thigh_5a,
Tlow_5a
40
60
% of
Tper_5a
Trise_5a,
Tfall_5a
—
3.0
ns
Tjitter_5a
—
± 250
ps
Table 5 RC32365 Clock Parameters
1.
The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3).
2. Ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must
3.
be less than or equal to 1/2 CLK frequency.
PCI clock (PCICLK) frequency must be less than or equal to two times CLK.
Thigh_5a
Tper_5a
Tlow_5a
CLK
Tjitter_5a
Tjitter_5a
Trise_5a
Tfall_5a
Figure 3 Clock Parameters Waveform
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AC Timing Characteristics
The values given below are based on systems running at recommended operating supply voltages and temperatures as shown in Tables 14 and
15.
Signal
150MHz
Symbol
Reference
Edge
Min
Max
Tpw_6a1
none
110
Unit
Conditions
—
ms
Cold reset
—
5.0
ns
Cold reset
CLK rising
2.0
9.0
ns
Cold reset
none
2(CLK)
—
ns
Cold reset
COLDRSTN
rising
3.0
—
ns
Cold reset
Timing
Diagram
Reference
Reset and System
COLDRSTN
Trise_6a
2
Tdo_6b
RSTN2
1
RSTN (output)
(input)
MDATA[15:0]
Boot Configuration
Vector
Tpw_6c
Thld_6d
Tdz_6d1
COLDRSTN
falling
—
2(CLK)
ns
Cold reset
Tdz_6d1
RSTN falling
—
2(CLK)
ns
Warm reset
Tzd_6d1
RSTN rising
3.0
—
ns
Warm reset
See Figures 4
and 5
Table 6 Reset and System AC Timing Characteristics
1.
The values for this symbol were determined by calculation, not by testing.
2.
RSTN is a bidirectional signal. It is treated as an asynchronous input.
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RC32365
2
1
3
4
5
6
7
8
CLK
SDCLKOUT
Trise_6a
COLDRSTN
Thld_6d
Tdo_6b
RSTN
Tdz_6d
FFFF_FFFF
BOOT VECTOR
MDATA[31:0]
BDIRN
BOEN[1:0]
>= 100 ms
>=10ms
>= 4096 CLK clock cycles
>= 4096 CLK clock cycles
(RSTN sampled)
(RSTN ignored during this period
to allow pull-up to drive signal high)
Tpw_6a
1.
COLDRSTN asserted by external logic.
2.
RC32365 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response.
3.
External logic begins driving valid boot configuration vector on the data bus, and the RC32365 starts sampling it.
4.
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deasserted. The RC32365 stops sampling the boot configuration vector.
5.
The RC32365 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high.
6.
SYSCLK may be held constant after this point if Hold SYSCLK Constant is selected in the boot configuration vector.
7.
RSTN negated by the RC32365.
8.
CPU begins executing by taking MIPS reset exception, and the RC32365 starts sampling RSTN as a warm reset input.
Figure 4 Cold Reset AC Timing Waveform
1
2
3
4
5
CLK
COLDRSTN
Tdz_6d
Tzd_6d
RSTN
FFFF_FFFF
MDATA[31:0]
Mem Control Signals
Active
Deasserted
>= 4096 CLK clock cycles
Active
>= 4096 CLK clock cycles
(RSTN sampled)
(RSTN ignored during this period
to allow pull-up to drive signal high)
1.
Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32365 asserts RSTN output low in response.
2.
The RC32365 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc.
3.
The RC32365 deasserts RSTN.
4.
The RC32365 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input.
5.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
Figure 5 Warm Reset AC Timing Waveform
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Signal
Symbol
Reference
Edge
150MHz
Unit
Min
Max
1.0
—
ns
1.7
—
ns
1.2
6.0
ns
1.2
7.0
ns
1.2
8.0
ns
Conditions
Timing
Diagram
Reference
Memory and Peripheral Bus - SDRAM Access
MDATA[31:0]
Tsu_7a
Thld_7a
Tdo_7a
1
Tdz_7a
SDCLKINP
rising
SDCLKOUT
rising
Tzd_7a1
MADDR[20:2]
Tdo_7b
SDCLKOUT
rising
1.2
6.0
ns
RASN
Tdo_7c
SDCLKOUT
rising
1.2
6.0
ns
CASN
Tdo_7d
SDCLKOUT
rising
1.2
6.0
ns
SDWEN
Tdo_7e
SDCLKOUT
rising
1.2
6.0
ns
SDCSN[1:0]
Tdo_7f
SDCLKOUT
rising
1.2
6.0
ns
BDIRN
Tdo_7g
SDCLKOUT
rising
1.2
6.0
ns
BOEN[1:0]
Tdo_7h
SDCLKOUT
rising
1.2
6.0
ns
BWEN[3:0]
Tdo_7i
SDCLKOUT
rising
1.2
6.0
ns
SDCLKINP
Tdelay_7k
SDCLKOUT
rising
0.0
2.5
ns
SDCKENP
Tdo_7l
SDCLKOUT
rising
2.0
6.0
ns
See Figures 6
and 7
See Figures 6
and 8
Table 7 Memory and Peripheral Bus AC Timing Characteristics
1. The
values for this symbol were determined by calculation, not by testing.
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CLK
SDCLKOUT
Tdo_7b
MADDR[21:0]
SDRAM CAS Latency
Tdelay_7k
Addr
Tdo_7i
BWEN[3:0]
1111
BE's
1111
Tdo_7c, 7d, and 7e
CMD[2:0]*
NOP
READ
NOP
Tdo_7f
SDCSN[1:0]
11
Chip-Sel
11
Tdo_7g
Tdo_7g
BDIRN
Tdo_7h
BOEN[1:0]
11
Tdo_7h
Buffer Enables
Tdz_7a
11
Tsu_7a Thld_7a
Tzd_7a
Data
MDATA[31:0]
RC32365
samples
read data
SDCLKINP
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}
Figure 6 Memory and Peripheral Bus AC Timing Waveform - SDRAM Read Access
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CLK
SDCLKOUT
SDRAM
samples
write data
Tdo_7b
Addr
MADDR[21:0]
Tdo_7i
BWEN[3:0]
1111
BE's
1111
Tdo_7c, 7d, and 7e
CMD[2:0]*
NOP
SDCSN[1:0]
11
WRITE
NOP
Chip-Sel
11
Tdo_7f
Tdo_7g
BDIRN
Tdo_7h
BOEN[1:0]
11
Buff Enable
11
Tdo_7a
MDATA[31:0]
Data
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}
Figure 7 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access
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RC32365
Vcc
pull-up
SDCLKOUT
RSTN
Tdelay_7k
COLDRSTN
RC32365
CLK
SDCLKINP
Memory Bus
external
buffer
SRAM,
SDRAM
EPROM,
etc.
Figure 8 SDCLKOUT - SDCLKINP Relationship
Signal
Symbol
Reference
Edge
150MHz
Unit
Min
Max
2.5
—
ns
Thld_8a
1.0
—
ns
Tdo_8a
2.0
6.5
ns
Tdz_8a2
2.0
9.5
ns
Tzd_8a2
2.0
10.5
ns
Conditions
Timing
Diagram
Reference
Memory and Peripheral Bus1 — Device Access
MDATA[31:0]
Tsu_8a
CLK rising
MADDR[21:0]
Tdo_8b
CLK rising
2.0
6.5
ns
MADDR[25:22]
Tdo_8c
CLK rising
3.0
7.5
ns
CSN[5:0]
Tdo_8d
CLK rising
2.0
6.5
ns
RWN
Tdo_8e
CLK rising
2.0
6.5
ns
OEN
Tdo_8f
CLK rising
2.0
6.5
ns
BWEN[1:0]
Tdo_8g
CLK rising
2.0
6.5
ns
BDIRN
Tdo_8h
CLK rising
2.0
6.5
ns
BOEN[1:0]
Tdo_8i
CLK rising
2.0
6.5
ns
WAITACKN3
Tsu_8j
CLK rising
2.0
—
ns
0.5
—
ns
2(CLK)
—
ns
Thld_8j
Tpw_8j2
none
See Figures 9
and 10
Table 8 Memory and Peripheral Bus AC Timing Characteristics — Device Access (Part 1 of 2)
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RC32365
150MHz
Symbol
Reference
Edge
Min
Max
CEN14, CEN24
Tdo_8k
CLK rising
3.0
7.5
ns
4
REGN
Tdo_8l
CLK rising
3.0
7.5
ns
IORDN4
Tdo_8m
CLK rising
3.0
7.5
ns
IOWRN4
Tdo_8n
CLK rising
3.0
7.5
ns
Signal
Unit
Conditions
Timing
Diagram
Reference
See Figures 9
and 10 (cont.)
Table 8 Memory and Peripheral Bus AC Timing Characteristics — Device Access (Part 2 of 2)
1. The RC32365 provides bus turnaround cycles to prevent bus contention when going from a read to write and write to read. For example,
there are no cycles where an external device and the RC32365 are both driving. See Chapter 6, Device Controller, in the RC32365
User Reference Manual.
2. The values
for this symbol were determined by calculation, not by testing.
3.
WAITACKN must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous.
4.
CEN1, CEN2, REGN, IORDN, and IOWRN are alternate functions of GPIO[12:8].
CLK
Tdo_8b
Addr[21:0]
MADDR[21:0]
Tdo_8c
MADDR[25:22]
Addr[25:22]
RWN
Tdo_8d
Tdo_8d
CSN[5:0]
1111
BWEN[3:0]
Tdo_8f
Tdo_8f
OEN
Thld_8a
Tsu_8a
Tdz_8a
Tzd_8a
Data
MDATA[31:0]
RC32365
samples
read data
Tdo_8h
BDIRN
Tdo_8i
Tdo_8h
Tdo_8i
BOEN[1:0]
WAITACKN
Figure 9 Memory and Peripheral Bus AC Timing Waveform - Device Read Access
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CLK
Tdo_8b
Addr[21:0]
MADDR[21:0]
Tdo_8c
Addr[25:22]
MADDR[25:22]
Tdo_8e
RWN
Tdo_8d
CSN[5:0]
Tdo_8g
BWEN[3:0]
1111
Byte Enables
1111
OEN
Tdo_8a
Data
MDATA[31:0]
BDIRN
Tdo_8i
BOEN[1:0]
WAITACKN
Figure 10 Memory AC and Peripheral Bus Timing Waveform - Device Write Access
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Signal
150MHz
Symbol
Reference
Edge
Min
Max
Tper_9a
None
53.3
—
ns
23.0
—
ns
10.0
—
ns
1.0
—
ns
Unit
Conditions
Timing
Diagram
Reference
Ethernet1
MIIMDC
Thigh_9a,
Tlow_9a
MIIMDIO
Tsu_9b
MIIMDC rising
Thld_9b
Tdo_9b
MIIxRXCLK, MIIxTXCLK2
MIIxRXCLK,
MIIxTXCLK2
MIIxRXD[3:0],
MIIxRXDV, MIIxRXER
MIIxTXD[3:0],
MIIxTXENP, MIIxTXER
1(ICLK) 3(ICLK)
ns
399.96
400.4
ns
Thigh_9c,
Tlow_9c
140
260
ns
Trise_9c,
Tfall_9c
—
3.0
ns
39.9
40.0
ns
Thigh_9d,
Tlow_9d
14.0
26.0
ns
Trise_9d,
Tfall_9d
—
2.0
ns
MIIxRXCLK
rising
3.0
—
ns
2.0
—
ns
MIIxTXCLK
rising
5.0
13
ns
Tper_9c
Tper_9d
Tsu_9e
Thld_9e
Tdo_9f
None
None
See Figure 11
10 Mbps
100 Mbps
Table 9 Ethernet AC Timing Characteristics
1.
There are two MII interfaces and the timing is the same for each. “x” represents interface 0 or 1 (For example, MIIxRXCLK can be
either MII0RXCLK or MII1RXCLK).
2.
The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 CLK (MIIxRXCLK and MIIxTXCLK 0.6(VccI/O)
+26.7(VOUT)
mA
0.6(VccI/O) > VOUT > 0.1(VccI/O)
LOW Drive
Output with
Schmitt Trigger
Input (STI)
HIGH Drive
Output with
Standard Input
Clock Drive
Output
PCI
IOL(AC) Switching
—
+38(VccI/O)
mA
VOUT = 0.18(VccI/O)
VIL
-0.3
0.3(VccI/O)
V
—
VIH
0.5(VccI/O)
5.5
V
—
CIN
—
10
pF
—
I/OLEAK
—
20
μA
—
Capacitance
Leakage
Table 16 DC Electrical Characteristics
Power Consumption
Parameter
Power
Dissipation
Unit
Typical
Max.
60
80
mA
Normal mode
710
750
mA
Standby mode1
620
660
mA
Normal mode
2.07
2.2
W
Standby mode1
1.8
2.0
W
IccI/O
IccCore
150MHz
Conditions
CL = 25pF (affects I/O)
Ta = 25oC
Maximum values use the maximum
voltages listed in Table 14.
Typical values use the typical voltages
listed in Table 14.
Table 17 RC32365 Power Consumption
1. RISCore 32300 CPU core enters Standby mode by executing WAIT instructions; however, other logic continues to function.
Standby mode reduces power consumption by 0.6 mA per MHz of the CPU pipeline clock, PCLK.
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RC32365
Power Curve
The following graph contains a power curve that shows power consumption at various bus frequencies.
Typical Power Curve
Power (W @ 3.3v IO & 2.5v core)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
70
75
80
85
90
95
100
System Bus Speed (MHz)
Figure 25 Typical Power Usage
Absolute Maximum Ratings
Symbol
Parameter
Min1
Max1
Unit
VCCI/O
I/O Supply Voltage
-0.6
4.0
V
VCCCore
Core Supply Voltage
-0.3
3.0
V
VCCPLL
PLL Supply Voltage
-0.3
3.0
V
Vimin
Input Voltage - undershoot
-0.6
—
V
Vi
I/O Input Voltage
Gnd
VCCI/O+0.6
V
Ta,
Industrial
Ambient Operating
Temperature
-40
+85
°C
Ta,
Commercial
Ambient Operating
Temperature
0
+70
°C
Tstg
Storage Temperature
-40
+125
°C
Table 18 Absolute Maximum Ratings
1.
Functional and tested operating conditions are given in Table 14. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
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October 5, 2005
RC32365
Package Pin-out — 256-Pin CABGA
The following table lists the pin numbers and signal names for the RC32365.
Pin
Function
Alt
Pin
Function
A1
MII0RXD[0]
E1
GPIO[15]
A2
MII0RXDV
E2
A3
MII0RXER
A4
Alt
1
Pin
Function
Alt
Pin
Function
J1
PCIGNTN[1]
N1
PCIAD[4]
JTAG_TRST_N
J2
PCIDEVSELN
N2
PCIAD[20]
E3
JTAG_TDO
J3
PCIGNTN[0]
N3
PCIAD[19]
MII0TXCLK
E4
JTAG_TDI
J4
PCIFRAMEN
N4
PCIAD[11]
A5
MII0TXD[2]
E5
VccCORE
J5
VccI/O
N5
PCIAD[13]
A6
MII0CRS
E6
VccI/O
J6
Vss
N6
PCIAD[15]
A7
VssPLL
E7
VccI/O
J7
Vss
N7
BOEN[0]
A8
MII1RXCLK
E8
VccI/O
J8
Vss
N8
CSN[2]
A9
MII1TXD[2]
E9
VccI/O
J9
Vss
N9
CSN[3]
A10
MII1CL
E10
VccI/O
J10
Vss
N10
RWN
A11
JTAG_TCK
E11
VccI/O
J11
Vss
N11
MDATA[1]
A12
GPIO[9]
1
E12
VccCORE
J12
VccI/O
N12
MDATA[3]
A13
GPIO[5]
1
E13
MADDR[5]
J13
SDWEN
N13
MDATA[12]
A14
GPIO[3]
1
E14
MADDR[16]
J14
SDCLKINP
N14
MDATA[30]
A15
GPIO[1]
1
E15
MADDR[17]
J15
BWEN[2]
N15
MDATA[11]
A16
MADDR[10]
E16
MADDR[6]
J16
BWEN[3]
N16
MDATA[27]
B1
MII0RXD[3]
F1
GPIO[14]
1
K1
PCICBEN[1]
P1
PCIAD[5]
B2
MII0RXD[1]
F2
GPIO[13]
1
K2
PCICBEN[2]
P2
PCIAD[21]
B3
MII0RXCLK
F3
PCITRDYN
K3
PCICBEN[0]
P3
PCIAD[23]
B4
MII0TXER
F4
PCISTOPN
K4
PCICLK
P4
PCIAD[10]
B5
MII0TXD[3]
F5
VccCORE
K5
VccI/O
P5
PCIAD[28]
B6
MII0CL
F6
VccI/O
K6
Vss
P6
PCIAD[30]
B7
VccPLL
F7
Vss
K7
Vss
P7
BDIRN
B8
MII1RXDV
F8
Vss
K8
Vss
P8
CSN[1]
B9
MII1TXD[3]
F9
Vss
K9
Vss
P9
CSN[4]
B10
MII1CRS
F10
Vss
K10
Vss
P10
WAITACKN
B11
GPIO[12]
1
F11
VccI/O
K11
Vss
P11
MDATA[17]
B12
GPIO[8]
1
F12
VccCORE
K12
VccCORE
P12
MDATA[19]
B13
GPIO[4]
1
F13
MADDR[3]
K13
BWEN[1]
P13
MDATA[5]
B14
GPIO[2]
1
F14
MADDR[14]
K14
RASN
P14
MDATA[9]
B15
MADDR[21]
F15
MADDR[15]
K15
CASN
P15
MDATA[10]
B16
MADDR[20]
F16
MADDR[4]
K16
BWEN[0]
P16
MDATA[26]
C1
MIIMDC
G1
PCIRSTN
L1
PCIAD[16]
R1
PCIAD[6]
C2
MIIMDIO
G2
PCISERRN
L2
PCIAD[1]
R2
PCIAD[7]
Alt
Table 19: 256-pin CABGA Package Pin-Out (Part 1 of 2)
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October 5, 2005
RC32365
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
C3
MII0RXD[2]
G3
PCIPERRN
L3
PCIAD[0]
R3
PCIAD[24]
C4
MII0TXENP
G4
PCIREQN[0]
L4
PCICBEN[3]
R4
PCIAD[25]
C5
MII0TXD[1]
G5
VccCORE
L5
VccCORE
R5
PCIAD[27]
C6
MII1RXD[3]
G6
Vss
L6
VccI/O
R6
PCIAD[29]
C7
MII1RXD[0]
G7
Vss
L7
Vss
R7
PCIAD[31]
C8
MII1RXER
G8
Vss
L8
Vss
R8
BOEN[1]
C9
MII1TXENP
G9
Vss
L9
Vss
R9
OEN
C10
MII1TXD[0]
G10
Vss
L10
Vss
R10
MDATA[16]
C11
EJTAG_TMS
G11
Vss
L11
VccI/O
R11
MDATA[18]
C12
GPIO[10]
1
G12
VccI/O
L12
VccCORE
R12
MDATA[20]
C13
GPIO[6]
1
G13
MADDR[1]
L13
CLK
R13
MDATA[21]
C14
GPIO[0]
1
G14
MADDR[12]
L14
SDCLKOUT
R14
MDATA[7]
C15
MADDR[9]
G15
MADDR[13]
L15
MDATA[15]
R15
MDATA[24]
C16
MADDR[19]
G16
MADDR[2]
L16
MDATA[31]
R16
MDATA[25]
D1
SDI
H1
PCIPAR
M1
PCIAD[18]
T1
PCIAD[22]
D2
COLDRSTN
H2
PCIREQN[1]
M2
PCIAD[3]
T2
PCIAD[8]
D3
SDO
H3
PCILOCKN
M3
PCIAD[2]
T3
PCIAD[9]
D4
SCK
H4
PCIRDYN
M4
PCIAD[17]
T4
PCIAD[26]
D5
MII0TXD[0]
H5
VccI/O
M5
VccCORE
T5
PCIAD[12]
D6
MII1RXD[2]
H6
Vss
M6
VccI/O
T6
PCIAD[14]
D7
MII1RXD[1]
H7
Vss
M7
VccI/O
T7
RSTN
D8
MII1TXER
H8
Vss
M8
VccI/O
T8
CSN[0]
D9
MII1TXCLK
H9
Vss
M9
VccI/O
T9
CSN[5]
D10
MII1TXD[1]
H10
Vss
M10
VccI/O
T10
MDATA[0]
D11
JTAG_TMS
H11
Vss
M11
VccI/O
T11
MDATA[2]
D12
GPIO[11]
1
H12
VccI/O
M12
VccCORE
T12
MDATA[4]
D13
GPIO[7]
1
H13
SDCSN[0]
M13
MDATA[14]
T13
MDATA[6]
D14
MADDR[7]
H14
SDCSN[1]
M14
MDATA[13]
T14
MDATA[22]
D15
MADDR[18]
H15
MADDR[11]
M15
MDATA[28]
T15
MDATA[23]
D16
MADDR[8]
H16
MADDR[0]
M16
MDATA[29]
T16
MDATA[8]
Alt
Table 19: 256-pin CABGA Package Pin-Out (Part 2 of 2)
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October 5, 2005
RC32365
RC32365 Power Pins
VccI/O
VccI/O
VccCore
VccPLL
E6
J5
E5
B7
E7
J12
E12
E8
K5
F5
E9
L6
F12
E10
L11
G5
E11
M6
K12
F6
M7
L5
F11
M8
L12
G12
M9
M5
H5
M10
M12
H12
M11
Table 20 RC32365 Power Pins
RC32365 Ground Pins
Vss
Vss
Vss
VssPLL
F7
H7
K6
A7
F8
H8
K7
F9
H9
K8
F10
H10
K9
G6
H11
K10
G7
J6
K11
G8
J7
L7
G9
J8
L8
G10
J9
L9
G11
J10
L10
H6
J11
Table 21 RC32365 Ground Pins
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October 5, 2005
RC32365
Alternate Pin Functions
Pin
Primary
Alt #1
C14
GPIO[0]
U0SOUT
A15
GPIO[1]
U0SINP
B14
GPIO[2]
MADDR[22]
A14
GPIO[3]
MADDR[23]
B13
GPIO[4]
MADDR[24]
A13
GPIO[5]
MADDR[25]
C13
GPIO[6]
N/A
D13
GPIO[7]
SDCKENP
B12
GPIO[8]
CEN1
A12
GPIO[9]
CEN2
C12
GPIO[10]
REGN
D12
GPIO[11]
IORDN
B11
GPIO[12]
IOWRN
F2
GPIO[13]
PCIREQN[2]
F1
GPIO[14]
PCIGNTN[2]
E1
GPIO[15]
PCIMUNITN
Table 22 Alternate Pin Functions
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October 5, 2005
RC32365
RC32365 Pinout — Top View
1
2
3
A
4
5
6
7
8
9
10
11
12
13
14
15
16
VssPLL
B
VccPLL
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Vss (Ground)
VccI/O (Power)
VccCore (Power)
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October 5, 2005
RC32365
Package Drawing - 256-pin CABGA
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October 5, 2005
RC32365
Package Drawing - page two
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October 5, 2005
RC32365
Ordering Information
79RCXX
Product
Type
YY
Operating
Voltage
XXXX
999
Device
Type
Speed
A
A
Package
Temp range/
Process
Blank
Commercial Temperature
(0°C to +70°C Ambient)
I
Industrial Temperature
(-40° C to +85° C Ambient)
BC
BCG
256-pin CABGA
256-pin Green CABGA
150
150 MHz Pipeline Clk
365
Integrated Core Processor
T
2.5V +/-5% Core Voltage
79RC32
32-bit Embedded
Microprocessor
Valid Combinations
79RC32T365 - 150BC
256-pin CABGA package, Commercial Temperature
79RC32T365 - 150BCG
256-pin CABGA package, Commercial Temperature (Green)
79RC32T365 - 150BCI
256-pin CABGA package, Industrial Temperature
79RC32T365 - 150BCGI
256-pin CABGA package, Industrial Temperature (Green)
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
44 of 44
for Tech Support:
email: rischelp@idt.com
phone: 408-284-8208
October 5, 2005
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