IDTCV126PAG

IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR DESCRIPTION: FEATURES: • • • • • • • • • IDTCV126 IDTCV126 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU, SRC/PCI, and 48MHz IO clocks. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU and SRC/ PCI has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. One high precision PLL for CPU, SSC, and N programming One high precision PLL for SRC/PCI, SSC, and N programming One high precision PLL for 48MHz Band-gap circuit for differential outputs Support spread spectrum modulation, down spread 0.5% and others Support SMBus block read/write, index read/write Selectable output strength for REF, 48MHz, PCI Allows for CPU frequency to change to a higher frequency for maximum system computing power Available in SSOP and TSSOP packages OUTPUTS: • • • • • 4*0.7V current –mode differential CPU CLK pair 5*0.7V current –mode differential SRC CLK pair 7*PCI, 3 free running, 33.3MHz 1*48MHz 2*REF KEY SPECIFICATIONS: • CPU/SRC CLK cycle to cycle jitter < 50ps • PCI CLK cycle to cycle jitter < 500ps FUNCTIONAL BLOCK DIAGRAM PLL1 SSC N Programmable XTAL_IN CPU CLK Output Buffers Stop Logic XTAL Osc Amp CPU[3:0] IREF REF[1:0] XTAL_OUT SDATA SCLK SM Bus Controller SRC CLK Output Buffer Stop Logic PLL2 SSC N Programmable SRC[4:0] PCI[3:0], PCIF[2:0] IREF VTT_PWRGD#/PD Control Logic FSA.B.C 48MHz Output BUffer PLL3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 48MHz JUNE 22, 2006 1 © 2005 Integrated Device Technology, Inc. DSC 6581/9 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD_PCI 1 56 FSC/TEST_SEL VSS_PCI 2 55 REF0 PCI0 3 54 REF1 PCI1 4 53 VDD_REF PCI2 5 52 XTAL_IN PCI3 6 51 XTAL_OUT VSS_PCI 7 50 VSS_REF VDD_PCI 8 49 FSB/TEST_MODE PCIF0 9 48 FSA PCIF1 10 47 VDD_CPU PCIF2 11 46 CPU0 VDD_48MHz 12 45 CPU0# 48MHz 13 44 VDD_CPU VSS_48MHz 14 43 CPU1 VDD_SRC 15 42 CPU1# SRC0 16 41 VSS_CPU SRC0# 17 40 CPU2 SRC1# 18 39 CPU2# SRC1 19 38 VDD_CPU VSS_SRC 20 37 CPU3 SRC2 21 36 CPU3# SRC2# 22 35 VDDA SRC3# 23 34 VSSA SRC3 24 33 IREF VDD_SRC 25 32 NC SRC4 26 31 VTT_PWRGD#/PWRDWN SRC4# 27 30 SDA VDD_SRC 28 29 SCL Min 3.3V Core Supply Voltage VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 TSTG Storage Temperature TAMBIENT Ambient Operating Temperature TCASE Case Temperature ESD Prot Input ESD Protection –65 0 Max Unit 4.6 V 4.6 V +150 °C +70 °C +115 °C 2000 V Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN DESCRIPTION Pin# Pin Name 52 XTAL_IN 51 XTAL_OUT 54, 55 REF[1:0] 3-6 PCI[3:0] 9-11 PCIF[2:0] 13 USB48 36,37,39 CPU[3:0] 40,42,43 CPU#[3:0] 45, 46 16-19, SRC[4:0] 21-24, SRC#[4:0] 26, 27 49 FSB/TEST_MODE SSOP/ TSSOP TOP VIEW CPU AND SRC SPREAD SPECTRUM MAGNITUDE CONTROL SMC[2:0] 000 001 010 011 100 101 110 111 Description VDDA % - 0.25 - 0.5 - 0.75 -1 ±0.125 ±0.25 ±0.375 ±0.5 2 Type I O O O O O O Description 14.318 XTAL input 14.318 XTAL output 14.318 MHz 33.33MHz PCI clock 33.33MHz PCI free running clock 48MHz CPU differential clock O SRC differential clock I Frequency select. When in test mode, 0 = clock Hi-Z, 1 = clk REF/N Frequency select. Select test mode if pulled to 2V and above when VTT_PWRGD# assertion. Frequency select, sampled on VTT_PWRGD# assertion. Reference current for differential outputs 3.3V LVTTL input, a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL inputs. After VTT_PWRGD# assertion, becomes a realtime input for asserting power down (active HIGH). SMBus data SMBus clock 56 FSC/TEST_SEL I 48 FSA I 33 31 IREF VTT_PWRGD#/PD I I 30 29 SDA SCL I/O I IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE FSC, B, A CPU SRC[7:1] PCI USB REF 101 100 100 33.3 48 14.318 001 133 100 33.3 48 14.318 011 166 100 33.3 48 14.318 010 200 100 33.3 48 14.318 000 266 100 33.3 48 14.318 100 333 100 33.3 48 14.318 110 400 100 33.3 48 14.318 111 Reserved 100 33.3 48 14.318 RESOLUTION CPU (MHz) 100 133 166 200 266 333 400 SE SIGNAL STRENGTH SELECTION Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150 Str[1:0] 00 01 10 11 Strength 0.6x 0.8x 1x 1.2x INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master INDEX BYTE READ INDEX BYTE WRITE Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 0Eh Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. Setting bit[11:18] = starting address, bit[20:27] = 01h. 3 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 SRCT0, SRCC0 Output Enable Tristate Enable RW 1 1 SRCT1, SRCC1 Output Enable Tristate Enable RW 1 2 SRCT2, SRCC2 Output Enable Tristate Enable RW 1 3 SRCT3, SRCC3 Output Enable Tristate Enable RW 1 4 SRCT4, SRCC4 Output Enable Tristate Enable RW 1 5 Reserved RW 1 6 Reserved RW 1 7 Reserved RW 1 BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 Spread Spectrum Enable Spread Spectrum mode enable Spread off Spread on RW 0 1 CPUT0, CPUC0 Output Enable Tristate Enable RW 1 2 CPUT1, CPUC1 Output Enable Tristate Enable RW 1 3 Reserved RW 1 4 CPUT2, CPUC2 Output Enable Tristate Enable RW 1 5 CPUT3, CPUC3 Output Enable Tristate Enable RW 1 6 REF0 Output Enable Tristate Enable RW 1 7 REF1 Output Enable Tristate Enable RW 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 USB_48 Output Enable Disable Enable RW 1 1 PCIF0 Output Enable Disable Enable RW 1 2 PCIF1 Output Enable Disable Enable RW 1 3 PCIF2 Output Enable Disable Enable RW 1 4 PCI0 Output Enable Disable Enable RW 1 5 PCI1 Output Enable Disable Enable RW 1 6 PCI2 Output Enable Disable Enable RW 1 7 PCI3 Output Enable Disable Enable RW 1 BYTE 2 4 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 3 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 SRCT0, SRCC0 SRCT1, SRCC1 SRCT2, SRCC2 SRCT3, SRCC3 SRCT4, SRCC4 PCIF0 PCIF1 PCIF2 Allow controlled by software PCI_STOP# assertion Bit Output(s) Affected Description / Function 0 CPUT0, CPUC0 Allow control of CPU_0 with assertion of CPU_STOP# 1 CPUT1, CPUC1 Allow control of CPU_1 with assertion of CPU_STOP# 2 CPUT2, CPUC2 3 CPUT3, CPUC3 4 5 6 7 CPUT0, CPUT1, CPUT2, CPUT3, 0 1 Type Power On Free running, not affected by PCI_STOP# Stopped with PCI_STOP# RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 1 Type Power On RW 1 RW 1 Allow control of CPU_2 with assertion of CPU_STOP# RW 1 Allow control of CPU_3 with assertion of CPU_STOP# RW 1 RW RW RW RW 0 0 0 0 BYTE 4 CPUC0 CPUC1 CPUC2 CPUC3 Free running, not stopped by CPU_STOP# CPU PWRDWN Mode Driven in power down Stopped with CPU_STOP# Tristate in power down BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 CPUT0 CPU0 CPU_Stop drive mode Driven in CPU_Stop Tristate in CPU_Stop RW 0 1 CPUT1 CPU1 CPU_Stop drive mode Driven in CPU_Stop Tristate in CPU_Stop RW 0 2 CPUT2 CPU2 CPU_Stop drive mode Driven in CPU_Stop Tristate in CPU_Stop RW 0 3 CPUT3 CPU3 CPU_Stop drive mode Driven in CPU_Stop Tristate in CPU_Stop 4 Reserved 5 SRC SRC Pwrdwn drive mode Driven in power down Tristate in power down RW 0 6 SRC PCI_STOP drive mode Driven in PCI_Stop Tristate in power down RW 0 7 Reserved RW 0 5 RW 0 RW 0 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 6 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 FSA latched value on power up R FSA 1 FSB latched value on power up R FSB 2 FSC latched value on power up R FSC RW 1 RW 1 RW 1 RW 0 3 Software PCI_STOP 4 REFstr1 5 Reserved 6 Stop all PCI/F and SRC except PCIF[2:0], and SRC clocks set to free running No stop REF drive strength, works with Byte 12, Bit 2 (see Str table) Test mode entry control Normal operation Test mode, controlled by Byte 6, Bit 7 7 Only valid when Byte 6, Bit 6 is HIGH Hi-Z REF/N RW 0 Description / Function 0 1 Type Power On BYTE 7 Bit Output(s) Affected 0 Vendor ID R 1 1 Vendor ID R 0 2 Vendor ID R 1 3 Vendor ID R 0 4 Revision ID R 0 5 Revision ID R 0 6 Revision ID R 0 7 Revision ID R 0 Type Power On BYTE 8 (BLOCK READ BYTE COUNT) Bit Output(s) Affected Description / Function 0 0 1 2 3 4 5 6 7 1 0 1 1 1 0 0 0 0 6 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 9 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 SRC SMC0 SRC SMC1 SRC SMC2 Reserved CPU SMC0 CPU SMC1 CPU SMC2 Reserved SSC control (see SMC table) 0 1 SSC control (see SMC table) Type Power On RW RW RW RW RW RW RW RW 1 0 0 0 1 0 0 0 Type Power On(1) RW RW RW RW RW RW RW RW 0 1 1 0 1 0 0 1 Type Power On RW RW RW RW RW RW RW RW 0 1 1 0 1 0 0 1 Type Power On RW RW RW 1 1 1 RW RW RW RW RW 0 0 1 0 1 BYTE 10 Bit Output(s) Affected 0 1 2 3 4 5 6 7 CPU_N0, LSB CPU_N1 CPU_N2 CPU_N3 CPU_N4 CPU_N5 CPU_N6 CPU_N7, MSB Description / Function 0 1 CPU CLK = N* Resolution NOTE: 1. The default value depends on the value of frequency select signals FSA, FSB, and FSC at power-on. BYTE 11 Bit Output(s) Affected 0 1 2 3 4 5 6 7 SRC_N0, LSB SRC_N1 SRC_N2 SRC_N3 SRC_N4 SRC_N5 SRC_N6 SRC_N7, MSB Description / Function 0 1 CPU CLK = N* Resolution BYTE 12 Bit Output(s) Affected 0 1 2 48MHzStr0 48MHStr1 REFStr0 3 4 5 6 7 Reserved PCIStrC0 PCIStrC1 PCIFStr0 PCIFStr1 Description / Function 0 USB48MHz strength selection Work with Byte 6 Bit 4 REFstr1 ( see strength table) PCI strength selection PCIF strength selection 7 1 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 13 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 Test_scl On chip test mode enable Normal RW 0 N Programming enable Disable SCLK=1, CLK outputs=1 SCLK=0, CLK outputs=0 enable USB PLL power down SRC PLL power down CPU PLL power down Normal Normal Normal Power down Power down Power down RW RW RW RW RW RW RW 0 0 0 0 0 0 0 1 2 3 4 5 6 7 Reserved Reserved Reserved BYTE 62 = 61h BYTE 63 = 12h 8 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 — VDD + 0.3 V VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 — 0.35 V Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 µA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current mA IIL FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB All differential pairs driven — — 70 All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 pF XTAL_IN and XTAL_OUT pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_PD(2) CPU output enable after PD de-assertion — — 300 us TFALL_PD(2) Fall time of PD — — 5 ns TRISE_PD(2) Rise time of PD — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 9 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 1150 mV VLOW Voltage LOW(2) oscilloscope math function –300 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal / -0.5% spread 2.4993 — 2.5133 333.33MHz nominal / -0.5% spread 2.9991 — 3.016 266.66MHz nominal / -0.5% spread 3.7489 — 3.77 200MHz nominal / -0.5% spread 4.9985 — 5.0266 166.66MHz nominal / -0.5% spread 5.9982 — 6.032 133.33MHz nominal / -0.5% spread 7.4978 — 7.54 100MHz nominal / -0.5% spread 9.997 — 10.0533 96MHz nominal 10.4135 — 10.4198 400MHz nominal / -0.5% spread 2.4143 — — 333.33MHz nominal / -0.5% spread 2.9141 — — 266.66MHz nominal / -0.5% spread 3.6639 — — 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 4.9135 5.9132 — — — — 133.33MHz nominal / -0.5% spread 7.4128 — — 100MHz nominal / -0.5% spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation(2) — — 125 ps d-tF dT3 Fall Time Variation(2) Duty Cycle(2) — 45 — — 125 55 ps % Measurement from differential waveform NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 10 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol tSK3 tJCYC-CYC Parameter Min. Typ. Max. Unit — — — — 100 250 ps Skew, SRC(2) — — 250 Jitter, Cycle to Cycle, CPU[3:0](2) — — 50 — — 125 Skew, CPU[1:0](2) Skew, CPU2(2) Jitter, Cycle to Cycle, SRC(2) Test Conditions VT = 50% Measurement from differential waveform ps NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol Parameter Test Conditions ppm Static Error(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values TPERIOD Clock Period(2) — — 0 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 IOL Output LOW Current VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 500 ps VT = 1.5V — — 500 ps Cycle(1) dT1 Duty tSK1 Skew(1) tJCYC-CYC Jitter, Cycle to Cycle(1) NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 11 mA IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS, 48MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions ppm Static Error(1,2) See Tperiod Min. - Max. values TPERIOD Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage VOL IOH IOL Min. Typ. Max. Unit — — 0 ppm 20.8257 — 20.834 ns IOH = -1mA 2.4 — — V Output LOW Voltage IOL = 1mA — — 0.55 V Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % — — 350 ps Min. Typ. Max. Unit — — 0 ppm tJCYC-CYC Jitter, Cycle to Cycle NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol ppm TPERIOD Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal 69.827 — 69.855 ns VOH Output HIGH Voltage(1) IOH = -1mA 2.4 — — V VOL Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — IOL Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 12 IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PCI STOP FUNCTIONALITY If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit. PCI_STOP (Byte 6 bit 3) 1 CPU Normal CPU# Normal SRC Normal SRC# Normal PCIF/PCI 33MHz 48MHz 48MHz REF 14.318MHz 0 Normal Normal IREF * 6 or float Low Low 48MHz 14.318MHz PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PD CPU CPU# SRC SRC# PCIF/PCI USB 0 Normal 1 IREF * 2 or float Normal Normal Normal 33MHz Float IREF * 2 or float Float Low PD ASSERTION PD CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 13 DOT96 DOT96# REF 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float Low IDTCV126 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. tSTABLE