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ISL22414
DATASHEET
Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI®
Bus, 256 Taps
The ISL22414 integrates a single digitally controlled
potentiometer (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the WR.
The ISL22414 also has 14 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
The ISL22414 features a dual supply that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
FN6424
Rev 2.00
September 21, 2015
Features
• 256 resistor taps
• SPI serial interface with write/read capability
• Daisy Chain Configuration
• Shutdown mode
• Non-volatile EEPROM storage of wiper position
• 14 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T 55°C
• Wiper resistance: 70 typical @ 1mA
• Standby current DCP2 --> ... --> DCP(N-1). The
write instruction is executed on the rising edge of CS for all N
DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20,
and Figure 21.
The first part starts by HIGH to LOW transition on CS line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS line,
followed by N number of two bytes NOP instructions on SDI
line and LOW to HIGH transition of CS. The data is read on
every even byte during second part of read sequence while
every odd byte contains instruction code + address from which
the data is being read.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break within an extremely short period of time
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