DATASHEET
ISL28148, ISL28248
4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output Op Amps with Very
Low Input Bias Current
FN6337
Rev 5.00
January 22, 2016
The ISL28148, ISL28248 are 4.5MHz low-power single and
dual operational amplifiers. The parts are optimized for single
supply operation from 2.4V to 5.5V, allowing operation from
one lithium cell or two Ni-Cd batteries.
Features
The single and dual feature an Input Range Enhancement
Circuit (IREC), which enables them to maintain CMRR
performance for input voltages greater than the positive
supply. The input signal is capable of swinging 0.25V above the
positive supply and to 100mV below the negative supply with
only a slight degradation of the CMRR performance. The
output operation is rail-to-rail.
• 1.8mV maximum offset voltage (ISL28248)
The parts draw minimal supply current (900µA per amplifier)
while meeting excellent DC accuracy, AC performance, noise
and output drive specifications. The ISL28148 features an
enable pin that can be used to turn the device off and reduce
the supply current to a maximum of 16µA. Operation is
guaranteed across the -40°C to +125°C temperature range.
• 4.5MHz gain bandwidth product
• 900µA supply current (per amplifier)
• 1pA typical input bias current
• Down to 2.4V single supply operation
• Rail-to-rail input and output
• Enable pin (ISL28148 SOT-23 package only)
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
Applications
• Low-end audio
• 4mA to 20mA current loops
• Medical devices
• Sensor amplifiers
• ADC buffers
• DAC output amplifiers
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL28148FHZ-T7 (Notes 1, 4)
PART MARKING
TAPE AND REEL QUANTITY
(UNITS)
GABT
3k
ISL28148FHZ-T7A (Notes 1, 4)
GABT
250
ISL28248FBZ
28248 FBZ
ISL28248FBZ-T7 (Note 1)
28248 FBZ
ISL28248FUZ
8248Z
ISL28248FUZ-T7 (Note 1)
8248Z
ISL28148EVAL1Z
Evaluation Board
ISL28248MSOPEVAL1Z
Evaluation Board
ISL28248SOICEVAL1Z
Evaluation Board
1k
1.5k
PACKAGE
(RoHS Compliant)
6 Ld SOT-23
PKG.
DWG. #
P6.064A
6 Ld SOT-23
P6.064A
8 Ld SOIC
M8.15E
8 Ld SOIC
M8.15E
8 Ld MSOP
M8.118A
8 Ld MSOP
M8.118A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL28148, ISL28248. For more information on MSL, please see tech
brief TB363.
4. The part marking is located on the bottom of the part.
FN6337 Rev 5.00
January 22, 2016
Page 1 of 17
ISL28148, ISL28248
Pin Configurations
OUT 1
V- 2
+ -
IN+ 3
ISL28248
(8 LD MSOP)
TOP VIEW
ISL28248
(8 LD SOIC)
TOP VIEW
ISL28148
(6 LD SOT-23)
TOP VIEW
6 V+
OUT_A 1
5 EN
IN-_A 2
4 IN-
IN+_A 3
8 V+
- +
+ -
V- 4
OUT_A 1
7 OUT_B
IN-_A 2
6 IN-_B
IN+_A 3
5 IN+_B
V- 4
8 V+
7 OUT_B
- +
6 IN-_B
+ -
5 IN+_B
Pin Descriptions
ISL28148
(6 Ld SOT-23)
ISL28248
(8 Ld SOIC)
(8 Ld MSOP)
PIN NAME
2 (A)
6 (B)
ININ-_A
IN-_B
4
FUNCTION
EQUIVALENT CIRCUIT
inverting input
V+
IN-
IN+
VCircuit 1
3 (A)
5 (B)
IN+
IN+_A
IN+_B
4
V-
3
2
Noninverting input
Negative supply
(See circuit 1)
V+
CAPACITIVELY
COUPLED
ESD CLAMP
VCircuit 2
1
1 (A)
7 (B)
OUT
OUT_A
OUT_B
Output
V+
OUT
VCircuit 3
6
5
8
V+
Positive supply
EN
Chip enable
(See circuit 2)
V+
EN
VCircuit 4
FN6337 Rev 5.00
January 22, 2016
Page 2 of 17
ISL28148, ISL28248
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200V
Thermal Resistance (Typical, Note 5)
JA (°C/W)
6 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
8 Ld MSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications (VS ±5V) V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER
VOS
DESCRIPTION
Input Offset Voltage
V OS
--------------T
Input Offset Voltage vs Temperature
IOS
Input Offset Current
IB
Input Bias Current
CMIR
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ISL28148
-2.3
-2.8
0
2.3
2.8
mV
ISL28248
-1.8
-2.8
0
1.8
2.8
mV
0.03
µV/°C
-35
-80
±5
35
80
pA
TA = -40°C to +85°C
-30
-80
±1
30
80
pA
TA = -40°C to +85°C
Common-Mode Voltage Range
Guaranteed by CMRR
0
5
V
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
75
70
98
dB
PSRR
Power Supply Rejection Ratio
V+ = 2.4V to 5.5V
80
75
98
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100kΩto VCM
200
150
580
V/mV
VO = 0.5V to 4.5V, RL = 1kΩto VCM
50
V/mV
Output low, RL = 100kΩto VCM
3
6
8
mV
Output low, RL = 1kΩto VCM
50
70
110
mV
VOUT
Maximum Output Voltage Swing
Output high, RL = 100kΩto VCM
4.994
4.99
4.998
V
Output high, RL = 1kΩto VCM
4.93
4.89
4.95
V
IS,ON
Quiescent Supply Current, Enabled
Per Amplifier
0.9
1.25
1.4
mA
IS,OFF
Quiescent Supply Current, Disabled
ISL28148 SOT-23 package only
10
14
16
µA
IO+
Short-Circuit Output Source Current
RL = 10Ωto VCM
IO-
Short-Circuit Output Sink Current
RL = 10Ωto VCM
VSUPPLY
Supply Operating Range
V+ to V-
VENH
EN Pin High Level
ISL28148 SOT-23 package only
FN6337 Rev 5.00
January 22, 2016
48
45
75
-68
2.4
2
mA
-48
-45
mA
5.5
V
V
Page 3 of 17
ISL28148, ISL28248
Electrical Specifications (VS ±5V) V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
VENL
EN Pin Low Level
ISL28148 SOT-23 package only
0.8
V
IENH
EN Pin Input High Current
V EN = V+, ISL28148 SOT-23 package only
1
1.5
1.6
µA
IENL
EN Pin Input Low Current
V EN = V-, ISL28148 SOT-23 package only
12
25
30
nA
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
AV = 100, Rf = 100kΩRg = 1kΩ
RL = 10kΩto VCM
4.5
MHz
Unity Gain
Bandwidth
-3dB Bandwidth
AV = 1, Rf = 0ΩVOUT = 10mVP-P,
RL = 10kΩto VCM
13
MHz
eN
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
2
µVPP
Input Noise Voltage Density
fO = 1kHz
28
nV/Hz
iN
Input Noise Current Density
fO = 1kHz
0.016
pA/Hz
CMRR at 60Hz
Input Common-Mode Rejection Ratio
VCM = 1VP-P, RL = 10kΩto VCM
85
dB
PSRR- At
120Hz
Power Supply Rejection Ratio (V-)
V+, V- = ±1.2V and ±2.5V,
VSOURCE = 1VP-P, RL = 10kΩto VCM
-82
dB
PSRR+ At
120Hz
Power Supply Rejection Ratio (V+)
V+, V- = ±1.2V and ±2.5V
VSOURCE = 1VP-P, RL = 10kΩto VCM
-100
dB
TRANSIENT RESPONSE
SR
Slew Rate
±4
V/µs
tr, tf, Large
Signal
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 3VP-P, Rg = Rf = 10kΩ
RL = 10kΩto VCM
530
ns
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 3VP-P, Rg = Rf = 10kΩ
RL = 10kΩto VCM
530
ns
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 10kΩto VCM
50
ns
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 10kΩto VCM
50
ns
Enable to Output Turn-On Delay Time, 10%
EN to 10% VOUT, (ISL28148)
EN = 5V to 0V, AV = +2,
Rg = Rf = RL = 1kΩto VCM
5
µs
Enable to Output Turn-Off Delay Time, 10%
EN to 10% VOUT, (ISL28148)
VEN = 0V to 5V, AV = +2,
Rg = Rf = RL = 1kΩ to VCM
0.2
µs
tr, tf, Small
Signal
tEN
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6337 Rev 5.00
January 22, 2016
Page 4 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open.
1
0
10
Rf = Rg = 100k
Rf = Rg = 10k
5
0
V+ = 5V
-5 RL = 1k
CL = 16.3pF
-10 AV = +2
VOUT = 10mVP-P
-15
100
1k
10k
Rf = Rg = 1k
100k
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
15
100M
VOUT = 100mV
-1
-2
VOUT = 50mV
-3
VOUT = 10mV
-4
VOUT = 1V
-5
-6 V = 5V
+
-7 RL = 1k
CL = 16.3pF
-8
AV = +1
-9
1k
10k
FREQUENCY (Hz)
10M
100M
FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k
1
1
0
0
-1
VOUT = 100mV
-2
VOUT = 50mV
-3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1M
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES
Rf/Rg
VOUT = 10mV
-4
VOUT = 1V
-5
-6
V+ = 5V
RL = 10k
CL = 16.3pF
AV = +1
-7
-8
-9
1k
10k
-2
VOUT = 50mV
-3
VOUT = 10mV
-4
1M
10M
-6
-7
-9
100M
VOUT = 1V
-5
-8
100k
VOUT = 100mV
-1
V+ = 5V
RL = 100k
CL = 16.3pF
AV = +1
1k
10k
FREQUENCY (Hz)
1
-1
70
60
GAIN (dB)
RL = 100k
-3
-4
-5
-6
-7
-8
-9
V+ = 5V
VOUT = 10mVP-P
CL = 16.3pF
AV = +1
1k
10k
100M
40
30
20
AV = 101
V+ = 5V
CL = 16.3pF
RL = 10k
VOUT = 10mVP-P
AV = 10
10
0
100k
1M
10M
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs RL
FN6337 Rev 5.00
January 22, 2016
10M
AV = 1, Rg = INF, Rf = 0
AV = 10, Rg = 1k, Rf = 9.09k
AV = 101, Rg = 1k, Rf = 100k
AV = 1001, Rg = 1k, Rf = 1M
AV = 1001
50
RL = 10k
-2
1M
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k
RL = 1k
0
100k
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k
NORMALIZED GAIN (dB)
100k
100M
-10
100
AV = 1
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
Page 5 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
1
V+ = 5V
-1
-2
V+ = 2.4V
-3
-4
-5
-6
-7
-8
RL = 10k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-9
10k
100k
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
100M
8
7
6
5
4
3
2
1
0
-1
-2
-3 V+ = 5V
-4 RL = 1k
-5 A = +1
V
-6
VOUT = 10mVP-P
-7
-8
10k
100k
FREQUENCY (Hz)
CL = 26.7pF
CL = 16.7pF
CL = 4.7pF
1M
10M
100M
FIGURE 8. GAIN vs FREQUENCY vs CL
10
20
0
0
-10
PSRR-
-20
PSRR (dB)
-20
CMRR (dB)
CL = 37.7pF
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
-30
-40
-50
V+ = 2.4V, 5V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
-60
-70
-80
-90
100
1k
10k
100k
FREQUENCY (Hz)
1M
-40
-60
PSRR+
-80
-100
-120
100
10M
FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V
20
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V
-40
-60
PSRR+
-80
-100
1k
10k
100k
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
1M
10M
INPUT VOLTAGE NOISE (nV/Hz)
PSRR-
-20
-120
100
1k
V+, V- = ±1.2V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
1000
0
PSRR (dB)
CL = 51.7pF
CL = 43.7pF
V+ = 5V
Rf = 1k Rg = 1k
AV = +2
100
10
FREQUENCY (Hz)
100
1k
FREQUENCY (Hz)
FIGURE 11. PSRR vs FREQUENCY V+, V- = ±2.5V
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FN6337 Rev 5.00
January 22, 2016
1
10
10k
100k
Page 6 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
0
0.1
-0.5
INPUT NOISE (µV)
INPUT CURRENT NOISE (pA/Hz)
V+ = 5V
Rf = 1k Rg = 1k
AV = +2
-1.0
-1.5
-2.0
RL = 10k
V+ = 5V
CL = 16.3pF AV = 10k
Rg = 10
Rf = 100k
-2.5
0.01
1
10
100
1k
10k
-3.0
100k
0
1
2
3
4
FREQUENCY (Hz)
5
6
TIME (s)
7
8
9
10
FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
0.025
2.0
1.0
SMALL SIGNAL (V)
0.5
0
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg = Rf = 10k
AV = 2
VOUT = 3VP-P
-0.5
-1.0
-1.5
-2.0
0
1
2
3
4
5
6
TIME (µs)
7
8
9
0.020
0.010
10
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg= Rf = 10k
AV = 2
VOUT = 10mVP-P
0.015
0
1
2
3
5
6
7
8
9
10
TIME (µs)
FIGURE 15. LARGE SIGNAL STEP RESPONSE
FIGURE 16. SMALL SIGNAL STEP RESPONSE
1.2
3.5
VOUT
VEN
3.0
1.0
2.5
VENABLE (V)
4
0.8
V+ = 5V
Rg = Rf = 10k
CL = 16.3pF
AV = +2
VOUT = 1VP-P
2.0
1.5
1.0
0.5
0.6
0.4
0.2
RL = 10k
0
0
-0.5
OUTPUT (V)
LARGE SIGNAL (V)
1.5
0
10
20
30
40
50
60
TIME (µs)
70
80
90
-0.2
100
FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE
FN6337 Rev 5.00
January 22, 2016
Page 7 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
100
800
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1k
600
200
60
40
IBIAS (pA)
VOS (µV)
400
0
-200
20
0
-20
-40
-400
-60
-600
-80
-800
-1
0
1
2
3
VCM (V)
4
5
-100
6
FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT
VOLTAGE
0
1
2
3
VCM (V)
4
5
6
10.5
MAX
9.5
1.1
MAX
1.0
MEDIAN
0.9
0.8
8.5
CURRENT (µA)
CURRENT (mA)
-1
FIGURE 19. INPUT BIAS CURRENT vs COMMON-MODE INPUT
VOLTAGE
1.2
MIN
MEDIAN
7.5
6.5
MIN
5.5
0.7
4.5
0.6
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
3.5
-40
120
FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE V+,
V- = ±2.5V
0
20
40
60
80
TEMPERATURE (°C)
100
120
2.0
MAX
1.5
MAX
1.5
1.0
1.0
VOS (mV)
0.5
MEDIAN
0
-0.5
0.5
MEDIAN
0
-0.5
-1.0
-1.0
MIN
-1.5
-2.0
-40
-20
FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE V+,
V- = ±2.5V
2.0
VOS (mV)
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1k
80
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V
FN6337 Rev 5.00
January 22, 2016
MIN
-1.5
-2.0
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 23. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V
Page 8 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
2.0
300
MAX
1.5
250
200
0.5
IBIAS- (pA)
VOS (mV)
1.0
MEDIAN
0
-0.5
150
50
MIN
-1.5
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-50
-40
120
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 25. IBIAS- vs TEMPERATURE V+, V- = ±2.5V
250
10
0
200
MEDIAN
100
50
MAX
-10
MAX
150
IOS (pA)
IBIAS- (pA)
MIN
0
FIGURE 24. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V
MIN
-20
MEDIAN
-30
MIN
-40
-50
0
-50
-40
MEDIAN
100
-1.0
-2.0
-40
MAX
-60
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-70
-40
120
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 27. IOS vs TEMPERATURE V+, V- = ±2.5V
FIGURE 26. IBIAS- vs TEMPERATURE V+, V- = ±1.2V
20
1750
10
1550
MAX
-10
-20
AVOL (V/mV)
IOS (pA)
0
MEDIAN
-30
MIN
1350
1150
950
-40
550
-50
350
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
FIGURE 28. IOS vs TEMPERATURE V+, V- = ±1.2V
FN6337 Rev 5.00
January 22, 2016
120
MAX
750
150
-40
MEDIAN
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 29. AVOL vs TEMPERATURE RL = 100k, V+, V- = ±2.5V, VO = 2V TO +2V
Page 9 of 17
ISL28148, ISL28248
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
80
140
70
130
MAX
50
MEDIAN
40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
70
-40
120
20
40
60
80
TEMPERATURE (°C)
100
120
MAX
4.960
VOUT (V)
PSRR (dB)
0
4.965
MAX
120
110
100
MEDIAN
MIN
80
-20
0
20
40
60
80
TEMPERATURE (°C)
4.955
MEDIAN
4.950
90
MIN
4.945
100
4.940
-40
120
FIGURE 32. PSRR vs TEMPERATURE V+, V- = ±1.2V TO ±2.75V
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 33. VOUT HIGH vs TEMPERATURE RL = 1k,
V+, V- = ±2.5V
75
4.9994
70
4.9992
MAX
MAX
65
VOUT (mV)
4.9990
VOUT (V)
-20
4.970
130
4.9988
MEDIAN
60
MEDIAN
55
50
MIN
MIN
4.9984
4.9982
-40
MIN
FIGURE 31. CMRR vs TEMPERATURE VCM = -2.5V TO +2.5V, V+, V- =
±2.5V
140
4.9986
MEDIAN
100
80
MIN
FIGURE 30. AVOL vs TEMPERATURE RL = 1k, V+, V- = ±2.5V, VO = -2V
TO +2V
70
-40
110
90
30
20
-40
MAX
120
60
CMRR (dB)
AVOL (V/mV)
Typical Performance Curves
45
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 34. VOUT HIGH vs TEMPERATURE RL = 100k,
V+, V- = ±2.5V
FN6337 Rev 5.00
January 22, 2016
100
120
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 35. VOUT LOW vs TEMPERATURE RL = 1k,
V+, V- = ±2.5V
Page 10 of 17
ISL28148, ISL28248
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)
95
3.3
+ OUTPUT SHORT CIRCUIT
CURRENT (mA)
3.1
VOUT (mV)
2.9
MAX
2.7
2.5
2.3
MEDIAN
2.1
MIN
1.9
1.7
1.5
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
90
80
MEDIAN
75
70
MIN
65
60
-40
120
MAX
85
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 37. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE
VIN = 2.55V, RL = 10, V+, V- = ±2.5V
FIGURE 36. VOUT LOW vs TEMPERATURE RL = 100k,
V+, V- = ±2.5V
- OUTPUT SHORT CIRCUIT
CURRENT (mA)
-50
-55
MAX
-60
MEDIAN
-65
-70
MIN
-75
-80
-85
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 38. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V
FN6337 Rev 5.00
January 22, 2016
Page 11 of 17
ISL28148, ISL28248
Applications Information
Introduction
The ISL28148, ISL28248 are single and dual channel CMOS
rail-to-rail input, output (RRIO) micropower precision operational
amplifiers. The parts are designed to operate from a single
supply (2.4V to 5.5V) or a dual supply (±1.2V to ±2.75V). The
parts have an input common-mode range that extends 0.25V
above the positive rail and 100mV below the negative supply rail.
The output can swing within about 3mV of the supply rails with a
100kΩ load.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs, a
long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties
have to be paid for this circuit topology. As the input signal moves
from one supply rail to another, the operational amplifier
switches from one input pair to the other causing drastic changes
in input offset voltage and an undesired change in magnitude
and polarity of input offset current.
The parts achieve input rail-to-rail operation without sacrificing
important precision specifications and degrading distortion
performance. The devices’ input offset voltage exhibits a smooth
behavior throughout the entire common-mode input range. The
input bias current vs the common-mode voltage range gives us
an undistorted behavior from typically 100mV below the negative
rail and 0.25V higher than the V+ rail.
Rail-to-Rail Output
A pair of complementary MOS devices are used to achieve the
rail-to-rail output swing. The NMOS sinks current to swing the
output in the negative direction. The PMOS sources current to
swing the output in the positive direction. The devices’ with a
100kΩ load will swing to within 3mV of the positive supply rail and
within 3mV of the negative supply rail.
Results of Overdriving the Output
Caution should be used when overdriving the output for long
periods of time. Overdriving the output can occur in two ways:
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or
2. The output current required is higher than the output stage can
deliver. These conditions can result in a shift in the Input Offset
Voltage (VOS) as much as 1µV/hr. of exposure under these
conditions.
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (see “Pin
Descriptions” table - Circuit 1 on page 2). For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input currents
never exceed 5mA (Figure 39).
VIN
RIN
+
VOUT
RL
FIGURE 39. INPUT CURRENT LIMITING
Enable/Disable Feature
The ISL28148 offers an EN pin that disables the device when
pulled up to at least 2.0V. In the disabled state (output in a high
impedance state), the part consumes typically 10µA at room
temperature. By disabling the part, multiple ISL28148 parts can
be connected together as a MUX. In this configuration, the
outputs are tied together in parallel and a channel can be
selected by the EN pin. The loading effects of the feedback
resistors of the disabled amplifier must be considered when
multiple amplifier outputs are connected together. Note that
feed-through from the IN+ to IN- pins occurs on any Mux Amp
disabled channel where the input differential voltage exceeds
0.5V (e.g., active channel VOUT = 1V, while disabled channel
VIN = GND), so the Mux implementation is best suited for small
signal applications. If large signals are required, use series IN+
resistors, or large value Rf, to keep the feed-through current low
enough to minimize the impact on the active channel. See
“Limitations of the Differential Input Protection” on page 12 for
more details.The EN pin also has an internal pull-down. If left
open, the EN pin will pull to the negative rail and the device will
be enabled by default. When not used, the EN pin should either
be left floating or connected directly to the V- pin.
Limitations of the Differential Input
Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the input
current never exceeds 5mA. For noninverting unity gain applications
the current limiting can be via a series IN+ resistor, or via a feedback
resistor of appropriate value. For other gain configurations, the
series IN+ resistor is the best choice, unless the feedback (Rf) and
gain setting (Rg) resistors are both sufficiently large to limit the input
current to 5mA.
Large differential input voltages can arise from several sources:
• During open loop (comparator) operation. Used this way, the
IN+ and IN- voltages don’t track, so differentials arise.
• When the amplifier is disabled but an input signal is still
present. An RL or Rg to GND keeps the IN- at GND, while the
varying IN+ signal creates a differential voltage. Mux Amp
applications are similar, except that the active channel VOUT
determines the voltage on the IN- terminal.
• When the slew rate of the input pulse is considerably faster
than the op amp’s slew rate. If the VOUT cannot keep up with
the IN+ signal, a differential voltage results and visible
distortion occurs on the input and output signals. To avoid this
issue, keep the input slew rate below 4.8V/µs, or use
appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
FN6337 Rev 5.00
January 22, 2016
Page 12 of 17
ISL28148, ISL28248
Using Only One Channel
Power Dissipation
If the application does not use all channels, then the user must
configure the unused channel(s) to prevent them from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the negative input and ground the positive input (as
shown in Figure 40).
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related in Equation 1:
T JMAX = T MAX + JA xPD MAXTOTAL
(EQ. 1)
-
Where:
+
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
FIGURE 40. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in the
circuit board layout. The PC board surface must remain clean
and free of moisture to avoid leakage currents between adjacent
traces. Surface coating of the circuit board will reduce surface
moisture and provide a humidity barrier, reducing parasitic
resistance on the board. When input leakage current is a
concern, the use of guard rings around the amplifier inputs will
further reduce leakage currents. Figure 41 shows a guard ring
example for a unity gain amplifier that uses the low impedance
amplifier output at the same voltage as the high impedance
input to eliminate surface leakage. The guard ring does not need
to be a specific width, but it should form a continuous loop
around both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
• PDMAX for each amplifier can be calculated as shown in
Equation 2:
V OUTMAX
PD MAX = 2*V S I SMAX + V S - V OUTMAX ---------------------------R
L
(EQ. 2)
Where:
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
.
HIGH IMPEDANCE INPUT
V+
IN
FIGURE 41. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
Current Limiting
These devices have no internal current limiting circuitry. If the
output is shorted, it is possible to exceed the absolute maximum
rating for output current or power dissipation, potentially
resulting in the destruction of the device.
FN6337 Rev 5.00
January 22, 2016
Page 13 of 17
ISL28148, ISL28248
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
January 22, 2016
FN6337.5
-Removed part number ISL28448 throughout the datasheet.
-Updated 3rd bullet under Features section.
-Ordering information table on page 1: Added ISL28248MSOPEVAL1Z, ISL28248SOICEVAL1Z.
-Electrical spec table on page 3, Changed VOS limits for the ISL28148: Min from -1.8, -2 to -2.3, -2.8 and Max
from 1.8, 2 to 2.3, 2.8.
Thermal Information table on page 3, changes are:
6ld SOT-23: from 230C/W, to 165C/W
8ld SOIC: from 125C/W, to 120C/W
8ld MSOP: from 175C/W, to 160C/W
- Added revision history and About Intersil verbiage
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2007-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6337 Rev 5.00
January 22, 2016
Page 14 of 17
ISL28148, ISL28248
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6337 Rev 5.00
January 22, 2016
Page 15 of 17
ISL28148, ISL28248
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN6337 Rev 5.00
January 22, 2016
Page 16 of 17
ISL28148, ISL28248
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
FN6337 Rev 5.00
January 22, 2016
Page 17 of 17
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