ISL6611AIRZ-T

DATASHEET ISL6611A FN6881 Rev 1.00 August 28, 2012 Phase Doubler with Integrated Drivers and Phase Shedding Function The ISL6611A utilizes Intersil’s proprietary Phase Doubler scheme to modulate two-phase power trains with single PWM input. It doubles the number of phases that Intersil’s ISL63xx multiphase controllers can support. At the same time, the PWM line can be pulled high to disable the corresponding phase or higher phase(s) when the enable pin (EN_PH) is pulled low. This simplifies the phase shedding implementation. For layout simplicity and improving system performance, the device integrates two 5V drivers (ISL6609) and current balance function. The ISL6611A is designed to minimize the number of analog signals interfacing between the controller and drivers in high phase count and scalable applications. The common COMP signal, which is usually seen with conventional cascaded configuration, is not required; this improves noise immunity and simplifies the layout. Furthermore, the ISL6611A provides low part count and a low cost advantage over the conventional cascaded technique. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6611A features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6611A also features an input that recognizes a high-impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the Schottky diode that may be utilized in a power system to protect the load from negative output voltage damage. Features • Proprietary Phase Doubler Scheme with Phase Shedding Function (Patent Pending) - Enhanced Light to Full Load Efficiency • Patented Current Balancing with rDS(ON) Current Sensing and Adjustable Gain • Quad MOSFET Drives for Two Synchronous Rectified Bridge with Single PWM Input • Channel Synchronization and Interleaving Options • Adaptive Zero Shoot-Through Protection • 0.4 On-Resistance and 4A Sink Current Capability • 36V Internal Bootstrap Schottky Diode • Bootstrap Capacitor Overcharging Prevention (ISL6611A) • Supports High Switching Frequency (Up to 1MHz) - Fast Output Rise and Fall • Tri-State PWM Input for Output Stage Shutdown • Phase Enable Input and PWM Forced High Output to Interface with Intersil’s Controller for Phase Shedding • QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Utilization, Thinner Profile - Pb-Free (RoHS Compliant) Applications • High Current Low Voltage DC/DC Converters • High Frequency and High Efficiency VRM and VRD • High Phase Count and Phase Shedding Applications Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” In addition, the ISL6611A’s bootstrap function is designed to prevent the BOOT capacitor from overcharging, should excessively large negative swings occur at the transitions of the PHASE node. FN6881 Rev 1.00 August 28, 2012 Page 1 of 14 ISL6611A Ordering Information PART NUMBER (Notes 1, 2, 3) TEMP. RANGE (°C) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # ISL6611ACRZ 66 11ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4 ISL6611AIRZ* 66 11AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6611A. For more information on MSL please see techbrief TB363. Pinout SYNC PWM1 VCC PHASEA ISL6611A (16 LD QFN) TOP VIEW 16 15 14 13 GND 1 12 UGATEA LGATEA 2 11 BOOTA 17 GND PVCC 3 10 BOOTB FN6881 Rev 1.00 August 28, 2012 5 6 7 8 LGATEB EN_PH PHASEB 9 PGND IGAIN 4 UGATEB Page 2 of 14 ISL6611A Block Diagram RBOOT PVCC VCC BOOTA UGATEA 4.9k SHOOTTHROUGH PROTECTION PHASEA CHANNEL A PVCC PWM LGATEA 4.6k PGND CONTROL LOGIC PVCC EN_PH BOOTB UGATEB SYNC IGAIN PGND RBOOT SHOOTTHROUGH PROTECTION CURRENT BALANCE BLOCK PHASEB CHANNEL B PVCC PHASEA LGATEB PHASEB PGND GND PAD MUST BE SOLDERED TO THE CIRCUIT’S GROUND INTEGRATED 3 RESISTOR (RBOOT) IN ISL6611A FN6881 Rev 1.00 August 28, 2012 Page 3 of 14 ISL6611A Functional Pin Descriptions PACKAGE PIN # PIN SYMBOL 1 GND 2 LGATEA 3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from this pin to PGND. 4 IGAIN A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on page 11 for more details. 5 PGND Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits. 6 LGATEB Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET. 7 EN_PH Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to VCC at the PWM falling edge and then enters tri-state. FUNCTION Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the rDS(ON) current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC. Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET. 8 PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin provides a return path for the upper gate drive. 9 UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET. 10 BOOTB Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap Considerations” on page 9 for guidance in choosing the capacitor value. 11 BOOTA Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap Considerations” on page 9 for guidance in choosing the capacitor value. 12 UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET. 13 PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin provides a return path for the upper gate drive. 14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic capacitor from this pin to GND. 15 PWM The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and the PWM input starts transitioning low. 16 SYNC A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180° out-of-phase. 17 PAD FN6881 Rev 1.00 August 28, 2012 Connect this pad to the power ground plane (GND) via thermally enhanced connection. Page 4 of 14 ISL6611A Typical Application I (2-Phase Controller for 4-Phase Operation) +5V +5V SYNC VCC AND PVCC EN_PH COMP FB +5V BOOTA +12V UGATEA PHASEA SYNC LGATEA VSEN +VCORE ISL6611A PWM1 VCC BOOTB PWM +12V UGATEB PHASEB VR_RDY EN LGATEB MAIN CONTROL IGAIN ISL63xx GND AND PGND VID ISEN1ISEN1+ +5V EN_PH FS VCC AND PVCC EN_PH SYNC BOOTA +12V UGATEA PHASEA LGATEA ISL6611A PWM2 PWM BOOTB +12V UGATEB PHASEB LGATEB IGAIN GND AND PGND ISEN2ISEN2+ GND FN6881 Rev 1.00 August 28, 2012 Page 5 of 14 ISL6611A Typical Application II (4-Phase Controller to 8-Phase Operation) +VCORE +5V SYNC COMP PWM1 FB +5V +5V VCC & PVCC EN_PH SYNC BOOTA PWM BOOTB ISL6611A VSEN +12V UGATEA PHASEA LGATEA +12V UGATEB PHASEB LGATEB IGAIN VCC GND & PGND ISEN1- VR_RDY ISEN1+ EN +5V EN_PH2 MAIN CONTROL ISL63xx VID PWM2 VCC & PVCC EN_PH SYNC BOOTA PWM BOOTB ISL6611A +12V UGATEA PHASEA LGATEA +12V UGATEB PHASEB LGATEB IGAIN FS GND & PGND ISEN2ISEN2+ +5V EN_PH3 VCC & PVCC EN_PH SYNC PWM3 BOOTA BOOTB PWM ISL6611A +12V UGATEA PHASEA LGATEA +12V UGATEB PHASEB LGATEB IGAIN GND & PGND ISEN3ISEN3+ +5V EN_PH4 PWM4 VCC & PVCC EN_PH SYNC BOOTA PWM BOOTB ISL6611A +12V UGATEA PHASEA LGATEA +12V UGATEB PHASEB LGATEB IGAIN GND & PGND ISEN4GND FN6881 Rev 1.00 August 28, 2012 ISEN4+ Page 6 of 14 ISL6611A Absolute Maximum Ratings Thermal Information Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . -0.3V to 6.7V Input Voltage (VEN_PH, VPWM, VSYNC) . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 27V (DC) or 36V (