L6611N

L6611 DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OV/UV DETECTION FOR 3.3V, +5V, ±12V RAILS AND 5V (OR 3.3V) AUX. VOLTAGE AC MAINS UV (BROWNOUT) DETECTION WITH HYSTERESIS ON-LINE DIGITAL TRIMMING FOR 5V/12V, 3.3V, 5V (OR 3.3V) AUX. FEEDBACK REFERENCES AND AC MAINS UV. DIGITALLY SELECTABLE OPTIONS ERROR AMPLIFIERS FOR 5V/12V RAILS (MAIN SUPPLY), 3V3 POST-REGULATOR (MAG_AMP OR LINEAR) AND AUXILIARY SUPPLY. MAIN SUPPLY ON/OFF CONTROL AND POWER GOOD SIGNAL 50mA CROWBAR DRIVE FOR AUXILIARY OUTPUT OVP. OPEN GROUND PROTECTION 8ms DIGITAL SOFT START 64 ms UV/OC BLANKING AT START-UP BCD TECHNOLOGY DIP20 ORDERING NUMBERS: ) s ( ct e t le r P e t e l o s b O o r P ) s t( L6611D L6611DTR(T & Reel) APPLICATIONS ■ SWITCHING POWER SUPPLIES FOR DESKTOP PC'S, SERVERS AND WEB SERVERS o s b O - SUPERVISOR FOR DISTRIBUTED POWER +12V u d o + WIDE RANGE MAINS c u d L6611N ■ TYPICAL APPLICATION CIRCUIT SO20 +5V COM - -12V +3.3V MAIN CONTROL +5Vaux AUXILIARY CONTROL Bout VDD Dmon Cout 12V 5V MFault -12V Aout Gnd 3V3 L6611 April 2002 1/28 L6611 Vdd L U V Soft Start Reset 1.25V(B) 2.50V(B) 2.50V( C) 1.25V( A) 2.50V( A) +5V +12V 2.50V(B) OCP Bounce 1.25V (A) V r e f 2.50V(A) 1.25V (B) BLOCK DIAGRAM Binv Bout Aout Ainv Gnd Vdd Cout Cinv Vdd ov uv ov UV OV 3V3 +5V UV +/-12V UV 2.50V( B) Disable _ + 10mA Debounce 75ms uv ov uv ov uv ov ov uv 2.50V( C) Programming input 2.50V(B) Vdd +3V3 +5V +12V 50uA Vdd Obs d o r P e t ole Prog Dmon 2/28 b O (s) Logic and Programmable Trimming t c u od r P e t e l o s b -O ) s ( t uc t e l so +3V3 +5V +12V --12V ACsns Mfault PW -OK / Data - PS -ON / Clock - Vreg Dfault L6611 DESCRIPTION The L6611 is a control and housekeeping IC developed in BCD technology; it is intended for acting at the secondary side of desktop PC's or server's switching power supplies, in presence of standard voltage rails (+3.3V, +5V, ±12V) generated by a main converter and of a supply line generated by an auxiliary converter. The typical application circuit is showed on the front page. The Housekeeping's main function is to control and monitor the voltages generated by both the main and the auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation and, upon detection of an undervoltage (UV), or overvoltage (OV) condition, reports such fault and takes proper action to protect the system. However, the peculiar feature of this IC is its digital programming capability that enables an accurate trimming of the output voltage rails during production test via software, without any use of external discrete trimming components or need for manual intervention on the PSU. It is also possible to program some of the monitoring functions and select how UV and OC conditions are handled in the main converter: whether latched-mode (the information is latched and released only by forcing the restart of the IC) or bouncing-mode (an attempt is made to automatically restart the converter after 1 second wait). A key feature of this IC is its contribution to a very low external component count. Besides the extensive use of onboard programmable switches, which prevents the need for external trimming components, the IC embeds reference voltages, error amplifiers and most of the housekeeping circuitry normally required. PIN CONNECTION (top view) MFAULT Binv Bout Aout Ainv Cout Cinv Dmon ) s ( ct o s b O - DFAULT Vdd u d o r P e o r P 12V 5V 3V3 PROG GND --12V VREF PS-ON PW-OK ACsns e t le c u d ) s t( PIN DESCRIPTION 1 t e l o 2 Binv Inverting input to the error amplifier for the 3V3 post-regulator (either mag-amp or linear). The non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed. Bout Output of the 3V3 error amplifier. It typically drives either a PNP transistor that sets the mag-amp core or the pass element of a linear regulator. Also node for error amplifier compensation. The maximum positive level of this output is clamped at about 3.5V to improve response time. Large signal slew rate is limited to reduce noise sensitivity. Pin # s b O 3 Name Description Main converter on/off control. This pin is a 10mA current sink used for driving an opto-isolator. It is normally low when PS-ON (#13) is pulled low. If a fault is detected or PS-ON goes high, this MFAULT pin goes high too. To allow power up, the functions are digitally blanked out for a period (UVB function) and MFAULT (#1) stays low. There is no delay for the OV protection function. 3/28 L6611 PIN DESCRIPTION (continued) Pin # Name Description 4 Aout Output of the error amplifier for the main converter. This pin typically drives an optocoupler and is also used for compensation along with Ainv (pin #5). 5 Ainv Main loop error amplifier inverting input. The non-inverting input is connected to an internal 2.5V reference that can be digitally trimmed. A high impedance internal divider from +12V and +5V UV/OV sense pins (#19, #20) eliminates the need for external divider in most applications. The pin is used for error amplifier compensation. 6 Cout Auxiliary loop optocoupler drive. Also node for error amp compensation. Large signal slew rate is limited to reduce sensitivity to switching noise. 7 Cinv Inverting input for Auxiliary error amplifier. The non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed. 8 Dmon Dual or Auxiliary UV/OV monitor, Dmon is programmable to monitor 3V3 or 5V. To allow a correct power up, the UV function on this pin is blanked out during initial start-up. There is no delay for the OV function. 9 DFAULT Dual or Auxiliary fault protection. When Dmon (#8) recognizes an over voltage, DFAULT and MFAULT (#1) go high. DFAULT is capable of sourcing up to 50mA. Possible applications are a crowbar across the Auxiliary output or an opto-coupled fault signal to the primary side. Vdd Positive input supply voltage. Vdd is normally supplied from the Auxiliary power supply output voltage. If Vdd-UVL detects a sustained under voltage, PW-OK (#12) will be pulled low and sending MFAULT (#1) high will disable the main converter. ACsns Analog of bulk voltage for AC fail warning. The usual source of this analog pin is one of the secondary windings of the main transformer. Hysteresis is provided through a trimmable 50µA current sink on this pin that is activated as the voltage at the pin falls below the internal reference (2.5V). PW-OK /Data Power good signal for the Main converter. When asserted high, this pin indicates that the voltages monitored are above their UV limits. There will be typically 250ms delay from the Main outputs becoming good and PW-OK being asserted. This is nominally an open drain signal. To improve robustness, this output has a limited current sink capability. In programming mode, this pin is used for data input; then the absolute maximum rating will be Vdd+0.5V. PS-ON / Clock Control pin to enable the Main converter. This pin has debouncing logic. A recognized high value on this pin will cause PW-OK (#12) to go immediately low and, after a delay of 2.5ms, to shut down the main PWM by allowing MFAULT (#1) to go high. During normal operation (or if not used) this pin has to be connected to a voltage lower than 0.8V. In programming mode, this pin will be used to clock serial data into the chip. 10 11 12 13 e t le ) s ( ct o r P o s b O - u d o r P e VREF 2.5V reference for external applications. This is a buffered pin. Shorting this pin to ground or to Vdd (#10) will not affect integrity of control or monitor references. An external capacitor (max. 100nF) is required whenever the pin is loaded (up to 5 mA), otherwise it can be left floating. 15 t e l o -12V -12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #14), the function will be disabled. 16 GND Ground pin. The connection integrity of this pin is constantly monitored and in case of either a bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#9) will be forced high switching off the supply. PROG The chip has 2 operating modes, depending on PROG input pin biasing: – normal mode: PROG should be floating or shorted to ground; – programming mod e: forcing PROG high (+5V), the chip enters programming mode. PW_OK (#12) and PS_ON (#13) pins are disconnected from their normal functionality and they become inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode allows selecting some options and adjusting some setpoints; 14 bs O c u d ) s t( 17 4/28 L6611 PIN DESCRIPTION (continued) Pin # Name Description 18 3V3 19 5V Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference separate from that used for feedback. This pin connects the 5V part of the Main error amplifier feedback divider. 20 12V Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a reference separate from that used for feedback. This pin connects the 12V part of the Main error amplifier feedback divider. 3V3 UV/OV monitor. It uses a separate reference to the feedback reference. FUNCTION DESCRIPTION Name Description OVP Whenever one of the Main output voltages is detected going above its own OVP threshold, this function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON (#13) switch or by reducing Vdd (#10) below the UV threshold. UVP Whenever one of the Main output voltages is detected going under its own UVP threshold, this function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched. Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#11) is low due to a brownout condition, UVP is disabled. UVB Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts as the ACsns pin detects a valid input voltage for the converter. PW-OK delay PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV threshold the PW-OK pin (#12) will be kept low for additional 250ms (typ.) to make sure all the outputs are settled. OFF delay Power-off delay. As soon as PS-ON (#13) pin is recognized high, indicating an imminent turn-off condition, PW-OK (#12) pin will go low immediately . The converter will be turned off after a delay of 2.5ms. Debounce The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored inputs have digital filtering/debounce logic on board for high noise immunity. AC-hysteresis AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#11) to avoid undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the voltage ripple across the bulk capacitor. c u d e t le ) s ( ct o r P o s b O - u d o r P e t e l o Vdd-OVP ) s t( Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#9) are latched high. Vdd-UVL To prevent false signals of any of IC’s output pins, an under voltage lock-out circuit monitors Vdd and keeps all IC’s output at their default OFF level until Vdd reaches a sufficient minimum voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and volatile programming memory cleared. Dual-OVP Dmon (#8) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and DFAULT (#9) are latched high. Dual-UVP Dmon (#8) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is latched high and Cout (#6) is pulled low. s b O 5/28 L6611 FUNCTION DESCRIPTION (continued) Name Description Soft-start The IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A error amplifier reference voltage, in order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up. In fact, if this reference gets the nominal value as soon as the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus forcing PWM to work with the maximum duty-cycle. Bounce or Latch-mode This option allows setting either latched-mode or auto restart after 1 second delay in case of undervoltage faults. ABSOLUTE MAXIMUM RATINGS Symbol Vdd Parameter Supply voltage Voltage on PROG, PS-ON/Clock, DFAULT, VREF, and error amplifier pins Symbol Max. Thermal Resistance junction-to-ambient (*) r P e (*) mounted on board t e l o s b O 6/28 u d o Parameter V 10 mA -25 to 150 °C -50 to 150 °C 300 °C b O - Lead Temperature (soldering, 10 seconds) Rth j-amb so Storage Temperature ) s ( ct uc ) s t( V d o r P e let Operating Junction Temperature THERMAL DATA V -16 to +5 Maximum current in ESD clamp diodes TL -0.5 to +7 -0.5 to +16 Voltage on and -12V UV/OV sense pin TSTO Unit -0.5 to Vdd+0.5 Voltage on MFAULT, PW-OK, Dmon and positive UV, OV, OC, AC sense pins. TJ Value V DIP20 SO20 Unit 70 120 °C/W L6611 ELECTRICAL CHARACTERISTCS (unless otherwise specified: TJ = 0 to 105°C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol Parameter Test Condition Min. Typ. Max. Unit 4.2 4.3 4.6 V 3.7 3.8 4.1 V SUPPLY SECTION VDD(ON) Start-up threshold VDD(OFF) Minimum operating voltage after turn-on VDD(H) Hysteresis 0.25 0.5 0.75 V VDDOV Vdd overvoltage 6.1 6.3 6.8 V IDD-ON Operating supply current 5 7 mA No Fault FAULT THRESHOLDS Vout = 3.3V UV 3V3 undervoltage 2.80 OV 3V3 overvoltage 4.00 uc 3.00 V 4.30 V 50 65 µA 10.60 10.80 11.00 V 13.50 14.00 14.50 V 100 130 µA -9.00 -9.50 -10.0 V -14.4 -15.0 -15.6 V 1.3 1.5 1.7 V -65 -50 3V3 undervoltage 2.80 2.90 3.00 V 3V3 overvoltage 4.00 4.15 4.30 V 3V3 bias current e t le Vout = 12V UV 12V undervoltage OV 12V overvoltage 12V bias current Vout = -12V UV -12V undervoltage OV -12V overvoltage VD -12V disable voltage u d o r P e -12V bias current ) s ( ct o s b O - Voltage to disable comparator t e l o Pr 2.90 ) s t( od 4.15 µA Vout = 3.3V Aux/Dual (Dmon option) UV bs OV O Vout = 5V Aux/Dual (Dmon option) UV 5V undervoltage 4.25 4.40 4.55 V OV 5V overvoltage 6.00 6.25 6.50 V 50 65 µA 5 10 µA Bias current ACsense / Hysteresis Bias current VACsns = 2.7V 7/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105°C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol UV Parameter Test Condition AC undervoltage Trim range Min. Typ. Max. Unit 2.375 2.50 2.625 V +5 % -5 Trim resolution IACH HS 0.64 Hysteresis current 20 Hysteresis trim range -20 Hysteresis adjust step 50 % 80 µA +20 % 5 % FAULT OUTPUTS VPOKH PW-OK high state No faults VPOKL PW-OK low state ISINK = 15mA MFAULT high state leakage PS-ON = high MFAULT sink current PS-ON = low, VMFAULT = 4V MFAULT OV debounce Minimum OV pulse before MFAULT is latched. MFAULT debounce ±12V UV Minimum UV pulse before MFAULT is latched. MFAULT debounce +5V, 3V3, UV Minimum UV pulse before MFAULT is latched. IL MFISNK 3 ) s t( V V 1 µA c u d ro 10 15 mA 6 8 µs 4 6 8 µs 250 450 650 µs Overvoltage condition VDFAULT = 1.5V -25 -50 -95 mA IDFAULT = 0mA, Tamb = 25oC, Overvoltage condition 2.1 2.4 2.7 V 0.3 0.5 0.7 V ) s ( ct 6 0.4 P e let o s b O - 4 DFIOH DFAULT output high source current DFVOH DFAULT output high voltage VOUT DFAULT output low voltage IDFAULT = 1mA, no faults DFAULT OV debounce Minimum OV pulse before DFAULT is latched. 4 6 8 µs Minimum UV pulse before DFAULT is latched. 250 450 650 µs u d o r P e t e l o DFAULT UV debounce s b O START-UP / SHUTDOWN FUNCTIONS t5 DFAULT UV blanking delay Delay from VDD(on) to DFAULT UV active. 44 64 84 ms t1 MFAULT UV blanking delay Delay from ACSNS high to Main UV active 44 64 84 ms t2 PW-OK blanking delay Main’s UV good to PW-OK high 175 250 325 ms PS-ON delay time Delay from PS-ON input to MFAULT 1.75 2.5 3.25 ms t4 (tDELAY) 8/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105°C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol Parameter VIH PS-ON Input High Voltage VIL PS-ON Input Low Voltage Test Condition Min. Typ. Max. 2.0 IIN = -200µA Unit V 0.8 PS-ON Input high clamp IPS-ON = 100 µA PS-ON Pull-up to VDD VPS-ON = 0V 25 50 100 KΩ t3 PS-ON debounce PS-ON input minimum pulse width for a valid logic change. 50 75 100 ms tSS Error Amp. A Soft-Start period VFB quasi-monothonic ramp from 0 to 2.5V 8 Soft Start Step Ramp 0V to 2.5V 39 RPS-ON VSTEP Vdd +0.7 V ISC Output Voltage IREF = 1 - 5 mA; CREF = 47nF Short circuit current VREF = 0 e t le MAIN CONVERTER FEEDBACK (ERROR AMPLIFIER A) VFB Input Voltage T j = 25° C Trim Range About nominal Trim resolution ZFB ) s ( ct Divider impedance Temperature coefficient W5 u d o Divider 5/12 weighting r P e AVOL Voltage gain GBW Unity gain bandwidth t e l o 2.375 o s b O - from Ainv to GND. 5V and 12V connected to GND. ) s t( mV 2.50 2.625 V 10 20 mA 2.50 2.625 V +5 % o r P 2.375 ms c u d VOLTAGE REFERENCE (BUFFERED EXTERNAL PIN) VREF V -5 0.64 35 50 % 65 Ω/°C 26 5V contribution to 5/12 feedback 47 2V