DATASHEET
ISL80102, ISL80103
FN6660
Rev.9.02
Jun 11, 2020
High Performance 2A and 3A Linear Regulators
Features
The ISL80102 and ISL80103 are low voltage, high-current,
single output LDOs specified for 2A and 3A output current,
respectively. These LDOs operate from the input voltages of
2.2V to 6V and are capable of providing the output voltages of
0.8V to 5.5V.
• Stable with ceramic capacitors (Note 11)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
An external capacitor on the soft-start pin provides adjustment
for applications that demand inrush current less than the
current limit. The ENABLE feature allows the part to be placed
into a low quiescent current shutdown mode. A submicron
BiCMOS process is used for this product family to deliver
best-in-class analog performance and overall value.
• ±1.8% VOUT accuracy assured over line, load, and TJ = -40°C
to +125°C
• Very low 120mV dropout voltage at 3A (ISL80103)
• Very fast transient response
• Excellent 62dB PSRR
These CMOS (LDOs) consume significantly lower quiescent
current as a function of load over bipolar LDOs, so they are
more efficient and allow packages with smaller footprints. The
quiescent current has been modestly compromised to enable
a leading class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
• 49µVRMS output noise
• Power-good output
• Adjustable inrush current limiting
• Short-circuit and over-temperature protection
• Available in a 10 Ld DFN
Related Literature
Applications
For a full list of related documents, visit our website
• Servers
• ISL80102, ISL80103 product pages
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Routers and switchers
ISL80102, ISL80103
2.5V ±10%
VIN
9
CIN
10
10µF
1.8V
VIN
VOUT
VIN
VOUT
1
2
VOUT
COUT
10µF
RPG
100kΩ
R1
10kΩ
4
7
EN
OPEN DRAIN COMPATIBLE
6
*CSS
PGOOD
PG
ENABLE
**CPB
SS
GND
ADJ
3
47pF
5
R3
2.61kΩ
R4
1.0kΩ
*CSS is optional (see Note 12 on page 5).
**CPB is optional (see “Functional Description” on page 12 for more information).
FIGURE 1. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION
FN6660 Rev.9.02
Jun 11, 2020
Page 1 of 16
ISL80102, ISL80103
Pin Descriptions
TABLE 1. COMPONENTS VALUE SELECTION
VOUT
(V)
RTOP
(kΩ)
RBOTTOM
(Ω)
CPB
(pF)
COUT
(µF)
PIN
NUMBER
PIN
NAME
5.0
2.61
287
47
10
1, 2
VOUT
Output voltage pin
3.3
2.61
464
47
10
3
ADJ
ADJ pin for externally set VOUT.
2.5
2.61
649
47
10
4
PG
1.8 (Note 1)
2.61
1.0k
47
10
VOUT in regulation signal. Logic low defines when
VOUT is not in regulation. Must be grounded if not
used.
1.8 (Note 1)
2.61
1.0k
82
22
5
GND
1.5
2.61
1.3k
82
22
6
SS
1.2
2.61
1.87k
150
47
1.0
2.61
2.61k
150
47
0.8
2.61
4.32k
150
47
7
NOTE:
1. Either option can be used depending on cost/performance
requirements
GND pin
External cap adjusts inrush current. Leave this pin
open if not used.
ENABLE VIN independent chip enable. TTL and CMOS
compatible.
8
DNC
Do not connect this pin to ground or supply. Leave
floating.
9, 10
VIN
Input supply pin
EPAD
Pin Configuration
10 LD 3x3 DFN
TOP VIEW
DESCRIPTION
EPAD must be connected to a copper plane with as
many vias as possible for proper electrical and
optimal thermal performance.
Block Diagram
VOUT
1
VOUT
2
ADJ
3
PG
4
7 ENABLE
GND
5
6 SS
10 VIN
9 VIN
EPAD
8 DNC
VIN
R5
10µA
10µA
IL/10000
M4
M5
M3
M1
POWER PMOS
IL
VOUT
+
R8
R7
M6
-
R9
EN
+
EN
EN
ENABLE
R1
500mV
R4
EN
ADJ
+
-
M7
V TO I
SS
M8
EN
500mV
-
+
-
+
485mV
+
-
PG
M2
*R3
GND
*R3 is open for ADJ versions.
FIGURE 2. BLOCK DIAGRAM
FN6660 Rev.9.02
Jun 11, 2020
Page 2 of 16
ISL80102, ISL80103
Ordering Information
PART NUMBER
(Notes 2, 4, 4)
PART
MARKING
VOUT
VOLTAGE
TEMP. RANGE
(°C)
TAPE AND REEL
(Units) (Note 1)
PACKAGE
(RoHS COMPLIANT)
PKG
DWG. #
ISL80102IRAJZ
DZJA
ADJ
-40 to +125
-
10 Ld 3x3 DFN
L10.3x3
ISL80102IRAJZ-T
DZJA
ADJ
-40 to +125
6k
10 Ld 3x3 DFN
L10.3x3
ISL80102IRAJZ-TK
DZJA
ADJ
-40 to +125
1k
10 Ld 3x3 DFN
L10.3x3
ISL80102IRAJZ-T7A
DZJA
ADJ
-40 to +125
250
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ
DZAA
ADJ
-40 to +125
-
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ-T
DZAA
ADJ
-40 to +125
6k
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ-TK
DZAA
ADJ
-40 to +125
4k
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ-T7A
DZAA
ADJ
-40 to +125
250
10 Ld 3x3 DFN
L10.3x3
ISL80102EVAL2Z
Evaluation Board
ISL80103EVAL2Z
Evaluation Board
NOTES:
2. See TB347 for details about reel specifications.
3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see the ISL80102 and ISL80103 product information pages. For more information about MSL, see TB363.
FN6660 Rev.9.02
Jun 11, 2020
Page 3 of 16
ISL80102, ISL80103
Absolute Maximum Ratings (Note 8)
Thermal Information
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, ADJ, SS, Relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F). . . . . . . . . . . . . . .2.2kV
Charge Device Model (Tested per JESD22-C101C) . . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Ld 3x3 DFN Package (Notes 5, 6) . . . .
45
4
θJB at Pin 3 (Note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W
θJB at Pin 5 (Note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.9°C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5.5V
PG, ENABLE, ADJ, SS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJB, the board temperature is taken on the board near the edge of the package, on a copper trace at either lead #3 or lead #5, as applicable. See
TB379
8. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Refer to “Functional Description” on page 12 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure TJ = TA defines established limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
2.2V < VIN < 6V; ILOAD = 0A
2.2V < VIN < 6V; 0A < ILOAD < 3A
0.5
-1.8
2.9V < VIN < 6V; ILOAD = 0A
Feedback Pin
DC Input Line Regulation
DC Output Load Regulation
VADJ
(VOUT Low Line - VOUT
High Line)/
VOUT Low Line
(VOUT No Load - VOUT
High Load)/
VOUT No Load
Feedback Input Current
Ground Pin Current
Ground Pin Current in Shutdown
FN6660 Rev.9.02
Jun 11, 2020
IQ
ISHDN
%
1.8
0.5
2.9V < VIN < 6V; 0A < ILOAD < full load
-1.8
0A < ILOAD < full load
491
2.2V < VIN < 3.6V, VOUT = 1.8V
-0.4
2.9V < VIN < 6V, VOUT = 2.5V
%
%
-1.8
%
500
509
mV
0.1
0.4
%
-0.8
0.1
0.8
%
ISL80103, 0A < ILOAD < 3A,
2.9V < VIN < 6V; VOUT = 2.5V
-0.8
-0.2
0.8
%
ISL80102, 0A < ILOAD < 2A
2.9V < VIN < 6V; VOUT = 2.5V
-0.6
-0.2
0.6
%
VADJ = 0.5V
0.01
1
µA
ILOAD = 0A, VOUT + 0.4V < VIN < 6V
VOUT = 2.5V
7.5
9
mA
ILOAD = 3A, VOUT + 0.4V < VIN < 6V
VOUT = 2.5V
8.5
12
mA
EN = 0V, VIN = 5V
0.4
EN = 0V, VIN = 6V
3.3
µA
16.0
µA
Page 4 of 16
ISL80102, ISL80103
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Refer to “Functional Description” on page 12 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)
PARAMETER
Dropout Voltage (Note 10)
Output Short-Circuit Current
(3A Version)
TYP
MAX
(Note 9)
UNIT
ISL80103, ILOAD = 3A, VOUT = 2.5V
120
185
mV
ISL80102, ILOAD = 2A, VOUT = 2.5V
81
125
mV
ISL80103, ILOAD = 3A, VOUT = 5.5V
120
244
mV
ISL80102, ILOAD = 2A, VOUT = 5.5V
60
121
mV
ISL80103, VOUT = 0V
5.0
A
ISL80102, VOUT = 0V
2.8
A
SYMBOL
VDO
ISC
Output Short-Circuit Current
(2A Version)
TEST CONDITIONS
MIN
(Note 9)
Thermal Shutdown Temperature
TSD
160
°C
Thermal Shutdown Hysteresis
TSDn
15
°C
55
dB
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
Output Noise Voltage
f = 1kHz, ILOAD = 1A; VIN = 2.2V
f = 120Hz, ILOAD = 1A; VIN = 2.2V
62
dB
VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A,
BW = 100Hz < f < 100kHz
49
µVRMS
ENABLE PIN CHARACTERISTICS
Turn-On Threshold
VEN(HIGH)
2.2V < VIN < 6V
0.616
0.800
Turn-Off Threshold
VEN(LOW)
2.2V < VIN < 6V
0.463
0.600
V
Hysteresis
VEN(HYS)
2.2V < VIN < 6V
135
mV
COUT = 10µF, ILOAD = 1A
150
Enable Pin Turn-On Delay
tEN
VIN = 6V, EN = 3V
Enable Pin Leakage Current
0.950
V
µs
1
µA
SOFT-START CHARACTERISTICS
Reset Pull-Down Resistance
RPD
Soft-Start Charge Current
ICHG
323
Ω
-7.0
-4.5
-2.0
µA
75
84
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
47
100
mV
0.05
1
µA
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value.
11. Minimum cap of 10µF X5R/X7R on VIN and VOUT required for stability.
12. If the current limit for inrush current is acceptable in the application, do not use this feature (leave the SS pin open). Use only when large bulk capacitance
is required on VOUT for the application.
FN6660 Rev.9.02
Jun 11, 2020
Page 5 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A.
2.0
1.8
1.8
OUTPUT VOLTAGE (V)
VOUT (%)
1.2
0.6
0
-0.6
-1.2
1.6
+125°C
1.4
1.2
-40°C
+25°C
1.0
0.8
0.6
0.4
0.2
-1.8
-50
-25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
125
0
150
FIGURE 3. VOUT vs TEMPERATURE
GROUND CURRENT (mA)
+25°C
0.0
-0.6
-40°C
-1.2
6
+125°C
0
0.5
1.0
7
6
5
4
3
2
1
1.5
2.0
2.5
0
3.0
2
3
OUTPUT CURRENT (A)
FIGURE 5. VOUT vs OUTPUT CURRENT
4
INPUT VOLTAGE (V)
9.1
12.0
8.9
11.5
11.0
8.7
-40°C
8.5
8.3
+25°C
8.1
+125°C
7.9
-40°C
10.5
10.0
9.5
+125°C
9.0
+25°C
8.0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
FIGURE 7. GROUND CURRENT vs OUTPUT CURRENT
FN6660 Rev.9.02
Jun 11, 2020
6
8.5
7.7
0
5
FIGURE 6. GROUND CURRENT vs SUPPLY VOLTAGE
CURRENT (mA)
GROUND CURRENT (mA)
5
8
0.6
7.5
3
2
4
SUPPLY VOLTAGE (V)
9
1.2
VOUT (%)
1
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
-1.8
0
3.0
7.5
0.8
1.4
2.0
2.6
3.2
3.8
OUTPUT VOLTAGE (V)
4.4
5.0
FIGURE 8. GROUND CURRENT vs OUTPUT VOLTAGE (VIN = VOUT + VDO)
Page 6 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
5.0
12
11
10
9
8
7
6
5
4.0
GROUND CURRENT (µA)
GROUND CURRENT (µA)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
VIN = 5V
0.5
0.0
-40 -25 -10
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
95
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
FIGURE 10. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
DROPOUT VOLTAGE (mV)
150
140
130
120
110
2A
100
3A
90
80
70
60
50
40
30
20
1A
10
0
-40 -25 -10
5 20 35 50 65 80
TEMPERATURE (°C)
VIN = 6V
0
-40 -25 -10
FIGURE 9. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
DROPOUT VOLTAGE (mV)
4
3
2
1
110 125
FIGURE 11. DROPOUT VOLTAGE vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 12. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
VOLTAGE (V)
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
-40 -25 -10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 13. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
FN6660 Rev.9.02
Jun 11, 2020
Page 7 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
EN (1V/DIV)
EN (1V/DIV)
SS (500mV/DIV)
SS (200mV/DIV)
VOUT (500mV/DIV)
PG (1V/DIV)
VOUT (500mV/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (6.4ms/DIV)
FIGURE 14. ENABLE START-UP SS CAP 1nF
FIGURE 15. ENABLE SHUTDOWN SS CAP 1nF
EN (1V/DIV)
EN (1V/DIV)
SS (1V/DIV)
SS (200mV/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
VOUT (500mV/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (2ms/DIV)
FIGURE 16. ENABLE START-UP SS CAP 100nF
FIGURE 17. ENABLE START-UP (NO SS CAP)
300
EN (1V/DIV)
SS (1V/DIV)
VOUT (1V/DIV)
START-UP TIME (µs)
250
200
150
100
50
PG (1V/DIV)
TIME (5ms/DIV)
FIGURE 18. ENABLE SHUTDOWN (NO SS CAP)
FN6660 Rev.9.02
Jun 11, 2020
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
FIGURE 19. START-UP TIME vs SUPPLY VOLTAGE
Page 8 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
300
OUTPUT CURRENT (A)
START-UP TIME (µs)
250
200
150
100
50
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
FIGURE 20. START-UP TIME vs TEMPERATURE
OUTPUT CURRENT (A)
ISL80103
ISL80102
-40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FIGURE 21. CURRENT LIMIT vs TEMPERATURE
IOUT (1A/DIV)
ISL80103
ISL80102
VOUT (1V/DIV)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE(V)
FIGURE 22. CURRENT LIMIT vs SUPPLY VOLTAGE
TIME (10ms/DIV)
FIGURE 23. CURRENT LIMIT RESPONSE (ISL80102)
EN (1V/DIV)
IOUT (2A/DIV)
IINRUSH (2A/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (5ms/DIV)
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80103)
FN6660 Rev.9.02
Jun 11, 2020
PG (1V/DIV)
TIME (200µs/DIV)
FIGURE 25. INRUSH CURRENT WITH NO SOFT-START CAPACITOR,
COUT = 1000µF
Page 9 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
EN (1V/DIV)
VOUT (50mV/DIV)
IINRUSH (1A/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
TIME (1ms/DIV)
FIGURE 26. INRUSH WITH 22nF SOFT-START CAPACITOR,
COUT = 1000µF
VOUT (50mV/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 28. LOAD TRANSIENT 0A TO 3A, COUT = 10µF
CERAMIC + 100µF OSCON
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 27. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC
VOUT (50mV/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 29. LOAD TRANSIENT 1A TO 3A, COUT = 10µF CERAMIC
VOUT (20mV/DIV)
VOUT (50mV/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
di/dt = 3A/µs
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 1A TO 3A, COUT = 10µF
CERAMIC + 100µF OSCON
FN6660 Rev.9.02
Jun 11, 2020
TIME (50µs/DIV)
FIGURE 31. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,
NO CPB
Page 10 of 16
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
3.2V
2.2V
VOUT (20mV/DIV)
VIN (1V/DIV)
di/dt = 3A/sec
IOUT (2A/DIV)
VOUT (10mV/DIV)
di/dt = 3A/µs
TIME (200µs/DIV)
TIME (50µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,
CPB = 1500pF
FIGURE 33. LINE TRANSIENT
90
90
80
80
100mA
70
PSRR (dB)
PSRR (dB)
60
NO LOAD
60
50
40
30
1000mA
300mA
20
50
100mA
40
30
1000mA
20
10
100
1k
10k
100k
0
10
1M
100
1k
FIGURE 34. PSRR vs FREQUENCY FOR VOUT = 1.0V, VIN = 2.5V;
COUT = 47µF, CPB = 150pF
90
300mA
80
100k
1M
FIGURE 35. PSRR vs FREQUENCY FOR VOUT = 1.2V; VIN = 2.5V;
COUT = 47µF, CPB = 150pF
90
100mA
1000mA
80
100mA
70
70
NO LOAD
60
60
PSRR (dB)
NO LOAD
50 2000mA
1000mA
40
30
50
40
20
10
10
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 36. PSRR vs FREQUENCY FOR VOUT = 1.5V, VIN = 2.5V;
COUT = 22µF, CPB = 82pF
FN6660 Rev.9.02
Jun 11, 2020
1M
2000mA
3000mA
30
20
0
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR (dB)
300mA
10
10
0
NO LOAD
70
0
10
300mA
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 37. PSRR vs FREQUENCY FOR VOUT = 1.8V, VIN = 2.5V;
COUT = 22µF, CPB = 82pF
Page 11 of 16
1M
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
90
10
100mA
80
300mA
70
50
2000mA
1000mA
NOISE µV/√Hz
PSRR (dB)
60
NO LOAD
40
30
3000mA
1
0.1
20
10
0
10
IL = 3A
100
1k
10k
100k
0.01
10
1M
100
FREQUENCY (Hz)
FIGURE 38. PSRR vs FREQUENCY FOR VOUT = 2.5V, VIN = 3.3V;
COUT = 10µF, CPB = 47pF
Functional Description
Input Voltage Requirements
This family of LDOs is optimized for a true 2.5V to 1.8V
conversion in which the input supply can have a tolerance of as
much as ±10% for conditions noted in the “Electrical
Specifications” table on page 4. The minimum guaranteed input
voltage is 2.2V; however, due to the nature of an LDO, VIN must
be some margin higher than the output voltage plus dropout at
the maximum rated current of the application if active filtering
(PSRR) is expected from VIN to VOUT. The dropout of this family of
LDOs has been generously specified to allow applications to
design for a level of efficiency that can accommodate the
smaller outline package.
Enable Operation
The Enable turn-on threshold is typically 800mV with a hysteresis of
135mV. This pin must not be left floating. This pin must be tied to
VIN if it is not used. A 1kΩ to 10kΩ pull-up resistor is required for
applications that use open collector or open drain outputs to control
the Enable pin. The Enable pin can be connected directly to VIN for
applications that are always on.
10k
100k
1M
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
Soft-Start Operation (Optional)
If the current limit for inrush current is acceptable in the
application, do not use the soft-start (SS) feature (leave the SS
pin open). The soft-start circuit controls the rate at which the
output voltage comes up to regulation at power-up or LDO
enable. The external soft-start capacitor always gets discharged
to ground pin potential at the beginning of start-up or enabling.
After the capacitor discharges, it will immediately begin charging
by a constant current source. The discharge rate is the RC time
constant of RPD and CSS. Refer to Figures 14 through 18 in the
“Typical Operating Performance Curves” beginning on page 8.
RPD is the ON-resistance of the pull-down MOSFET, M8. RPD is
typically 323Ω.
The soft-start feature effectively reduces the inrush current at
power-up or LDO enable until VOUT reaches regulation. The
in-rush current can be an issue for applications that require large,
external bulk capacitances on VOUT where high levels of charging
current can be seen for a significant period of time. The inrush
currents can cause VIN to drop below minimum which could
cause VOUT to shutdown. Figure 26 on page 10 shows the
relationship between inrush current and CSS with a COUT of
1000µF.
Power-Good Operation
5.0
4.5
INRUSH CURRENT LIMIT (A)
Applications not using the power-good (PGOOD) feature must
connect this pin to ground. The PGOOD flag is an open-drain
NMOS that can sink up to 10mA during a fault condition. The
PGOOD pin requires an external pull-up resistor, which is typically
connected to the VOUT pin. The PGOOD pin should not be pulled
up to a voltage source greater than VIN. PGOOD faults can be
caused by the output voltage going below 84% of the nominal
output voltage, or the current limit fault, or low input voltage.
PGOOD does not function during thermal shutdown.
1k
FREQUENCY (Hz)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
CSS (nF)
80
100
FIGURE 40. INRUSH CURRENT vs SOFT-START CAPACITANCE
FN6660 Rev.9.02
Jun 11, 2020
Page 12 of 16
ISL80102, ISL80103
Output Voltage Selection
Current Limit Protection
An external resistor divider scales the output voltage relative to
the internal reference voltage. This voltage is then fed back to
the error amplifier. The output voltage can be programmed to
any level between 0.8V and 5.5V. An external resistor divider, R3
and R4, sets the output voltage as shown in Equation 1. The
recommended value for R4 is 200Ω to 5kΩR3is then chosen
according to Equation 2:
The ISL80102 and ISL80103 family of LDOs incorporates
protection against overcurrent due to a short overload condition
applied to the output and the inrush current that occurs at
start-up. The LDO performs as a constant current source when
the output current exceeds the current limit threshold noted in
the “Electrical Specifications” table on page 4. If the short or
overload condition is removed from VOUT, then the output returns
to normal voltage mode regulation. In the event of an overload
condition, the LDO may begin to cycle on and off due to the die
temperature exceeding the thermal fault condition.
(EQ. 1)
V OUT
R 3 = R 4 ---------------- – 1
0.5V
(EQ. 2)
External Capacitor Requirements
External capacitors are required for proper operation. To ensure
optimal performance, pay careful attention to the layout
guidelines and selection of capacitor type and value.
OUTPUT CAPACITOR
The ISL80102 and ISL80103 apply state-of-the-art internal
compensation to keep selection of the output capacitor simple
for the customer. Stable operation over full temperature, VIN
range, VOUT range, and load extremes are guaranteed for all
ceramic capacitors and values assuming a 10µF X5R/X7R is
used for local bypass on VOUT. This minimum capacitor (see
Table 1 on page 2 for component value selections) must be
connected to the VOUT and ground pins of the LDO with PCB
traces no longer than 0.5cm.
Lower cost Y5V and Z5U type ceramic capacitors are acceptable
if the size of the capacitor is large enough to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value in Ceramic, POSCAP, or Alum/Tantalum
Electrolytic types can be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output voltage
tolerances.
INPUT CAPACITOR
The minimum input capacitor required for proper operation is a
10µF with a ceramic dielectric. This minimum capacitor must be
connected to VIN and ground pins of the LDO with PCB traces no
longer than 0.5cm.
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10µF or larger ceramic capacitors.
Applications can see improved performance with the addition of
a small ceramic capacitor CPB as shown in Figure 1 on page 1.
The conditions in which CPB may be beneficial are:
• VOUT > 1.5V
• COUT = 10µF
• Tight AC voltage regulation band
CPB introduces phase lead with the product of R3 and CPB that
results in increasing the bandwidth of the LDO. Typical R3 x CPB
should be less than 0.4μs (400ns).
FN6660 Rev.9.02
Jun 11, 2020
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 3:
P D = V IN – V OUT I OUT + V IN I GND
(EQ. 3)
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) determine the
maximum allowable power dissipation as shown in Equation 4:
(EQ. 4)
P D MAX = T J MAX – T A JA
where JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation calculated
in Equation 3, PD , is less than the maximum allowable power
dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 41 shows a curve for the JA
of the DFN package for different copper area sizes.
46
44
JA (°C/W)
R3
V OUT = 0.5V ------- + 1
R4
42
40
38
36
34
2
4
6
8
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 41. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
Thermal Fault Protection
If the die temperature exceeds typically +160°C, the output of
the LDO shuts down until the die temperature can cool down to
typically +145°C. The level of power combined with the thermal
impedance of the package (+48°C/W for DFN) determine if the
junction temperature exceeds the thermal shutdown
temperature.
Page 13 of 16
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest revision.
DATE
REVISION
Jun 11, 2020
9.02
Updated Ordering Information table by removing retired parts, adding tape and reel info, and updated notes.
Removed information throughout the document related to the retired parts.
Added Theta JB information.
CHANGE
Dec 3, 2019
9.01
Updated Links throughout.
Updated Figures 15 and 17.
Updated disclaimer.
Mar 19, 2018
9.00
Added Related Literature section to page 1.
Changed values in Output Voltage Selection section on page 13 from “500Ω to 1kΩ” to “200Ω to 5kΩ”.
Removed About Intersil section and added Renesas disclaimer.
Sep 2, 2016
8.00
Removed Note 8 “Electromigration specification defined as lifetime average junction temperature of +110°C where
max rated DC current = lifetime average current” from Recommended Operating Conditions.
Apr 8, 2016
7.00
Updated Ordering Information table (on page 3), Note 1 to include quantities for tape and reel options.
Changed VOUT range upper limit from “5V to 5.5V” on page 1, in the “Recommended Operating Conditions (Note 7)”
on page 4 and in the “Output Voltage Selection” on page 12
Electrical Spec table test conditions changed from: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
ILOAD = 0A, to: 2.2V < VIN < 6V, VOUT = 0,5V, TJ = +25°C, ILOAD = 0A
Changed Test conditions in “Output Noise Voltage” on page 5 from: ILOAD = 10mA, BW = 300Hz
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