ISL80101IRAJZ-T

DATASHEET ISL80101-ADJ FN7834 Rev 3.00 August 26, 2015 High Performance 1A LDO The ISL80101-ADJ is a low voltage, high current, single output LDO specified at 1A output current. This LDO operates from input voltages from 2.2V to 6V, and is capable of providing output voltages from 0.8V to 5V. The ISL80101-ADJ features an adjustable output. For the fixed output version of the ISL80101-ADJ, please refer to the ISL80101 datasheet. Features A submicron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. This CMOS LDO will consume significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. State of the art internal compensation achieves a very fast load transient response. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. A Power-good logic output signals a fault condition. • Programmable soft-starting Table 1 shows the differences between the ISL80101-ADJ and others in its family: • DSP, FPGA and µP core power supplies TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS PART NUMBER PROGRAMMABLE ILIMIT ILIMIT (DEFAULT) ADJ OR FIXED VOUT ISL80101-ADJ No 1.75A ADJ ISL80101 No 1.75A 1.8V, 2.5V, 3.3V, 5.0V ISL80101A Yes 1.62A ADJ ISL80121-5 Yes 0.75A 5.0V • ±1.8% VOUT accuracy guaranteed over line, load and TJ = -40°C to +125°C • Very low 130mV dropout voltage at VOUT = 2.5V • Very fast transient response • Power-good output • Excellent 65dB PSRR • Current limit protection • Thermal shutdown function • Available in a 10 Ld DFN package • Pb-Free (RoHS compliant) Applications • Noise-sensitive instrumentation systems • Post regulation of switched mode power supplies • Industrial systems • Medical equipment • Telecommunications and networking equipment • Servers • Hard disk drives (HD/HDD) Related Literature • AN1592, “ISL80101 High Performance 1A LDO Evaluation Board User Guide” 10 10µF CIN 9 10k R3 VIN VOUT VIN VOUT ADJ 1 2 82pF CPB 3 1.00k R1 ISL80101-ADJ 7 6 0.01µF CSS ENABLE PG 2.61k R2 4 SS GND 5 1.8V 140 10µF COUT 120 100k RPG DROPOUT VOLTAGE (mV) 2.5V ± 10% 100 80 60 40 20 0 VOUT = 2.5V 0 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) FIGURE 1. TYPICAL APPLICATION CIRCUIT FN7834 Rev 3.00 August 26, 2015 FIGURE 2. DROPOUT vs LOAD CURRENT Page 1 of 12 ISL80101-ADJ Block Diagram VIN EN CONTROL LOGIC EA REFERENCE + SOFT-START THERMAL SENSOR PG PG + FET DRIVER WITH CURRENT LIMIT VOUT SS ADJ + - GND Ordering Information PART NUMBER (Notes 3, 4) PART MARKING ISL80101IRAJZ (Note 1) DZAB ISL80101EVAL2Z Evaluation Board VOUT VOLTAGE (Note 2) TEMP RANGE (°C) ADJ -40 to +125 PACKAGE (RoHS Compliant) 10 Ld 3x3 DFN PKG DWG. # L10.3x3 NOTES: 1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil Marketing. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see product information page for ISL80101-ADJ. For more information on MSL please see techbrief TB363. FN7834 Rev 3.00 August 26, 2015 Page 2 of 12 ISL80101-ADJ Pin Configurations ISL80101-ADJ (10 LD 3x3 DFN) TOP VIEW VOUT 1 10 VIN VOUT 2 ADJ 3 PG 4 GND 5 9 VIN EPAD 8 NC 7 ENABLE 6 SS Pin Descriptions PIN NUMBER PIN NAME 1, 2 VOUT Regulated output voltage. A X5R/X7R output capacitor is required for stability. See “External Capacitor Requirements” on page 8 for more details. 3 ADJ This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the output voltage. In addition, the PGOOD circuit uses this input to monitor the output voltage status. 4 PG This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not in regulation. Must be grounded if not used. 5 GND 6 SS 7 ENABLE 8 NC No connection; Leave floating. 9, 10 VIN Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External Capacitor Requirements” on page 8 for more details. - EPAD FN7834 Rev 3.00 August 26, 2015 DESCRIPTION Ground External capacitor on this pin adjusts start-up ramp and controls inrush current. VIN independent chip enable. TTL and CMOS compatible. EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. Page 3 of 12 ISL80101-ADJ Absolute Maximum Ratings Thermal Information VIN Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V PG, ENABLE, ADJ, SS Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV Latch-up (Tested per JESD78C, Class 2, Level A) . . . . ±100mA at +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld DFN Package (Notes 6, 7) . . . . . . . . 48 7 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions (Notes 8, 9) Junction Temperature Range (TJ) (Note 8) . . . . . . . . . . . .-40°C to +125°C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V PG, ENABLE, ADJ, SS relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .