DATASHEET
ISL8014A
4A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator
FN7525
Rev 2.00
December 16, 2014
The ISL8014A is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 4A
continuous output current from a 2.8V to 5.5V input supply. It
uses a current control architecture to deliver very low duty
cycle operation at high frequency with fast transient response
and excellent loop stability.
Features
The ISL8014A integrates a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency and
minimize external component count. The 100% duty-cycle
operation allows less than 400mV dropout voltage at 4A
output current. High 1MHz pulse-width modulation (PWM)
switching frequency allows the for use of small external
components and the SYNC input enables multiple ICs to
synchronize out-of-phase to reduce ripple and eliminate beat
frequencies.
• 3% output accuracy over-temperature/load/line
The ISL8014A can be configured for discontinuous or forced
continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides high efficiency by reducing
switching losses at light loads.
• Selectable forced PWM mode and PFM mode
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions, an
output overvoltage comparator and over-temperature monitor
circuit. A power-good output voltage monitor indicates when
the output is in regulation.
• Internal current mode compensation
The ISL8014A is offered in a space saving 4mmx4mm QFN,
lead free package with exposed pad lead frames for low
thermal resistance.
• High efficiency synchronous buck regulator with up to 97%
efficiency
• Power-good (PG) output with a 1ms delay
• 2.8V to 5.5V supply voltage
• 4A output current
• Pin compatible to ISL8013A
• Start-up with prebiased output
• Internal soft-start - 1ms
• Soft-stop output discharge during disabled
• 35µA quiescent supply current in PFM mode
• External synchronization up to 4MHz
• Less than 1µA logic controlled shutdown current
• 100% maximum duty cycle
• Peak current limiting and hiccup mode short-circuit
protection
• Over-temperature protection
• Small 16 Ld 4mmx4mm QFN
• Pb-Free (RoHS compliant)
Applications
The ISL8014A offers a 1ms power-good (PG) timer at
power-up. When shutdown, ISL8014A discharges the output
capacitor. Other features include internal soft-start, internal
compensation, overcurrent protection, and thermal shutdown.
• DC/DC POL modules
The ISL8014A is offered in a 16 Ld 4mmx4mm QFN package
with 1mm maximum height. The complete converter occupies
less than 0.4in2 area.
• Portable instruments
• µC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Test and measurement systems
• Li-ion battery powered devices
• Small form factor (SFP) modules
• Barcode readers
FN7525 Rev 2.00
December 16, 2014
Page 1 of 16
ISL8014A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP.
RANGE
(°C)
PART
MARKING
ISL8014AIRZ
80 14AIRZ
ISL8014AEVAL2Z
Evaluation Board
PACKAGE
(Pb-Free)
-40 to +85
16 Ld 4x4 QFN
PKG.
DWG. #
L16.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8014A. For more information on MSL please see tech brief TB363.
Pin Configuration
NC
LX
LX
NC
ISL8014A
(16 LD QFN)
TOP VIEW
16
15
14
13
VIN 1
12 PGND
VIN 2
11 PGND
PAD
10 SGND
VDD 3
5
6
7
8
NC
PG
VFB
9
EN
SYNCH 4
SGND
REFER TO APPLICATION NOTE AN1366 FOR MORE LAYOUT SUGGESTIONS.
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VIN
Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
3
VDD
Input supply voltage for the analog circuitry. Connect to VIN pin.
5
EN
Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output
capacitor when driven to low. Do not leave this pin floating.
7
PG
1ms timer output. At power-up or EN HI, this output is a 1ms delayed power-good signal for the output
voltage.
4
SYNCH
Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the negative
edge trigger. Do not leave this pin floating.
14, 15
LX
11, 12
PGND
Power ground
9, 10
SGND
Signal ground
8
VFB
Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output
voltage. For 0.8V output voltage, connect this pin to the output.
6, 13, 16
NC
No connect
-
Exposed Pad
FN7525 Rev 2.00
December 16, 2014
Switching node connection. Connect to one terminal of the inductor.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as much
vias as possible under the pad connecting to SGND plane for optimal thermal performance.
Page 2 of 16
ISL8014A
Typical Application
INPUT
2.8V TO 5.5V
VIN
LX
OUTPUT
1.8V
L
1.5µH
C2
2 x 22µF
VDD
C1
2 x 22µF
R2
124k
PGND
C3
47pF
ISL8014A
EN
R1
100k
VFB
R3
100k
PG
SYNCH
SGND
Block Diagram
SYNCH
SOFT
Soft
START
27pF
SHUTDOWN
390k
SHUTDOWN
BANDGAP 0.8V
+
EN
VIN
OSCILLATOR
+
COMP
-
EAMP
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
3pF
+
LX
PGND
VFB
SLOPE
Slope
COMP
6k
+
0.736V
PG
-
1ms
DELAY
SGND
+
CSA
+
OCP
-
1.4V
+
SKIP
-
0.5V
ZERO-CROSS
SENSING
0.2V
FN7525 Rev 2.00
December 16, 2014
SCP
+
Page 3 of 16
ISL8014A
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
LX . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V
Thermal Resistance (Typical, Notes 4, 5)
JA (°C/W) JC (°C/W)
16 Ld 4x4 QFN Package . . . . . . . . . . . . .
39
3
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established across the recommended operating conditions and
the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are
at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
MIN
(Note 7) TYP (Note 7)
UNITS
INPUT SUPPLY
VDD Undervoltage Lockout Threshold
Quiescent Supply Current
Shut Down Supply Current
VUVLO
IVIN
ISD
Rising, no load
-
2.6
2.8
V
Falling, no load
2.15
2.35
-
V
SYNCH = GND, no load at the output
-
35
-
µA
SYNCH = GND, no load at the output and no switches
switching
-
30
45
µA
SYNCH = VDD, fSW = 1MHz, no load at the output
-
6.5
10
mA
VIN = 5.5V, EN = low
-
0.1
2
µA
0.790
0.8
0.810
V
VFB = 0.75V
-
0.1
-
µA
VIN = VO + 0.5V to 5.5V (minimal 2.8V)
-
0.2
-
%/V
-
1
-
ms
OUTPUT REGULATION
Reference Voltage
VREF
VFB Bias Current
IVFB
Line Regulation
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
-
17
-
Clock pulses
Overcurrent and Auto Restart Period
tOCOFF
-
4
-
SS cycle
Switch Current Limit
ILIMIT
(Note 6)
4.9
6.0
7.1
A
Peak Skip Limit
ISKIP
(Note 6)
-
1.3
-
A
-
20
-
µA/V
0.17
0.20
0.23
Ω
VIN = 5V, IO = 200mA
-
50
75
mΩ
VIN = 2.8V, IO = 200mA
-
70
100
mΩ
COMPENSATION
Error Amplifier Transconductance
Trans-Resistance
RT
LX
P-Channel MOSFET ON-Resistance
FN7525 Rev 2.00
December 16, 2014
Page 4 of 16
ISL8014A
Electrical Specifications
Unless otherwise noted, all parameter limits are established across the recommended operating conditions and
the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are
at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
N-Channel MOSFET ON-resistance
TEST CONDITIONS
-
50
75
mΩ
VIN = 2.8V, IO = 200mA
-
70
100
mΩ
-
100
-
%
0.80
1.0
1.20
MHz
SYNCH = High
-
-
140
ns
Sinking 1mA
-
-
0.3
V
0.65
1
1.35
ms
-
0.01
0.1
µA
fSW
LX Minimum On-time
UNITS
VIN = 5V, IO = 200mA
LX Maximum Duty Cycle
PWM Switching Frequency
MAX
MIN
(Note 7) TYP (Note 7)
PG
Output Low Voltage
Delay Time (Rising Edge)
PG Pin Leakage Current
PG = VIN = 3.6V
PGOOD Rising Threshold
Percentage of regulation voltage
89
92
95
%
PGOOD Falling Threshold
Percentage of regulation voltage
85
88
91
%
-
15
-
µs
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
-
0.1
1
µA
-
0.1
1
µA
Thermal Shutdown
-
140
-
°C
Thermal Shutdown Hysteresis
-
25
-
°C
PGOOD Delay Time (Falling Edge)
EN, SYNCH
Synch Logic Input Leakage Current
ISYNCH
Enable Logic Input Leakage Current
IEN
Pulled up to 5.5V
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7525 Rev 2.00
December 16, 2014
Page 5 of 16
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A .
100
100
90
2.5VOUT-PWM
80
EFFICIENCY (%)
EFFICIENCY (%)
90
1.8VOUT-PWM
1.5VOUT-PWM
70
1.2VOUT-PWM
60
50
1.8VOUT-PFM
70
60
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
40
0.0
4.0
1.0
90
0.9
2.5VOUT-PWM
70
1.8VOUT-PWM
EFFICIENCY (%)
100
80
1.5VOUT-PWM
3.3VOUT-PWM
0.1
0.2
0.3
0.4
0.5
0.6
0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
FIGURE 2. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
FIGURE 1. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM)
1.2VOUT-PWM
60
50
0.8 2.5VOUT-PFM
3.3VOUT-PFM
1.5VOUT-PFM
1.8VOUT-PFM
0.7
1.2VOUT-PFM
0.6
0.5
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.4
0.0
4.0
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
POWER DISSIPATION (mW)
1.50
1.25
1.00
3.3VIN-PFM
5VIN-PWM
0.75
0.25
0
0.0
0.2
0.3
0.4
0.5
0.6
0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
125
1.75
0.50
0.1
FIGURE 4. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
2.00
POWER DISSIPATION (W)
1.5VOUT-PFM 1.2VOUT-PFM
50
40
0.0
EFFICIENCY (%)
2.5VOUT-PFM
80
3.3VIN-PWM
5VIN-PFM
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
FIGURE 5. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
FN7525 Rev 2.00
December 16, 2014
100
75
50
25
0
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
FIGURE 6. POWER DISSIPATION WITH NO LOAD vs VIN
(PWM VOUT = 1.8V)
Page 6 of 16
5.5
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A . (Continued)
1.24
1.23
OUTPUT VOLTAGE (V)
0.20
0.15
0.10
0.05
0
2.0
3.3VIN-PWM
1.21
1.20
1.19
5VIN-PFM
1.18
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
1.16
0.0
5.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 8. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.55
1.83
1.53
1.82
3.3VIN-PFM
3.3VIN-PWM
1.52
1.51
1.50
5VIN-PFM
1.49
5VIN-PWM
3.3VIN-PFM
5VIN-PWM
1.81
1.80
1.79
1.78 3.3V
IN-PWM
5VIN-PFM
1.77
1.76
1.47
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.75
0.0
4.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
2.52
3.0
3.36
3.35
3.3VIN-PFM
3.3VIN-PWM
OUTPUT VOLTAGE (V)
2.50
2.5
FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
2.51
4.0
OUTPUT LOAD (A)
1.48
OUTPUT VOLTAGE (V)
5VIN-PWM
FIGURE 7. POWER DISSIPATION WITH NO LOAD vs VIN
(PFM VOUT = 1.8V)
1.54
OUTPUT VOLTAGE (V)
1.22 3.3V
IN-PFM
1.17
OUTPUT VOLTAGE (V)
POWER DISSIPATION (mW)
0.25
2.49
2.48
2.47
5VIN-PWM
2.46
2.45
2.44
0.0
5VIN-PFM
0.5
4.5VIN-PWM
5VIN-PWM
3.34
3.33
3.32
3.31
3.30
4.5VIN-PFM
5VIN-PFM
3.29
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
FN7525 Rev 2.00
December 16, 2014
4.0
3.28
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT LOAD (A)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
Page 7 of 16
4.0
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A . (Continued)
1.83
1.83
1.82
0A LOAD PWM
4A LOAD PWM
1.81
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.82
1.80
1.79
1.78
1.77
0A LOAD
1.80
1.79
1.78
1.77
1.76
1.76
1.75
2.0
4A LOAD
1.81
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.75
2.0
2.5
FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN
(PWM VOUT = 1.8 )
LX 2V/DIV
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN
(PFM VOUT = 1.8V)
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
FIGURE 15. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PFM)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 17. STEADY STATE OPERATION WITH FULL LOAD
FN7525 Rev 2.00
December 16, 2014
IL 1A/DIV
FIGURE 18. MODE TRANSITION CCM TO DCM
Page 8 of 16
5.5
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A . (Continued)
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 19. MODE TRANSITION DCM TO CCM
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
FIGURE 20. LOAD TRANSIENT (PWM)
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 21. LOAD TRANSIENT (PFM)
EN 5V/DIV
PG 5V/DIV
FIGURE 22. SOFT-START WITH NO LOAD (PWM)
EN 5V/DIV
VOUT 0.5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM)
FN7525 Rev 2.00
December 16, 2014
FIGURE 24. SOFT-START WITH PRE-BIASED 1V
Page 9 of 16
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A . (Continued)
EN 2V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
VOUT 0.5V/DIV
IL 2A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD
FIGURE 26. SOFT-DISCHARGE SHUTDOWN
LX 2V/DIV
LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
FIGURE 27. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FN7525 Rev 2.00
December 16, 2014
VOUT RIPPLE 20mV/DIV
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD (PWM)
WITH FREQUENCY = 4MHz
Page 10 of 16
ISL8014A
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A . (Continued)
LX 2V/DIV
LX 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
VOUT 0.5V/DIV
PG 5V/DIV
PG 5V/DIV
IL 2A/DIV
FIGURE 32. OUTPUT SHORT CIRCUIT RECOVERY
FIGURE 31. OUTPUT SHORT CIRCUIT
5.500
OUTPUT CURRENT (A)
5.375
OCP_3.3VIN
5.250
5.125
5.000
4.875
OCP_5VIN
4.750
4.625
4.500
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 33. OUTPUT CURRENT LIMIT vs TEMPERATURE
FN7525 Rev 2.00
December 16, 2014
Page 11 of 16
ISL8014A
Theory of Operation
VEAMP
The ISL8014A is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed switching frequency under heavy load conditions to
allow smaller external inductors and capacitors to be used for
minimal printed-circuit board (PCB) area. At light load, the regulator
reduces the switching frequency, unless forced to the fixed
frequency, to minimize the switching loss and to maximize the
battery life. The quiescent current when the output is not loaded is
typically only 35µA. The supply current is typically only 0.1µA when
the regulator is shut down.
VCSA
DUTY
CYCLE
IL
VOUT
PWM Control Scheme
FIGURE 34. PWM OPERATION WAVEFORMS
Pulling the SYNCH pin HI (>2.5V) forces the converter into PWM
mode, regardless of output current. The ISL8014A employs the
current-mode pulse-width modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. “Block
Diagram” is shown on page 3. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The gain for the
current sensing circuit is typically 200mV/A. The control reference
for the current loops comes from the error amplifier's (EAMP)
output.
SKIP Mode
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
(237mV/µs) reaches the control reference of the current loop, the
PWM comparator COMP sends a signal to the PWM logic to turn
off the P-MOSFET and turn on the N-Channel MOSFET. The
N-MOSFET stays on until the end of the PWM cycle. Figure 34 on
page 12 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.8V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 27pF and 390kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
Pulling the SYNCH pin LO (
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