ISL8014
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL8014A
DATASHEET
4A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator
The ISL8014 is a high efficiency, monolithic,
synchronous step-down DC/DC converter that can
deliver up to 4A continuous output current from a 2.7V
to 5.5V input supply. It uses a current control
architecture to deliver very low duty cycle operation at
high frequency with fast transient response and
excellent loop stability.
Features
The ISL8014 integrates a pair of low ON-resistance
P-Channel and N-Channel internal MOSFETs to
maximize efficiency and minimize external component
count. The 100% duty-cycle operation allows less than
400mV dropout voltage at 4A output current. High
1MHz pulse-width modulation (PWM) switching
frequency allows the use of small external components
and SYNC input enables multiple ICs to synchronize
out of phase to reduce ripple and eliminate beat
frequencies.
• 4A Output Current
The ISL8014 can be configured for discontinuous or
forced continuous operation at light load. Forced
continuous operation reduces noise and RF
interference while discontinuous mode provides high
efficiency by reducing switching losses at light loads.
Fault protection is provided by internal hiccup mode
current limiting during short circuit and overcurrent
conditions, an output over voltage comparator and
over-temperature monitor circuit. A power good output
voltage monitor indicates when the output is in
regulation.
The ISL8014 is offered in a space saving 4x4 QFN lead
free package with exposed pad lead frames for low
thermal.
The ISL8014 offers a 1ms Power-Good (PG) timer at
power-up. When shutdown, ISL8014 discharges the
output capacitor. Other features include internal
soft-start, internal compensation, overcurrent
protection, and thermal shutdown.
FN6576
Rev 4.00
November 23, 2009
• High Efficiency Synchronous Buck Regulator with
up to 97% Efficiency
• Power-Good (PG) Output with a 1ms Delay
• 2.7V to 5.5V Supply Voltage
• 3% Output Accuracy Over-Temperature/Load/Line
• Pin Compatible to ISL8013
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms
• Soft-Stop Output Discharge During Disabled
• 35µA Quiescent Supply Current in PFM Mode
• Selectable Forced PWM Mode and PFM Mode
• External Synchronization up to 4MHz
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short
Circuit Protection
• Over-Temperature Protection
• Small 16 Ld 4mmx4mm QFN
• Pb-Free (RoHS Compliant)
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
• Test and Measurement Systems
• Li-ion Battery Powered Devices
• Small Form Factor (SFP) Modules
• Bar Code Readers
The ISL8014 is offered in a 16 Ld 4mmx4mm QFN
package with 1mm maximum height. The complete
converter occupies less than 0.4in2 area.
FN6576 Rev 4.00
November 23, 2009
Page 1 of 17
ISL8014
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP.
RANGE
(°C)
PART
MARKING
ISL8014IRZ
80 14IRZ
PACKAGE
(Pb-Free)
-40 to +85
16 Ld 4x4 QFN
PKG.
DWG. #
L16.4x4
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8014. For more information on MSL please see
techbrief TB363.
Pin Configuration
NC
LX
LX
NC
ISL8014
(16 LD QFN)
TOP VIEW
16
15
14
13
VIN 1
12 PGND
VIN 2
11 PGND
VDD 3
10 SGND
5
6
7
8
NC
PG
VFB
Pin Descriptions
9
EN
SYNCH 4
SGND
PIN NUMBER
PIN NAME
1, 2
VIN
Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
3
VDD
Input supply voltage for the analog circuitry. Connect to VIN pin.
5
EN
Regulator enable pin. Keep the EN voltage low in disabled state until VIN settles or is
above 2.5V. Enable the output when driven to high. Shut down the chip and discharge
output capacitor when driven to low. Do not connect directly to VIN or leave this pin
floating.
7
PG
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal
for the output voltage.
4
SYNCH
Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect
to logic low or ground for PFM mode. Connect to an external function generator for
synchronization with the negative edge trigger. Do not leave this pin floating.
14, 15
LX
11, 12
PGND
Power ground
9, 10
SGND
Signal ground.
8
VFB
Buck regulator output feedback. Connect to the output through a resistor divider for
adjustable output voltage. For 0.8V output voltage, connect this pin to the output.
6, 13, 16
NC
No connect.
-
Exposed Pad
FN6576 Rev 4.00
November 23, 2009
DESCRIPTION
Switching node connection. Connect to one terminal of the inductor.
The exposed pad must be connected to the SGND pin for proper electrical performance.
Place as much vias as possible under the pad connecting to SGND plane for optimal
thermal performance.
Page 2 of 17
ISL8014
Typical Application
INPUT 2.7V TO 5.5V
LX
VIN
OUTPUT
1.8V
L
1.5µH
C2
2 x 22µF
VDD
C1
2 x 22µF
R2
124k
PGND
R1
100k
C3
47pF
ISL8014
PG
VFB
R3
100k
EN
SYNCH
SGND
FIGURE 1. TYPICAL APPLICATION DIAGRAM
Block Diagram
SYNCH
SOFT
Soft
START
SHUTDOWN
27pF
SHUTDOWN
390k
-
BANDGAP 0.8V
+
EN
VIN
OSCILLATOR
+
COMP
-
EAMP
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
3pF
+
LX
PGND
VFB
SLOPE
Slope
COMP
6k
+
0.736V -
PG
1ms
DELAY
SGND
+
CSA
+
OCP
-
1.4V
+
SKIP
-
0.5V
ZERO-CROSS
SENSING
0.2V
SCP
+
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN6576 Rev 4.00
November 23, 2009
Page 3 of 17
ISL8014
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN, VDD . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN, SYNCH, PG . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
LX . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance (Typical, Notes 4, 5)JA (°C/W)JC (°C/W)
Recommended Operating Conditions
16 Ld 4x4 QFN Package . . . . . . .
39
3
Junction Temperature Range . . . . . . . . . . -55°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VIN Supply Voltage Range . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameter limits are established over the recommended
operating conditions and the typical specification are measured at the following conditions:
TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7)
UNITS
INPUT SUPPLY
VDD Undervoltage Lockout
Threshold
VUVLO
Quiescent Supply Current
IVIN
Shut Down Supply Current
ISD
Rising, no load
-
2.5
2.7
V
Falling, no load
2.2
2.4
-
V
SYNCH = GND, no load at the output
-
35
-
µA
SYNCH = GND, no load at the output
and no switches switching
-
30
45
µA
SYNCH = VDD, FS = 1MHz, no load at
the output
-
6.5
10
mA
VIN = 5.5V, EN = low
-
0.1
2
µA
0.790
0.8
0.810
V
VFB = 0.75V
-
0.1
-
µA
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
-
0.2
-
%/V
-
1
-
ms
OUTPUT REGULATION
Reference Voltage
VREF
VFB Bias Current
IVFB
Line Regulation
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
-
17
-
Clock pulses
Overcurrent and Auto Restart
Period
tOCOFF
-
4
-
SS cycle
Switch Current Limit
ILIMIT
(Note 6)
4.9
6.0
7.1
A
Peak Skip Limit
ISKIP
(Note 6)
-
1.3
-
A
-
20
-
µA/V
0.17
0.20
0.23
COMPENSATION
Error Amplifier
Trans-Conductance
Trans-Resistance
FN6576 Rev 4.00
November 23, 2009
RT
Page 4 of 17
ISL8014
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameter limits are established over the recommended
operating conditions and the typical specification are measured at the following conditions:
TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7)
UNITS
LX
P-Channel MOSFET
ON-Resistance
VIN = 5V, IO = 200mA
-
50
75
m
VIN = 2.7V, IO = 200mA
-
70
100
m
N-Channel MOSFET
ON-Resistance
VIN = 5V, IO = 200mA
-
50
75
m
VIN = 2.7V, IO = 200mA
-
70
100
m
-
100
-
0.80
1.0
1.20
MHz
SYNCH = High
-
-
140
ns
Sinking 1mA
-
-
0.3
V
0.65
1
1.35
ms
-
0.01
0.1
µA
LX Maximum Duty Cycle
PWM Switching Frequency
fS
LX Minimum On-Time
PG
Output Low Voltage
Delay Time (Rising Edge)
PG Pin Leakage Current
PG = VIN = 3.6V
PGOOD Rising Threshold
Percentage of regulation voltage
89
92
95
%
PGOOD Falling Threshold
Percentage of regulation voltage
85
88
91
%
-
15
-
µs
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
-
0.1
1
µA
-
0.1
1
µA
Thermal Shutdown
-
140
-
°C
Thermal Shutdown Hysteresis
-
25
-
°C
PGOOD Delay Time (Falling Edge)
EN, SYNCH
Synch Logic Input Leakage
Current
ISYNCH
Enable Logic Input Leakage
Current
IEN
Pulled up to 5.5V
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
FN6576 Rev 4.00
November 23, 2009
Page 5 of 17
ISL8014
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A).
100
90
80
70
1.2VOUT-PWM
60
50
2.5VOUT-PFM
80
1.8VOUT-PFM 1.5VOUT-PFM1.2VOUT-PFM
70
60
50
40
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
40
0.0
4.0
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM)
EFFICIENCY (%)
EFFICIENCY (%)
90
2.5VOUT-PWM
1.8VOUT-PWM
1.5VOUT-PWM
100
100
90
90
80
2.5VOUT-PWM
1.8VOUT-PWM 1.5VOUT-PWM
70
3.3VOUT-PWM
1.2VOUT-PWM
60
0.1
0.2
40
0.0
0.9
1.0
80
70
2.5VOUT-PFM 1.8VOUT-PFM
1.2VOUT-PFM
1.5VOUT-PFM
3.3VOUT-PFM
60
0.5
1.0
1.5
2.0
2.5
3.0
3.5
40
0.0
4.0
0.1
0.2
OUTPUT LOAD (A)
3.3VIN-PWM
1.75
1.50
5VIN-PFM
1.00
0.75
3.3VIN-PFM
5VIN-PWM
0.25
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT LOAD (A)
FIGURE 7. POWER DISSIPATION vs LOAD (1MHz,
VOUT = 1.8V)
FN6576 Rev 4.00
November 23, 2009
0.4
0.5
0.6
0.7
0.8
0.9
1.0
4.0
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
125
POWER DISSIPATION (mW)
2.00
1.25
0.3
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
POWER DISSIPATION (W)
0.8
50
50
0.50
0.3 0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
EFFICIENCY (%)
EFFICIENCY (%)
100
100
75
50
25
0
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
FIGURE 8. POWER DISSIPATION WITH NO LOAD vs
VIN (PWM VOUT = 1.8V)
Page 6 of 17
ISL8014
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)
1.24
OUTPUT VOLTAGE (V)
POWER DISSIPATION (mW)
0.25
0.20
0.15
0.10
0.05
1.22 3.3V
IN-PFM
3.3VIN-PWM
1.21
1.20
1.19
5VIN-PFM
1.18
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
1.16
0.0
5.5
3.3VIN-PFM
3.3VIN-PWM
1.52
1.51
1.50
5VIN-PFM
1.49
5VIN-PWM
1.48
2.5
3.0
3.5
4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.80
1.79
1.78
5VIN-PWM
1.77
5VIN-PFM
1.75
0.0
4.0
3.3VIN-PWM
1.81
0.5
1.0
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.5V)
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
4.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.8V)
2.52
3.36
3.3VIN-PFM
OUTPUT VOLTAGE (V)
2.50
2.0
1.82 3.3V
IN-PFM
1.76
1.47
0.0
2.51
1.5
1.83
OUTPUT VOLTAGE (V)
1.53
1.0
FIGURE 10. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.2V)
1.55
1.54
0.5
OUTPUT LOAD (A)
FIGURE 9. POWER DISSIPATION WITH NO LOAD vs
VIN (PFM VOUT = 1.8V)
OUTPUT VOLTAGE (V)
5VIN-PWM
1.17
0
2.0
OUTPUT VOLTAGE (V)
1.23
3.3VIN-PWM
2.49
2.48
2.47
5VIN-PWM
2.46
2.45
2.44
0.0
5VIN-PFM
0.5
1.0
4.5VIN-PWM
5VIN-PWM
3.34
3.33
3.32
3.31
3.30
4.5VIN-PFM
5VIN-PFM
3.29
1.5
2.0
2.5
3.0
3.5
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz,
VOUT = 2.5V)
FN6576 Rev 4.00
November 23, 2009
3.35
4.0
3.28
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT LOAD (A)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz,
VOUT = 3.3V)
Page 7 of 17
4.0
ISL8014
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)
1.830
1.820
0A LOAD PWM
4A LOAD PWM
1.810
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.830
1.800
1.790
1.780
1.770
4A LOAD
1.810
0A LOAD
1.800
1.790
1.780
1.770
1.760
1.760
1.750
2.0
1.820
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.750
2.0
2.5
FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN
(PWM VOUT = 1.8 )
LX 2V/DIV
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN
(PFM VOUT = 1.8V)
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD
(PWM)
FIGURE 18. STEADY STATE OPERATION AT NO LOAD
(PFM)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL
LOAD
FN6576 Rev 4.00
November 23, 2009
IL 1A/DIV
FIGURE 20. MODE TRANSITION CCM TO DCM
Page 8 of 17
ISL8014
Typical Operating Performance
LX 2V/DIV
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)
VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 21. MODE TRANSITION DCM TO CCM
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
FIGURE 22. LOAD TRANSIENT (PWM)
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 23. LOAD TRANSIENT (PFM)
EN 5V/DIV
PG 5V/DIV
FIGURE 24. SOFT-START WITH NO LOAD (PWM)
EN 5V/DIV
VOUT 0.5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT NO LOAD (PFM)
FN6576 Rev 4.00
November 23, 2009
FIGURE 26. SOFT-START WITH PRE-BIASED 1V
Page 9 of 17
ISL8014
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)
EN 2V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
VOUT 0.5V/DIV
IL 2A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 27. SOFT-START AT FULL LOAD
FIGURE 28. SOFT-DISCHARGE SHUTDOWN
LX 2V/DIV
LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD
WITH FREQUENCY = 2MHz
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 30. STEADY STATE OPERATION AT FULL
LOAD WITH FREQUENCY = 2MHz
LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
FIGURE 31. STEADY STATE OPERATION AT NO LOAD
WITH FREQUENCY = 4MHz
FN6576 Rev 4.00
November 23, 2009
VOUT RIPPLE 20mV/DIV
FIGURE 32. STEADY STATE OPERATION AT FULL
LOAD (PWM) WITH FREQUENCY = 4MHz
Page 10 of 17
ISL8014
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)
LX 2V/DIV
LX 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
VOUT 0.5V/DIV
PG 5V/DIV
PG 5V/DIV
IL 2A/DIV
FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY
FIGURE 33. OUTPUT SHORT CIRCUIT
OUTPUT CURRENT (A)
5.500
5.375
OCP_3.3VIN
5.250
5.125
5.000
4.875
OCP_5VIN
4.750
4.625
4.500
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE
Theory of Operation
The ISL8014 is a step-down switching regulator
optimized for battery-powered handheld applications.
The regulator operates at 1MHz fixed switching
frequency under heavy load conditions to allow smaller
external inductors and capacitors to be used for minimal
printed-circuit board (PCB) area. At light load, the
regulator reduces the switching frequency, unless forced
to the fixed frequency, to minimize the switching loss and
to maximize the battery life. The quiescent current when
the output is not loaded is typically only 35µA. The
supply current is typically only 0.1µA when the regulator
is shut down.
PWM Control Scheme
Pulling the SYNCH pin HI (>2.5V) forces the converter
into PWM mode, regardless of output current. The
ISL8014 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 2
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit
FN6576 Rev 4.00
November 23, 2009
and the slope compensation for the current loop stability.
The gain for the current sensing circuit is typically
200mV/A. The control reference for the current loops
comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the
MOSFET starts to ramp up. When the sum of the current
amplifier CSA and the slope compensation (237mV/µs)
reaches the control reference of the current loop, the
PWM comparator COMP sends a signal to the PWM logic
to turn off the P-MOSFET and turn on the N-Channel
MOSFET. The N-MOSFET stays on until the end of the
PWM cycle. Figure 36 shows the typical operating
waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and
the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP
voltage to the current loop. The bandgap circuit outputs
a 0.8V reference voltage to the voltage loop. The
feedback signal comes from the VFB pin. The soft-start
block only affects the operation during the start-up and
Page 11 of 17
ISL8014
will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage
error signal to a current output. The voltage loop is
internally compensated with the 27pF and 390k RC
network. The maximum EAMP voltage output is precisely
clamped to 1.6V.
VEAMP
capacitor. When the output voltage drops to the nominal
voltage, the P-MOSFET will be turned on again at the
rising edge of the internal clock as it repeats the previous
operations.
The regulator resumes normal PWM mode operation
when the output voltage drops 1.5% below the nominal
voltage.
Synchronization Control
VCSA
The frequency of operation can be synchronized up to
4MHz by an external signal applied to the SYNCH pin.
The falling edge on the SYNCH triggers the rising edge of
the LX pulse. Make sure that the minimum on time of the
LX node is greater than 140ns.
DUTY
CYCLE
IL
Overcurrent Protection
VOUT
FIGURE 36. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCH pin LO (
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