ISL81401AFRZ-T7A

DATASHEET ISL81401, ISL81401A FN9310 Rev.1.0 May 28, 2021 40V 4-Switch Synchronous Buck-Boost Controller The ISL81401 and ISL81401A are 4-switch synchronous buck-boost controller with peak and average current sensing and monitoring at both ends. The ISL81401 is a bidirectional device that can conduct current in both directions while the ISL81401A is an unidirectional device. Features • Single inductor 4-switch buck-boost controller • On-the-fly bidirectional operation with independent control of voltage and current on both ends • Proprietary algorithm for smoothest mode transition The ISL81401 and ISL81401A use the proprietary buck-boost control algorithm with valley current modulation for Boost mode and peak current modulation for Buck mode control. • MOSFET drivers with adaptive shoot-through protection The ISL81401 and ISL81401A have four independent control loops for input and output voltages and currents. Inherent peak current sensing at both ends and cycle-by-cycle current limit of this family of products ensures high operational reliability by providing instant current limit in fast transient conditions at either ends and in both directions. It also has two current monitoring pins at both input and output to facilitate Constant Current (CC) limit and other system management functions. CC operation down to low voltages avoids any runaway condition at over load or short-circuit conditions. In addition to multilayer overcurrent protection, it also provides full protection features such as OVP, UVP, OTP, and average and peak current limit on both input and output to ensure high reliability in both unidirectional and bidirectional operation. • Wide output voltage range: 0.8V to 40V The IC is packaged in a space conscious 32 Ld 5mmx5mm QFN package to improve thermal dissipation and noise immunity. The unique DE/Burst mode at light-load dramatically lowers standby power consumption with consistent output ripple over different load levels. • Complete protection: OCP, SCP, OVP, OTP, and UVP VIN Rs_out Rs_in UG1 Q4 Q1 LG1 UG2 PH2 Q2 Q3 • Supports pre-biased output with SR soft-start • Programmable frequency: 100kHz to 600kHz • Supports parallel operation current sharing with cascade phase interleaving • External sync with clock out or frequency dithering • External bias for higher efficiency supports 5V - 36V input • Output and input current monitor • Selectable PWM mode operation between PWM/DE/Burst modes • Accurate EN/UVLO and PGOOD indicator • Low shut down current: 2.7µA • Dual-level OCP protection with average current and pulse-by-pulse peak current limit • Selectable OCP response with either hiccup or constant current mode • Negative pulse-by-pulse peak current limit VOUT L PH1 • Wide input voltage range: 4.5V to 40V LG2 Applications • Battery backup • Type-C power supply and chargers • Battery powered industrial applications • Aftermarket automotive • Redundant power supplies Figure 1. Buck-Boost Power Train Topology • Robot and drones • Medical equipment • Security surveillance FN9310 Rev.1.0 May 28, 2021 Page 1 of 46 © 2018 Renesas Electronics ISL81401, ISL81401A 9'' &6 &6 )%B,1 9,1 (189/2 9,1 9287 9'' %227 3*1' 8* 9&&9 3+$6( ,021B,1 ,6/4)1 /* ,021B287 6*1' /* 2&B02'( 3//B&203 576 8.6V, EXTBIAS = 0V, IL = 75mA 4.8 5.2 V VIN = 4.5V, EXTBIAS > 9.0V, IL = 75mA 4.8 5.2 V VVDD = 0V, EXTBIAS = 0V, VIN = 12V 120 mA VVDD = 4.5V, EXTBIAS = 12V, VIN = 4.5V 160 mA EXTBIAS Supply Switch Over Threshold Voltage, Rising VEXT_THR EXTBIAS voltage 4.5 4.8 5 V Switch Over Threshold Voltage, Falling VEXT_THF EXTBIAS voltage 4.25 4.45 4.7 V FN9310 Rev.1.0 May 28, 2021 Page 13 of 46 ISL81401, ISL81401A 3. Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Min (Note 6) Typ VIN voltage, 0mA on VCC5V and VDD 3.20 3.50 3.85 V VUVLOTHF VIN voltage, 0mA on VCC5V and VDD 3.0 3.2 3.4 V VCC5V Rising POR Threshold VPORTHR VCC5V voltage, 0mA on VCC5V and VDD 3.7 4.0 4.3 V VCC5V Falling POR Threshold VPORTHF VCC5V voltage, 0mA on VCC5V and VDD 3.30 3.55 3.75 V Parameter Symbol VIN Rising UVLO Threshold (Note 10) VUVLOTHR VIN Falling UVLO Threshold Test Conditions Max (Note 6) Unit VIN UVLO VCC5V Power-On Reset EN/UVLO Threshold EN Rise Threshold VENSS_THR VIN > 5.6V 0.75 1.05 1.30 V EN Fall Threshold VENSS_THF VIN > 5.6V 0.60 0.90 1.10 V EN Hysteresis VENSS_HYST VIN > 5.6V 70 150 300 mV UVLO Rise Threshold VUVLO_THR VIN > 5.6V 1.77 1.80 1.83 V UVLO Hysteresis Current IUVLO_HYST VIN = 12V, EN/UVLO = 1.815V 2.5 4.2 5.5 µA Soft-Start Current SS/TRK Soft-Start Charge Current ISS SS/TRK = 0V 2.00 µA tSS_MIN SS/TRK open 1.7 ms Default Internal Minimum Soft-Starting Default Internal Output Ramping Time Power-Good Monitors PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Low Level Voltage PGOOD Leakage Current VPGOV VPGUV VPGLOW I_SINK = 2mA IPGLKG PGOOD = 5V 107 109 87 90 112 % 92 % 0.35 V 0 150 nA 5 ms PGOOD Timing VOUT Rising Threshold to PGOOD Rising (Note 9) tPGR 1.1 VOUT Falling Threshold to PGOOD Falling tPGF 80 µs VREFV 0.800 V Reference Section Internal Voltage Loop Reference Voltage Reference Voltage Accuracy Internal Current Loop Reference Voltage TA = 0°C to +85°C -0.75 +0.75 % TA = -40°C to +125°C -1.00 +1.00 % 1.200 VREFI Reference Voltage Accuracy V TA = 0°C to +85°C -0.75 +0.75 % TA = -40°C to +125°C -1.00 +1.00 % +50 nA PWM Controller Error Amplifiers FB_OUT Pin Bias Current FB_OUT Error Amp GM FB_OUT Error Amp Voltage Gain FB_OUT Error Amp Gain-BW Product FN9310 Rev.1.0 May 28, 2021 IFBOUTLKG -50 0 Gm1 1.75 mS AV1 82 dB GBW1 8 MHz Page 14 of 46 ISL81401, ISL81401A 3. Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Parameter Symbol Test Conditions Min (Note 6) FB_OUT Error Amp Output Current Capability Typ Max (Note 6) Unit ±310 µA COMP Max High Voltage VCOMP_HIGH FB_OUT = 0V 3.8 V COMP Min Low Voltage VCOMP_LOW FB_OUT = 1V 0.01 V FB_IN Pin Bias Current IFBINLKG -50 0 +50 nA FB_IN Error Amp GM Gm2 12 µS FB_IN Error Amp Voltage Gain AV2 72 dB GBW2 5 MHz FB_IN Error Amp Gain-BW Product FB_IN Active Range (Note 10) VFB_IN_ACT FB_IN Logic Low Threshold (Note 10) VFB_IN_L FB_IN Logic High Threshold (Note 10) VFB_IN_H VCC5V = 5V 0 4.3 V 4.7 V 0.2 V VCC5V = 5V PWM Regulator tOFF_MIN1 220 Buck Mode Minimum On-Time tON_MIN1 100 ns Boost Mode Minimum Off-Time tOFF_MIN2 180 ns Boost Mode Minimum On-Time tON_MIN2 140 ns Buck Mode Peak-to-Peak Sawtooth Amplitude DVRAMP1 VIN = VOUT = 12V, fSW = 300kHz 1.0 V Boost Mode Peak-to-Peak Sawtooth Amplitude DVRAMP2 VIN = VOUT = 12V, fSW = 300kHz 0.93 V Buck Mode Minimum Off-Time ns Buck Mode Ramp Offset VROFFSET1 0.88 0.95 1.11 V Boost Mode Ramp Offset VROFFSET2 2.84 3.15 3.7 V Current Sense, Current Monitors, and Average Current Loop Input Current Sense Differential Voltage Range Input Current Sense Common-Mode Voltage Range IMON_IN Offset Current VCS+ - VCS- -80 +150 mV CMIRCS 0 40 V ICSOFFSET CS+ = CS- = 12V 17.5 20 22 µA 12V common-mode voltage applied to CS+/- pins, 0 to 40mV differential voltage 170 200 220 µS Input Current Sense Voltage to IMON_IN Current Source Gain GmCS IMON_IN Error Amp GM Gm3 12 µS IMON_IN Error Amp Voltage Gain AV3 72 dB IMON_IN Active Range (Note 10) VIMON_IN_ACT VCC5V = 5V IMON_IN Logic High Threshold (Note 10) VIMON_IN_H VCC5V = 5V IMON_IN Error Amp Gain-BW Product GBW3 Output Current Sense Differential Voltage Range Output Current Sense Common-Mode Voltage Range IMON_OUT Offset Current FN9310 Rev.1.0 May 28, 2021 0 4.3 V 4.7 V 5 MHz VISEN+ - VISEN- -80 +150 mV CMIRISEN 0 40 V 22 µA IISENOFFSET ISEN+ = ISEN- = 12V 17.5 20 Page 15 of 46 ISL81401, ISL81401A 3. Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Parameter IMON_OUT Current Output Current Sense Voltage to IMON_OUT Current Source Gain Min (Note 6) Typ ISEN+ = 12V. ISEN- = 11.96V 25.5 27.6 29 µA 12V common-mode voltage applied to ISEN+/- pins, 0mV to 40mV differential voltage 170 200 220 µS Symbol GmISEN Test Conditions Max (Note 6) Unit IMON_OUT Error Amp GM Gm4 12 µS IMON_OUT Error Amp Voltage Gain AV4 72 dB GBW4 5 MHz IMON_OUT Error Amp Gain-BW Product Switching Frequency and Synchronization Switching Frequency RT Voltage fSW VRT RT = 144kΩ 220 245 265 kHz RT = 72kΩ 420 450 485 kHz RT Open or to VCC5V 90 120 145 kHz RT = 0V 470 575 650 kHz RT = 72kΩ 580 fSYNC 140 SYNC Input Logic High VSYNCH 3.2 SYNC Input Logic Low VSYNCL SYNC Synchronization Range mV 600 kHz 0.5 V V Clock Output and Frequency Dither CLKOUT Output High VCLKH ISOURCE = 1mA, VCC5V = 5V CLKOUT Output Low VCLKL ISINK = 1mA CLKOUT Frequency fCLK Dither Mode Setting Current Source IDITHER_MODE_SO Dither Mode Setting Threshold Low VDITHER_MODE_L Dither Mode Setting Threshold High VDITHER_MODE_H RT = 72kΩ 4.55 420 V 450 0.3 V 485 kHz 10 µA 0.26 V 0.34 V Dither Source Current IDITHERSO 8 µA Dither Sink Current IDITHERSI 10 µA Dither High Threshold Voltage VDITHERH 2.2 V Dither Low Threshold Voltage VDITHERL 1.05 V Diode Emulation Mode Detection MODE Input Logic High 3.2 V MODE Input Logic High 1 V Buck Mode Diode Emulation Phase Threshold (Note 11) VCROSS1 VIN = 12V 2 mV Boost Mode Diode Emulation Shunt Threshold (Note 12) VCROSS2 VIN = 12V -2 mV Diode Emulation Burst Mode Burst Mode Enter Threshold VIMONOUTBSTEN IMON_OUT pin voltage 0.815 0.84 0.855 Burst Mode Exit Threshold VMONOUTBSTEX IMON_OUT pin voltage 0.86 0.88 0.89 V 16 27 39 mV Burst Mode Peak Current Limit Input Shunt Set Point FN9310 Rev.1.0 May 28, 2021 VBST-CS VCS+ - VCS- , 12V common-mode voltage applied to CS+/- pins V Page 16 of 46 ISL81401, ISL81401A 3. Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Parameter Symbol Test Conditions Min (Note 6) Typ Max (Note 6) Unit Burst Mode Peak FB Voltage Limit Set Point VBST-VFB-UTH 0.82 V Burst Mode Exit FB Voltage Set Point VBST-VFB-LTH 0.78 V PWM Gate Drivers Driver 1, 2 BOOT Refresh Trip Voltage VBOOTRF1,2 BOOT voltage - PHASE voltage 3.45 3.9 4.35 V Driver 1, 2 Source and Upper Sink Current IGSRC1,2 2000 mA Driver 1, 2 Lower Sink Current IGSNK1,2 3000 mA Driver 1, 2 Upper Drive Pull-Up RUG_UP1,2 2.2 Ω Driver 1, 2 Upper Drive Pull-Down RUG_DN1,2 1.7 Ω Driver 1, 2 Lower Drive Pull-Up RLG_UP1,2 3 Ω Driver 1, 2 Lower Drive Pull-Down RLG_DN 2 Ω Driver 1, 2 Upper Drive Rise Time tGR_UP COUT = 1000pF 10 ns Driver 1, 2 Upper Drive Fall Time tGF_UP COUT = 1000pF 10 ns Driver 1, 2 Lower Drive Rise Time tGR_DN COUT = 1000pF 10 ns Driver 1, 2 Lower Drive Fall Time tGF_DN COUT = 1000pF 10 ns Overvoltage Protection VOVTH_OUT 112 114 116 % LG2/OC_MODE Current Source IMODELG2 7.5 10 12.5 µA LG2/OC_MODE Threshold Low VMODETHLOC 0.26 LG2/OC_MODE Threshold High VMODETHHOC Output OVP Threshold Overcurrent Protection Pulse-by-Pulse Peak Current Limit Input Shunt Set Point Hiccup Peak Current Limit Input Shunt Set Point Pulse-by-Pulse Negative Peak Current Limit Output Shunt Set Point VOCSET-CS VOCSET-CS-HIC VOCSET-ISEN VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins 73 VCS+ - VCSVISEN+ - VISEN-, 12V common-mode voltage applied to ISEN+/- pins V 83 0.34 V 93 mV 100 mV -70 -59 -48 mV 1.185 1.2 1.215 V Hiccup and Current Input Constant Limit Set Point VIMONINCC IMON_IN Pin Voltage Input Constant and Hiccup Current Limit Set Point at CS+/- Input VAVOCP_CS VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +125°C 44 51 64 mV VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +85°C 44 51 60 mV 1.185 1.2 1.215 V Output Constant and Hiccup Current Limit Set Point FN9310 Rev.1.0 May 28, 2021 VIMONOUTCC IMON_OUT Pin Voltage Page 17 of 46 ISL81401, ISL81401A 3. Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Min (Note 6) Typ VISEN+ - VISEN-, 12V common-mode applied to ISEN+/- pins, RIMON_OUT = 40.2k, TJ = -40°C to +125°C 44 51 64 mV VISEN+ - VISEN-, 12V common-mode applied to ISEN+/- pins, RIMON_OUT = 40.2k, TJ = -40°C to +85°C 44 51 60 mV Parameter Symbol Test Conditions Output Constant and Hiccup Current Limit Set Point at ISEN+/- Input VAVOCP_ISEN Max (Note 6) Unit tHICC_OFF 50 ms Over-Temperature Shutdown TOT-TH 160 °C Over-Temperature Hysteresis TOT-HYS 15 °C Hiccup OCP Off-Time Over-Temperature Notes: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. This is the total shutdown current with VIN = 5.6V and 40V. 8. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 9. When soft-start time is less than 4.5ms, tPGR increases. With internal soft-start (the fastest soft-start time), tPGR increases close to its max limit 5ms. 10. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 11. Threshold voltage at the PHASE1 pin for turning off the buck bottom MOSFET during DE mode. 12. Threshold voltage between the ISEN+ and ISEN- pins for turning off the boost top MOSFET during DE mode. FN9310 Rev.1.0 May 28, 2021 Page 18 of 46 ISL81401, ISL81401A 4. 4. Typical Performance Curves Typical Performance Curves Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. 4.7 5.0 4.5 4.6 Quiescent Current (mA) Shutdown Current (μA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Vin = 12V Vin = 40V 0.5 Vin = 4.5V Vin = 5.6V 4.5 4.4 Vin = 12V Vin = 40V Vin = 4.5V Vin = 5.6V 4.3 4.2 4.1 4.0 0.0 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 -60 140 -40 -20 0 20 40 60 80 100 120 140 Temperature (°V) Figure 6. Shutdown Current vs Temperature Figure 7. Quiescent Current vs Temperature 5.4 6 5.2 5 5.0 VDD (V) VDD (V) 4 3 2 4.8 4.6 4.4 VIN = 12V, Vextbias = 0 1 VDD vs VIN 4.2 VIN = 4.5V, Vextbias = 12V VDD Vs Vextbias 4.0 0 0 20 40 60 80 Load Current (mA) 100 120 0 140 Figure 8. VDD Load Regulation at 12V Input 10 20 30 VIN, Vextbias (V) 40 50 Figure 9. VDD Line Regulation at 20mA Load 5.1 6 5.0 5 4.9 VCC5V (V) VCC5V (V) 4 3 4.8 4.7 2 4.6 1 4.5 4.4 0 0 20 40 60 80 100 Load Current (mA) Figure 10. VCC5V Load Regulation at 12VIN FN9310 Rev.1.0 May 28, 2021 120 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) Figure 11. VCC5V Line Regulation at 20mA Load Page 19 of 46 ISL81401, ISL81401A 4. Typical Performance Curves Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued) 241 500 239 238 400 fSW (kHz) Switching Frequency (kHz) 240 450 350 RT= 72kΩ 300 237 236 235 234 RT= 144kΩ 233 250 232 231 200 -50 0 50 100 0 150 10 20 Temperature (°C) 40 50 Figure 13. Switching Frequency vs VIN, RT = 144k 0.808 1.205 0.806 1.204 1.2V Reference Voltage (V) 0.8V Reference Voltage (V) Figure 12. Switching Frequency vs Temperature 0.804 0.802 0.800 0.798 0.796 0.794 1.203 1.202 1.201 1.200 1.199 1.198 1.197 1.196 0.792 1.195 -50 0 50 150 100 -50 0 Temperature (°C) 50 150 100 Temperature (°C) Figure 14. 0.8V Reference Voltage vs Temperature Figure 15. 1.2V Reference Voltage vs Temperature 1.00 120 0.95 100 0.90 V_IMON_IN (V) Normalized Output Voltate (% ) 30 VIN (V) 80 60 40 0.85 0.80 0.75 0.70 20 TA = +25°C 0.65 TA = +125°C TA = -40°C 0.60 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Soft-Start Pin Voltage (V) Figure 16. Normalized Output Voltage vs Voltage on Soft-Start Pin FN9310 Rev.1.0 May 28, 2021 0 2 4 6 8 10 IIN 㸦A) Figure 17. Input Current IIN (DC) vs IMON_IN Pin Voltage, RS_IN = 3mΩ, RIM_IN = 37.4k Page 20 of 46 ISL81401, ISL81401A 4. Typical Performance Curves 1.3 100 1.2 95 1.1 Efficiency (%) V_IMON_OUT (V) Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued) 1.0 0.9 0.8 TA = +25°C 0.7 TA = +125°C 90 85 80 VIN = 6V VIN = 12V VIN = 36V 75 TA = -40°C 70 0.6 0 2 4 6 8 0.0 10 1.6 3.2 4.8 6.4 8.0 IOUT (A) IOUT(A) Figure 18. Output Current IOUT (DC) vs IMON_OUT Pin Voltage, RS_OUT = 4mΩ, RIM_OUT = 43.2k Figure 19. CCM Mode Efficiency 12.20 100 VIN = 6V VIN = 12V VIN = 36V 12.15 95 12.10 90 VOUT (V) Efficiency (%) VIN = 9V VIN = 24V 85 80 75 VIN = 6V VIN = 9V VIN = 12V VIN = 24V VIN = 9V VIN = 24V 12.05 12.00 11.95 11.90 11.85 VIN = 36V 11.80 70 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 IOUT (A) IOUT (A) Figure 20. DEM Mode Efficiency Figure 21. CCM Load Regulation at +25°C 12.00 PHASE1 5V/Div 11.99 11.98 VOUT (V) 11.97 11.96 PHASE2 10V/Div 11.95 11.94 VOUT 200mV/Div 11.93 11.92 IL 10A/Div 11.91 11.90 5 10 15 20 25 30 35 VIN (V) Figure 22. CCM Line Regulation at 10A Load +25°C FN9310 Rev.1.0 May 28, 2021 4µs/Div Figure 23. Boost Mode Waveforms, VIN = 6V, IOUT = 8A, CCM Mode Page 21 of 46 ISL81401, ISL81401A 4. Typical Performance Curves Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued) PHASE1 10V/Div PHASE1 50V/Div PHASE2 10V/Div PHASE2 10V/Div VOUT 200mV/Div VOUT 200mV/Div IL 10A/Div IL 10A/Div 4µs/Div 4µs/Div Figure 24. Buck-Boost Mode Waveforms, VIN = 12V, IOUT = 8A, CCM Mode Figure 25. Buck Mode Waveforms, VIN = 40V, IOUT = 8A, CCM Mode PHASE1 5V/Div PHASE1 5V/Div PHASE2 10V/Div PHASE2 10V/Div VOUT 50mV/Div VOUT 200mV/Div IL 1A/Div IL 10A/Div 2ms/Div 4µs/Div Figure 26. DEM Mode Waveforms, VIN = 6V, IOUT = 0.01A PHASE1 10V/Div Figure 27. Burst Mode Waveforms, VIN = 6V, IOUT = 0.1A PHASE1 50V/Div PHASE2 10V/Div PHASE2 10V/Div VOUT 200mV/Div VOUT 200mV/Div IL 10A/Div IL 10A/Div 2ms/Div 2ms/Div Figure 28. Burst Mode Waveforms, VIN = 12V, IOUT = 0.1A Figure 29. Burst Mode Waveforms, VIN = 40V, IOUT = 0.1A FN9310 Rev.1.0 May 28, 2021 Page 22 of 46 ISL81401, ISL81401A 4. Typical Performance Curves Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued) VOUT 200mV/Div VOUT 200mV/Div IOUT 5A/Div IOUT 5A/Div 2ms/Div 2ms/Div Figure 30. Load Transient, VIN = 6V, IOUT = 0A to 8A, 2.5A/µs, CCM Figure 31. Load Transient, VIN = 12V, IOUT = 0A to 8A, 2.5A/µs, CCM VOUT 200mV/Div VIN 20V/Div VOUT 200mV/Div IL 5A/Div IL 10A/Div 2ms/Div 10ms/Div Figure 32. Load Transient, VIN = 40V IOUT = 0A to 8A, 2.5A/µs, CCM Figure 33. Line Transient, VIN = 6V to 40V, 1V/ms, IOUT = 0A VIN 20V/Div PHASE1 5V/Div PHASE2 10V/Div VOUT 200mV/Div VOUT 5V/Div IL 10A/Div IL 10A/Div 20ms/Div 4ms/Div Figure 34. Line Transient, VIN = 40V to 6V, 0.5V/ms, IOUT = 0A Figure 35. Start-Up Waveform, VIN = 6V IO = 8A, CCM FN9310 Rev.1.0 May 28, 2021 Page 23 of 46 ISL81401, ISL81401A 4. Typical Performance Curves Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued) PHASE1 10V/Div PHASE1 50V/Div PHASE2 10V/Div PHASE2 10V/Div VOUT 5V/Div VOUT 5V/Div IL 10A/Div IL 10A/Div 4ms/Div 4ms/Div Figure 36. Start-Up Waveform, VIN = 12V IO = 8A, CCM Figure 37. Start-Up Waveform, VIN = 40V IO = 8A, CCM PHASE1 10V/Div 14 12 10 VOUT (V) PHASE2 10V/Div VOUT 5V/Div 8 6 4 VIN = 6V 2 VIN = 12V VIN = 40V 0 IL 20A/Div 0 40ms/Div 2 4 6 8 10 12 IOUT (A) Figure 38. OCP Response, Output Short-Circuited from No Load to Ground and Released, CCM Mode, VIN = 12V Figure 39. Constant Voltage (CV) and Constant Current (CC) Operation VOUT 10V/Div VIN 5V/Div IL 20A/Div 4ms/Div Figure 40. Bi-Directional Operation VIN = 18V, VIN Regulation at 6V, Remove VIN DC Source with 1A Load Applied on Input Terminals FN9310 Rev.1.0 May 28, 2021 Page 24 of 46 ISL81401, ISL81401A 5. 5. Functional Description Functional Description 5.1 General Description The ISL81401 and ISL81401A implement a complete buck-boost switching control with a PWM controller, internal drivers, references, protection circuitry, current and voltage control inputs, and monitor outputs. Refer to Figure 5 on page 6. The ISL81401 and ISL81401A are current-mode controllers. They use a proprietary control algorithm to automatically switch between Buck and Boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads. The controllers integrate four control loops to regulate not only VOUT, but also average IOUT and IIN for constant current control and VIN for reverse direction control. The driver and protection circuits are also integrated to simplify the end design. The part has an independent enable/disable control line, which provides a flexible power-up sequencing and a simple VIN UVP implementation. The soft-start time is programmable by adjusting the soft-start capacitor connected from SS/TRK. 5.2 Internal 5.3V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V) The ISL81401 and ISL81401A provide two input pins, VIN and EXTBIAS, and two internal LDOs for VDD gate driver supply. A third LDO generates VCC5V from VDD. VCC5V provides power to all internal functional circuits other than the gate drivers. Bypass the linear regulator’s outputs (VDD) with a 10µF capacitor to the power ground. Also bypass the third linear regulator output (VCC5V) with a 10µF capacitor to the signal ground. VCC5V is monitored by a power-on-reset circuit, which disables all regulators when VCC5V falls below 3.5V. Both LDOs from VIN and EXTBIAS can source over 75mA for VDD to power the buck and boost gate drivers. When driving large FETs at high switching frequency, little or no regulator current may be available for external loads. The LDO from VDD to VCC5V can also source over 75mA to supply the IC internal circuit. Although the current consumed by the internal circuit is low, the current supplied by VCC5V to the external loads is limited by VDD. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also, at higher input voltages with larger FETs, the power dissipation across the internal 5.3V LDO increases. Excessive power dissipation across this regulator must be avoided to prevent junction temperature rise. Thermal protection may be triggered if die temperature increases above +150°C due to excessive power dissipation. When large MOSFETs are used, an external 5V bias voltage can be applied to the EXTBIAS pin to alleviate excessive power dissipation. When the voltage at the EXTBIAS pin is higher than typical 4.8V, the LDO from EXTBIAS activates and the LDO from VIN is disconnected. The recommended maximum voltage at the EXTBIAS pin is 36V. For applications with VOUT significantly lower than VIN, EXTBIAS is usually back biased by VOUT to reduce the LDO power loss. EXTBIAS is allowed to activate only after soft-start is finished to avoid early activation during the VOUT rising stage. An external UVLO circuit might be necessary to ensure smooth soft-starting. Renesas recommends adding a 10µF capacitor on the EXTBIAS pin and using a diode to connect the EXTBIAS pin to VOUT to avoid the EXTBIAS pin voltage being pulled low at the VOUT short-circuit condition. The two VDD LDOs have an overcurrent limit for short-circuit protection. The VIN to VDD LDO current limit is set to typical 120mA. The EXTBIAS to VDD LDO current limit is set to typical 160mA. 5.3 Enable (EN/UVLO) and Soft-Start Operation Pulling the EN/UVLO pin high or low can enable or disable the controller. When the EN/UVLO pin voltage is higher than 1.3V, the three LDOs are enabled. After the VCC5V reaches the POR threshold, the controller is powered up to initialize its internal circuit. When EN/UVLO is higher than the 1.8V accurate UVLO threshold, the ISL81401 and ISL81401A soft-start circuitry becomes active. The internal 2µA charge current begins charging up the soft-start capacitor connected from the SS/TRK pin to GND. The voltage error amplifier reference voltage is FN9310 Rev.1.0 May 28, 2021 Page 25 of 46 ISL81401, ISL81401A 5. Functional Description clamped to the voltage on the SS/TRK pin. The output voltage thus rises from 0V to regulation as SS/TRK rises from 0V to 0.8V. Charging of the soft-start capacitor continues until the voltage on the SS/TRK pin reaches 3V. Typical applications for the ISL81401 and ISL81401A use programmable analog soft-start or the SS/TRK pin for tracking. The soft-start time can be set by the value of the soft-start capacitor connected from SS/TRK to GND. Inrush current during start-up can be alleviated by adjusting the soft-starting time. The typical soft-start time is set according to Equation 2: (EQ. 2) C SS t SS = 0.8V  -----------  2A When the soft-starting time set by external CSS or tracking is less than 1.5ms, an internal soft-start circuit of 1.5ms takes over the soft-start. PGOOD toggles to high when the output voltage is in regulation. Pulling the EN/UVLO lower than the EN threshold of 1.3V disables the PWM output and internal LDOs to achieve low standby current. The SS/TRK pin is also discharged to GND by an internal MOSFET with 70Ω rDS(ON). For applications with a larger than 1µF capacitor on the SS/TRK pin, Renesas recommends adding a 100Ω to 1kΩ resistor in series with the capacitor to share the power loss at the discharge. With use of the accurate UVLO threshold, an accurate VIN Undervoltage Protection (UVP) feature can be implemented by feeding the VIN into the EN/UVLO pin using a voltage divider, RUV1 and RUV2, shown in Figure 41. VIN RUV1 ISL81401/ ISL81041A EN/UVLO RUV2 Figure 41. VIN Undervoltage Protection The VIN UVP rising threshold can be calculated by Equation 3. (EQ. 3) V UVLO _ THR  R UV1 + R UV2  –  – 1.1x10 – 6  R UV1 R UV2 V UVRISE = -------------------------------------------------------------------------------------------------------------------------------------------------R UV2 where VUVLO_THR is the EN/UVLO pin UVLO rising threshold, typically 1.8V. The VIN UVP falling threshold can be calculated by Equation 4. (EQ. 4) V UVLO _ THR  R UV1 + R UV2  –  I UVLO _ HYST  R UV1 R UV2 V UVFALL = ---------------------------------------------------------------------------------------------------------------------------------------------------------R UV2 where IUVLO_HYST is the UVLO hysteresis current, typically 4.2µA. FN9310 Rev.1.0 May 28, 2021 Page 26 of 46 ISL81401, ISL81401A 5.4 5. Functional Description Tracking Operation The ISL81401 and ISL81401A can track an external supply. To implement tracking, connect a resistive divider between the external supply output and ground. Connect the center point of the divider to the SS/TRK pin of the ISL81401 and ISL81401A. The resistive divider ratio sets the ramping ratio between the two voltage rails. To implement coincident tracking, set the tracking resistive divider ratio exactly the same as the ISL81401 and ISL81401A output resistive divider given by Equation 5 on page 27. Make sure that the voltage at SS/TRK is greater than 0.8V when the master rail reaches regulation. To minimize the impact of the 2µA soft-start current on the tracking function, Renesas recommends using resistors less than 10kΩ for the tracking resistive divider. When the SS/TRK pin voltage is pulled down to less than 0.3V by the external tracking source, the prebias startup DEM function is enabled again. The output voltage may not be able to be pull down if the load current is not highenough. When Overcurrent Protection (OCP) is triggered, the internal minimum soft-start circuit determines the 50ms OCP soft-start hiccup off-time. 5.5 Control Loops The ISL81401 and ISL81401A are current-mode controllers that can provide an output voltage above, equal to, or below the input voltage. Referring to Figure 2 on page 2 (Typical Application circuit) and Figure 5 on page 6 (Block Diagram), the Renesas proprietary control architecture uses a current sense resistor in series with the buck upper FET to sense the inductor current in Buck or Boost mode. The inductor current is controlled by the voltage on the COMP pin, which is the lowest output of the error amplifiers Gm1 - Gm4. As the simplest example, when the output is regulated to a constant voltage, the FB_OUT pin receives the output feedback signal, which is compared to the internal reference by Gm1. Lower output voltage creates higher COMP voltage, which leads to higher PWM duty cycle to push more current to the output. Conversely, higher output voltage creates lower COMP voltage, which leads to lower PWM duty cycle to reduce the current to the output. The ISL81401 and ISL81401A have four error amplifiers (Gm1-4) which can control output voltage (Gm1), input voltage (Gm2), input current (Gm3), and output current (Gm4). In a typical application, the output voltage is regulated by Gm1, and the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. In other applications, such as a battery charger, the output current regulator (Gm4) implements constant current charging until a predetermined voltage is reached, at which point the output voltage regulator (Gm1) takes control. 5.5.1 Output Voltage Regulation Loop The ISL81401 and ISL81401A provide a precision 0.8V internal reference voltage to set the output voltage. Based on this internal reference, the output voltage can be set from 0.8V up to a level determined by the feedback voltage divider, as shown in Figure 42 on page 28. A resistive divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT pin. The output voltage value is determined by Equation 5. (EQ. 5)  R FBO1 + R FBO2 V OUT = 0.8V  --------------------------------------------- R FBO2   where RFBO1 is the top resistor of the feedback divider network and RFBO2 is the bottom resistor connected from FB_OUT to ground, shown in Figure 42. FN9310 Rev.1.0 May 28, 2021 Page 27 of 46 ISL81401, ISL81401A 5. Functional Description VOUT RFBO1 FB_OUT _ + COMP GM1 + 0.8V _ REF RFBO2 RCOMP CCOMP2 CCOMP1 Figure 42. Output Voltage Regulator As shown in Figure 42, the RCOMP, CCOMP1, and CCOMP2 network connected on the Gm1 regulator output COMP pin is needed to compensate the loop for stable operation. The loop stability can be affected by many different factors such as VIN, VOUT, load current, switching frequency, inductor value, output capacitance, and the compensation network on COMP pin. For most applications, 22nF is a good value for CCOMP1. A larger CCOMP1 makes the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. CCOMP2 is typically 1/10th to 1/30th of CCOMP1 to filter high frequency noise. A good starting value for RCOMP is 10k. Lower RCOMP improves stability but slows the loop response. Optimize the final compensation network with a bench test. 5.5.2 Input Voltage Regulation Loop As shown in Figure 43, the input voltage VIN can be sensed by the FB_IN pin using a resistor divider RFBIN1/RFBIN2 and regulated by Gm2. When the FB_IN pin voltage falls below the 0.8V reference voltage, the COMP pin voltage is pulled low to reduce the PWM duty cycle and the input current. For applications with a high input source impedance, such as a solar panel, the input voltage regulation loop can prevent the input voltage from being pulled too low in high output load conditions. For applications with a low input source impedance, such as batteries, the VIN feedback loop can prevent the battery from being over-discharged. For applications with loads on the VIN supply, such as a DC back up system, the input voltage regulation loop can reduce the input current to negative area to reverse power conversion direction to discharge the backup battery or supper capacitor to supply a regulated VIN for the loads. The regulated input voltage value is determined by Equation 6. (EQ. 6)  R FBIN1 + R FBIN2 V IN = 0.8V  ------------------------------------------------ R FBIN2   VIN RFBIN1 FB_IN COMP + _ RFBIN2 GM2 + 0.8V _ REF Figure 43. VIN Feedback Loop FB_IN is a dual-function pin. It also sets the phase angle of the clock output signal on the CLKOUT/DITHER pin, shown in Table 2 on page 35. The VIN feedback loop is disabled when the FB_IN pin voltage is below 0.3V or above 4.7V. The VIN feedback loop is also disabled in DEM mode and during soft-start. FN9310 Rev.1.0 May 28, 2021 Page 28 of 46 ISL81401, ISL81401A 5.5.3 5. Functional Description Input and Output Average Current Monitoring and Regulation Loops As shown in Figure 44, the ISL81401 and ISL81401A have two current sense operational amplifiers (op amps), A1 and A2, which monitor both input and output current. The voltage signals on the input and output current sense resistor RS_IN and RS_OUT are sent to the differential inputs of CS+/CS- and ISEN+/ISEN-, respectively, after the RC filters RS_IN1/CS_IN1, RS_IN2/CS_IN2, RS_OUT1/CS_OUT1, and RS_OUT2/CS_OUT2. Renesas recommends using a 1Ω value for RS_IN1, RS_IN2, RS_OUT1, and RS_OUT2, and a 10nF value for CS_IN1, CS_IN2, CS_OUT1, and CS_OUT2 to effectively damp the switching noise without delaying the current signal too much introducing too much error by the op amp bias current. The Gm op amps A1 and A2 then transfer the current sense voltage signals to current signals ICS and IISEN. (EQ. 7) I CS =   I IN R S_IN + V CSOFFSET Gm CS where • IIN is the input current in Q1 drain • VCSOFFSET is the A1 input offset voltage • GmCS is the gain of A1 • VCSOFFSET GmCS = ICSOFFSET. The typical value of ICSOFFSET is 20µA (EQ. 8) I ISEN =   I OUT R S_OUT + V ISENOFFSET Gm ISEN where • IOUT is the output current in Q4 drain • VISENOFFSET is the A2 input offset voltage • GmISEN is the gain of A2 • VISENOFFSET GmISEN = IISENOFFSET. The typical value of IISENOFFSET is 20µA R S_IN VIN R S_OUT UG1 R S_IN1 Q1 R S_IN2 L Q4 PH1 C S_IN1 C S_IN2 CS+ LG1 UG2 R S_OUT1 PH2 Q2 Q3 LG2 R S_OUT2 C S_OUT1 C S_OUT2 ISEN- ISEN+ CS- V ISEN_OFFSET V CS_OFFSET A2 A1 IISEN Ics Gm3 + _1.2V IMON_IN R IM_IN1 C IM_IN2 VOUT C IM_IN1 Gm4 + 1.2V_ IMON_OUT COMP R IM_IN R IM_OUT R IM_OUT1 C IM_OUT1 C IM_OUT2 Figure 44. Input and Output Average Current Monitoring and Regulation Loops FN9310 Rev.1.0 May 28, 2021 Page 29 of 46 ISL81401, ISL81401A 5. Functional Description By connecting resistor RIM_IN and RIM_OUT on the IMON_IN and IMON_OUT pins, the ICS and IISEN current signals are transferred to voltage signals. The RC networks on the IMON_IN and IMON_OUT pins RIM_IN1/CIM_IN1/CIM_IN2 and RIM_OUT1/CIM_OUT1/CIM_OUT2 are needed to remove the AC content in the ICS and IISEN signals and ensure stable loop operation. The average voltages at the IMON_IN and IMON_OUT pins are regulated to 1.2V by Gm3 and Gm4 for constant input and output current control. The input constant current loop set point IINCC is calculated by Equation 9. 1.2 – I CSOFFSET xR IMIN I INCC = -----------------------------------------------------------------R IMIN xR xGm (EQ. 9) S_IN CS where RIMIN is the resistance of RIM_IN. The output constant current loop set point IOUTCC is calculated by Equation 10. 1.2 – I ISENOFFSET xR IMOUT I OUTCC = -----------------------------------------------------------------------------R IMOUT xR xGm (EQ. 10) S_OUT ISEN where RIMOUT is the resistance of RIM_OUT. Similar to the voltage control loops, the loop stability can be affected by many different factors such as VIN, VOUT, switching frequency, inductor value, output and input capacitance, and the RC network on the IMON_IN or IMON_OUT pin. Due to the high AC content in ICS and IISEN, large CIM_IN1 and CIM_OUT1 are needed. Larger CIM_IN1 and CIM_OUT1 can also make the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. For most applications, 47nF is a good value for CIM_IN1 and CIM_OUT1. CIM_IN2 and CIM_OUT2 are typically 1/10th to 1/30th of CIM_IN1 and CIM_OUT1 to filter high frequency noise. RIM_IN1 and RIM_OUT1 are needed to boost the phase margin. A good starting value for RIM_IN1 and RIM_OUT1 is 5k. Optimize the final compensation network with iSim simulation and bench testing. 5.6 Buck-Boost Conversion Topology and Control Algorithm The ISL81401 and ISL81401A use the Renesas proprietary buck-boost control algorithm to achieve optimized power conversion performance. The buck-boost topology is shown in Figure 45. The ISL81401 and ISL81401A control the four power switches Q1, Q2, Q3, and Q4 to work in either Buck or Boost mode. When VIN is far lower than VOUT, the converter works in Boost mode. When VIN is far higher than VOUT, the converter works in Buck mode. When VIN is equal or close to VOUT, the converter alternates between Buck and Boost mode as necessary to provide a regulated output voltage, which is called Buck-Boost mode. Figure 46 shows the relationship between the operation modes and VOUT - VIN. Q3 Max Duty RS_IN UG1 RS_OUT V OUT Q4 Q1 UG2 L PH1 LG1 PH2 Q2 Q3 LG2 Boost Mode VOUT - VIN VIN 0 Buck/Boost Mode Q1 On, Q2 Off Q3, Q4 PWM Switching 4-Switch PWM Q3 Min Duty Q2 Min Duty Buck Mode Q4 On, Q3 Off Q1, Q2 PWM Switching Q2 Max Duty Figure 45. Buck-Boost Topology Figure 46. Operation Modes vs VOUT - VIN RS_IN is a current sense resistor to sense the inductor current during Q1 on-time. As shown in the “Block Diagram” on page 6, the sensed signal is fed into the CS+ and CS- pins and used for peak or valley current-mode control, DEM control, input average current monitor, constant current control, and protections. RS_OUT is a current sense resistor to sense the inductor current during Q4 on-time. As shown in the Block Diagram, the sensed signal is fed into the ISEN+ and ISEN- pins and used for negative peak inductor current limit, output average current monitor, constant current control, and protections. FN9310 Rev.1.0 May 28, 2021 Page 30 of 46 ISL81401, ISL81401A 5.6.1 5. Functional Description Buck Mode Operation (VIN >> VOUT) In Buck mode, Q4 is always on and Q3 is always off unless boot refresh or inductor negative peak current limit is tripped. Q1 and Q2 runs in a normal peak current controlled sync buck operation mode. Q1 turns on by the clock. During Q1 on-time, op amp A1 senses the inductor current by the voltage on RS_IN. Q1 turns off when the sensed signal combined with the slope compensation ramp is higher than the COMP pin voltage, which is the error signal from the upper voltage or current regulator. The equivalent circuit and operation waveforms are shown in Figure 47. VIN RS_OUT RS_IN UG1 Q1 L PH1 LG1 VOUT PH2 Q2 CLOCK Q1 UG1 Q2 LG1 Q3 LG2 0V Q4 UG2 5V IL Figure 47. Buck Mode Equivalent Circuit and Operation Waveforms In Buck mode, the Q1 duty cycle is given by: DQ1 = VOUT / VIN x 100% As VIN decreases close to VOUT, DQ1 increases close to its maximum value decided by its minimum off-time. When DQ1 reaches its maximum value, the converter moves to Buck-Boost mode. When VIN is much higher than VOUT, DQ1 decreases to close to its minimum duty cycle decided by its minimum on-time. To allow stable loop operation and avoid duty cycle jitter, Renesas recommends keeping the Q1 on-time always two to three times higher than the minimum on-time. 5.6.2 Boost Mode Operation (VIN =< VOUT) In Buck-Boost mode, the converter runs in one cycle of Buck mode followed by one cycle of Boost mode operation mode. It takes two clock cycles to finish a full buck-boost period. When VIN is higher than VOUT, Q3 runs in minimum duty in the Boost mode cycle. Q1 duty cycle DQ1 is modulated in the buck cycle to keep VOUT in regulation. As VIN increases, DQ1 decreases. When DQ1 decreases to less than 66.7% of the clock period, the converter moves to Buck mode. When VIN is lower than VOUT, Q1 runs in maximum duty in the Buck mode cycle. Q3 duty cycle DQ3 is modulated in the Boost mode cycle to keep VOUT in regulation. As VIN decreases, DQ3 increases. When DQ3 increases to more than 33.3% of the clock period, the converter moves to Boost mode. FN9310 Rev.1.0 May 28, 2021 Page 32 of 46 ISL81401, ISL81401A 5. Functional Description VIN RS_IN UG1 RS_OUT VOUT Q4 Q1 UG2 L PH1 LG1 PH2 Q2 Q3 LG2 CLOCK Q1 UG1 Q2 LG1 Q3 LG2 Q4 UG2 IL Figure 49. Buck-Boost Mode Equivalent Circuit and Operation Waveforms 5.7 Light-Load Efficiency Enhancement The ISL81401 and ISL81401A can be set to DEM and Burst mode to improve light-load efficiency by connecting the MODE pin to VCC5V. When DEM mode is set, the buck sync FET driven by LG1 and the boost sync FET driven by UG2 are all running in DEM mode. The inductor current is not allowed to reverse (discontinuous operation) depending on the zero cross detection reference level VCROSS1 for buck sync FET and VCROSS2 for boost sync FET. At light load condition, the converter goes into diode emulation. When the load current is less than the level set by VIMONOUTBSTEN typical 0.84V on the IMON_OUT pin, the part enters Burst mode. Equation 11 sets the Burst mode operation enter condition. (EQ. 11) R IMOUT x  I SENOFFSET + I OUT xR S_OUT xGm ISEN   0.84V where (refer to Figure 44 on page 29): RIMOUT is the resistance of RIM_OUT ISENOFFSET is the output current sense op amp internal offset current, typical 20µA GmISEN is the output current sense op amp Gm, typical 195µS. The part exits Burst mode when the output current increases to higher than the level set by VIMONOUTBSTEX typical 0.88V on the IMON_OUT pin. Equation 12 sets the Burst mode operation exit condition. (EQ. 12) R IMOUT x  I SENOFFSET + I OUT xR S_OUT xGm ISEN   0.88V When the part enters Burst mode, the BSTEN pin goes low. To fully avoid any enter/exit chattering, a 4-10MΩ resistor can be added between BETEN and IMON_OUT pins to further expand the hysteresis. In Burst mode, an internal window comparator takes control of the output voltage. The comparator monitors the FB_OUT pin voltage. When the FB_OUT pin voltage is higher than 0.82V, the controller enters Low Power Off mode. Some of the unnecessary internal circuitries are powered off. When the FB_OUT pin voltage drops to 0.8V, the controller wakes up and runs in a fixed level peak current controlled D/(1-D) Buck-Boost mode when VIN - VOUT < 2V and Buck mode when VIN -VOUT > 2V. In the D/(1-D) Buck-Boost mode, Q1 and Q3 conduct in D*T period, where D is the duty cycle and T is the switching period. Q2 and Q4 complimentarily conduct in (1-D)*T period. Q1 and Q3 are turned on by the clock signal and turned off when inductor current rises to the level that the input current sense op amp input voltage reaches VBST-CS, typical 27mV. After Q1 and Q3 are turned off, Q2 and Q4 are turned on to pass the energy stored in the inductor to the output until next cycle begins. The output FN9310 Rev.1.0 May 28, 2021 Page 33 of 46 ISL81401, ISL81401A 5. Functional Description voltage increases in the wake up period. When the output reaches 0.82V again, the controller enters into Low Power Off mode again. When the load current increases, the Low Power Off mode period decreases. When the off mode period disappears and the load current further increases but still does not meet the Equation 12 exit condition, the output voltage drops. When the FB_OUT pin voltage drops to 0.78V, the controller exits Burst mode and runs in normal DEM PWM mode. The voltage error amplifier takes control of the output voltage regulation. In Low Power Off mode, the CLKEN pin goes low. By connecting the BSTEN and CLKEN pins together in a multiple chip parallel system, the Burst mode enter/exit and burst on/off controls are all synchronized. Because the VOUT is controlled by a window comparator in Burst mode, higher than normal low frequency voltage ripples appear on the VOUT, which can generate audible noise if the inductor and output capacitors are not chosen properly. Also, the efficiency in D/(1-D) Buck-Boost mode is low. To avoid these drawbacks, the Burst mode can be disabled by choosing a bigger RIMOUT to set the IMON_OUT pin voltage higher than 0.88V at no load condition, shown in Equation 13. The part runs in DEM mode only. Pulse Skipping mode can also be implemented to lower the light load power loss with much lower output voltage ripple as the VOUT is always controlled by the regulator Gm1. (EQ. 13) 5.8 R IMOUT xI SENOFFSET  0.88V Prebiased Power-Up The ISL81401 and ISL81401A have the ability to soft-start with a prebiased output by running in forced DEM mode during soft-start. The output voltage is not pulled down during prebiased start-up. PWM mode is not active until the soft-start ramp reaches 90% of the output voltage times the resistive divider ratio. Forced DEM mode is set again when the SS/TRK pin voltage is pulled to less than 0.3V by either internal or external circuit. The overvoltage protection function is still alive during soft-start of the DEM operation. 5.9 Frequency Selection Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency improves efficiency by reducing MOSFET switching loss. To meet the output ripple and load transient requirements, operation at a low switching frequency would require larger inductance and output capacitance. The switching frequency of the ISL81401 and ISL81401A is set by a resistor connected from the RT/SYNC pin to GND according to Equation 1 on page 10. The frequency setting curve shown in Figure 50 assists in selecting the correct value for RT. 3,000 2,500 fSW (kHz) 2,000 1,500 1,000 500 0 0 50 100 150 200 250 RT (k:) Figure 50. RT vs Switching Frequency fSW 5.10 Phase Lock Loop (PLL) The ISL81401 and ISL81401A integrate a high performance PLL. The PLL ensures the wide range of accurate clock frequency and phase setting. It also easily synchronizes the internal clock to an external clock with the frequency either lower or higher than the internal setting. FN9310 Rev.1.0 May 28, 2021 Page 34 of 46 ISL81401, ISL81401A 5. Functional Description As shown in Figure 51, an external compensation network of RPLL, CPLL1, and CPLL2 is needed to connect to the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩ for RPLL, 10nF for CPLL1, and 820pF for CPLL2. With the recommended compensation network, the PLL stability is ensured in the full clock frequency range of 100kHz to 600kHz. ISL81401/ISL81401A PLL_COMP RPLL CPLL2 CPLL1 Figure 51. PLL Compensation Network 5.11 Frequency Synchronization and Dithering The RT/SYNC pin can synchronize the ISL81401 and ISL81401A to an external clock or the CLKOUT/DITHER pin of another ISL81401. When the RT/SYNC pin is connected to the CLKOUT/DITHER pin of another ISL81401, the two controllers operate in cascade synchronization with phase interleaving. When the RT/SYNC pin is connected to an external clock, the ISL81401 and ISL81401A synchronizes to this external clock frequency. The frequency set by the RT resistor can be either lower or higher than, or equal to the external clock frequency. The CLKOUT/DITHER pin outputs a clock signal with approximately 300ns pulse width. The signal frequency is the same as the frequency set by the resistor from the RT pin to ground or the external sync clock. The signal rising edge phase angle to the rising edge of the internal clock or the external clock to the RT/SYNC pin can be set by the voltage applied to the FB_IN and IMON_IN pins. The phase interleaving can be implemented by the cascade connecting of the upper chip CLKOUT/DITHER pin to the lower chip RT/SYNC pin in a parallel system. Table 2 shows the CLKOUT/DITHER phase settings with different FB_IN and IMON_IN pin voltages. Table 2. CLKOUT Phase Shift vs FB_IN and IMON_IN Voltage CLKOUT Phase Shift FB_IN Voltage IMON_IN Voltage 120° 90° 60° 180° Active 1 1 Active 1 Active 1 Active Note: “1” means logic high 4.7V to 5V. “Active” means logic low 0V to 4.3V. When FB_IN is connected to 4.5V, the VIN feedback control loop is disabled. When IMON_IN is connected to 4.5V, the average input current control loop and input current hiccup OCP are disabled. In multi-chip cascade parallel operation, the CLKOUT pin of the upstream chip is connected to the RT/SYNC pin of the downstream chip. Renesas recommends leaving the RT/SYNC pin open for all the slave chips. The FB_IN, SS/TRK, COMP, FB_OUT, IMON_OUT, EN/UVLO, IMON_IN, and MODE pins of all the paralleled chips should be tied together. Refer to ISL81601 datasheet for the current sharing approach in parallel operation. The CLKOUT/DITHER pin provides a dual function option. When a capacitor CDITHER is connected on the CLKOUT/DITHER pin, the internal circuit disables the CLKOUT function and enables the DITHER function. When the CLKOUT/DITHER pin voltage is lower than 1.05V, a typical 8µA current source IDITHERSO charges the capacitor on the pin. When the capacitor voltage is charged to more than 2.2V, a typical 10µA current source IDITHERSI discharges the capacitor on the pin. A sawtooth voltage waveform shown in Figure 52 is generated on the CLKOUT/DITHER pin. The internal clock frequency is modulated by the sawtooth voltage on the CLKOUT/DITHER pin. The clock frequency dither range is set to typically ±15% of the frequency set by the resistor on the RT/SYNC pin. The dither function is lost when the chip is synchronized to an external clock. FN9310 Rev.1.0 May 28, 2021 Page 35 of 46 ISL81401, ISL81401A 5. Functional Description ISL81401 CLKOUT/ DITHER CDITHER a. Frequency Dithering Operation 1 FDITHER 2.2V 1.05V b. CLKOUT/DITHER Pin Voltage Waveform in Dither Operation Figure 52. Frequency Dithering Operation The dither frequency FDITHER can be calculated by Equation 14. Renesas recommends setting CDITHER between 10nF and 1µF. With a too low CDITHER the part may not be able to set to Dither mode. With a higher CDITHER, the discharge power loss at disable or power off is higher, leading to a higher thermal stress to the internal discharge circuit. (EQ. 14) 5.12 3.865x10e  – 6  F DITHER = ----------------------------------------C DITHER Gate Drivers The ISL81401 and ISL81401A integrate two almost identical high voltage driver pairs to drive both buck and boost MOSFET pairs. Each driver pair consists of a gate control logic circuit, a low side driver, a level shifter, and a high side driver. The ISL81401 and ISL81401A incorporate an adaptive dead time algorithm that optimizes operation with varying MOSFET conditions. This algorithm provides approximately 16ns dead time between the switching of the upper and lower MOSFETs. This dead time is adaptive and allows operation with different MOSFETs without having to externally adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead time circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. When the upper MOSFET gate-to-source voltage drops below a threshold of 1V, the LGATE is allowed to rise. Renesas recommends not using a resistor between the driver outputs and the respective MOSFET gates, because it can interfere with the dead time circuitry. The low-side gate driver is supplied from VDD and provides a 3A peak sink and 2A peak source current. The high-side gate driver can also deliver the same currents as the low-side gate driver. Gate-drive voltage for the upper N-channel MOSFET is generated by a flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high-side MOSFET driver. As shown in Figure 53 on page 37, the boot capacitor is charged up to VDD by an external Schottky diode during low-side MOSFET on-time (phase node low). To limit the peak current in the Schottky diode, an external resistor can be placed between the BOOT pin and the boot capacitor. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. FN9310 Rev.1.0 May 28, 2021 Page 36 of 46 ISL81401, ISL81401A 5. Functional Description At start-up, the low-side MOSFET turns on first and forces PHASE to ground to charge the BOOT capacitor to 5.3V if the diode voltage drop is ignored. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5.3V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5.3V regulator supplied from either VIN or EXTBIAS pin. The BOOT to PHASE voltage is monitored internally. When the voltage drops to 3.9V at no switching condition, a minimum off-time pulse is issued to turn off the upper MOSFET and turn on the low-side MOSFET to refresh the bootstrap capacitor and maintain the upper driver bias voltage. To optimize EMI performance or reduce phase node ringing, a small resistor can be placed between the BOOT pin to the positive terminal of the bootstrap capacitor. VDD BOOT UGATE External Schottky VIN RBOOT CB PHASE ISL81401/ISL81401A Figure 53. Upper Gate Driver Circuit 5.13 Power-Good Indicator The power-good pin can monitor the status of the output voltage. PGOOD is true (open drain) 1.1ms after the FB_OUT pin is within ±10% of the reference voltage. There is no extra delay when the PGOOD pin is pulled low. FN9310 Rev.1.0 May 28, 2021 Page 37 of 46 ISL81401, ISL81401A 6. 6. Protection Circuits Protection Circuits The converter output and input are monitored and protected against overload, overvoltage, and undervoltage conditions. 6.1 Input Undervoltage Lockout The ISL81401 and ISL81401A include input UVLO protection, which keeps the devices in a reset condition until a proper operating voltage is applied. UVLO protection shuts down the ISL81401 and ISL81401A if the input voltage drops below 3.2V. The controller is disabled when UVLO is asserted. When UVLO is asserted, PGOOD is valid and is deasserted. If the input voltage rises above 4V, UVLO is deasserted to allow the start-up operation. 6.2 VCC5V Power-On Reset (POR) The ISL81401 and ISL81401A set their VCC5V POR rising threshold at 4V and falling threshold at 3.5V when supplied by VIN. EXTBIAS can activate only after VCC5V reaches its POR rising threshold. 6.3 Overcurrent Protection (OCP) 6.3.1 Input and Output Average Overcurrent Protection As described in “Input and Output Average Current Monitoring and Regulation Loops” on page 29, the ISL81401 and ISL81401A can regulate both input and output currents with close loop control. This provides a constant current type of overcurrent protection for both input and output average current. It can be set to a hiccup type of protection by selecting a different value of the resistor connected between LG2/OC_MODE and GND. The input and output constant or hiccup average OCP set points IINCC and IOUTCC can be calculated by Equations 9 and 10 in Input and Output Average Current Monitoring and Regulation Loops. The average OCP mode is set by a resistor connected from the LG2/OC_MODE pin to ground during the initiation stage before soft-start. During the initiation stage, the LG2/OC_MODE pin sources out a typical 10µA current IMODELG2 to set the voltage on the pin. If the pin voltage is less than 0.3V, the OCP is set to Constant Current-mode. Otherwise, the OCP is set to hiccup mode. In hiccup OCP mode, after the average current is higher than the set point for 32 consecutive switching cycles the converter turns off for 50ms before a restart-up is issued. 6.3.2 First Level Pulse-by-Pulse Peak Current Limit As shown in Figure 44 on page 29 in Input and Output Average Current Monitoring and Regulation Loops, the inductor peak current is sensed by the shunt resistor RS_IN and op amp A1. When the voltage drop on RS_IN reaches the set point VOCSET-CS typical 83mV, Q1 is turned off in Buck mode or Q3 is turned off in Boost mode. The first level peak current limit set point IOCPP1 can be calculated by Equation 15. (EQ. 15) FN9310 Rev.1.0 May 28, 2021 V OCSET – CS I OCPP1 = ---------------------------------R S_IN Page 38 of 46 ISL81401, ISL81401A 6.3.3 6. Protection Circuits Second Level Hiccup Peak Current Protection To avoid any false trip in peak current-mode operation, a minimum on or blanking time is set to the PWM signal. The first level pulse-by-pulse current limit circuit cannot further reduce the PWM duty cycle in the minimum on-time. In output dead short conditions, especially at high VIN, the inductor current runs away with the minimum on PWM duty. The ISL81401 and ISL81401A integrate a second level hiccup type of peak current protection. When the voltage drop on RS_IN reaches the set point VOCSET-CS-HIC (typical 100mV), the converter turns off by turning off all four switches Q1, Q2, Q3, and Q4 for 50ms before a restart is issued. The second level peak current protection set point IOCPP2 can be calculated by Equation 16. (EQ. 16) 6.3.4 V OCSET-CS-HIC I OCPP2 = ------------------------------------------R S_IN Pulse-by-Pulse Negative Peak Current Limit In cases of reverse direction operation and OVP protection, the inductor current goes to negative. The negative current is sensed by the shunt resistor RS_OUT and op amp A2 shown in Figure 44. When the voltage drop on RS_IN reaches the set point VOCSET-ISEN (typical -59mV), Q2 and Q4 are turned off and Q1 and Q3 are turned on. The negative peak current limit set point IOCPPN can be calculated by Equation 17. (EQ. 17) V OCSET-ISEN I OCPPN = ------------------------------------R ISEN The device can be damaged in negative peak current limit conditions. In these conditions, the energy flows from output to input. If the impedance of the input source or devices is not low enough, the VIN voltage increases. When VIN increases to higher than its maximum limit, the IC can be damaged. 6.4 Overvoltage Protection The overvoltage set point is set at 114% of the nominal output voltage set by the feedback resistors. In the case of an overvoltage event, the IC attempts to bring the output voltage back into regulation by keeping Q1 and Q3 turned off and Q2 and Q4 turned on. If the OV condition continues, the inductor current goes negative to trip the negative peak current limit. The converter reverses direction to transfer energy from the output end to the input end. Input voltage is pushed high if the input source impedance is not low enough. The IC may be damaged if the input voltage goes to higher than its maximum limit. If the overvoltage condition is corrected and the output voltage drops to the nominal voltage, the controller resumes work in normal PWM switching. 6.5 Over-Temperature Protection The ISL81401 and ISL81401A incorporate an over-temperature protection circuit that shuts the IC down when a die temperature of +160°C is reached. Normal operation resumes when the die temperature drops below +145°C through the initiation of a full soft-start cycle. During OTP shutdown, the IC consumes only 100µA current. When the controller is disabled, thermal protection is inactive. This helps achieve a very low shutdown current of 5µA. FN9310 Rev.1.0 May 28, 2021 Page 39 of 46 ISL81401, ISL81401A 7. 7. Layout Guidelines Layout Guidelines Careful attention to layout requirements is necessary for successful implementation of ISL81401 and ISL81401A based DC/DC converters. The ISL81401 and ISL81401A switch at a very high frequency, so the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in an extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and ringing. Careful component selection and proper Printed Circuit Board (PCB) layout minimize the magnitude of these voltage spikes. The three sets of critical components in a DC/DC converter using the ISL81401 and ISL81401A are the following: • the controller • the switching power components • the small signal components The switching power components are the most critical from a layout point of view because they switch a large amount of energy, which tends to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended. 7.1 Layout Considerations (1) Place the input capacitors, buck FETs, inductor, boost FETs, and output capacitor first. Isolate these power components on dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output high frequency decoupling ceramic capacitors very close to the MOSFETs. (2) If signal components and the IC are placed in a separate area to the power train, use full ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise, use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND together close to the IC. DO NOT connect them together anywhere else. (3) Keep the loop formed by the input capacitor, the buck top FET, and the buck bottom FET as small as possible. Keep the loop formed by the output capacitor, the boost top FET, and the boost bottom FET as small as possible. (4) Ensure the current paths from the input capacitor to the buck FETs, the power inductor, the boost FETs, and the output capacitor are as short as possible with maximum allowable trace widths. (5) Place the PWM controller IC close to the lower FETs. The low side FETs gate drive connections should be short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area. (6) Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND pin. Connect the PGND pin to the ground plane by a via. Do not directly connect the PGND pin to the SGND EPAD. (7) Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC. (8) Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output capacitors to load to avoid inductance and resistances. (9) Use copper filled polygons or wide short traces to connect the junction of the buck or boost upper FET, buck or boost lower FET, and output inductor. Also keep the buck and boost PHASE nodes connection to the IC short. DO NOT oversize the copper islands for the PHASE nodes. Because the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry tends to couple switching noise. (10) Route all high speed switching nodes away from the control circuitry. (11) Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths including feedback resistors, current monitoring resistors and capacitors, soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors should be connected to this SGND plane. FN9310 Rev.1.0 May 28, 2021 Page 40 of 46 ISL81401, ISL81401A 7. Layout Guidelines (12) Use a pair of traces with minimum loop for the input or output current sensing connection. (13) Ensure the feedback connection to the output capacitor is short and direct. 7.2 General EPAD Design Considerations Figure 54 illustrates how to use vias to remove heat from the IC. Figure 54. PCB Via Pattern Fill the thermal pad area with vias. A typical via array fills the thermal pad footprint so that their centers are three times the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow. Connect all vias to the ground plane. The vias must have a low thermal resistance for efficient heat transfer. Ensure a complete connection of the plated through hole to each plane. FN9310 Rev.1.0 May 28, 2021 Page 41 of 46 ISL81401, ISL81401A 8. 8. Component Selection Guideline Component Selection Guideline 8.1 MOSFET Considerations The MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirement. Select these MOSFETs based upon rDS(ON), gate supply requirements, and thermal management considerations. The buck MOSFETs’ maximum operation voltage is decided by the maximum VIN voltage, and the boost MOSFETs’ maximum operation voltage is decided by the maximum VOUT voltage. Choose the buck or boost MOSFETs based on their maximum operation voltage with sufficient margin for safe operation. The MOSFETs’ power dissipation is based on conduction loss and switching loss. In Buck mode, the power loss of the buck upper and lower MOSFETs are calculated by Equations 18 and 19. The conduction losses are the main source of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the lower MOSFET’s body diode. 2 (EQ. 18)  I OUT   r DS  ON    V OUT   I OUT   V IN   t SW   f SW  P UPPERBUCK = ---------------------------------------------------------------------- + ----------------------------------------------------------------V IN 2 2 (EQ. 19)  I OUT   r DS  ON    V IN – V OUT  P LOWERBUCK = -------------------------------------------------------------------------------------V IN In Boost mode, there is only conduction loss on the buck upper MOSFET calculated by Equation 20. 2 (EQ. 20) 2  I OUT   V OUT  P UPPERBUCK = ----------------------------------------------  r DS  ON   2  V IN  In Boost mode, the boost upper and lower MOSFETs power loss are calculated by Equations 21 and 22. The conduction losses are the main component of power dissipation for the upper MOSFET. Only the lower MOSFET has significant switching losses, because the upper device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the upper MOSFET’s body diode. 2 (EQ. 21) (EQ. 22) 2 2  I OUT   V OUT   V OUT – V IN   r DS  ON    I OUT   V OUT   t SW   f SW  P LOWERBOOST = ---------------------------------------------- ----------------------------------------------------------------- + -------------------------------------------------------------------------2 V OUT 2  V IN   V IN  2  I OUT   r DS  ON    V OUT  P UPPERBOOST = ---------------------------------------------------------------------V IN In Buck mode, the conduction loss exists on the boost upper MOSFET calculated by Equation 23. (EQ. 23) 2 P UPPERBOOST =  I OUT   r DS  ON   A large gate-charge increases the switching time, tSW , which increases the switching losses of the buck upper and boost lower MOSFETs. Ensure that all four MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. FN9310 Rev.1.0 May 28, 2021 Page 42 of 46 ISL81401, ISL81401A 8.2 8. Component Selection Guideline Inductor Selection The inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current, and the ripple voltage is a function of the ripple current and the output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 24 for Buck mode and Equation 25 for Boost mode. (EQ. 24)  V IN – V OUT   V OUT  I LBuck = -------------------------------------------------------- f SW   L   V IN  (EQ. 25)  V OUT – V IN   V IN  I LBoost = -------------------------------------------------- f SW   L   V OUT  The ripple current ratio is usually 30% to 70% of the inductor average current at the full output load condition. 8.3 Output Capacitor Selection In general, select the output capacitors to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the inductor, so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to its new level. The ISL81401 and ISL81401A provide either 0% or maximum duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown in Equation 26 for Buck mode and Equation 27 for Boost mode: 2 (EQ. 26)  L   I TRAN  C OUTBuck = -----------------------------------------------------------------2  V IN – V OUT   DV OUT  (EQ. 27)  L   V OUT   I TRAN  C OUTBoost = -----------------------------------------------------2 2  V IN   DV OUT  2 where COUT is the output capacitor(s) required, L is the inductor, ITRAN is the transient load current step, VIN is the input voltage, VOUT is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate of change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the Equivalent Series Resistance (ESR) and voltage rating requirements as well as actual capacitance requirements. In Buck mode, the output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 28: (EQ. 28) V RIPPLE = I LBuck  ESR  where ILBuck is calculated in Equation 24. FN9310 Rev.1.0 May 28, 2021 Page 43 of 46 ISL81401, ISL81401A 8. Component Selection Guideline In Boost mode, the current to the output capacitor is not continuous. The output voltage ripple is much higher as defined by Equation 29: (EQ. 29)   I OUT   V OUT  I LBoost V RIPPLE =  --------------------------------------- + ------------------------  ESR  2 V IN   where ILBoost is calculated in Equation 25 on page 43. Place high frequency decoupling capacitors as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching regulator applications for the bulk capacitors. In most cases, multiple small case electrolytic capacitors perform better than a single large case capacitor. The stability requirement on the selection of the output capacitor is that the ESR zero (f Z) is between 2kHz and 60kHz. The ESR zero can help increase phase margin of the control loop. This requirement is shown in Equation 30: (EQ. 30) 1 C OUT = -----------------------------------2  ESR   f Z  In conclusion, the output capacitors must meet the following criteria: • They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. • The ESR must be sufficiently low to meet the desired output voltage ripple due to the supplied ripple current. • The ESR zero should be placed in a large range to provide additional phase margin. 8.4 Input Capacitor Selection The important parameters for the input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. In Buck mode the AC RMS input current varies with the load giving in Equation 31: (EQ. 31) I RMS = 2 DC – DC  I OUT where DC is duty cycle. The maximum RMS current supplied by the input capacitance occurs at VIN = 2 X VOUT, DC = 50% as shown in Equation 32: (EQ. 32) 1 I RMS = ---  I OUT 2 In Boost mode, the input current is continuous. The RMS current supplied by the input capacitance is much smaller. Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the MOSFETs to suppress the voltage induced in the parasitic circuit impedances. Solid tantalum capacitors can be used, but use caution with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. FN9310 Rev.1.0 May 28, 2021 Page 44 of 46 ISL81401, ISL81401A 9. 9. Revision History Revision History Rev. Date 1.0 May 28, 2021 Updated links throughout. Updated Figure 5. Updated Ordering information table. 0.0 Sep 11, 2018 Initial release FN9310 Rev.1.0 May 28, 2021 Description Page 45 of 46 ISL81401, ISL81401A 10. Package Outline Drawing 10. Package Outline Drawing For the most recent package outline drawing, see L32.5x5B. L32.5x5B 32 Lead Quad Flat No-lead Plastic Package Rev 3, 5/10 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .30 ± 0 . 15 17 (4X) 8 0.15 9 16 0.10 M C A B + 0.07 32X 0.40 ± 0.10 TOP VIEW 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN9310 Rev.1.0 May 28, 2021 Page 46 of 46 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.