ISL83204AIBZT

DATASHEET ISL83204A FN6397 Rev.2.00 March 20, 2007 60V/2.5A Peak, High Frequency Full Bridge FET Driver The ISL83204A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The ISL83204A includes an input comparator used to facilitate the “hysteresis” and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the ISL83204A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. ISL83204A can also drive medium voltage brush motors, and two ISL83204As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. Features • Drives N-Channel FET Full Bridge Including High Side Chop Capability • Bootstrap Supply Max Voltage to 75VDC • Drives 1000pF Load at 1MHz in Free Air at +50°C with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • Charge-Pump and Bootstrap Maintain Upper Bias Supplies • DIS (Disable) Pin Pulls Gates Low • Input Logic Thresholds Compatible with 5V to 15V Logic Levels Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. • Very Low Power Consumption Ordering Information Applications PART NUMBER ISL83204AIPZ (Note) PART MARKING TEMP RANGE (°C) • Undervoltage Protection • Pb-Free Plus Anneal Available (RoHS Compliant) • Medium/Large Voice Coil Motors PKG. PACKAGE DWG. # ISL83204AIPZ -40 to +85 20 Ld PDIP (Pb-Free) E20.3 ISL83204AIBZ* ISL83204AIBZ -40 to +85 20 Ld SOIC (Note) (Pb-Free) M20.3 • Full Bridge Power Supplies • Switching Power Amplifiers • Uninterruptible Power Supplies • High Performance Motor Controls *Add “-T” suffix for tape and reel. • Noise Cancellation Systems NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Battery Powered Vehicles FN6397 Rev.2.00 March 20, 2007 Pinout ISL83204A (20 LD PDIP, 20 LD SOIC) TOP VIEW BHB 1 HEN 2 19 BHS DIS 3 18 BLO VSS 4 17 BLS OUT 5 16 VDD IN+ 6 15 VCC 20 BHO IN- 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO Page 1 of 15 ISL83204A Application Block Diagram 60V 12V BHO BHS HEN LOAD BLO DIS ISL83204A IN+ ALO AHS IN- AHO GND Functional Block Diagram GND (1/2 ISL83204A) 10 UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 11 AHO CBS AHS VDD 16 HEN HIGH VOLTAGE BUS  60VDC AHB 12 2 TURN-ON DELAY DBS DIS 3 OUT 5 IN+ 6 IN_ 7 HDEL 8 LDEL 9 VSS 4 FN6397 Rev.2.00 March 20, 2007 TO VDD (PIN 16) 15 VCC DRIVER + - TURN-ON DELAY ALO 13 ALS CBF +12VDC BIAS SUPPLY 14 Page 2 of 15 ISL83204A Typical Application (Hysteresis Mode Switching) 60V 1 BHB BHO 20 2 HEN BHS 19 DIS 3 DIS BLO 18 4 VSS BLS 17 5 OUT 6 IN+ 6V 7 ININ ISL83204A 12V 8 HDEL LOAD VDD 16 VCC 15 12V ALS 14 ALO 13 9 LDEL AHS 12 10 AHB AHO 11 GND + 6V GND FN6397 Rev.2.00 March 20, 2007 Page 3 of 15 ISL83204A Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . -6.0V (Transient) to 70V (+25°C to +125°C) Voltage on AHS, BHS . . -6.0V (Transient) to 70V (-55°C to +125°C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to VSS, unless otherwise specified. Thermal Resistance (Typical, Note 1) JA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation at +85°C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C (For SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . .VAHS, BHS +5V to VAHS, BHS +15V Voltage on AHs, BHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified TJ = +25°C PARAMETERS TJ = -40°C to +125°C MIN TYP MAX MIN MAX UNITS IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA Outputs switching f = 500kHz, No Load 8 12 15 8 15 mA IN- = 2.5V, Other Inputs = 0V, IALO = IBLO = 0 - 25 80 - 100 A f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC =VAHB = VBHB = 10V -50 -25 -11 -60 -10 A SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD VDD Operating Current IDDO VCC Quiescent Current ICC VCC Operating Current ICCO AHB, BHB Quiescent Current -Qpump Output Current IAHB, IBHB AHB, BHB Operating Current IAHBO, IBHBO f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA AHS, BHS, AHB, BHB Leakage Current IHLK VBHS = VAHS = 60V, VAHB = VBHB = 75V - 0.02 1.0 - 10 A 11.5 12.6 14.0 10.5 14.5 V -10 0 +10 -15 +15 mV IIB 0 0.5 2 0 4 A Input Offset Current IOS -1 0 +1 -2 +2 A Input Common Mode Voltage Range CMVR 1 - VDD - 1.5 1 VDD - 1.5 V AHB-AHS, BHB-BHS Qpump Output Voltage VAHB - VAHS IAHB = IAHB = 0, No Load VBHB - VBHS INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage Input Bias Current FN6397 Rev.2.00 March 20, 2007 VOS Over Common Mode Voltage Range Page 4 of 15 ISL83204A Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified (Continued) TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS TJ = -40°C to +125°C MIN TYP MAX MIN MAX UNITS - 25 - - - V/mV Voltage Gain AVOL OUT High Level Output Voltage VOH IN+ >IN-, IOH = -250A VDD - 0.4 - - VDD - 0.5 - V OUT Low Level Output Voltage VOL IN+ IN- HEN U/V DIS ALO AHO BLO BHO X X X 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 X X 1 X 0 0 0 0 FN6397 Rev.2.00 March 20, 2007 Page 6 of 15 ISL83204A Pin Descriptions PIN NUMBER SYMBOL 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 VSS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN6397 Rev.2.00 March 20, 2007 DESCRIPTION Page 7 of 15 ISL83204A Timing Diagrams tHPHL tDT tLPLH U/V = DIS 0 HEN 1 IN+ > INALO AHO BLO BHO tLPHL tHPLH tR tF (10% - 90%) (90% - 10%) tDT FIGURE 1. BI-STATE MODE tHEN-PHL tHEN-PLH U/V = DIS 0 HEN IN+ > INALO AHO BLO BHO FIGURE 2. HIGH SIDE CHOP MODE tDLPLH tDIS tREF-PW U/V or DIS HEN IN+ > INALO AHO BLO BHO tUEN FIGURE 3. DISABLE FUNCTION FN6397 Rev.2.00 March 20, 2007 Page 8 of 15 ISL83204A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified. 13.0 14 IDD SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 12.5 12 10 8 6 4 12.0 11.5 11.0 10.5 2 8 10 12 10.0 14 200k 400k 600k 800k SWITCHING FREQUENCY (Hz) 0 VDD SUPPLY VOLTAGE (V) FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 1M FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (Hz) +125°C 20 ICC SUPPLY CURRENT (mA) FLOATING SUPPLY BIAS CURRENT (mA) 5 15 10 5 0 +75°C 4 +25°C 0°C 3 -40°C 2 1 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M SWITCHING FREQUENCY (Hz) SWITCHING FREQUENCY (Hz) FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (Hz) TEMPERATURE 2.5 COMPARATOR INPUT CURRENT (A) FLOATING SUPPLY BIAS CURRENT (mA) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) 2.0 1.5 1.0 0.5 0.0 0 400k 200k 600k 800k SWITCHING FREQUENCY (Hz) 1M FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FN6397 Rev.2.00 March 20, 2007 1.0 0.5 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V Page 9 of 15 ISL83204A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified. (Continued) -180 LOW LEVEL INPUT CURRENT (A) LOW LEVEL INPUT CURRENT (A) -90 -100 -110 -120 -50 -25 0 25 50 75 100 -190 -200 -210 -220 -230 -40 125 -20 0 JUNCTION TEMPERATURE (°C) PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) 80 100 120 80 14 13 12 11 70 60 50 40 30 -20 0 20 40 60 80 100 -40 120 -20 JUNCTION TEMPERATURE (°C) 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY tDISHIGH vs TEMPERATURE 80 PROPAGATION DELAY (ns) 525 PROPAGATION DELAY (ns) 60 FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 15 500 475 450 425 -50 40 JUNCTION TEMPERATURE (°C) FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 10 -40 20 70 60 50 40 30 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) FIGURE 14. DISABLE TO UPPER ENABLE tUEN PROPAGATION DELAY vs TEMPERATURE FN6397 Rev.2.00 March 20, 2007 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY tDISLOW vs TEMPERATURE Page 10 of 15 ISL83204A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified. (Continued) 80 70 PROPAGATION DELAY (ns) REFRESH PULSE WIDTH (ns) 450 425 400 375 60 50 40 30 350 -50 -25 0 25 50 75 100 20 -40 125 150 -20 JUNCTION TEMPERATURE (°C) 40 60 80 100 120 FIGURE 17. DISABLE TO LOWER ENABLE tDLPLH PROPAGATION DELAY vs TEMPERATURE 90 PROPAGATION DELAY (ns) 90 PROPAGATION DELAY (ns) 20 JUNCTION TEMPERATURE (°C) FIGURE 16. tTREF-PW REFRESH PULSE WIDTH vs TEMPERATURE 80 70 60 50 80 70 60 50 40 40 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) -40 120 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY tHPHL vs TEMPERATURE FIGURE 19. UPPER TURN-ON PROPAGATION DELAY tHPLH vs TEMPERATURE 90 90 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 0 80 70 60 50 80 70 60 50 40 40 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY tLPHL vs TEMPERATURE FN6397 Rev.2.00 March 20, 2007 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 FIGURE 21. LOWER TURN-ON PROPAGATION DELAY tLPLH vs TEMPERATURE Page 11 of 15 ISL83204A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 13.5 13.5 12.5 12.5 TURN-ON RISE TIME (ns) GATE DRIVE FALL TIME (ns) 100K, and TA = +25°C, Unless Otherwise Specified. 11.5 10.5 9.5 8.5 -40 -20 0 20 40 60 80 100 11.5 10.5 9.5 8.5 -40 120 -20 0 JUNCTION TEMPERATURE (°C) FIGURE 22. GATE DRIVE FALL TIME tF vs TEMPERATURE 60 80 100 120 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 40 FIGURE 23. GATE DRIVE RISE TIME tR vs TEMPERATURE 6.0 5.0 1000 750 -40°C 0°C 500 4.5 +25°C 250 0 4.0 -40 -20 0 20 40 60 80 100 120 +75°C +125°C 10 12 JUNCTION TEMPERATURE (°C) FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100A 3.5 GATE DRIVE SINK CURRENT (A) 1500 1250 1000 750 -40°C 500 0°C +25°C 250 0 14 BIAS SUPPLY VOLTAGE (V) FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE VOL (mV) 20 JUNCTION TEMPERATURE (°C) +75°C +125°C 10 2.5 2.0 1.5 1.0 0.5 0.0 12 BIAS SUPPLY VOLTAGE (V) 14 FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100A FN6397 Rev.2.00 March 20, 2007 3.0 6 7 8 9 10 11 12 13 14 15 16 VCC, VDD, VAHG, VBHB (V) FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY VOLTAGE Page 12 of 15 ISL83204A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified. (Continued) 500 LOW VOLTAGE BIAS CURRENT (mA) GATE DRIVE SINK CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 14 15 200 100 10,000 50 3,000 20 1,000 10 100 5 2 1 0.5 0.2 0.1 16 1k 2k VCC, VDD, VABH, VBHB (V) 10k 20k 50k 100k 200k 500k 1M SWITCHING FREQUENCY (Hz) FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY VOLTAGE FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 9.0 BIAS SUPPLY VOLTAGE, VDD (V) 1000 500 LEVEL-SHIFT CURRENT (A) 5k 200 100 50 20 UV+ 8.8 8.6 UV8.4 8.2 10 10k 20k 50k 100k 200k 500k 1M 50 25 0 25 SWITCHING FREQUENCY (Hz) 50 75 100 125 FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 150 DEAD-TIME (ns) 120 90 60 30 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (k) 250 FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE FN6397 Rev.2.00 March 20, 2007 150 TEMPERATURE (°C) Page 13 of 15 ISL83204A Dual-In-Line Plastic Packages (PDIP) N E20.3 (JEDEC MS-001-AD ISSUE D) E1 INDEX AREA 1 2 3 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B- SYMBOL -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M C L eA A1 eC C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . MILLIMETERS MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 20 20 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6397 Rev.2.00 March 20, 2007 Page 14 of 15 ISL83204A Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.014 0.019 0.35 0.49 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e  B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N  NOTES: MILLIMETERS 20 0° 20 8° 0° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8° Rev. 2 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6397 Rev.2.00 March 20, 2007 Page 15 of 15