DATASHEET
ISL8323, ISL8324, ISL8325
Low-Voltage, Single Supply, Dual SPST Analog Switches
The Intersil ISL8323–ISL8325 devices are precision, dual
analog switches designed to operate from a single +2.7V to
+12V supply. Targeted applications include battery powered
equipment that benefit from the devices’ low power
consumption (5W), low leakage currents (100pA max), and
fast switching speeds. Excellent RON matching and flatness
maintain signal fidelity over the whole input range.
The ISL8323/ISL8324/ISL8325 are dual single-pole/singlethrow (SPST) devices. The ISL8323 has two normally open
(NO) switches; the ISL8324 has two normally closed (NC)
switches; the ISL8325 has one NO and one NC switch and
can be used as an SPDT. Table 1 summarizes the
performance of this family. For higher performance, pin
compatible versions, or SOT-23 packaged devices, see the
ISL5120-23 data sheet.
FN6023
Rev 2.00
October 7, 2015
Features
• Drop-in Replacements for MAX323 - MAX325 in Single
Supply Applications up to 12V.
• ON Resistance (RON) . . . . . . . . . . . . . . . . . . . 60 (Max)
• RON Matching Between Channels. . . . . . . . . . . . . 2 (Max)
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +12V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .2kV
Thermal Resistance (Typical, Note 5)
Operating Conditions
JA (oC/W)
8 LD SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Moisture Sensitivity (See Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Temperature Range
ISL832XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
4. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 7)
TYP
Full
0
-
V+
V
MAX
(NOTE 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
See Figure 5
25
-
-
60
Full
-
-
75
RON Matching Between Channels,
RON
V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3V
25
-
0.8
2
Full
-
-
4
RON Flatness, RFLAT(ON)
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V
Full
-
7
8
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
Note 8
25
-0.1
-
0.1
nA
Full
-5
-
5
nA
COM OFF Leakage Current,
ICOM(OFF)
V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V,
Note 8
25
-0.1
-
0.1
nA
Full
-5
-
5
nA
COM ON Leakage Current,
ICOM(ON)
V = 5.5V, VCOM = 5V, or VNO or VNC = 5V, Note 8
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
25
-
-
150
ns
ON Resistance, RON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V,
See Figure 1
Turn-OFF Time, tOFF
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V,
See Figure 1
Break-Before-Make Time Delay
(ISL8325), tD
Full
-
-
240
ns
25
-
-
100
ns
Full
-
-
150
ns
RL = 300, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V,
See Figure 3
Full
2
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0, See Figure 2
25
-
-
5
pC
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz, See Figure 4
25
-
72
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, See Figure 6
25
-
-85
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
9
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
9
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
22
-
pF
Full
2.7
Full
-1
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
FN6023 Rev 2.00
October 7, 2015
V+ = 5.5V, VIN = 0V or V+, all channels on or off
0.0001
12
V
1
A
Page 3 of 11
ISL8323, ISL8324, ISL8325
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 7)
TYP
MAX
(NOTE 7) UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
NOTES:
6. VIN = input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC.
Electrical Specifications - 3.3V Supply
PARAMETER
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 7)
Full
0
-
V+
V
25
-
-
175
Full
-
-
275
25
-
-
400
ns
500
ns
-
-
125
ns
TYP
MAX
(NOTE 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
Turn-OFF Time, tOFF
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
Full
-
-
175
ns
Break-Before-Make Time Delay
(ISL8325), tD
RL = 300, CL = 35pF, VNO or VNC = 1.5V,
VIN = 0 to 3V
Full
2
-
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0
25
-
-
5
pC
Full
-1
-
1
A
Full
25
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
FN6023 Rev 2.00
October 7, 2015
V+ = 3.6V, VIN = 0V or V+, all channels on or off
Page 4 of 11
ISL8323, ISL8324, ISL8325
Test Circuits and Waveforms
3V
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
0V
tOFF
SWITCH
INPUT VNO
VOUT
NO or NC
SWITCH
INPUT
COM
VOUT
IN
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
0V
CL
35pF
RL
1k
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R +R
L
FIGURE 1A. MEASUREMENT POINTS
ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
VOUT
RG
C
VOUT
COM
NO or NC
V+
LOGIC
INPUT
ON
ON
OFF
0V
VG
GND
IN
CL
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
3V
LOGIC
INPUT
0V
VOUT1
NO1
VNX
COM1
VOUT2 RL1
300
NC2
SWITCH
OUTPUT
VOUT1
90%
COM2
IN1
0V
RL2
300
IN2
SWITCH
OUTPUT
VOUT2
90%
0V
tD
LOGIC
INPUT
CL2
35pF
GND
tD
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS (ISL8325 ONLY)
FIGURE 3B. TEST CIRCUIT (ISL8325 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6023 Rev 2.00
October 7, 2015
Page 5 of 11
CL1
35pF
ISL8323, ISL8324, ISL8325
Test Circuits and Waveforms (Continued)
V+
V+
C
C
RON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
INX
0V or 2.4V
1mA
COM
ANALYZER
IN
V1
0.8V or 2.4V
COM
GND
GND
RL
FIGURE 5. RON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO1 or NC1
COM1
50
NO or NC
IN1
0V or 2.4V
COM2
ANALYZER
INX
IN2 0V or 2.4V
NO2 or NC2
GND
0V or 2.4V
IMPEDANCE
ANALYZER
NC
COM
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
FN6023 Rev 2.00
October 7, 2015
FIGURE 7. CAPACITANCE TEST CIRCUIT
Page 6 of 11
ISL8323, ISL8324, ISL8325
Detailed Description
Power-Supply Considerations
The ISL8323–ISL8325 dual analog switches offer precise
switching capability from a single 2.7V to 12V supply with
low on-resistance and high speed operation. The devices
are especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2.7V),
low power consumption (5W), low leakage currents (100pA
max), and the small SOIC packaging. High frequency
applications also benefit from the wide bandwidth, and the
very high off isolation and crosstalk rejection.
The ISL832X construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 13V
maximum supply voltage, the ISL832X 15V maximum
supply voltage provides plenty of room for the 10% tolerance
of 12V supplies, as well as room for overshoot and noise
spikes.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
FN6023 Rev 2.00
October 7, 2015
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the logic levels to switched V+ and
GND signals to drive the analog switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a
supply range of 3V to 11V (see Figure 12). At 12V the VIH
level is about 2.5V. This is still below the TTL guaranteed
high output minimum level of 2.8V, but noise margin is
reduced. For best results with a 12V supply, use a logic
family the provides a VOH greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog-signal
paths and V+ or GND.
Page 7 of 11
ISL8323, ISL8324, ISL8325
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
45
0.5
0.4
0.3
V+ = 3.3V
ICOM = 1mA
40
35
0.2
30
85oC
25
25oC
-40oC
15
30
25
RON ()
RON ()
20
V+ = 5V
85oC
25oC
-40oC
20
15
10
20
85oC
15
V+ = 12V
25oC
85oC
0.1
0
0.25
0.2
0.15
V+ = 5V
0.1
-40oC
0
4
2
6
VCOM (V)
8
10
12
V+ = 12V
25oC
-40oC
0.05
0
85oC
85oC
0.05
0
0.15
-40oC
-40oC
25oC
0.1
10
5
V+ = 3.3V
ICOM = 1mA
25oC
85oC
25oC
-40oC
0
4
2
6
VCOM (V)
8
10
12
FIGURE 10. RON MATCH vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
3.0
60
50
2.5
40
VINH AND VINL (V)
VINH
Q (pC)
30
20
V+ = 5V
10
V+ = 12V
V+ = 3.3V
0
85oC
25oC
1.5
85oC
-40oC
25oC
1.0
-10
-20
-40oC
2.0
VINL
85oC
0
4
2
6
VCOM (V)
8
10
12
0.5
2
FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE
100
5
4
6
7
8
V+ (V)
9
10
11
12
13
FIGURE 12. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
35
VCOM = (V+) - 1V
90
3
VCOM = (V+) - 1V
RL = 1k
RL = 1k
80
30
85oC
60
tOFF (ns)
tON (ns)
70
85oC
25
50
-40oC
-40oC
40
20
-40oC
25oC
30
20
25oC
2
3
4
5
6
7
V+ (V)
8
9
10
11
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FN6023 Rev 2.00
October 7, 2015
12
15
2
3
4
5
6
7
V+ (V)
8
9
10
11
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
Page 8 of 11
12
ISL8323, ISL8324, ISL8325
Die Characteristics
DIE DIMENSIONS:
ISL832X:
54 mils x 28 mils (1370m x 710m)
METALLIZATION:
Type: Metal 1: AISi(1%)
Thickness: Metal 1: 8kÅ
Type: Metal 2: AISi (1%)
Thickness: Metal 2: 10kÅ
PASSIVATION:
Type: Silox
Thickness: 13kÅ
TRANSISTOR COUNT:
ISL8323: 66
ISL8324: 66
ISL8325: 66
PROCESS:
Si Gate CMOS
SUBSTRATE POTENTIAL (POWERED UP):
GND
FN6023 Rev 2.00
October 7, 2015
Page 9 of 11
ISL8323, ISL8324, ISL8325
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 7, 2015
FN6023.1
CHANGE
Updated the Ordering Information table on page page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M8.15 to the latest revision. Changes are as follows:
-New Revision. Remove "u" symbol from drawing (overlaps the "a" on Side View).
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Changed Note 1 "1982" to "1994".
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2003-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6023 Rev 2.00
October 7, 2015
Page 10 of 11
ISL8323, ISL8324, ISL8325
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6023 Rev 2.00
October 7, 2015
Page 11 of 11
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