ISL8500IRZ-T

DATASHEET ISL8500 FN6611 Rev 0.00 December 10, 2007 2A Standard Buck PWM Regulator The ISL8500 is a high-performance, simple output controller that provides a single, high frequency power solution for a variety of point-of-load applications. The ISL8500 integrates a 2A standard buck PWM controller and switching MOSFET. The PWM controller in the ISL8500 drives an internal switching N-Channel power MOSFET and requires an external Schottky diode to generate an output voltage from 0.6V to 19V. The integrated power switch is optimized for excellent thermal performance up to 2A of output current. The standard buck input voltage range supports a fixed 5V or variable 5.5V to 25V range. The PWM regulator switches at a fixed frequency of 500kHz and utilizes simple voltage mode control with input voltage feed forward to provide flexibility in component selection and minimize solution size. Protection features include overcurrent, undervoltage and thermal overload protection integrated into the IC. The ISL8500 power good signal output indicates loss of regulation on the PWM output. ISL8500 is available in a small 4mmx3mm Dual Flat No-Lead (DFN) package. ISL8500IRZ PART TEMP. MARKING RANGE (°C) • Standard Buck Controller with Integrated Switching Power MOSFET • Integrated Boot Diode • Input Voltage Range - Fixed 5V ±10% - Variable 5.5V to 25V • PWM Output Voltage Adjustable from 0.6V to 19V with Continuous Output Current up to 2A • ±1% VFB Tolerance • Voltage Mode Control with Voltage Feed Forward • Fixed 500kHz Switching Frequency • Externally Adjustable Soft-Start Time • Output Undervoltage Protection • Enable Inputs • PGOOD Output • Overcurrent Protection Ordering Information PART NUMBER (Note) Features • Thermal Overload Protection PACKAGE (Pb-free) PKG. DWG. # 500Z -40 to +85 12 Ld DFN L12.4x3 ISL8500IRZ-T* 500Z -40 to +85 12 Ld DFN L12.4x3 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Internal 5V LDO regulator Applications • General Purpose • WLAN Cards-PCMCIA, Cardbus32, MiniPCI Cards-Compact Flash Cards • Hand-Held Instruments • LCD Panel • Set-top Box Pinout ISL8500 (12 LD DFN) TOP VIEW FB 1 12 VIN COMP 2 11 SS 3 VIN 10 PHASE DFN 4x3 EN 4 PG 5 GND FN6611 Rev 0.00 December 10, 2007 6 GND 9 PHASE 8 BOOT 7 VDD Page 1 of 15 ISL8500 Typical Application Schematic R3 301 C3 100pF VOUT C2 2.2nF R4 3.16k FB SS C1 10pF COMP R2 51.1k C5 0.1F R1 10k VIN 5.5V TO 25V C9 10uF EN PG ISL8500 L 10H PHASE BOOT C10 0.1F VOUT = 2.5V C11 100F D B340LB GND VDD C13 1µF FIGURE 1. VIN RANGE FROM 5.5V TO 25V FN6611 Rev 0.00 December 10, 2007 Page 2 of 15 ISL8500 BOOT FB COMP Functional Block Diagram VDD SOFT-START CONTROL 30µA VIN (x2) VOLTAGE MONITOR OC MONITOR PWM EA + - + - VDD SS 0.6V REFERENCE FAULT MONITOR EN THERMAL MONITOR +150°C RAMP GENERATOR VIN GATE DRIVE PHASE (x2) OSCILLATOR OC MONITOR POR VIN VDD LDO POWER-ON RESET MONITOR VDD GND PG EPAD GND FN6611 Rev 0.00 December 10, 2007 Page 3 of 15 ISL8500 Absolute Maximum Ratings (Note 1) Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 26V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.03V to 6V VDD, FB, EN, COMP, PG, SS . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Thermal Resistance Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 4.5V to 25V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . -40°C to +85° JA (°C/W) JC (°C/W) QFN Package (Notes 1, 2). . . . . . . . . . 39 3 Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details. 3. Test Condition: VIN = 15V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 4. Excluding the blanking time. 5. Specifications at -40°C to +85°C are established by +25°C test with margin limits. Electrical Specifications Unless Otherwise Noted, All Parameter Limits are Established Over the Recommended Operating Conditions and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 5), VIN = 5.5V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 5.5 - 25 V 4.5 5.0 5.5 V SUPPLY VOLTAGE VIN Voltage Range VIN VIN connected to VDD VIN Operating Supply Current IOP Note 3 - 2 2.5 mA VIN Shutdown Supply Current ISD VIN = 15V, EN = GND - 80 100 µA 4.00 4.15 4.30 V - 275 - mV 4.5 5.00 5.5 V VIN = 5.5V to 25V, IREF = 0 0.594 0.6 0.606 V FB Line Regulation IOUT = 0mA, VIN = 5.5V to 25V -0.05 - 0.05 % FB Leakage Current VFB = 0.6V -50 0 50 nA 450 500 550 kHz 0.65 0.75 0.95 V/V - 1.3 - V 0.75 0.8 0.85 V 80 - - % POWER-ON RESET VDD POR Threshold Rising Edge Hysteresis INTERNAL VDD LDO VDD Output Voltage Range VIN = 5.5V to 25V, IVDD = 0mA to 30mA REFERENCE Reference Voltage VFB STANDARD BUCK PWM REGULATOR OSCILLATOR AND PWM MODULATOR Nominal Switching Frequency fSW Modulator Gain AMOD VIN = 12V (AMOD = 8/VIN) Peak-to-Peak Sawtooth Amplitude VRAMP VIN = 12V (VP-P = VIN/8) PWM Ramp Offset Voltage Maximum Duty Cycle FN6611 Rev 0.00 December 10, 2007 VOFFSET DCmax COMP > 4V Page 4 of 15 ISL8500 Electrical Specifications Unless Otherwise Noted, All Parameter Limits are Established Over the Recommended Operating Conditions and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 5), VIN = 5.5V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 88 - dB - 15 - MHz - 5 - V/µs 1.2 1.7 2.2 V - 400 - mV -1 - 1 µA Rising Threshold - 150 - °C THYS Hysteresis - 15 - °C VUV Referred to Nominal VOUT 70 75 80 % - 270 - ns 2.56 3.2 3.94 A - 100 - ns Lower Level, Falling Edge, with typically 15mV hysteresis 85 88 91 % Upper Level, Rising Edge, with typically 15mV hysteresis 108 112 116 % - 9 - µs ERROR AMPLIFIER Open-Loop Gain Gain Bandwidth Product Slew Rate GBWP SR COMP = 10pF ENABLE SECTION EN Threshold Rising Edge Hysteresis EN Logic Input Current FAULT PROTECTION Thermal Shutdown Temperature PWM UV Trip Level TSD PWM UVP Propagation Delay PWM OCP Threshold VIN = VDD = 5V, Note 4 OCP Blanking Time POWER GOOD PG Trip Level Referred to Nominal VOUT PG Propagation Delay PG Low Voltage ISINK = 4mA - 0.05 0.3 V PG Leakage Current VPG = 5.5V, VFB = 0.6V, VDD = 5.5V -1 - 1 µA Soft-Start Threshold to Enable Buck 0.9 1 1.1 V Soft-Start Threshold to Enable PG 2.5 3.0 3.5 V - 3.45 - V 20 30 40 µA VSS = 3.0V - 25 - mA IOUT = 100mA, Die Resistance - 120 200 m SOFT-START SECTION Soft-Start Voltage High Soft-Start Charging Current Soft-Start Pull-down POWER MOSFET rDS(ON) FN6611 Rev 0.00 December 10, 2007 Page 5 of 15 ISL8500 Pin Descriptions BOOT (Pin 8) FB (Pin 1) and COMP (Pin 2) The standard buck regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. Connecting an AC network across COMP and FB provides loop compensation to the amplifier. In addition, the PWM regulator power good and undervoltage protection circuitry use FB to monitor the regulator output voltage. Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn and hold on the internal N-Channel MOSFET. Connect an external capacitor from this pin to PHASE. PHASE (Pins 9, 10) Switch node connections to internal power MOSFET source, external output inductor and external diode cathode. VIN (Pins 11, 12) The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF). SS (Pin 3) Program pin for soft-start duration. A regulated 30µA pull-up current source charges a capacitor connected from the pin to GND. The output voltage of the converter follows the ramping voltage on the SS pin. EN (Pin 4) PWM controller enable input. The PWM converter output is held off when the pin is pulled to ground. When the voltage on this pin rises above 1.7V, the chip is enabled. PG (Pin 5) PWM converter power good output. Open drain logic output that is pulled to ground when the output voltage is outside regulation limits. Connect a 100k resistor from this pin to VDD. Pin is low when the buck regulator output voltage is not within 10% of the respective nominal voltage, or during the soft-start interval. Pin is high impedance when the output is within regulation. GND (Pin 6) Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to GND and soldered to the PCB. All voltage levels are measured with respect to this pin. VDD (Pin 7) Internal 5V linear regulator output provides bias to all the internal control logic. The ISL8500 may be powered directly from a 5V (±10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VDD pin must always be decoupled to GND with a ceramic bypass capacitor (minimum 1µF) located close to the pin. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 5.5V to 25V Connect the input supply to the VIN pin only. The VDD pin will provide a 5V output from the internal linear regulator. 5V ±10% Connect the input supply to the VIN and VDD pins. FN6611 Rev 0.00 December 10, 2007 Page 6 of 15 ISL8500 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 10µH, COUT = 100µF, C2 = 2x22µF, IOUT = 0A to 2A. See “The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6. 100 2.5VOUT 90 100 1.8VOUT 80 70 1.2VOUT 60 1.5VOUT 50 40 3.3VOUT 30 70 60 50 1.5VOUT 1.2VOUT 40 0.5 1.0 1.5 20 0.0 2.0 0.5 OUTPUT LOAD (A) 1.4 EFFICIENCY (%) POWER DISSIPATION (W) 5VOUT 70 60 1.2VOUT 1.5VOUT 2.5VOUT 1.8VOUT 30 20 0.0 1.2 1.0 25VIN 0.8 0.6 12VIN 0.4 5VIN 0.2 0.5 1.0 1.5 0.0 0.0 2.0 0.5 FIGURE 4. EFFICIENCY vs LOAD, 25VIN 1.5 2.0 FIGURE 5. POWER DISSIPATION vs LOAD, 2.5VOUT 1.510 1.206 1.509 1.205 25VIN 12VIN 1.204 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.0 OUTPUT LOAD (A) OUTPUT LOAD (A) 1.203 1.202 1.201 5VIN 1.200 1.199 1.198 0.0 2.0 1.6 80 40 1.5 FIGURE 3. EFFICIENCY vs LOAD, 12VIN 12VOUT 50 1.0 OUTPUT LOAD (A) FIGURE 2. EFFICIENCY vs LOAD, 5VIN 90 1.8VOUT 30 20 0.0 100 5VOUT 80 EFFICIENCY (%) EFFICIENCY (%) 2.5VOUT 3.3VOUT 90 25VIN 12VIN 1.508 1.507 1.506 1.505 5VIN 1.504 1.503 0.5 1.0 1.5 OUTPUT LOAD (A) FIGURE 6. VOUT REGULATION vs LOAD, 1.2VOUT FN6611 Rev 0.00 December 10, 2007 2.0 1.502 0.0 0.5 1.0 1.5 OUTPUT LOAD (A) FIGURE 7. VOUT REGULATION vs LOAD, 1.5VOUT Page 7 of 15 2.0 ISL8500 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 10µH, COUT = 100µF, C2 = 2x22µF, IOUT = 0A to 2A. See “The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6. (Continued) 2.506 1.814 1.812 2.505 25VIN 12VIN OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.813 1.811 1.810 1.809 5VIN 1.808 2.503 12VIN 2.502 2.501 2.500 5VIN 2.499 1.807 1.806 0.0 25VIN 2.504 0.5 1.0 1.5 2.498 0.0 2.0 0.5 OUTPUT LOAD (A) FIGURE 8. VOUT REGULATION vs LOAD, 1.8VOUT 12VIN 4.98 25VIN OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.0 4.99 3.328 3.324 3.322 3.320 7VIN 3.318 3.316 3.314 0.0 1.5 FIGURE 9. VOUT REGULATION vs LOAD, 2.5VOUT 3.330 3.326 1.0 OUTPUT LOAD (A) 25VIN 4.97 4.96 4.95 7VIN 4.94 4.93 12VIN 4.92 0.5 1.0 1.5 2.0 4.91 0.0 0.5 FIGURE 10. VOUT REGULATION vs LOAD, 3.3VOUT 1.0 1.5 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 11. VOUT REGULATION vs LOAD, 5VOUT PHASE 10V/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV FIGURE 12. STEADY STATE OPERATION AT NO LOAD (5µs/DIV) FN6611 Rev 0.00 December 10, 2007 VOUT RIPPLE 20mV/DIV IL 1A/DIV FIGURE 13. STEADY STATE OPERATION AT FULL LOAD (1µs/DIV) Page 8 of 15 2.0 ISL8500 Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 10µH, COUT = 100µF, C2 = 2x22µF, IOUT = 0A to 2A. See “The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6. (Continued) PHASE 10V/DIV EN 5V/DIV VOUT 2V/DIV VOUT RIPPLE 100mV/DIV IL 0.5mA/DIV PG 5V/DIV IL 1A/DIV SS 5V/DIV FIGURE 14. LOAD TRANSIENT (200µs/DIV) FIGURE 15. SOFT-START AT NO LOAD (2ms/DIV) EN 5V/DIV EN 5V/DIV VOUT 2V/DIV VOUT 2V/DIV IL 2A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV SS 5V/DIV FIGURE 16. SOFT-START AT FULL LOAD (2ms/DIV) FIGURE 17. SHUT DOWN CIRCUIT (100µs/DIV) PHASE 10V/DIV PHASE 10V/DIV VOUT 1V/DIV VOUT 2V/DIV IL 2A/DIV PG 5V/DIV FIGURE 18. OUTPUT SHORT CIRCUIT (5µs/DIV) FN6611 Rev 0.00 December 10, 2007 IL 2A/DIV PG 5V/DIV FIGURE 19. OUTPUT SHORT CIRCUIT RECOVERY (1ms/DIV) Page 9 of 15 ISL8500 Detailed Description Power-On Reset and Undervoltage Lockout The ISL8500 combines a standard buck PWM controller with an integrated switching MOSFET. The buck controller drives an internal N-Channel MOSFET and requires an external diode to deliver load current up to 2A. A Schottky diode is recommended for improved efficiency and performance over a standard diode. The standard buck regulator can operate from either an unregulated DC source, such as a battery, with a voltage ranging from +5.5V to +25V, or from a regulated system rail of +5V. When operating from +5.5V or greater, the controller is biased from an internal +5V LDO voltage regulator. The converter output is regulated down to 0.6V from either input source. These features make the ISL8500 ideally suited for FPGA and wireless chipset power applications. The PWM portion of the ISL8500 automatically initializes upon receipt of input power. The power-on reset (POR) function continually monitors the VDD voltage. While below the POR thresholds, the controller inhibits switching off the internal power MOSFET. Once exceeded, the controller initializes the internal soft-start circuitry. If either input supply drops below their falling POR threshold during soft-start or operation, the buck regulator latches off. The PWM control loop uses a single output voltage loop with input voltage feed forward, which simplifies feedback loop compensation and rejects input voltage variation. External feedback loop compensation allows flexibility in output filter component selection. The regulator switches at a fixed 500kHz. The buck regulator is equipped with a lossless current limit scheme. The current limit in the buck regulator is achieved by monitoring the drain-to-source voltage drop of the internal switching power MOSFET. The current limit threshold is internally set at 3.5A. The part also features undervoltage protection by latching the switching MOSFET driver to the OFF-state during an overcurrent, when the output voltage is lower than 70% of the regulated output. This helps minimize power dissipation during a short-circuit condition. Due to only the switching power MOSFET integration, there is no overvoltage protection feature for this part. +5V Internal Bias Supply (VDD) Voltage applied to the VIN pin with respect to GND is regulated to +5V DC by an internal LDO regulator. The output of the LDO, VDD, is the bias voltage used by all the internal control and protection circuitry. The VDD pin requires a ceramic capacitor connected to GND. The capacitor serves to stabilize the LDO and to decouple load transients. The input voltage range for the ISL8500 is specified as +5.5V to +25V or +5V ±10%. In the case of an unregulated supply case, the power supply is connected to VIN only. Once enabled, the linear regulator will turn-on and rise to +5V on VDD. In the +5V supply case, the VDD and VIN pins must be tied together to bypass the LDO. The external decoupling capacitor is still required in this mode. Operation Initialization The power-on reset circuitry and enable inputs prevent false start-up of the PWM regulator output. Once all the input criteria are met, the controller soft-starts the output voltage to the programmed level. FN6611 Rev 0.00 December 10, 2007 Enable and Disable All internal power devices are held in a high-impedance state, which ensures they remain off while in shutdown mode. Typically, the enable input for a specific output is toggled high after the input supply to that regulator is active and the internal LDO has exceeded it’s POR threshold. The EN pin enables the buck controller portion of the ISL8500. When the voltage on the EN pin exceeds the POR rising threshold, the controller initiates the soft-start function for the PWM regulator. If the voltage on the EN pin drops below the POR falling threshold, the buck regulator shuts down. Pulling the EN pin low simultaneously put the output into shutdown mode and supply current drops to 100µA typical. Soft-Start Once the input supply latch and enable threshold are met, the soft-start function is initialized. The soft-start circuitry begins sourcing 30µA, from an internal current source, which charges the external soft-start capacitor. The voltage on SS begins ramping linearly from ground until the voltage across the soft-start capacitor reaches 3.0V. This linear ramp is applied to the non-inverting input of the internal error amplifier and overrides the nominal 0.6V reference. The output voltage reaches its regulation value when the soft-start capacitor voltage reaches 1.6V. Connect a capacitor from SS pin to ground. This capacitor (along with an internal 30µA current source) sets the soft-start interval of the converter, TSS. C SS  F  = 50  T SS  s  (EQ. 1) Upon disable, the SS pin voltage will discharge to zero voltage. Power Good PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After the soft-start period terminates, PG becomes high impedance as long as the output voltage is within ±12% of the nominal regulation voltage set by FB. When VOUT drops 12% below or rises 12% above the nominal regulation voltage, the ISL8500 pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor between PG and VDD. A 100k resistor works well in most applications. Page 10 of 15 ISL8500 Output Voltage Selection The regulator output voltages can be programmed using external resistor dividers that scale the voltage feedback relative to the internal reference voltage. The scaled voltage is fed back to the inverting input of the error amplifier; refer to Figure 20. The output voltage programming resistor, R4, will depend on the value chosen for the feedback resistor, R1, and the desired output voltage, VOUT, of the regulator; see Equation 2. The value for the feedback resistor is typically between 1k and 10k. R 1  0.6V R 4 = ---------------------------------V OUT – 0.6V (EQ. 2) The protection circuitry attempts to recover from the overcurrent condition after waiting 4 soft-start cycles. The internal overcurrent flag and counter are reset. A normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. If the overcurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. There is 100ns blanking time for noise immunity. It is recommended to operate the duty cycle higher than the blanking time to insure proper overcurrent protection. If the output voltage desired is 0.6V, then RP is left unpopulated. VOUT R1 + - EA cycles, the overcurrent fault counter overflows, indicating an overcurrent fault condition exists. The regulator is shut down and power good goes low. If the overcurrent condition clears prior to the counter reaching four consecutive cycles, the internal flag and counter are reset. R4 0.6V REFERENCE FIGURE 20. EXTERNAL RESISTOR DIVIDER The buck output can be programmed as high as 19V. Proper heatsinking must be provided to insure that the junction temperature does not exceed +125°C. When the output is set greater than 2.7V, it is recommended to pre-load at least 10mA and make sure that the input rise time is >> faster than the VOUT1 rise time. This allows the BOOT capacitor adequate time to charge for proper operation. Protection Features The ISL8500 limits current in the power devices to limit on-chip power dissipation. Overcurrent limits on the regulator protect the internal power device from excessive thermal damage. Undervoltage protection circuitry on the buck regulator provides a second layer of protection for the internal power device under high current condition. Undervoltage Protection If the voltage detected on the buck regulator FB pin falls 25% below the internal reference voltage, the undervoltage fault condition flag is set. The regulator is shutdown. The controller enters a recovery mode similar to the overcurrent hiccup mode. No action is taken for 4 soft-start cycles and the internal undervoltage counter and fault condition flag are reset. A normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. If the undervoltage counter overflows during soft-start, the converter is shut down and this hiccup mode operation repeats. Thermal Overload Protection Thermal overload protection limits total power dissipation in the ISL8500. There is a sensor on the chip to monitor the junction temperature of the internal LDO and PWM switching power N-Channel MOSFET. When the junction temperature (TJ) of the sensor exceeds +150°C, the thermal sensor sends a signal to the fault monitor. The fault monitor commands the buck regulator to shut down. The buck regulator soft-starts turn on again after the IC’s junction temperature cools by +20°C. The buck regulator experiences hiccup mode operation during continuous thermal overload conditions. For continuous operation, do not exceed the +125°C junction temperature rating. Buck Regulator Overcurrent Protection During the PWM on-time, the current through the internal switching MOSFET is sampled and scaled through an internal pilot device. The sampled current is compared to a nominal 3.5A overcurrent limit. If the sampled current exceeds the overcurrent limit reference level, an internal overcurrent fault counter is set to 1 and an internal flag is set. The internal power MOSFET is immediately turned off and will not be turned on again until the next switching cycle. The protection circuitry continues to monitor the current and turns off the internal MOSFET as described. If the overcurrent condition persists for eight sequential clock FN6611 Rev 0.00 December 10, 2007 Application Guidelines Operating Frequency The ISL8500 operates at a fixed switching frequency of 500kHz. Buck Regulator Output Capacitor Selection An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the Page 11 of 15 ISL8500 transient load current. These requirements are generally met with a mix of capacitors and careful layout. Embedded processor systems are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switchingregulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equation 3: I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR (EQ. 3) Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8500 will provide either 0% or 80% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. FN6611 Rev 0.00 December 10, 2007 The response time to a transient is different for the application of load and the removal of load. Equation 4 gives the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 4) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check Equation 4 at the minimum and maximum output levels for the worst case response time. Rectifier Selection Current circulates from ground to the junction of the MOSFET and the inductor when the high-side switch is off. As a consequence, the polarity of the switching node is negative with respect to ground. This voltage is approximately -0.5V (a Schottky diode drop) during the off-time. The rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. The power dissipation is shown in Equation 5: V OUT  P D  W  = I OUT  V D   1 – ---------------- V IN   (EQ. 5) where VD is the voltage of the Schottky diode = 0.5V to 0.7V Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the switching MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFET VIN pins (switching MOSFET drain) and the Schottky diode anode. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through Equation 6: I RMS MAX = V OUT  V IN – V OUT V OUT 2 2 1 --------------  I OUT + ------   -----------------------------  --------------    V IN V IN   L  fs 12 MAX (EQ. 6) For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors Page 12 of 15 ISL8500 must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. VIN DRIVER OSC PWM COMPARATOR VDDQ PHASE 5. Place 2ND Pole at Half the Switching Frequency. ESR (PARASITIC) 6. Check Gain against Error Amplifier’s Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. ZIN + Compensation Break Frequency Equations REFERENCE DETAILED COMPENSATION COMPONENTS ZFB C1 C2 C3 FB + ISL8500 R3 R1 COMP 1 F P1 = -------------------------------------------------------- C 1 x C 2 2 x R 2 x  ----------------------  C1 + C2  1 F Z2 = ------------------------------------------------------2 x  R 1 + R 3  x C 3 1 F P2 = -----------------------------------2 x R 3 x C 3 VOUT ZIN R2 1 F Z1 = -----------------------------------2 x R 2 x C 2 R4 REFERENCE FIGURE 21. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION Feedback Compensation Figure 21 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC . 100 1 F ESR = -------------------------------------------2 x ESR x C O FP2 OPEN LOOP ERROR AMP GAIN 60 40 20 20LOG (R2/R1) 20LOG (VIN/VOSC) 0 COMPENSATION GAIN MODULATOR GAIN -20 CLOSED LOOP GAIN FLC 10 100 1k FESR 10k 100k 1M 10M FREQUENCY (Hz) (EQ. 7) The compensation network consists of the error amplifier (internal to the ISL8500) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180°. Equation 8 relates the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in FN6611 Rev 0.00 December 10, 2007 FP1 80 -60 1 F LC = ------------------------------------------2 x L O x C O FZ1 FZ2 -40 Modulator Break Frequency Equations (EQ. 8) Figure 22 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 22. Using the previously mentioned guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 4 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. GAIN (dB) VE/A ERROR AMP 3. Place 2ND Zero at Filter’s Double Pole. 4. Place 1ST Pole at the ESR Zero. CO D ZFB 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). LO + VOSC Figure 22. Use the following guidelines for locating the poles and zeros of the compensation network: FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. Page 13 of 15 ISL8500 A more detailed explanation of voltage mode control of a buck regulator can be found in TB417, entitled “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators.” VIN VIN CIN ISL8500 Layout Considerations As an example, consider the turn-off transition of the upper MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL8500 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 23 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. L VDD 5V VOUT1 PHASE CBP1 GND COMP D LOAD Layout is very important in high frequency switching converter design. With power devices switching efficiently between 100kHz and 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. COUT1 C2 C1 R2 R1 FB R4 C3 R3 GND PAD KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 23. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS In order to dissipate heat generated by the internal LDO and MOSFET, the ground pad, pin 13, should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL8500 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper and Schottky diode and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required. © Copyright Intersil Americas LLC 2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6611 Rev 0.00 December 10, 2007 Page 14 of 15 ISL8500 Dual Flat No-Lead Plastic Package (DFN) L12.4x3 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C) 2X 0.15 C A A D MILLIMETERS 2X 0.15 C B SYMBOL 0.80 A1 - A3 E b 6 INDEX AREA D2 B 0.18 // A SIDE VIEW C SEATING PLANE 0.08 A3 C - - 0.05 - 0.23 0.30 5,8 3.15 3.30 3.40 7,8 3.00 BSC 1.55 e 1.70 1.80 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 12 2 Nd 6 3 7 NOTES: 8 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. D2/2 1 C NOTES 1.00 Rev. 1 2/05 D2 (DATUM B) 0.10 MAX 0.90 4.00 BSC E E2 NOMINAL 0.20 REF D TOP VIEW 6 INDEX AREA MIN A 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 2 4. All dimensions are in millimeters. Angles are in degrees. NX k 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. (DATUM A) E2/2 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW NX (b) 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 5 0.10 M C A B CL (A1) L 5 e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE FN6611 Rev 0.00 December 10, 2007 Page 15 of 15