DATASHEET
ISL85412
FN8378
Rev 1.00
March 13, 2015
Wide VIN 150mA Synchronous Buck Regulator
The ISL85412 is a 150mA synchronous buck regulator with an
input range of 3.5V to 40V. It provides an easy to use, high
efficiency low BOM count solution for a variety of applications.
Features
The ISL85412 integrates both high-side and low-side NMOS
FETs and features a PFM mode for improved efficiency at light
loads. This feature can be disabled if forced PWM mode is
desired. The part switches at a default frequency of 700kHz.
By integrating both NMOS devices and providing internal
configuration, minimal external components are required,
reducing BOM count and complexity of design.
• Synchronous operation for high efficiency
With the wide VIN range and reduced BOM, the part provides
an easy to implement design solution for a variety of
applications while giving superior performance. It will provide
a very robust design for high voltage industrial applications as
well as an efficient solution for battery powered applications.
• Internal soft-start
The part is available in a small Pb-free 3mmx3mm TDFN
plastic package with an operation junction temperature range
of -40°C to +125°C.
• Wide input voltage range of 3.5V to 40V
• No compensation required
• Integrated high-side and low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal switching frequency 700kHz
• Continuous output current up to 150mA
• Minimal external components required
• Power-good and enable functions available
Applications
• Industrial control
• Medical devices
• Portable instrumentation
Related Literature
• Distributed power supplies
• AN1929, “ISL85413EVAL1Z, ISL85412EVAL1Z Evaluation
Boards”
• Cloud infrastructure
• AN1931, “ISL85413DEMO1Z, ISL85412DEMO1Z Wide VIN
Synchronous Buck Regulator - Short Form”
100
VOUT
VIN
GND
C6
0.1µF
C1
20µF
3
4
fSW = 700kHz
VOUT
GND
MAX 150mA
C8
L1
FB
BOOT
VCC
VIN
PHASE
PG
PGND
+3.5 ... +40V
2
MODE
9
MODE
EN
90
C4
R1
8
R2
7
6
C5
1µF
5
Device must be
connected to GND
plane with vias.
PG
EN
EFFICIENCY (%)
U1 ISL85412
1
80
70
3.3VOUT
1.5VOUT
60
1.2VOUT
1.8VOUT
1.0VOUT
50
40
0.00
0.03
0.06
5.0VOUT
2.5VOUT
0.09
0.12
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION
FN8378 Rev 1.00
March 13, 2015
FIGURE 2. EFFICIENCY vs LOAD, PFM, VIN = 12V
Page 1 of 19
0.15
ISL85412
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Efficiency Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
15
16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
17
17
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
17
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8378 Rev 1.00
March 13, 2015
Page 2 of 19
ISL85412
Pin Configuration
ISL85412
(8 LD 3x3 TDFN)
TOP VIEW
MODE 1
8
FB
7
VCC
VIN 3
6
PG
PHASE 4
5
EN
BOOT 2
GND
Pin Descriptions
PIN #
SYMBOL
PIN DESCRIPTION
1
MODE
Mode Selection pin. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for PFM
mode. Logic ground enables the IC to automatically choose PFM or PWM operation. There is an internal
5MΩ pull-down resistor to prevent an undefined logic state if MODE is left floating.
2
BOOT
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-channel MOSFET. Connect an external 100nF capacitor from this
pin to PHASE.
3
VIN
The input supply for the power stage of the regulator and the source for the internal linear bias regulator.
Place a minimum of 10µF ceramic capacitance from VIN to GND and close to the IC for decoupling.
4
PHASE
5
EN
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the
voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not
connect EN pin to VCC since the LDO is controlled by EN voltage.
6
PG
Open drain power-good output that is pulled to ground when the output voltage is below regulation limits
or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
7
VCC
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.
8
FB
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In
addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.
EPAD
GND
Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage levels
are measured with respect to this pin. The EPAD MUST not float.
Switch node output. It connects the switching FETs with the external output inductor.
TABLE 1. EXTERNAL COMPONENT SELECTION (Refer to Figure 1)
VOUT
(V)
C4
(pF)
C8
(µF)
L1
(µH)
R1
(kΩ)
R2
(kΩ)
1.0
100
2x22
10
90.9
137
1.2
100
2x22
10
90.9
90.9
1.5
100
2x22
16
90.9
60.4
1.8
100
2x22
16
90.9
45.3
2.5
100
22
22
90.9
28.7
3.3
100
22
33
90.9
20.0
5.0
100
22
47
90.9
12.4
12.0
100
22
100
90.9
4.75
FN8378 Rev 1.00
March 13, 2015
Page 3 of 19
ISL85412
Functional Block Diagram
VIN
PG
EN
FB
POWERGOOD
LOGIC
5M
VCC
BIAS
LDO
EN/SOFTSTART
FB
FAULT
LOGIC
600mV VREF
MODE
930mV/A
CURRENT
SENSE
OSCILLATOR
5M
PWM/PFM
SELECT LOGIC
PFM
CURRENT
SET
BOOT
FB
GATE
DRIVE
AND
PWM DEADTIME
PWM
s Q
R Q
ZERO CURRENT
DETECTION
PHASE
PGND
450mV/T SLOPE
COMPENSATION
(PWM ONLY)
150k
INTERNAL = 50µs
54pF
INTERNAL
COMPENSATION
PACKAGE
PADDLE
GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL85412FRTZ
5412
ISL85412EVAL1Z
Evaluation Board
ISL85412DEMO1Z
Demonstration Board
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(RoHS Compliant)
8 Ld TDFN
PKG.
DWG. #
L8.3x3H
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85412. For more information on MSL please see techbrief TB363.
FN8378 Rev 1.00
March 13, 2015
Page 4 of 19
ISL85412
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 44V (20ns)
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FS, PG, MODE, SS, VCC to GND. . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
TDFN Package (Note 4, 5) . . . . . . . . . . . . . .
47
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5V to 40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TJ = -40°C to +125°C, VIN = 3.5V to 40V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction temperature range.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8
UNITS
40
V
SUPPLY VOLTAGE
VIN Voltage Range
VIN
3.5
VIN Quiescent Supply Current
IQ
VFB = 0.7V, MODE = 0V
50
VIN Shutdown Supply Current
ISD
EN = 0V, VIN = 40V (Note 6)
1.8
2.5
µA
µA
VCC Voltage
VCC
VIN = 40V
4.5
5.1
5.5
V
VIN = 12V; IOUT = 0A to 10mA
4.35
5
5.45
V
3.3
3.46
V
POWER-ON RESET
VCC POR Threshold
Rising Edge
Falling Edge
2.76
600
3
V
OSCILLATOR
Nominal Switching Frequency
fSW
fSW = VCC
Minimum Off-Time
tOFF
VIN = 3.5V
130
700
784
kHz
ns
Minimum On-Time
tON
(Note 9)
90
ns
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
gm
Current Sense Amplifier Gain
FB Voltage
50
VFB = 0.6V
FB Leakage Current
RT
TA = -40°C to +125°C
µA/V
1
100
nA
0.84
0.93
1.02
V/A
0.589
0.599
0.606
V
91
94
%
POWER-GOOD
Lower PG Threshold - VFB Rising
Lower PG Threshold - VFB Falling
81.5
Upper PG Threshold - VFB Rising
85
118
Upper PG Threshold - VFB Falling
121
%
111
%
PG Propagation Delay
Percentage of the soft-start time
10
%
PG Low Voltage
ISINK = 3mA, EN = VCC, VFB = 0V
0.05
FN8378 Rev 1.00
March 13, 2015
107
%
0.3
V
Page 5 of 19
ISL85412
Electrical Specifications TJ = -40°C to +125°C, VIN = 3.5V to 40V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction temperature range. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8
UNITS
1.5
2.3
3.1
ms
TRACKING AND SOFT-START
Internal Soft-Start Ramp Time
EN/SS = VCC
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
Rising Threshold
150
°C
THYS
Hysteresis
20
°C
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
PFM Peak Current Limit
IPK_PFM
(Note 7)
0.36
0.4
0.44
A
0.17
0.22
0.27
A
-0.33
-0.30
-0.27
A
1300
mΩ
Zero Cross Threshold
Negative Current Limit
5
INLIMIT
(Note 7)
mA
POWER MOSFET
High-side
RHDS
IPHASE = 100mA, VCC = 5V
900
Low-side
RLDS
IPHASE = 100mA, VCC = 5V
500
800
mΩ
EN = PHASE = 0V
50
300
nA
VIN = 40V
10
PHASE Leakage Current
PHASE Rise Time
tRISE
ns
EN/MODE
Mode Input Threshold
Rising Edge, Logic High
Falling Edge, Logic Low
EN Threshold
1.3
0.4
Rising Edge, Logic High
1.2
Falling Edge, Logic Low
0.4
EN Logic Input Leakage Current
EN = 0V/40V
-0.5
MODE Logic Input Leakage Current
MODE = 0V
MODE Pull-down Resistor
1.45
1.0
V
V
1.45
0.9
V
V
0.5
µA
10
100
nA
5
6.15
MΩ
NOTES:
6. Test Condition: VIN = 40V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included.
7. Established by both current sense amplifier gain test and current sense amplifier output test at IL = 0A.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Minimum On-Time required to maintain loop stability.
FN8378 Rev 1.00
March 13, 2015
Page 6 of 19
ISL85412
fSW = 700kHz, TA = +25°C, CIN = 20µF
100
100
90
90
80
1.5VOUT
70
1.8VOUT
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency Curves
3.3VOUT
2.5VOUT
1.2VOUT
60
1.0VOUT
50
40
0
80
1.8VOUT
70
1.5VOUT
0.06
0.09
OUTPUT LOAD (A)
0.12
40
0.15
1.0VOUT
0
100
100
90
90
80
70
60
1.2VOUT
3.3VOUT
50
1.0VOUT
40
0
0.03
1.8VOUT
40
0.15
1.5VOUT
90
90
80
70
1.2VOUT
50
40
1.8VOUT
1.0VOUT
0
0.03
0.06
0.09
3.3VOUT
12VOUT
1.2VOUT
1.0VOUT
0
OUTPUT LOAD (A)
FIGURE 7. EFFICIENCY vs LOAD, PFM, VIN = 24V
FN8378 Rev 1.00
March 13, 2015
0.03
0.06
0.09
OUTPUT LOAD (A)
2.5VOUT
0.12
0.15
0.15
5.0VOUT
12VOUT
80
70
60
1.5VOUT
1.2VOUT
50
5.0VOUT
0.12
EFFICIENCY (%)
EFFICIENCY (%)
100
2.5VOUT
5.0VOUT
2.5VOUT
FIGURE 6. EFFICIENCY vs LOAD, PWM, VIN = 12V
100
1.5VOUT
0.15
3.3VOUT
1.8VOUT
60
FIGURE 5. EFFICIENCY vs LOAD, PFM, VIN = 12V
60
0.12
70
50
0.12
0.06
0.09
OUTPUT LOAD (A)
80
5.0VOUT
2.5VOUT
0.06
0.09
OUTPUT LOAD (A)
0.03
FIGURE 4. EFFICIENCY vs LOAD, PWM, VIN = 5V
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 3. EFFICIENCY vs LOAD, PFM, VIN = 5V
1.5VOUT
3.3VOUT
1.2VOUT
60
50
0.03
2.5VOUT
40
1.8VOUT
1.0VOUT
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD, PWM, VIN = 24V
Page 7 of 19
ISL85412
Efficiency Curves
fSW = 700kHz, TA = +25°C, CIN = 20µF (Continued)
100
100
12VOUT
5.0VOUT
90
5.0VOUT
90
12VOUT
EFFICIENCY (%)
EFFICIENCY (%)
3.3VOUT
80
70
60
50
40
0
1.5VOUT
1.2VOUT
2.5VOUT
0.03
0.06
0.09
3.3VOUT
70 2.5VOUT
60
50
1.8VOUT
0.12
80
40
0.15
1.2VOUT
0
0.03
0.06
OUTPUT LOAD (A)
0.15
1.23
5VIN PFM
5VIN PFM
24VIN PFM
1.010
12VIN PFM
1.005
1.000
0.995
12VIN PWM
5VIN PWM
0
0.03
24VIN PWM
0.06
0.09
OUTPUT LOAD (A)
0.12
1.19
36VIN PFM
24VIN PFM
1.50
5VIN PWM
1.47
0
12VIN PWM
0.03
24VIN PWM
0.06
0.09
36VIN PWM
0.12
0.15
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD, PWM, VOUT = 1.5V
FN8378 Rev 1.00
March 13, 2015
OUTPUT VOLTAGE (V)
1.82
1.49
12VIN PWM
36VIN PWM
0
0.03
0.06
0.09
OUTPUT LOAD (A)
0.12
0.15
FIGURE 12. VOUT REGULATION vs LOAD, VOUT = 1.2V
1.55
1.52
5VIN PWM
1.18
1.83
12VIN PFM
12VIN PFM
1.20
1.56
5VIN PFM
36VIN PFM
1.21
1.17
0.15
FIGURE 11. VOUT REGULATION vs LOAD, VOUT = 1V
1.53
24VIN PFM
1.22
OUTPUT VOLTAGE (V)
1.015
OUTPUT VOLTAGE (V)
0.12
FIGURE 10. EFFICIENCY vs LOAD, PWM, VIN = 36V
1.020
OUTPUT VOLTAGE (V)
0.09
1.8VOUT
OUTPUT LOAD (A)
FIGURE 9. EFFICIENCY vs LOAD, PFM, VIN = 36V
0.990
1.5VOUT
5VIN PFM
24VIN PFM 12VIN PFM
36VIN PFM
1.81
1.80
5VIN PWM
1.79
12VIN PWM
24VIN PWM
36VIN PWM
1.78
1.77
0
0.03
0.06
0.09
OUTPUT LOAD (A)
0.12
0.15
FIGURE 14. VOUT REGULATION vs LOAD, VOUT = 1.8V
Page 8 of 19
ISL85412
Efficiency Curves
2.55
fSW = 700kHz, TA = +25°C, CIN = 20µF (Continued)
2.54
2.53
12VIN PFM
24VIN PFM
2.52
2.51
12VIN PWM
5VIN PWM
2.50
2.49
24VIN PWM
0
0.03
36VIN PWM
0.06
0.09
OUTPUT LOAD (A)
0.12
3.31
3.30 5VIN PWM
0.15
12.28
12VIN PFM
36VIN PFM
24VIN PFM
5.00
4.98
12VIN PWM
0
0.03
36VIN PWM
0.06
0.09
OUTPUT LOAD (A)
0.12
FIGURE 17. VOUT REGULATION vs LOAD, VOUT = 5V
FN8378 Rev 1.00
March 13, 2015
36VIN PWM
0
0.03
0.06
0.09
OUTPUT LOAD (A)
0.12
0.15
FIGURE 16. VOUT REGULATION vs LOAD, VOUT = 3.3V
5.03
4.95
12VIN PWM
24VIN PWM
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
24VIN PFM
12.35
24VIN PWM
36VIN PFM
3.32
5.04
4.97
5VIN PFM
3.33
3.29
FIGURE 15. VOUT REGULATION vs LOAD, VOUT = 2.5V
5.01
12VIN PFM
3.34
36VIN PFM
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.35
5VIN PFM
0.15
24VIN PFM
12.20
12.13
36VIN PFM
12.05
24VIN PWM
11.98
11.90
0
0.03
36VIN PWM
0.06
0.09
OUTPUT LOAD (A)
0.12
0.15
FIGURE 18. VOUT REGULATION vs LOAD, VOUT = 12V
Page 9 of 19
ISL85412
Typical Performance Curves
COUT = 22µF.
VIN = 12V, VOUT = 3.3V, fSW = 700kHz, TA = +25°C, CIN = 20µF,
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 19. START-UP AT NO LOAD, PFM
FIGURE 20. START-UP AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
100ms/DIV
FIGURE 21. SHUTDOWN IN NO LOAD, PFM
100ms/DIV
FIGURE 22. SHUTDOWN AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
2ms/DIV
FIGURE 23. START-UP AT 150mA, PWM
FIGURE 24. SHUTDOWN AT 150mA, PWM
FN8378 Rev 1.00
March 13, 2015
Page 10 of 19
ISL85412
Typical Performance Curves
COUT = 22µF. (Continued)
VIN = 12V, VOUT = 3.3V, fSW = 700kHz, TA = +25°C, CIN = 20µF,
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
5ms/DIV
FIGURE 25. START-UP AT 150mA, PFM
FIGURE 26. SHUTDOWN AT 150mA, PFM
VIN 10V/DIV
VIN 10V/DIV
VOUT 1V/DIV
VOUT 2V/DIV
IL 100mA/DIV
IL 100mA/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 27. START-UP VIN AT 150mA LOAD, PFM
FIGURE 28. START-UP VIN AT 150mA LOAD, PWM
VIN 10V/DIV
VIN 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 100mA/DIV
IL 100mA/DIV
PG 5V/DIV
PG 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 29. SHUTDOWN VIN AT 150mA LOAD, PFM
FIGURE 30. SHUTDOWN VIN AT 150mA LOAD, PWM
FN8378 Rev 1.00
March 13, 2015
Page 11 of 19
ISL85412
Typical Performance Curves
COUT = 22µF. (Continued)
VIN = 12V, VOUT = 3.3V, fSW = 700kHz, TA = +25°C, CIN = 20µF,
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
VIN 10v/DIV
VIN 10v/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 31. START-UP VIN AT NO LOAD, PFM
FIGURE 32. START-UP VIN AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 1V/DIV
VOUT 2V/DIV
VIN 5v/DIV
VIN 10v/DIV
PG 5V/DIV
PG 5V/DIV
100ms/DIV
100ms/DIV
FIGURE 33. SHUTDOWN VIN AT NO LOAD, PFM
FIGURE 34. SHUTDOWN VIN AT NO LOAD, PWM
PHASE 1V/DIV
PHASE 1V/DIV
100ns/DIV
100ns/DIV
FIGURE 35. JITTER AT NO LOAD, PWM
FIGURE 36. JITTER AT FULL LOAD, PWM
FN8378 Rev 1.00
March 13, 2015
Page 12 of 19
ISL85412
Typical Performance Curves
VIN = 12V, VOUT = 3.3V, fSW = 700kHz, TA = +25°C, CIN = 20µF,
PHASE 10V/DIV
PHASE 10V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
COUT = 22µF. (Continued)
IL 100mA/DIV
IL 100mA/DIV
5ms/DIV
1µs/DIV
FIGURE 37. STEADY STATE AT NO LOAD, PFM
FIGURE 38. STEADY STATE AT NO LOAD, PWM
PHASE 10V/DIV
VOUT 20mV/DIV
IL 100mA/DIV
PHASE 10V/DIV
VOUT 20mV/DIV
IL 100mA/DIV
1µs/DIV
2µs/DIV
FIGURE 39. STEADY STATE AT 150mA LOAD, PWM
FIGURE 40. STEADY STATE AT 20mA LOAD, PFM
VOUT RIPPLE 100mV/DIV
IL 100mA/DIV
VOUT RIPPLE 50mV/DIV
IL 100mA/DIV
200µs/DIV
200µs/DIV
FIGURE 41. LOAD TRANSIENT, PFM
FIGURE 42. LOAD TRANSIENT, PWM
FN8378 Rev 1.00
March 13, 2015
Page 13 of 19
ISL85412
Typical Performance Curves
COUT = 22µF. (Continued)
VIN = 12V, VOUT = 3.3V, fSW = 700kHz, TA = +25°C, CIN = 20µF,
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 500mA/DIV
PG 5V/DIV
PG 5V/DIV
20µs/DIV
10ms/DIV
FIGURE 43. OUTPUT SHORT CIRCUIT
FIGURE 44. OVERCURRENT PROTECTION
PHASE1 10V/DIV
PHASE1 10V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL 50mA/DIV
IL 50mA/DIV
10µs/DIV
5µs/DIV
FIGURE 45. PFM TO PWM TRANSITION
PHASE 10V/DIV
FIGURE 46. PWM TO PFM TRANSITION
VOUT 2V/DIV
IL 200mA/DIV
VOUT 2V/DIV
PG 2V/DIV
PG 5V/DIV
10µs/DIV
FIGURE 47. OVERVOLTAGE PROTECTION
FN8378 Rev 1.00
March 13, 2015
200ms/DIV
FIGURE 48. OVERTEMPERATURE PROTECTION
Page 14 of 19
ISL85412
Detailed Description
The ISL85412 combines a synchronous buck PWM controller
with integrated power switches. The buck controller drives
internal high-side and low-side N-channel MOSFETs to deliver
load current up to 150mA. The buck regulator can operate from
an unregulated DC source, such as a battery, with a voltage
ranging from +3.5V to +40V. An internal LDO provides bias to the
low voltage portions of the IC.
Peak current mode control is utilized to simplify feedback loop
compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design.
The ISL85412 switches at a default 700kHz.
The buck regulator is equipped with an internal current sensing
circuit and the peak current limit threshold is typically set at
0.4A.
Power-On Reset
The ISL85412 automatically initializes upon receipt of the input
power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold, the IC is held in shutdown
and consumes typically 1.8µA from the VIN supply. If EN exceeds
its logic rising threshold, the regulator will enable the bias LDO
and begin to monitor the VCC pin voltage. When the VCC pin
voltage clears its rising POR threshold, the controller will initialize
the switching regulator circuits. If VCC never clears the rising POR
threshold, the controller will not allow the switching regulator to
operate. If VCC falls below its falling POR threshold while the
switching regulator is operating, the switching regulator will be
shut down until VCC returns.
Soft-Start
To avoid large inrush current, VOUT is slowly increased at start-up
to its final regulated value in 2.3ms.
A PWM cycle begins when a clock pulse sets the PWM latch and
the upper FET is turned on. Current begins to ramp up in the upper
FET and inductor. This current is sensed (VCSA), converted to a
voltage and summed with the slope compensation signal. This
combined signal is compared to VCOMP and when the signal is
equal to VCOMP, the latch is reset. Upon latch reset the upper FET is
turned off and the lower FET turned on allowing current to ramp
down in the inductor. The lower FET will remain on until the clock
initiates another PWM cycle. Figure 49 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the current sense and slope compensation signal.
Output voltage is regulated as the error amplifier varies its output
and thus output inductor current. The error amplifier is a
transconductance type and its output is terminated with a series
RC (150k/54pF) network to GND. The transconductance of the
error amplifier is 50µs. Its noninverting input is internally
connected to a 600mV reference voltage and its inverting input is
connected to the output voltage via the FB pin and its associated
divider network.
VCOMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 49. PWM OPERATION WAVEFORMS
Power-Good
Light Load Operation
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the
FB pin. PG is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
completes, PG becomes high impedance provided the FB pin is
within the range specified in the “Electrical Specifications” on
page 5. Should FB exit the specified window, PG will be pulled
low until FB returns. Over-temperature faults also force PG low
until the fault condition is cleared by an attempt to soft-start.
There is an internal 5MΩ internal pull-up resistor.
At light loads, converter efficiency may be improved by enabling
variable frequency operation (PFM). Connecting the MODE pin to
GND will allow the controller to choose such operation
automatically when the load current is low. Figure 50 shows the
PFM operation. The IC enters the PFM mode of operation when 8
consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak
inductor ripple current and set by Equation 1:
PWM Control Scheme
The ISL85412 employs peak current-mode pulse-width
modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block
Diagram” on page 4. The current loop consists of the current
sensing circuit, slope compensation ramp, PWM comparator,
oscillator and latch. Current sense transresistance is typically
930mV/A and slope compensation rate, Se, is typically 450mV/T
where T is the switching cycle period. The control reference for
the current loop comes from the error amplifier’s output.
FN8378 Rev 1.00
March 13, 2015
V OUT 1 – D
I OUT = ----------------------------------2Lf SW
(EQ. 1)
where D = duty cycle, fSW = switching frequency, L = inductor
value, IOUT = output loading current, VOUT = output voltage.
While operating in PFM mode, the regulator controls the output
voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV
reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The
current pulses are approximately 200mA and are issued at a
frequency equal to the converter’s PWM operating frequency.
Page 15 of 19
ISL85412
PWM
PFM
PULSE SKIP
PFM
PWM
CLOCK
8 CYCLES
IL
LOAD CURRENT
0
VOUT
FIGURE 50. PFM MODE OPERATION WAVEFORMS
Due to the pulsed current nature of PFM mode, the converter can
supply limited current to the load. Should load current rise
beyond the limit, VOUT will begin to decline. A second comparator
signals an FB voltage 1% lower than the 600mV reference and
forces the converter to return to PWM operation.
Output Voltage Selection
The regulator output voltage is easily programmed using an
external resistor divider to scale VOUT relative to the internal
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 51.
The output voltage programming resistor, R2, depends on the
value chosen for the feedback resistor, R1 and the desired output
voltage, VOUT, of the regulator. Equation 2 describes the
relationship between VOUT and resistor values.
R 1 x0.6V
R 2 = ---------------------------------V OUT – 0.6V
(EQ. 2)
If the desired output voltage is 0.6V, then R2 is left unpopulated
and R1 is 0Ω.
VOUT
FB
+
-
EA
R1
R2
0.6V
REFERENCE
FIGURE 51. EXTERNAL RESISTOR DIVIDER
Protection Features
The ISL85412 is protected from overcurrent, negative
overcurrent and over-temperature. The protection circuits
operate automatically.
Overcurrent Protection
During PWM on-time, current through the upper FET is monitored
and compared to a nominal 0.4A peak overcurrent limit. In the
FN8378 Rev 1.00
March 13, 2015
event that current reaches the limit, the upper FET will be turned
off until the next switching cycle. In this way, FET peak current is
always well limited.
If the overcurrent condition persists for 17 sequential clock
cycles, the regulator will begin its hiccup sequence. In this case,
both FETs will be turned off and PG will be pulled low. This
condition will be maintained for 8 soft-start periods after which
the regulator will attempt a normal soft-start.
Should the output fault persist, the regulator will repeat the
hiccup sequence indefinitely. There is no danger even if the
output is shorted during soft-start.
If VOUT is shorted very quickly, FB may collapse below 5/8ths of
its target value before 17 cycles of overcurrent are detected. The
ISL85412 recognizes this condition and will begin to lower its
switching frequency proportional to the FB pin voltage. This
insures that under no circumstance (even with VOUT near 0V) will
the inductor current run away.
Negative Current Limit
Should an external source somehow drive current into VOUT, the
controller will attempt to regulate VOUT by reversing its inductor
current to absorb the externally sourced current. In the event that
the external source is low impedance, current may be reversed to
unacceptable levels and the controller will initiate its negative
current limit protection. Similar to normal overcurrent, the
negative current protection is realized by monitoring the current
through the lower FET. When the valley point of the inductor
current reaches negative current limit, the lower FET is turned off
and the upper FET is forced on until current reaches the positive
current limit or an internal clock signal is issued. At this point, the
lower FET is allowed to operate. Should the current again be pulled
to the negative limit on the next cycle, the upper FET will again be
forced on and current will be forced to 1/6th of the positive current
limit. At this point the controller will turn off both FETs and wait for
error amplifier’s output to indicate return to normal operation.
During this time, the controller will apply a 100Ω load from PHASE
to PGND and attempt to discharge the output. Negative current
limit is a pulse-by-pulse style operation and recovery is automatic.
Negative current limit protection is disabled in PFM operating
mode because reverse current is not allowed to build due to the
diode emulation behavior of the lower FET.
Page 16 of 19
ISL85412
Over-Temperature Protection
Over-temperature protection limits maximum junction
temperature in the ISL85412. When junction temperature (TJ)
exceeds +150°C, both FETs are turned off and the controller
waits for temperature to decrease by approximately 20°C.
During this time PG is pulled low. When temperature is within an
acceptable range, the controller will initiate a normal soft-start
sequence. For continuous operation, the +125°C junction
temperature rating should not be exceeded.
Boot Undervoltage Protection
If the Boot capacitor voltage falls below 1.8V, the Boot
undervoltage protection circuit will turn on the lower FET for
400ns to recharge the capacitor. This operation may arise during
long periods of no switching such as PFM no load situations. In
PWM operation near dropout (VIN near VOUT), the regulator may
hold the upper FET on for multiple clock cycles. To prevent the
boot capacitor from discharging, the lower FET is forced on for
approximately 200ns every 34 clock cycles.
Application Guidelines
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these
considerations may mean an effective capacitance 50% lower
than nominal and this value should be used in all design
calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
I
V OUTripple = ------------------------------------8 f SW C OUT
(EQ. 4)
Where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 5)
Simplifying the Design
Layout Considerations
Table 1 on page 3 provides component value selections for a
variety of output voltages and will allow the designer to
implement solutions with a minimum of effort.
Proper layout of the power converter will minimize EMI and noise
and insure first pass success of the design. PCB layouts are
provided in multiple formats on the Intersil web site. In addition,
Figure 52 will make clear the important points in PCB layout. In
reality, PCB layout of the ISL85412 is quite simple.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 3:
V IN – V OUT V OUT
L = -------------------------------- ---------------V IN
F S I
(EQ. 3)
Increasing the value of inductance reduces the ripple current and
thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
The inductor current rating should be such that it will not saturate
in overcurrent conditions. For typical ISL85412 applications,
inductor values generally lies in the 10µH to 47µH range. In
general, higher VOUT will mean higher inductance.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors may also be
used.
A multi-layer printed circuit board with GND plane is
recommended. Figure 52 shows the connections of the critical
components in the converter. Note that capacitors CIN and COUT
could each represent multiple physical capacitors. The most
critical connections are to tie the PGND pin to the package GND
pad and then use vias to directly connect the GND pad to the
system GND plane. This connection of the GND pad to system
plane insures a low impedance path for all return current, as well
as an excellent thermal path to dissipate heat. With this
connection made, place the high frequency MLCC input capacitor
near the VIN pin and use vias directly at the capacitor pad to tie
the capacitor to the system GND plane.
The boot capacitor is easily placed on the PCB side opposite the
controller IC and 2 vias directly connect the capacitor to BOOT
and PHASE.
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
Place the feedback divider close to the FB pin and do not route
any feedback components near PHASE or BOOT.
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturers data sheet to
determine the actual in-application capacitance. Most
FN8378 Rev 1.00
March 13, 2015
Page 17 of 19
ISL85412
FIGURE 52. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 13, 2015
FN8378.1
Upgraded the max nom VIN from 36V to 40V and abs max to 43V.
- On page 1 - Changed all "36V" occurrences on to "40V" and also changed "36V" to "40V" in the Typical
Application diagram.
- On page 5 - Changed in the Abs Max Ratings: "42V" to "43V" (twice) and "43V" to "44V" (once) and in the
Recommended Operating Conditions "36V" to "40V".
On pages 5 and 6 - In the EC table, changed "36V" to "40V" all occurrences .
- on page 15 - Changed the occurrence "36V" to "40V" in the "Detailed Description".
April 11, 2014
FN8378.0
Initial Release.
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FN8378 Rev 1.00
March 13, 2015
Page 18 of 19
ISL85412
Package Outline Drawing
L8.3x3H
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 2/08
2.38
1.50 REF
3.00
A
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
6 X 0.50
6
B
1
8 X 0.40
4
2.20
3.00
(4X)
1.64
0.15
5
8
0.10 M C A B
TOP VIEW
8 X 0.25
BOTTOM VIEW
( 2.38 )
SEE DETAIL "X"
0 .80 MAX
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
2 . 80
( 2 .20 )
SIDE VIEW
( 1.64 )
C
0.2 REF
8X 0.60
0 . 00 MIN.
0 . 05 MAX.
( 8X 0.25 )
DETAIL “X”
( 6X 0 . 5 )
NOTES:
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8378 Rev 1.00
March 13, 2015
Page 19 of 19
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