DATASHEET
ISL97682, ISL97683, ISL97684
FN7689
Rev.2.00
Sep 19, 2017
Compact 2-3-4-Ch LED Drivers with Phase Shift Control
The ISL97682, ISL97683, ISL97684 are Intersil’s highly
integrated 2-3-4-channel LED drivers that are suitable for
medium size TFT-LCD backlights. These parts can drive
multiple channels of LEDs from inputs as low as 4V to outputs
of up to 45V. They can also operate from inputs as low as 3V to
outputs of up to 26.5V in bootstrap configuration (see Figure
26 for 3V operation).
Features
The ISL97682, ISL97683, ISL97684 feature optional channels
phase shift control. This feature is used to minimize the input,
output ripple characteristics and load transient, which help
eliminate or reduce the video and audio noise interference
from the backlight driver operation.
• Input Voltage 3.0V (see Figure 26)~24V with Max VOUT of 26.5V
The ISL97682, ISL97683, ISL97684 offer 8-bit PWM dimming
for systems that need frequency tuning flexibility. With the
unique adaptive boost switching architecture, the ISL97682,
ISL97683, ISL97684 also offer Direct PWM dimming with
output, which follows input and achieves linearity as low as
0.009% at 200Hz or 1.35% at 30kHz.
The drivers incorporate dynamic headroom control that monitors
the highest LED forward voltage string and uses its feedback
signal for the minimum output regulation. The ISL97682,
ISL97683, ISL97684 incorporate extensive fault protection
functions including string open and short circuit detections, OVP,
and OTP. The switching frequency can be selected at either
600kHz or 1.0MHz in PFM or PWM mode. These parts are
available in the thin and compact 16 Ld 3mmx3mm TQFN
package and operate in ambient temperature from -40°C to
+85°C.
• ISL97682 - 2 x 100mA Channels
• ISL97683 - 3 x 50mA Channels
• ISL97684 - 4 x 50mA Channels
• Input Voltage 4.0V~26.5V with Max VOUT of 45V
• PWM Dimming Linearity
- PWM Dimming with Adjustable Dimming Frequency with
Duty Cycle Linear from 0.4% to 100% = 9V AND WITH
GOOD LEDS MATCHING
PGND 10
CH1 13
CH2 14
CH3 15
CH4 16
10kΩ
8.2nF
1 AGND
*VIN >=9V AND WITH
GOOD LEDS MATCHING
FIGURE 1A. DIRECT PWM DIMMING
FIGURE 1B. PWM DIMMING WITH DIMMING FREQUENCY
ADJUSTMENT USING RFPWM
FIGURE 1. ISL97684 TYPICAL APPLICATION DIAGRAMS
FN7689 Rev.2.00
Sep 19, 2017
Page 1 of 18
ISL97682, ISL97683, ISL97684
Block Diagram
OUTPUT = 45V, 4 X 50mA*
VIN = 4~26.5V
10µH/1.5A
OPTIONAL FUSE
4.7µF/50V
LX
VIN
EN
ISL97684
INTERNAL
BIAS
REG
VDC
OSC &
RAMP
COMP
Σ
=0
LOGIC
OVP
OVP
O/P SHORT
FET
DRIVER
IMAX ILIMIT
FSW
PGND
PHASE
FSW
SELECT
DETECT
COMP
GM
AMP
8-BIT
DAC
VSET
RSET
+
-
REFOVP
DYNAMIC
HEADROOM
CONTROL
PE
OPEN CKT, SHORT CKT DETECTS
HIGHEST
VF
STRING
DETECT
+
-
CH1
CH4
1
REF
GEN
REFVSC
AGND
TEMP
SENSOR
PHASE SELECT
PWMI
FPWM/
DIRECTPWM
PHASE SHIFT
& PWM
CONTROLLER
8-BIT
DIGITIZER
*VIN >= 9V AND WITH
GOOD LEDS MATCHING
4
+
-
DIRECTPWM
DETECT
FIGURE 2. ISL97684 BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL97682IRTZ
PART MARKING
7682
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
16 LD 3x3 TQFN
PKG.
DWG. #
L16.3x3D
ISL97683IRTZ
7683
-40 to +85
16 LD 3x3 TQFN
L16.3x3D
ISL97684IRTZ
7684
-40 to +85
16 LD 3x3 TQFN
L16.3x3D
ISL97682IRTZEVALZ
Evaluation Board
ISL97683IRTZEVAL
Evaluation Board
ISL97684IRTZEVALZ
Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit or “-TK” suffix for 1k unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the product information page for ISL97682, ISL97683, ISL97684. For more information on MSL, see TB363.
FN7689 Rev.2.00
Sep 19, 2017
Page 2 of 18
ISL97682, ISL97683, ISL97684
Pin Configurations
ISL97683
(16 LD TQFN)
TOP VIEW
NC
CH2
NC
CH1
NC
CH3
CH2
CH1
ISL97682
(16 LD TQFN)
TOP VIEW
16
15
14
13
16
15
14
13
AGND 1
12 OVP
AGND 1
12 OVP
COMP 2
11 VDC
COMP 2
11 VDC
8
EN
VIN
FPWM_DIRECTPWM
9
FSW
9
LX
4
5
6
7
8
FPWM_DIRECTPWM
7
10 PGND
VIN
6
RSET 3
EN
5
PWMI
FSW 4
10 PGND
PWMI
RSET 3
LX
CH4
CH3
CH2
CH1
ISL97684
(16 LD TQFN)
TOP VIEW
16
15
14
13
AGND 1
12 OVP
COMP 2
11 VDC
10 PGND
RSET 3
FSW 4
FN7689 Rev.2.00
Sep 19, 2017
5
6
7
8
PWMI
EN
VIN
FPWM_DIRECTPWM
9
LX
Page 3 of 18
ISL97682, ISL97683, ISL97684
Pin Descriptions
PIN
ISL97682
ISL97683
ISL97684
1
AGND
AGND
AGND
Analog Ground for precision circuits
2
COMP
COMP
COMP
External Compensation Pin
3
RSET
RSET
RSET
Resistor connection for setting LED current, (see Equation 2 for calculating the ILEDpeak)
4
FSW
FSW
FSW
FSW = 0 ~ 0.11 * VDC, Boost Switching Frequency = 600kHz with phase shift and PFM mode enabled.
FSW = 0.34 * VDC ~ 0.44 * VDC, Boost Switching Frequency = 600kHz with phase shift and PWM mode
enabled.
FSW = 0.53 * VDC ~ 0.63 * VDC, Boost Switching Frequency = 1MHz with phase shift and PWM mode
enabled.
FSW = 0.86 * VDC ~ VDC, Boost Switching Frequency = 1MHz with phase shift and PFM mode enabled.
5
PWMI
PWMI
PWMI
6
EN
EN
EN
Enable, can be tied directly to VIN if the system lacks of I/O
7
VIN
VIN
VIN
LED and Driver Supply Voltage. LED supply and Driver supply can be separated if high voltage application
is needed and dual supplies are available
8
DESCRIPTION
PWM brightness control pin.
FPWM/
FPWM/
FPWM/
External PWM dimming with frequency modulation or Direct PWM dimming without frequency
DirectPWM DirectPWM DirectPWM modulation.
With a resistor connected to ground, the dimming frequency will be set by the Setting Resistor.
When this pin is floating, the part enters Direct PWM mode such that the dimming follows the input PWM
signal without frequency modulation.
9
LX
LX
LX
10
PGND
PGND
PGND
11
VDC
VDC
VDC
Input to boost switch
Power ground (LX, CIN, and COUT Power return)
De-couple capacitor for internally generated 5V supply
12
OVP
OVP
OVP
Overvoltage protection input
13
CH1
CH1
CH1
Input 1 to current source, CH, and monitoring
14
NC
CH2
CH2
Input 2 to current source, CH, and monitoring (ISL97682 is No Connect)
15
CH2
CH3
CH3
Input 3 to current source, CH, and monitoring
16
NC
NC
CH4
Input 4 to current source, CH, and monitoring (ISL97682, ISL97683 are No Connect)
FN7689 Rev.2.00
Sep 19, 2017
Page 4 of 18
ISL97682, ISL97683, ISL97684
Absolute Maximum Ratings
Thermal Information
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
VDC, PWMI, FPWM/DirectPWM, FSW, RSET, COMP, OVP . . . -0.3V to 5.5V
CH1 to CH4, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 LD TQFN (Notes 4, 5) . . . . . . . . . . . . . . .
51
4.6
Thermal Characterization (Typical)
PSIJT (°C/W)
Operating Conditions
0.11
16 Ld TQFN (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings.
Electrical Specifications
5.
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 20k,
unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
GENERAL
VIN
Backlight Supply Voltage, (Note 8)
TA = +25°C
IVIN
VIN Active Current
EN = 3.3V
4.0
26.5
V
IVIN_STBY
VIN Shutdown Current
EN = 0V, TA = 25°C
5
µA
VOUT
Output Voltage
4.0V < VIN 26.5V
45
V
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
5
2.2
mA
2.5
V
100
mV
LINEAR REGULATOR
VDC
LDO Output Voltage
VIN > 6V
VIN = 5V, IVDC = 20mA
VLDO
VDC LDO Dropout Voltage
ENLow
Guaranteed Range for EN Input Low Voltage
ENHi
Guaranteed Range for EN Input High Voltage
tEN(Low)
EN low time before shut-down
4.6
4.8
5
V
30
200
mV
0.5
V
1.5
V
29.5
ms
7
ms
BOOST SWITCHING REGULATOR
SS
Soft-start
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-Resistance
Eff_peak
Peak Efficiency
DMAX
DMIN
FN7689 Rev.2.00
Sep 19, 2017
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
100% LED Duty Cycle
1.4
1.8
2.3
A
500
m
VIN = 24V, 48 LEDs, 30mA
each, L = 10µH with DCR
100mTA = +25°C
90.1
%
VIN = 12V, 48 LEDs, 30mA
each, L = 10µH with
DCR 100mTA = +25°C
87
%
VFSW < 2.4V (FSW = 600kHz)
92
%
VFSW > 2.4V
(FSW =1.0MHz)
85
%
VFSW < 2.4V (FSW = 600kHz)
8
%
VFSW > 2.4V
(FSW = 1.0MHz)
15
%
Page 5 of 18
ISL97682, ISL97683, ISL97684
Electrical Specifications
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 20k,
unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
FSW
Boost Switching Frequency
FSW < 2.4V
500
600
650
kHz
FSW > 2.4V
0.9
1.0
1.1
MHz
ILX_leakage
LX Leakage Current
LX = 45V, EN = 0
10
µA
Channel-to-Channel DC Current Matching
RSET = 20k(ILED = 20mA for
ISL97683/4 and 40mA for
ISL97682)
-2
+2
%
RSET = 40k(ILED = 10mA for
ISL97683/4 and 20mA for
ISL97682)
-2.5
+2.5
%
-2
+2
%
REFERENCE
IMATCH
IACC
Current Accuracy
ILED = 20mA (ISL97683/4)
ILED = 40mA (ISL97682)
FAULT DETECTION
VSC
Channel Short Circuit Threshold
Vtemp
Over-Temperature Threshold
Vtemp_acc
Over-Temperature Threshold Accuracy
VOVPlo
Overvoltage Limit on OVP Pin
OVPfault
OVP Short Detection Fault Level
3.8
1.18
4.4
4.9
V
150
°C
5
°C
1.22
1.24
V
70
mV
500
(Note 9)
mV
90
mV
CURRENT SOURCES
VHEADROOM
VHEADROOM_RANGE
Dominant Channel Current Source Headroom
at CHx Pin
ILED = 20mA
Dominant Channel Current Sink Headroom
Range at CHx Pin
ILED = 20mA, TA = +25°C
VRSET
Voltage at RSET Pin
ILED(max)
Maximum LED Current per Channel
1.2
1.22
1.24
V
ISL97682
100
mA
ISL97683
50
mA
ISL97684
50
mA
PWM GENERATOR
VIL
Guaranteed Range for PWM Input Low Voltage
VIH
Guaranteed Range for PWM Input High Voltage
1.5
0.8
V
FPWMI
PWMI Input Frequency Range
100
DPWMACC
Direct PWM Dimming Output Maximum
Resolution
tDPWM_ON_MIN
Direct PWM Dimming Minimum On-Time
PWMACC
PWM Dimming with Adjustable Dimming
Frequency Output Resolution
PWMHYST
PWMI Input Allowable Jitter Hysteresis
-0.46
+0.46
LSB
FPWM
Generated PWM Dimming Frequency Range
100
30,000
Hz
VFPWM
Voltage at FPWM pin
1.24
V
V
30,000
Hz
85
Direct PWM Mode
250
ns
450
ns
8
RFPWM = 3.3k
1.20
1.22
bit
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN.
9. Varies within range specified by VHEADROOM_RANGE.
FN7689 Rev.2.00
Sep 19, 2017
Page 6 of 18
ISL97682, ISL97683, ISL97684
Typical Performance Curves
90
85
80
80
EFFICIENCY (%)
EFFICIENCY (%)
70
60
50
40
4.2VIN
30
3.7VIN
20
3VIN
0
20
70
40
60
80
60
50
100
3VIN
0
20
40
DC (%)
80
100
FIGURE 4. ISL97683 TYPICAL EFFICIENCY FOR 3V TO 4.2V IN A
3P7S, ILED = 20mA/CH CONFIGURATION AT
FSW = 600kHz IN PWM MODE WITH VIN SUPPLY = 5V
90
95
90
80
EFFICIENCY (%)
EFFICIENCY ( %)
60
DC (%)
FIGURE 3. ISL97683 TYPICAL EFFICIENCY FOR 3V TO 4.2V IN A
3P7S, ILED = 20mA/CH SINGLE SUPPLY
CONFIGURATION AT FSW = 600kHz IN PWM MODE
70
5V
60
50
4.2VIN
3.7VIN
65
55
10
0
75
85
80
600k PWM
75
0
50
DC (%)
100
70
0
5
10
15
20
25
30
DC (%)
FIGURE 5. ISL97683 TYPICAL EFFICIENCY FOR 5VIN IN A 3P7S,
ILED = 20mA/CH CONFIGURATION AT FSW = 600kHz
IN PWM MODE
93
FIGURE 6. ISL97684 EFFICIENCY FOR 4P10S AT 20mA/CH AT
600kHz IN PWM MODE
87
EFFICIENCY (%)
88
86
83
78
85
1000k PFM VIN = 15V
73
68
58
84
1000k PWM VIN = 15V
63
0
10
20
30
40
50
1000k PWM 50%
1000k PFM 50%
60
70
80
90
100
83
0
10
20
30
DC (%)
FIGURE 7. ISL97864 PWM vs PFM EFFICIENCY vs DC AT
VIN = 15V IN4P8S CONFIGURATION
FN7689 Rev.2.00
Sep 19, 2017
FIGURE 8. PFM vs PFM MODE FOR 4P8S vs VIN AT 1MHz
Page 7 of 18
ISL97682, ISL97683, ISL97684
Typical Performance Curves
(Continued)
4.5
CHANNEL CURRENT (mA)
4.0
CURRENT (mA)
3.5
3.0
2.5
2.0
1.5
CALCULATED
1.0
MEASURED
0.5
0
0
0.8
1.6
2.4
DC (%)
3.2
4.0
4.8
CH2
CH4
CH1
0
20
40
60
80
100
FIGURE 10. CURRENT LINEARITY vs PWM DIMMING DUTY CYCLE
AT 12VIN FOR 4P10S AT 20mA/CH
1.0
4
0.8
VHEADROOM (V)
5
3
2
1
0
CH3
DIMMING DUTY CYCLE (%)
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE AT 12VIN FOR 4P10S AT 20mA/CH
IIN (mA)
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0.6
CH4
0.4
CH2 CH1 CH3
0.2
0
5
10
15
20
25
30
0
0
FIGURE 11. QUIESCENT CURRENT vs VIN WITH EN = HIGH, NO
LEDS CONNECTED
10
20
30
VIN (V)
VIN (V)
FIGURE 12. CHANNEL VOLTAGE vs VIN FOR VIN = 12V AT 4P10S AT
20mA/CH
VIN (5V/DIV)
VIN (5V/DIV)
IIN (0.5A/DIV)
IIN (0.5A/DIV)
ILED (20mA/DIV)
FIGURE 13. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V
FOR 4P10S AT 20mA/C
FN7689 Rev.2.00
Sep 19, 2017
ILED (20mA/DIV)
FIGURE 14. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 4P10S AT 20mA/CH
Page 8 of 18
ISL97682, ISL97683, ISL97684
Typical Performance Curves
(Continued)
VOUT
(50mV/DIV)
Vout(50mV/Div)
VO (1V/DIV)
LXLx=20V/div
= 20V/DIV)
ILED (20mA/DIV)
FIGURE 15. LOAD REGULATION WITH ILED CHANGE FDROM 100%
TO 0% PWM DIMMING, VIN = 12V AT 20mA/CH
VVout
OUT
FIGURE 16. VOUT RIPPLE VOLTAGE, VIN = 12V, 4P10S AT 20mA/CH
VOUT
Vout
IIN
(0.5A/DIV)
Iin(0.5A/div)
IIN
(0.5A/DIV)
Iin(0.5A/div)
ILED
(20mA/DIV)
ILED(20mA/div)
EN
EN
ILED(20mA/div)
ILED (20mA/DIV)
FIGURE 17. IN-RUSH AND LED CURRENT AT VIN = 5V FOR 4P10S
AT 20mA/CH
FN7689 Rev.2.00
Sep 19, 2017
EN
EN
FIGURE 18. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 4P10S
AT 20mA/CH
Page 9 of 18
ISL97682, ISL97683, ISL97684
Theory of Operation
Current Matching and Current Accuracy
PWM Boost Converter
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 19.
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97682,
ISL97683, and ISL97684 employ current mode control boost
architecture that has a fast current sense loop and a slow voltage
feedback loop. Such architecture achieves a fast transient
response that is essential for the notebook backlight application
where the power can be a series of drained batteries or instantly
change to an AC/DC adapter without rendering a noticeable
visual nuisance. The number of LEDs that can be driven by the
ISL97682, ISL97683, ISL97684 depends on the type of LED
chosen in the application. The ISL97682, ISL97683, ISL97684
are capable of boosting up to 45V and typically driving 13 LEDs
in series for each of the 4 channels, enabling a total of 52 pieces
of the 3.2V/20mA type of LEDs.
The LED peak current is set by translating the RSET current to the
output with a scaling factor of 401.8/RSET. The source terminals
of the current source MOSFETs are designed to operate within a
range at about 500mV to optimize power loss versus accuracy
requirements. The sources of errors of the channel-to-channel
current matching come from the op amps offset, internal layout,
reference, and current source resistors. These parameters are
optimized for current matching and absolute current accuracy.
However, the absolute accuracy is additionally determined by the
external RSET. A 1% tolerance resistor is recommended.
OVP
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
The ISL97682, ISL97683, ISL97684 OVP threshold is set by
RUPPER and RLOWER shown by Equation 1:
VOUT_OVP = 1.22V * (RUPPER + RLOWER)/RLOWER
+
-
REF
+
-
RSET
(EQ. 1)
VOUT can only regulate between 42% and 100% of the VOUT_OVP
such that:
PWM DIMMING
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Allowable VOUT = 42% to 100% of VOUT_OVP
Dynamic Headroom Control
For example, if 10 LEDs are used with the worst case being VOUT
of 35V. If R1 and R2 are chosen such that the OVP level is set at
40V, then the VOUT is allowed to operate between 16.8V and 40V.
If the requirement is changed to 4 LEDs of 14V VOUT application,
then the OVP level must be reduced and users should follow the
VOUT = (42% ~100%) OVP level requirement. Otherwise, the
headroom control will be disturbed such that the channel voltage
can be much higher than expected and sometimes can prevent
the driver from operating properly.
The ISL97682, ISL97683, ISL97684 feature a proprietary
Dynamic Headroom Control circuit that detects the highest
forward voltage string or the lowest voltage from any of the CH
pins digitally. When the lowest CH voltage is lower than the short
circuit threshold (VSC), such voltage will be used as the feedback
signal for the boost regulator. The boost makes the output to the
correct level such that the lowest CH is at the target headroom
voltage. Since all LED stacks are connected to the same output
voltage, the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel will ensure that
each channel has the same current. The output voltage will
regulate cycle-by-cycle and it is always referenced to the highest
forward voltage string in the architecture.
The ratio of the OVP capacitor should be the inverse of the OVP
resistor. For example:
if RUPPER/RLOWER = 33/1, then CUPPER/CLOWER = 1/33 with
CUPPER = 100pF and CUPPER = 3.3nF.
Enable
An EN signal is required to enable the internal regulator for normal
operation. If there is no signal for longer than 28ms, the device will
enter shutdown.
Power Sequence
There is no specific power sequence requirement for the
ISL97682, ISL97683, ISL97684. The EN signal can be tied to VIN
but not the VDC that will prevent the device from powering up.
FN7689 Rev.2.00
Sep 19, 2017
Dimming Controls
The ISL97682, ISL97683, ISL97684 allow two ways of controlling
the LED current, and therefore, the brightness. They are:
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current control,
which will be described in the following.
Page 10 of 18
ISL97682, ISL97683, ISL97684
Maximum DC Current Setting
The initial brightness should be set by choosing an appropriate
value for RSET. This should be chosen to fix the maximum
possible LED current as shown in Equation 2 for ISL97682 and
Equation 3 for ISL97683 and ISL97684:
ILED1-20mA
ILED2-20mA
ILED3-20mA
804
I LEDmax = --------------R SET
(EQ. 2)
ILED4-20mA
ILED_Total_20mA
402
I LEDmax = --------------R SET
(EQ. 3)
DC Current Adjustment
5
10
TIME (ms)
FIGURE 21. PHASE SHIFT 4-Ch LED DRIVER WITH 10% PWM
DIMMING CHANNEL CURRENT (UPPER) AND TOTAL
CURRENT (LOWER)
Once RSET is fixed, the LED DC current can be adjusted.
For example, in the 4-channel ISL97684, if the maximum required
LED current (ILED(max)) is 20mA, rearranging Equation 3 yields
Equation 4:
R SET = 402 0.02 = 20.1k
(EQ. 4)
ILED4-20mA
ILED3-20mA
PWM Control
The ISL97682, ISL97683, ISL97684 have high speed 8-bit
digitizers that decode the incoming PWM signal and convert it into
2- 3- or 4- channels of 8-bit PWM current with a phase shift
function that will be described later. During the PWM On period,
the LED peak current is defined by the RSET resistor value. The
average LED current of each channel is controlled by ILEDmax and
the PWM duty cycle in percent shown by Equation 5:
I LED ave = I LEDmax PWM
ILED2-20mA
ILED1-20mA
ILED_Total_80mA
5
(EQ. 5)
When the PWM input = 0, all channels are disconnected and the
ILED is guaranteed to be 4.4V
CH1 faults out after 6 PWM cycle
(7-18 in direct PWM) time-out
CH2 through CH4 Normal
Highest VF of CH2
through CH4
4
CH1 Open Circuit
with infinite
resistance
OTP not triggered and
CH1 < 4.4V
VOUT will ramp to OVP. CH1 will
CH2 through CH4 Normal
time-out after 6 PWM cycles (7-18
in direct PWM) and switch off. VOUT
will drop to normal level.
Highest VF of CH2
through CH4
5
CH1 LED Open
Circuit but has
paralleled Zener
OTP not triggered and
CH1 < 4.4V
CH1 remains ON and has highest
VF, thus VOUT increases
CH2 through CH4 ON, Q2 through VF of CH1
Q4 burn power
6
CH1 LED Open
Circuit but has
paralleled Zener
OTP triggered but CH1 <
4.4V
CH1 goes off
Same as CH1
7
CH1 LED Open
Circuit but has
paralleled Zener
OTP not triggered but
CHx > 4.4V
CH1 remains ON and has highest
VF, thus VOUT increases.
VF of CH1
VOUT increases then CH-X
switches OFF after 6 PWM cycles.
This is an unwanted shut off and
can be prevented by setting OVP
at an appropriate level.
8
Channel-to-Channel
VF too high
OTP triggered but CHx <
4.4V
All channels switched off until chip cooled
9
Output LED stack
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that has insufficient headroom Highest VF of CH1
will fault out after 6 PWM cycle (7-18 in direct PWM) time-out.
through CH4
FN7689 Rev.2.00
Sep 19, 2017
CH2 through CH4 Normal
VOUT REGULATED
BY
Highest VF of CH2
through CH4
VF of CH1
Highest VF of CH1
through CH4
Page 14 of 18
ISL97682, ISL97683, ISL97684
Components Selections
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator
On-time is equal to the change of inductor current during the
switching regulator Off-time. Since the voltage across an inductor
is as shown in Equation 10:
V L = L I L t
(EQ. 14)
(EQ. 10)
(EQ. 11)
Applications
where D is the switching duty cycle defined by the turn-on time
over the switching periods. VD is a Schottky diode forward
voltage that can be neglected for approximation.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle as Equations 12 and 13:
VO VI = 1 1 – D
(EQ. 12)
D = VO – VI VO
(EQ. 13)
Input Capacitor
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. This reduces interaction between the regulator and input
supply, thereby improving system stability. The high switching
frequency of the loop causes almost all ripple current to flow in
the input capacitor, which must be rated accordingly.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and improve system efficiency, such
as X5R or X7R ceramic capacitors, which offer small size and a
lower value of temperature and voltage coefficient compared to
other ceramic capacitors.
It is recommended that an input capacitor of at least 10µF be
used. Ensure the voltage rating of the input capacitor is suitable
to handle the full supply range.
Inductor
The selection of the inductor should be based on its maximum
and saturation current (ISAT) characteristics, power dissipation
(DCR), EMI susceptibility (shielded vs unshielded), and size.
Inductor type and value influence many key parameters,
including ripple current, current limit, efficiency, transient
performance and stability.
The inductor’s maximum current capability must be adequate
enough to handle the peak current at the worst case condition.
Additionally if an inductor core is chosen with too low a current
rating, saturation in the core will cause the effective inductor
value to fall, leading to an increase in peak to average current
level, poor efficiency and overheating in the core. The series
resistance, DCR, within the inductor causes conduction loss and
heat dissipation. A shielded inductor is usually more suitable for
EMI susceptible applications, such as LED backlighting.
FN7689 Rev.2.00
Sep 19, 2017
IL peak = V O I O 85% V I + 1 2 V I V O – V I L V O f SW
The choice of 85% is just an average term for the efficiency
approximation. The first term is the average current, which is
inversely proportional to the input voltage. The second term is
the inductor current change, which is inversely proportional to L
and FSW as a result, for a given switching.
and IL @ On = IL @ Off, therefore:
V I – 0 L D tS = VO – V D – VI L 1 – D tS
The peak current can be derived from the voltage across the
inductor during the Off-period, expressed in Equation 14:
Low Voltage Operations
The ISL97682, ISL97683, ISL97684 VIN pin can be separately
biased from the LEDs power input to allow low voltage operation.
For systems that have only single supply, VOUT can be tied to the
driver VIN pin to allow initial start-up; see Figure 26. The circuit
works as follows; when the input voltage is available and the
device is not enabled, the VOUT follows VIN with a Schottky diode
voltage drop. The VOUT bootstrapped to VIN pin allows an initial
start-up once the part is enabled. Once the driver starts up with
VOUT regulating to the target, the VIN pin voltage also increases.
As long as the VOUT does not exceed 26.5V and the extra power
loss on VIN is acceptable, this configuration can be used for input
voltage as low as 3.0V. For systems where a single input supply
of 4V to 5.5V is available, the VIN pin can be shorted to VDC,
allowing a slight gain in efficiency due to bypassing the internal
LDO.
For systems that have dual supplies, the VIN pin can be biased
from 5V to 12V. The input voltage can be as low as 2.7V without
the limitations previously mentioned; see Figure 27.
VOUT < 26.5V
VIN = 3V ~ 24V
ISL97684
LX
VIN
VDC
OVP
PGND
EN
CH1
PWMI CH2
FSW CH3
RSET CH4
20mA
AGND
COMP
FIGURE 26. SINGLE SUPPLY 3V OPERATION
Page 15 of 18
ISL97682, ISL97683, ISL97684
VOUT < 26.5V
2.7 TO 24 VIN
5V TO 12V BIAS
ISL97684
LX
VIN
VDC
EN
PWMI
FSW
RSET
COMP
OVP
PGND
CH1
CH2
CH3
CH4
20mA
AGND
FIGURE 27. DUAL SUPPLIES 2.7V OPERATION
FN7689 Rev.2.00
Sep 19, 2017
Page 16 of 18
ISL97682, ISL97683, ISL97684
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not
warranted. Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
September 19, 2017
FN7689.2
Applied new header/footer.
Added Related Literature
Updated Ordering Information table.
Added VHEADROOM_RANGE spec to EC table.
Added Note 9.
In “Current Matching and Current Accuracy” on page 10 updated 2nd sentence in paragraph 2 for clarification.
Replaced Products section with About Intersil.
February 3, 2012
FN7689.1
On page 1, RC values on COMP pin in Figure 1A and 1B were both updated with values of 10kΩ, 8.2nF, and 33pF.
On page 4, the pin description for Pin#4 was updated with new numbers to set boost switching frequency and
PFM mode.
In Table 2 on page 12, the FSW pin setting was updated with new numbers to set boost switching frequency and
PFM mode.
March 11, 2011
FN7689.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2011-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7689 Rev.2.00
Sep 19, 2017
Page 17 of 18
ISL97682, ISL97683, ISL97684
Package Outline Drawing
For the most recent package outline drawing, see L16.3x3D.
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
8
0.10 M C A B
5
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
0.75 ±0.05
C
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
FN7689 Rev.2.00
Sep 19, 2017
Page 18 of 18
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