DATASHEET
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Description
Features
The MK1574 is a Phase-Locked Loop (PLL) based clock
synthesizer, which accepts an 8 kHz clock input as a
reference, and generates many popular communications
frequencies. All outputs are frequency locked together and
to the input. This allows for the generation of locked clocks
to the 8 kHz backplane clock, simplifying clock generation
and distribution in communications systems.
•
•
•
•
•
3.3 volt operation
Packaged in 16-pin SOIC
Accepts 8 kHz input clock
Output clock rates include T1, E1, T2, E2
Available in commercial (0º to + 70ºC) or industrial (-40 to
+85ºC) temperature ranges
• Available in Pb (lead) free package
• For jitter attenuation, use the MK2049
• For 5.0 V operation, use the MK1574-01A
ICS manufactures the largest variety of clock generators
and buffers, and can customize this device for a variety of
frequencies.
Block Diagram
VDD
GND
2
2
CLK1
FS0-3
8 kHz
input
clock
4
CLK2
PLL Clock
Synthesis
and Control
Circuitry
Input
Buffer
CAP1
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLK3
8 kHz
(recovered)
CAP2
1
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Pin Assignment
ICLK
1
16
FS3
VDD
2
15
NC
VDD
3
14
FS2
CAP1
4
13
FS1
GND
5
12
CLK3
CAP2
6
11
CLK2
GND
7
10
CLK1
FS0
8
9
8KOUT
Output Clocks Decoding Table
Decode
Address
ICLK
Multiplier
CLK1
CLK2
CLK3
FS3:0
(Hex)
pin1
On-chip
pin 10
pin 11
pin 12
0000
0
Reserved
Reserved
Reserved
Reserved
Reserved
0001
1
Reserved
Reserved
Reserved
Reserved
Reserved
0010
2
Reserved
Reserved
Reserved
Reserved
Reserved
0011
3
Reserved
Reserved
Reserved
Reserved
Reserved
0100
4
8.00 kHz
2940
23.52
11.76
5.88
0101
5
8.00 kHz
1960
15.68
7.84
3.92
0110
6
8.00 kHz
2760
22.08
11.04
5.52
0111
7
8.00 kHz
2640
21.12
10.56
5.28
1000
8
8.00 kHz
1920
15.36
7.68
3.84
1001
9
8.00 kHz
6480
51.84
25.92
12.96
1010
A
8.00 kHz
2112
16.896
8.448
4.224
1011
B
8.00 kHz
1578
12.624
6.312
3.156
1100
C
8.00 kHz
8192
65.536
32.768
16.384
1101
D
8.00 kHz
6176
49.408
24.704
12.352
1110
E
8.00 kHz
1024
8.192
4.096
2.048
1111
F
8.00 kHz
772
60176
3.088
1.544
0 = connect directly to ground, 1 = connect directly to VDD.
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
2
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock input. Connect to an 8 kHz clock input.
2
VDD
Power
Connect to 3.3 V.
3
VDD
Power
Connect to 3.3 V.
4
CAP1
Input
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
5
GND
Power
Connect to ground.
6
CAP2
Power
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
7
GND
Power
Connect to ground.
8
FS0
Input
Frequency select 0. Determines CLK outputs per table above.
9
8KOUT
10
CLK1
Output Clock 1 determined by status of FS3:0 per table above.
11
CLK2
Output Clock 2 determined by status of FS3:0 per table above.
12
CLK3
Output Clock 3 determined by status of FS3:0 per table above.
13
FS1
Input
Frequency select 1. Determines CLK outputs per table above.
14
FS2
Input
Frequency select 2. Determines CLK outputs per table above.
15
NC
—
16
FS3
Input
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
input.
No connect. Do not connect anything to this pin.
Frequency select 3. Determines CLK outputs per table above.
External Components
The MK1574 requires a minimum number of external components for proper operation. An RC network (see the
section “Loop Bandwidth and Loop Filter Component Selection”) should be connected between CAP1 and CAP2 as
close tot he device as possible. Decoupling capacitors of 0.01µF should be connected between VDD and GND on
pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33Ω may be used close to
each clock output pin to reduce reflections.
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
3
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1574. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD (referenced to GND)
-0.5 V to 7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70°C
Ambient Operating Temperature (industrial)
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Units
0
+70
°C
-40
+85
°C
+3.13
+5.5
V
DC Electrical Characteristics
VDD = 3.3 V, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
3.6
V
Operating Voltage
VDD
3.0
Input High Voltage
VIH
2
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -25 mA
2.4
V
Output Low Voltage
VOL
IOL = 25 mA
Operating Supply
Current
IDD
No Load
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
V
0.8
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
0.4
4
V
V
13
mA
±100
mA
7
pF
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
AC Electrical Characteristics
VDD = 3.3 V, Ambient Temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency
fIN
8.000
Output Clock Rise Time
tOR
0.8 to 2.0 V
1.5
ns
Output Clock Fall Time
tOF
2.0 to 0.8 V
1.5
ns
Output Clock Duty Cycle,
High time
tDC
At VDD/2
60
%
40
Absolute Clock Period
Jitter
49 to 51
kHz
1
Actual Mean Frequency
Error Versus Target (note
1)
Any clock selection
ns
0
0
ppm
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
Thermal Characteristics
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Min.
Typ.
Max. Units
θJA
Still air
120
°C/W
θJA
1 m/s air flow
115
°C/W
θJA
3 m/s air flow
105
°C/W
58
°C/W
θJC
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
BW (Hz) =
K1
Equation 1
C
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
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MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
R=
ζ * K2
Equation 2; ζ (zeta) is the damping factor
C
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7)
shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using equation 1,
400 =
K1
C
Therefore,
C=
( 0.0516 ) 2
= 16.6 nF (16 nF nearest standard value
400
3. A good value for the damping factor ζ is 0.707. From equation 2,
R=
0.707 * 6.2
16E-9
= 34.7 kΩ (36 kΩ nearest standard value)
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
6
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Loop Filter Constants
This table shows the constants K1 and K2 that are used with the equations on page 6 to calculate the external loop filter
components.
Loop Filter Contstants for MK1574-01
Decode
Address
Loop Filter Constants
FS3:0
(Hex)
K1
K2
0000
0
Reserved
Reserved
0001
1
Reserved
Reserved
0010
2
Reserved
Reserved
0011
3
Reserved
Reserved
0100
4
0.0430
7.4
0101
5
0.0527
6.0
0110
6
0.0444
7.2
0111
7
0.0454
7.0
1000
8
0.0533
6.0
1001
9
0.0410
7.8
1010
A
0.0508
6.3
1011
B
0.0587
5.4
1100
C
0.0365
8.7
1101
D
0.0420
7.6
1110
E
0.0516
6.2
1111
F
0.0594
5.4
PC Board Layout
A proper board layout is critical to the successful use of the MK1574. In particular, the CAP1 and CAP2 pins are
very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be as short as possible and
the capacitor and resistor must be mounted next to the device as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply decoupling capacitor. The high frequency output clocks on may benefit
from a series 33Ω resistor connected close to the pin (not shown).
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
7
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574 ROM, which yield the exact values shown for
the output clocks.
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Symbol
E
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Min
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.3859
.3937
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
C
8
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
MK1574-01S
MK1574-01STR
MK1574-01SLF
MK1574-01SLFTR
MK1574-01SI
MK1574-01SITR
MK1574-01SILF
MK1574-01SILFTR
MK1574-01S
MK1574-01S
MK1574-01SLF
MK1574-01SLF
MK1574-01SI
MK1574-01SI
MK1574-01SILF
MK1574-01SILF
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for
either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are
implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
9
MK1574
REV F 111605
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
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