MK2059-01SITR

DATASHEET MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR Description Features The MK2059-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that produces common telecommunications reference frequencies. The output clock is phase locked to an 8kHz (frame rate) input reference clock. The MK2059-01 also provides jitter attenuation. Included in the selection of output frequencies are these common system clocks: • Generates T1, E1, OC-3 and other common telecom • • • 1.544 MHz (T1) 2.048 (E1) • 19.44 MHz (OC-3) 16.384 MHz (8x E1) • This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet input clock jitter attenuation requirements. A loop bandwidth down to the Hz range is possible • • • • • • clock frequencies from an 8kHz frame clock Configurable jitter attenuation characteristics, excellent for use as a Stratum source de-jitter circuit 2:1 Input MUX for input reference clocks VCXO-based clock generation offers very low jitter and phase noise generation Output clock is phase and frequency locked to the selected input reference clock Fixed input to output phase relationship (except for 1.544 MHz and 2.048 MHz output selections) +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range Low power CMOS technology 20 pin SOIC package Single 3.3V power supply Available in Pb (lead) free package NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram Pullable Crystal X1 ISET 8kHz Ref Input ICLK2 8kHz Ref Input ICLK1 1 0 Phase Detector X2 VDD VDD 3 Output Divider VCXO CLK Charge Pump ISEL Feedback Divider SEL2:0 3 CHGP IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 1 VIN GND 4 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Pin Assignment Output Clock Selection Table X1 1 20 X2 VD D 2 19 GND VD D VD D 3 4 18 17 IS E L IC L K 1 V IN 5 16 IC L K 2 GND GND 6 15 SEL0 7 14 CLK 8 9 13 NC SEL1 GND CHG P IS E T 10 12 11 SEL2 Input SEL2 SEL1 SEL0 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 0 0 0 0 M M M M 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Clock (MHz) 1.544 2.048 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Crystal Used (MHz) 24.704 24.576 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating 20 pin 300 mil SOIC Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 2 3 4 5 X1 VDD VDD VDD VIN Power Power Power Input 6 7 8 9 GND GND GND CHGP Power Power Power Output 10 11 ISET SEL2 Input 12 SEL1 Input 13 14 15 NC CLK SEL0 Input Output Input 16 ICLK2 Input 17 ICLK1 Input 18 ISEL Input 19 20 GND X2 Power - Crystal Input. Connect this pin to the specified crystal. Power Supply. Connect to +3.3V. Power Supply. Connect to +3.3V. Power Supply. Connect to +3.3V. VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. Connect to ground Connect to ground Connect to ground Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. Charge pump current setting node, connection for setting resistor. Output Frequency Selection Pin 2. Determines output frequency as per table above. Internally biased to VDD/2. Output Frequency Selection Pin 1. Determines output frequency as per table above. Internal pull-up. No Internal Connection. Clock Output Output Frequency Selection Pin 0. Determines output frequency as per table above. Internal pull-up. Input Clock Connection 2. Connect an input reference clock to this pin. If unused, connect to ground. Input Clock Connection 1. Connect an input reference clock to this pin. If unused, connect to ground. Input Selection. Used to select which reference input clock is active. Low input level selects ICLK1, high input level selects ICLK2. Internal pull-up. Connect to ground. Crystal Output. Connect this pin to the specified crystal. IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 2 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Functional Description Quartz Crystal It is important that the correct type of quartz crystal is used with the MK2059-01. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The MK2059-01 is a clock generator IC that generates an output clock directly from an internal VCXO circuit which works in conjunction with an external quartz crystal. The VCXO is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an input reference clock. The MK2059-01 is configured to provide a MHz communications reference clock output from an 8kHz input clock. There are 12 selectable output frequencies. Please refer to the Output Clock Selection Table on Page 2. The MK2059-01 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the MK2059-01 is able to generate a low jitter, low phase-noise output clock within a low bandwidth PLL. This serves to provide input clock jitter attenuation and enables stable operation with a low frequency reference clock. The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The MK2059-01 incorporates variable load capacitors on-chip which “pull”, or change, the frequency of the crystal. The crystals specified for use with the MK2059-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2059-01 and the crystal. The VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth. A complete description of the recommended crystal parameters is shown in application note MAN05. Application Information A list of qualified crystal devices that meet these requirements can be found on the IDT web site. Output Frequency Configuration The MK2059-01 is configured to generate a set of output frequencies from an 8kHz input clock. Please refer to the Output Clock Selection Table on Page 2. Input bits SEL2:0 are set according to this table, as is the external crystal frequency. Please refer to the Quartz Crystal section on this page regarding external crystal requirements. PLL Loop Filter Components All analog PLL circuits use a loop filter to establish operating stability. The MK2059-01 uses external loop filter components for the following reasons: 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. Input Mux The Input Mux serves to select between two alternate input reference clocks. Upon reselection of the input clock, clock glitches on the output clock will not be generated due to the “fly-wheel” effect of the VCXO (the quartz crystal is a high-Q tuned circuit). When the input clocks are not phase aligned, the phase of the output clock will change to reflect the phase of newly selected input at a controlled phase slope (rate of phase change) as influenced by the PLL loop characteristics. IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Referencing the External Component Schematic on this page, the external loop filter is made up of components RS, CS and CP. RSET establishes PLL charge pump current and therefore influences loop filter characteristics. Tools for determining loop filter component values are on the IDT web site. 3 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER External Component Schematic CL Don't Stuff (Refer to Optional Crystal Tuning section) Crystal X1 1 2 3 4 5 6 7 8 9 10 VDD VDD VDD VIN RS CP CS CL GND GND GND CHGP ISET 20 19 18 17 16 15 14 13 12 11 X2 GND ISEL ICLK1 ICLK2 SEL0 CLK NC SEL1 SEL2 RSET Recommended Loop Filter Values Vs. Output Frequency Range Selection Crystal SEL2 SEL1 SEL0 Multiplier 0 0 0 0 M M M M 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 (N) 3088 3072 2048 2208 2316 2500 3125 3240 2430 2560 3088 3072 RSET RS CS CP 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 120 kΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 1.0 MΩ 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF Loop Bandwidth Damping Factor (-3dB point) 18 Hz 19 Hz 27 Hz 26 Hz 24 Hz 22 Hz 18 Hz 17 Hz 23 Hz 22 Hz 18 Hz 19 Hz 1.4 1.4 1.7 1.7 1.6 1.6 1.4 1.4 1.6 1.6 1.4 1.4 Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 4 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER A “normalized” PLL loop bandwidth may be calculated as follows: R S × I CP × 575 NBW = ----------------------------------------N Special considerations must be made in choosing loop components CS and CP. These recommendations can be found on the IDT web site. The “normalized” bandwidth equation above does not take into account the effects of damping factor or the second pole. However, it does provide a useful approximation of filter performance. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. (The optional series termination resistor is not shown in the External Component Schematic.) The loop damping factor is calculated as follows: Damping Factor = R S × 625 × I CP × C S ------------------------------------------N Decoupling Capacitors As with any high performance mixed-signal IC, the MK2059-01 must be isolated from system power supply noise to perform optimally. Where: RZ = Value of resistor in loop filter (Ohms) ICP = Charge pump current (amps) (refer to Charge Pump Current Table, below) N = Crystal multiplier shown in the above table C1 = Value of capacitor C1 in loop filter (Farads) Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2059-01 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. As a general rule, the following relationship should be maintained between components C1 and C2 in the loop filter: Recommended Power Supply Connection for Optimal Device Performance C CP = -----S20 V D D P in C onnection to 3.3V P ow er P lane Charge Pump Current Table RSET 1.4 MΩ 680 kΩ 540 kΩ 120 kΩ Charge Pump Current (ICP) 10 µA 20 µA 25 µA 100 µA IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR Ferrite Bead V D D P in B ulk D ecoupling C apacitor (such as 1 F Tantalum ) 0.01 5 V D D P in F D ecoupling C apacitors MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Crystal Load Capacitors 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK2059-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no via’s) been the crystal and device. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pf range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Please refer to application note MAN05 for the procedure to determine the capacitor values. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 6 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Recommended PCB Layout For m inim um output clock jitter, rem ove ground and pow er plane w ithin this entire area. A lso route all other traces aw ay from this area. G For m inim um output clock jitter, device V D D connections should be m ade to com m on bulk decoupling device (see text). G G G G 1 2 3 4 5 6 7 8 9 10 G G G G 20 19 18 17 16 15 14 13 12 11 NC Legend: G G = G round C onnection Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2059-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 175° C Soldering Temperature 260° C IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 7 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +85 °C +3.45 V -40 Power Supply Voltage (measured in respect to GND) +3.15 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 10 15 mA Operating Voltage VDD Supply Current IDD Input High Voltage, SEL2 VIH Input Low Voltage, SEL2 VIL Input High Voltage, ISEL, SEL1:0 VIH Input Low Voltage, ISEL, SEL1:0 VIL Input High Voltage, ICLK1, 2 VIH Input Low Voltage, ICLK1, 2 VIL Input High Current IIH VIH = VDD Input Low Current IIL VIL = 0 Input Capacitance, except X1 CIN Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -8 mA 2.4 V Output Low Voltage VOL IOL = 8 mA Short Circuit Current IOS VIN, VCXO Control Voltage VXC Nominal Output Impedance ZOUT Clock outputs unloaded, VDD = 3.3V VDD-0.5 V 0.5 2 V 0.8 VDD/2-1 V -10 +10 µA -10 +10 µA 7 pF 0.4 ±50 0 V mA VDD V Ω 20 8 V V VDD/2+1 IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR V MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol VCXO Crystal Pull Range fXP VCXO Crystal Nominal Frequency fX Input Jitter Tolerance tji Input pulse width (1) tpi Output Frequency Error Conditions Using Recommended Crystal Min. Typ. Max. Units -115 +115 ppm 13.5 27 MHz 0.4 UI In reference to input clock period 10 FOUT ICLK = 0 ppm error 0 Output Duty Cycle (% high time) tOD Measured at VDD/2, CL=15pF 40 Output Rise Time tOR Output Fall Time ns 0 0 ppm 60 % 0.8 to 2.0V, CL=15pF 1.5 ns tOF 2.0 to 0.8V, CL=15pF 1.5 ns Skew, Input to Output Clock Note 2 tIO All output clock selections except 1.544 and 2.048 MHz +5 ns Cycle Jitter (short term jitter) tja Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) tjf Timing Jitter, Filtered 65kHz-1.3MHz (OC-3) tjf -5 150 ps p-p Referenced to Mitel/Zarlink MT9045, Note 3 227 ps p-p Referenced to Mitel/Zarlink MT9045, Note 3 170 ps p-p Note 1: Minimum high or low time of input clock. Note 2: For the 1.544MHz and 2.048MHz output selections, the input to output clock skew is not controlled nor predictable and will change between power up cycles. Because it is dependent on the phase relationship between the output and feedback divider states following power up, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or MK2069 products. Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode (SEL2:0 = 100, 19.44 MHz external crystal). IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 9 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Package Outline and Package Dimensions (20 pin SOIC, 300 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Inches 20 Symbol E A A1 B C D E e H h L α H INDEX AREA 1 2 D A Min Max -2.65 1.10 -0.33 0.51 .18 .32 12.60 13.00 7.40 7.60 1.27 BASIC 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° Min Max -.104 .0040 -.013 .020 .007 .013 .496 .512 .291 .299 0.050 BASIC .394 .419 .010 0.029 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK2059-01SI* MK2059-01SI Tubes 20 pin SOIC -40 to +85° C MK2059-01SITR* MK2059-01SI Tape and Reel 20 pin SOIC -40 to +85° C MK2059-01SILF MK2059-01SILF Tubes 20 pin SOIC -40 to +85° C MK2059-01SILFTR MK2059-01SILF Tape and Reel 20 pin SOIC -40 to +85° C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 10 MK2059-01 REV G 122109 MK2059-01 VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR VCXO AND SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA