3.3V/2.5V 1:11 LVCMOS Zero Delay
Clock Generator
MPC9352
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 200 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
DATASHEET
MPC9352
Features
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Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3 2, 2 3,
1 3 and 1 2
2.5 V and 3.3 V LVCMOS Compatible
Maximum Output Skew of 200 ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package, Pb-Free
Ambient Temperature Range –40°C to +85°C
For functional replacement use 8T49N285
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:11
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL is optimized for its frequency range
and does not require external lock filter components. One output of the MPC9352 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different, but phase-aligned, clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each
output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is packaged in a 32 ld LQFP.
MPC9352 REVISION 8 MARCH 14, 2016
1
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
CCLK
CCLK
FB_IN
1
6
1
4
0
QA0
QA1
Ref
FB
Bank A
2
1
VCO 0
0
PLL
QA2
QA3
2
QA4
PLL_EN
Bank B
1
F_RANGE
QB0
QB1
0
FSELA
QB2
QB3
FSELB
Bank C
1
FSELC
QC0
QC1
0
MR/OE
(All input resistors have a value of 25 k)
GND
QB1
QB0
VCC
VCC
QA4
QA3
GND
Figure 1. MPC9352 Logic Diagram
24
23
22
21
20
19
18
17
VCC
25
16
VCC
QB2
26
15
QA2
QB3
27
14
QA1
GND
28
13
GND
MPC9352
GND
29
12
QA0
QC0
30
11
VCC
QC1
31
10
VCCA
VCC
32
2
3
4
5
6
7
8
F_RANGE
FSELC
FSELB
FSELA
MR/OE
CCLK
GND
FB_IN
9
1
PLL_EN
It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see Applications Information section for details.
Figure 2. MPC9352 32-Lead Package Pinout (Top View)
MPC9352 REVISION 8 MARCH 14, 2016
2
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
F_RANGE
Input
LVCMOS
PLL frequency range select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0–4, QB0–3, QC0–1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
VCCA
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin VCCA. Please
see Applications Information section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Negative power supply
Table 2. Function Table
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 9 and Table 10 for supported frequency ranges and output to input frequency ratios.
F_RANGE
0
VCO 1 (High input frequency range)
VCO 2 (Low input frequency range)
FSELA
0
Output divider 4
Output divider 6
FSELB
0
Output divider 4
Output divider 2
FSELC
0
Output divider 2
Output divider 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset, the PLL feedback loop is
open and the VCO is operating at its lowest frequency.
The MPC9352 requires reset at power-up and after
any loss of PLL lock. Loss of PLL lock may occur when
the external feedback path is interrupted. The length of
the reset pulse should be greater than two reference
clock cycles (CCLK).
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for
the internal VCO output. MPC9352 is fully static and
no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
MPC9352 REVISION 8 MARCH 14, 2016
3
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC 2
Condition
VTT
Output Termination Voltage
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch-Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
DC Output Voltage
–0.3
VCC + 0.3
V
DC Input Current
20
mA
DC Output Current
50
mA
125
C
VOUT
IIN
IOUT
TS
Storage Temperature
–65
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
VIH
Input high voltage
VIL
Input low voltage
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output impedance
IIN
ICCA
ICCQ(3)
Min
Typ
2.0
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
V
IOH = -24 mA(1)
V
V
IOL = 24 mA
IOL = 12 mA
2.4
0.55
0.30
14 – 17
Input Current(2)
Maximum PLL Supply Current
3.0
Maximum Quiescent Supply Current
Condition
200
A
VIN = VCC or
VIN = GND
5.0
mA
VCCA Pin
1.0
mA
All VCC Pins
1. The MPC9352 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
2. Inputs have pull-down resistors affecting the input current.
3. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
MPC9352 REVISION 8 MARCH 14, 2016
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©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)(1)
Symbol
fref
Characteristics
Input reference frequency in PLL
mode(2)
Min
4 feedback
6 feedback
8 feedback
12 feedback
Typ
50.0
33.3
25.0
16.67
Input reference frequency in PLL bypass mode(3)
fVCO
VCO lock frequency range(4)
2 output
4 output
6 output
8 output
12 output
(5)
fMAX
Output Frequency
frefDC
Reference Input Duty Cycle
tr, tf
CCLK Input Rise/Fall Time
t()
Propagation Delay CCLK to FB_IN
(static phase offset)
tsk(O)
Output-to-output Skew(6)
fref > 40 MHz
fref < 40 MHz
Max
Unit
100.0
66.6
50.0
33.3
MHz
MHz
MHz
MHz
250.0
MHz
200
400
MHz
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
MHz
MHz
MHz
MHz
25
75
%
1.0
ns
0.8 to 2.0 V
–50
–200
+150
+150
ps
ps
PLL locked
200
200
100
100
ps
ps
ps
ps
53
%
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
DC
Output duty cycle
47
0.1
50
tr, tf
Output Rise/Fall Time
1.0
ns
tPLZ, HZ
Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed
outputs are in any 4 and 6 combination
all outputs same frequency
400
250
100
ps
ps
ps
output frequencies mixed
outputs are in any 4 and 6 combination
all outputs same frequency
200
150
75
ps
ps
ps
tJIT(PER)
tJIT()
BW
tLOCK
1.
2.
3.
4.
5.
6.
7.
8.
Period Jitter
I/O Phase Jitter
4 feedback divider RMS (1 )(7)
6 feedback divider RMS (1 )
8 feedback divider RMS (1 )
12 feedback divider RMS (1 )
PLL closed loop bandwidth(8)
4 feedback
6 feedback
8 feedback
12 feedback
Maximum PLL Lock Time
Condition
15
20
18 – 20
25
ps
ps
ps
ps
3.0 – 10.0
1.5 – 6.0
1.0 – 3.5
0.5 – 2.0
MHz
MHz
MHz
MHz
10
0.55 to 2.4 V
ms
AC characteristics apply for parallel output termination of 50 to VTT.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a 2 divider for feedback.
In PLL bypass mode, the MPC9352 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
See Table 9 and Table 10 for output divider configurations.
See Applications Information section for part-to-part skew calculation.
See Applications Information section for a jitter calculation for other confidence factors than 1 .
-3 dB point of PLL transfer characteristics.
MPC9352 REVISION 8 MARCH 14, 2016
5
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
0.7
V
LVCMOS
V
IOH = –15 mA(1)
V
IOL = 15mA
VIL
Input Low Voltage
–0.3
VOH
Output High Voltage
1.8
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
(2)
17 – 20
Input Current
ICCA
ICCQ
0.6
Maximum PLL Supply Current
2.0
Maximum Quiescent Supply Current
200
A
VIN = VCC or
GND
5.0
mA
VCCA Pin
1.0
mA
All VCC Pins
1. The MPC9352 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
2. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1)
Symbol
fref
Characteristics
Input reference frequency in PLL
mode(2)
Min
4 feedback
6 feedback
8 feedback
12 feedback
Typ
50.0
33.3
25.0
16.67
Input reference frequency in PLL bypass mode(3)
fVCO
VCO lock frequency range(4)
2 output
4 output
6 output
8 output
12 output
(5)
fMAX
Output Frequency
frefDC
Reference Input Duty Cycle
tr, tf
CCLK Input Rise/Fall Time
t()
Propagation Delay CCLK to FB_IN
(static phase offset)
tsk(O)
Output-to-output Skew(6)
fref > 40 MHz
fref < 40 MHz
Max
Unit
100.0
66.6
50.0
33.3
MHz
MHz
MHz
MHz
250.0
MHz
200
400
MHz
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
MHz
MHz
MHz
MHz
25
75
%
1.0
ns
0.8 to 2.0 V
–50
–200
+150
+150
ps
ps
PLL locked
200
200
100
100
ps
ps
ps
ps
53
%
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
DC
Output duty cycle
47
0.1
50
tr, tf
Output Rise/Fall Time
1.0
ns
tPLZ, HZ
Output Disable Time
8
ns
tPZL, ZH
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed RMS (1 )
outputs are in any 4 and 6 combination RMS (1 )
all outputs same frequency RMS (1 )
400
250
100
ps
ps
ps
Period Jitter
output frequencies mixed RMS (1 )
outputs are in any 4 and 6 combination RMS (1 )
all outputs same frequency RMS (1 )
200
150
75
ps
ps
ps
tJIT(PER)
MPC9352 REVISION 8 MARCH 14, 2016
6
Condition
0.6 to 1.8 V
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1) (Continued)
Symbol
tJIT()
BW
tLOCK
1.
2.
3.
4.
5.
6.
7.
8.
Characteristics
I/O Phase Jitter
Min
Typ
Max
Unit
)(7)
4 feedback divider RMS (1
6 feedback divider RMS (1 )
8 feedback divider RMS (1 )
12 feedback divider RMS (1 )
15
20
18 – 20
25
ps
ps
ps
ps
4 feedback
6 feedback
8 feedback
12 feedback
1.0 – 8.0
0.7 – 3.0
0.5 – 2.5
0.4 – 1.0
MHz
MHz
MHz
MHz
PLL closed loop bandwidth(8)
Maximum PLL Lock Time
10
Condition
ms
AC characteristics apply for parallel output termination of 50 to VTT.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a 2 divider for feedback.
In PLL bypass mode, the MPC9352 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
See Table 9 and Table 10 for output divider configurations.
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 .
-3 dB point of PLL transfer characteristics.
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1 and 2:1. Table 9 and Table 10
illustrates the various output configurations and frequency
ratios supported by the MPC9352. See also Figure 3 to
Figure 6 for further reference. A 2 output divider cannot be
used for feedback.
Table 9. MPC9352 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1) [MHz]
FSELA
FSELB
FSELC
VCO 4(2)
50-100
0
0
0
fref
(50-100 MHz)
fref
(50-100 MHz)
fref * 2 (100-200 MHz)
0
0
1
fref
(50-100 MHz)
fref
(50-100 MHz)
fref
1
0
0
fref * 23 (33-66 MHz)
fref
(50-100 MHz)
fref * 2 (100-200 MHz)
1
0
1
fref * 23 (33-66 MHz)
fref
(50-100 MHz)
fref
1
0
0
fref
(33-66 MHz)
fref * 32 (50-100 MHz)
fref * 3 (100-200 MHz)
1
0
1
fref
(33-66 MHz)
fref * 32 (50-100 MHz)
fref * 32 (50-100 MHz)
1
1
0
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
fref * 3 (100-200 MHz)
1
1
1
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
fref * 32 (50-100 MHz)
VCO 6(3)
33.3-66.67
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
(50-100 MHz)
(50-100 MHz)
1. fref is the input clock reference frequency (CCLK).
2. QAx connected to FB_IN and FSELA=0.
3. QAx connected to FB_IN and FSELA=1.
MPC9352 REVISION 8 MARCH 14, 2016
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©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 10. MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
VCO 8
(2)
VCO 12(3)
fref(1) [MHz]
FSELA
FSELB
FSELC
25-50
0
0
0
fref
(25-50 MHz)
fref
(25-50 MHz)
fref * 2
0
0
1
fref
(25-50 MHz)
1
0
0
fref * 23
1
0
1
fref * 23
1
0
0
fref
(16-33 MHz)
fref * 32
1
0
1
fref
(16-33 MHz)
fref * 32
1
1
0
fref
(16-33 MHz)
fref * 3
(50-100 MHz)
fref * 3
1
1
1
fref
(16-33 MHz)
fref * 3
(50-100 MHz)
fref * 32 (25-50 MHz)
16.67-33.3
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
fref
(25-50 MHz)
fref
(16-33 MHz)
fref
(25-50 MHz)
fref * 2
(16-33 MHz)
fref
(25-50 MHz)
fref
(50-100 MHz)
(25-50 MHz)
(50-100 MHz)
(25-50 MHz)
(25-50 MHz)
fref * 3
(50-100 MHz)
(25-50 MHz)
fref * 32 (25-50 MHz)
(50-100 MHz)
1. fref is the input clock reference frequency (CCLK).
2. QAx connected to FB_IN and FSELA=0.
3. QAx connected to FB_IN and FSELA=1.
MPC9352 REVISION 8 MARCH 14, 2016
8
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Example Configurations for the MPC9352
fref = 100 MHz
QA0
QA1
QA2
QA3
QA4
CCLK
FB_IN
FSELA
FSELB
FSELD
F_RANGE
fref = 62.5 MHz
100 MHz
FB_IN
QB0
QB1
QB2
QB3
100 MHz
QC0
QC1
200 MHz
MPC9352
100 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
CCLK
VCC
FSELA
FSELB
FSELC
QB0
QB1
QB2
QB3
F_RANGE
QC0
QC1
MPC9352
62.5 MHz
62.5 MHz
62.5 MHz
62.5 MHz (Feedback)
MPC9352 default configuration (feedback of QB0 = 100 MHz).
All control pins are left open.
MPC9352 zero-delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
Frequency Range
Min
Max
Frequency Range
Min
Max
Input
50 MHz
100 MHz
Input
50 MHz
100 MHz
QA outputs
50 MHz
10 MHz
QA outputs
50 MHz
10 MHz
QB outputs
50 MHz
100 MHz
QB outputs
50 MHz
100 MHz
QC outputs
100 MHz
200 MHz
QC outputs
50 MHz
100 MHz
Figure 3. MPC9352 Default Configuration
fref = 33.3 MHz
QA0
QA1
QA2
QA3
QA4
CCLK
FB_IN
VCC
VCC
FSELA
FSELB
FSELC
VCC
F_RANGE
QB0
QB1
QB2
QB3
MPC9352
QC0
QC1
Figure 4. MPC9352 Zero Delay Buffer Configuration
fref = 33.3 MHz
CCLK
33.3 MHz
FB_IN
50 MHz
VCC
FSELA
FSELB
FSELC
VCC
F_RANGE
100 MHz
QA0
QA1
QA2
QA3
QQ4
33.3 MHz
QB0
QB1
QB2
QB3
33.3 MHz
QC0
QC1
33.3 MHz
MPC9352
33.3 MHz (Feedback)
33.3 MHz (Feedback)
MPC9352 configuration to multiply the reference
frequency by 3, 3 2 and 1. PLL feedback of
QA4 = 33.3 MHz.
MPC9352 zero-delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency Range
Min
Max
Frequency Range
Min
Max
Input
25 MHz
50 MHz
Input
25 MHz
50 MHz
QA outputs
50 MHz
10 MHz
QA outputs
25 MHz
50 MHz
QB outputs
50 MHz
100 MHz
QB outputs
25 MHz
50 MHz
QC outputs
100 MHz
200 MHz
QC outputs
25 MHz
50 MHz
Figure 5. MPC9352 Default Configuration
MPC9352 REVISION 8 MARCH 14, 2016
Figure 6. MPC9352 Zero Delay Buffer
Configuration 2
9
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Power Supply Filtering
The MPC9352 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCCA (PLL) power supply impacts the device
characteristics, for instance, I/O jitter. The MPC9352 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCCA) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC9352. Figure 7 illustrates a typical power
supply filter scheme. The MPC9352 frequency and phase
stability is most susceptible to noise with spectral content in
the 100 kHz to 20 MHz range; therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet, the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on
the VCCA pin. The resistor RF shown in Figure 7 should have
a resistance of 5–15 (VCC = 3.3 V) or 9–10 (VCC = 2.5 V)
to meet the voltage drop criteria.
RF = 5–15 for VCC = 3.3 V
RF = 9–10 for VCC = 2.5 V
VCC
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9352 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9352. Designs using the MPC9352 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9352 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a 4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9352 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9352 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
CF = 22 F for VCC = 3.3 V
CF = 22 F for VCC = 2.5 V
RF
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
VCCA
CF
10 nF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter.
MPC9352
VCC
33...100 nF
CCLKCommon
Figure 7. VCCA Power Supply Filter
QFBDevice 1
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics. The RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
3–5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9352 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
MPC9352 REVISION 8 MARCH 14, 2016
tPD,LINE(FB)
—t(ý)
tJIT()
Any QDevice 1
+tSK(O)
+t()
QFBDevice2
Any QDevice 2
Max. skew
tJIT()
+tSK(O)
tSK(PP)
Figure 8. MPC9352 Max. Device-to-Device Skew
10
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Due to the statistical nature of I/O jitter, a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 11.
technique terminates the signal at the end of the line with a
50 resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9352 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 10
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme, the fanout of the MPC9352 clock driver is
effectively doubled due to its capability to drive multiple lines.
Table 11. Confidence Factor CF
CF
Probability of clock edge within the distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
MPC9352
Output
Buffer
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation,
an I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –445 ps to 395 ps relative to CCLK:
IN
14
MPC9352
Output
Buffer
tSK(PP) = [–200ps...150ps] + [-200ps...200ps] +
[(15ps –3)...(15ps 3)] + tPD, LINE(FB)
IN
tSK(PP) = [–445ps...395ps] + tPD, LINE(FB)
RS = 36
ZO = 50
RS = 36
ZO = 50
RS = 36
ZO = 50
OutA
OutB0
14
OutB1
Due to the frequency dependence of the I/O jitter, Figure 9
can be used for a more precise timing performance analysis.
Figure 10. Single versus Dual Transmission Lines
Max. I/O Jitter versus frequency
30
The waveform plots in Figure 11 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9352 output buffer
is more than sufficient to drive 50 transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9352. The output waveform
in Figure 11 shows a step in the waveform. This step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36 series resistor,
plus the output impedance, does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
tJIT() [ps] ms
25
20
15
10
5
0
200
225
250
275
300
325
350
375
400
VCO frequency [MHz]
Figure 9. Max. I/O Jitter versus Frequency
Driving Transmission Lines
The MPC9352 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to application note AN1091. In
most high performance clock networks, point-to-point
distribution of signals is the method of choice. In a
point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
MPC9352 REVISION 8 MARCH 14, 2016
VL = VS (Z0 (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 (25 (18+17+25))
= 1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
11
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Since this step is well above, the threshold region, it will
not cause any false clock triggering; however, designers may
be uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 12 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
3.0
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
Voltage (V)
2.0
In
1.5
MPC9352
Output
Buffer
1.0
RS = 22
ZO = 50
RS = 22
ZO = 50
14
0.5
0
2
4
6
8
Time (ns)
10
12
14
14 + 22 || 22 = 50 || 50
25 = 25
Figure 11. Single versus Dual Waveforms
Figure 12. Optimized Dual Line Termination
MPC9352 DUT
Pulse
Generator
Z = 50
ZO = 50
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 13. CCLK MPC9352 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC9352 REVISION 8 MARCH 14, 2016
12
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
VCC
VCC 2
GND
VCC
VCC
VCC 2
CCLK
VCC 2
GND
GND
tSK(O)
VCC
VCC 2
FB_IN
GND
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
t()
Figure 14. Output-to-Output Skew tSK(O)
Figure 15. Propagation Delay (t(), static phase
offset) Test Reference
VCC
VCC 2
CCLK
GND
tP
FB_IN
T0
DC = tP/T0 x 100%
TJIT() = |T0–T1mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
Figure 16. Output Duty Cycle (DC)
TN
TN+1
Figure 17. I/O Jitter
TJIT(CC) = |TN–TN+1|
TJIT(PER) = |TN–1/f0|
T0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Period Jitter
VCC=3.3 V
tF
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
tR
Figure 20. Output Transition Time Test Reference
MPC9352 REVISION 8 MARCH 14, 2016
13
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
PACKAGE DIMENSIONS
4X
0.20 H
6
A-B D
D1
3
e/2
D1/2
PIN 1 INDEX
32
A, B, D
25
1
E1/2 A
F
B
6 E1
E
4
F
DETAIL G
8
17
9
7
D/2
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
4
D
A-B D
H
SEATING
PLANE
DETAIL G
D
4X
0.20 C
E/2
28X
e
32X
C
0.1 C
DETAIL AD
PLATING
BASE
METAL
b1
c
c1
b
8X
(θ1˚)
0.20
R R2
A2
5
8
C A-B D
SECTION F-F
R R1
A
M
0.25
GAUGE PLANE
A1
(S)
L
(L1)
θ˚
DETAIL AD
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
q
q1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0˚
7˚
12 REF
0.08
0.20
0.08
--0.20 REF
CASE 873A-03
ISSUE B
DATE 03/10/00
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC9352 REVISION 8 MARCH 14, 2016
14
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Revision History
Rev.
Originator
Date
7
Jinzhu Li
05/30/06
Corrected Figure 2, 32-Lead Package Pinout, pin 12 from nQA0 to QA0.
8
S. Nolan
11/16/12
Removed leaded parts.
8
J Dela Torre
1/7/13
NRND – Not Recommend for New Designs. Use replacement part ICS87952.
8
J Dela Torre
1/31/13
Removed replacement part from features list.
3/14/16
Product Discontinuation Notice - Last time buy expires September 7, 2016.
PDN N-16-02
8
MPC9352 REVISION 8 MARCH 14, 2016
Description of Change
15
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
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