MPC961PACR2

Low Voltage Zero Delay Buffer MPC961P DATASHEET OBSOLETE The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the device meets the needs of the most demanding clock tree applications. MPC961P Features • • • • • • • • • Fully Integrated PLL Up to 200 MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance LVPECL Reference Clock Options LQFP Packaging 32-lead Pb-free Package Available 50 ps Cycle-Cycle Jitter 150 ps Output Skews LOW VOLTAGE ZERO DELAY BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC961 is offered with two different input configurations. The MPC961P offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50  transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance. VCC Q0 50 k PCLK PCLK 50 k FB_IN 50 k AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Q1 PLL Ref 100 – 200 MHz 0 Q2 50 – 100 MHz 1 Q3 FB 50 k Q14 F_RANGE Q15 50 k Q16 OE 50 k QFB The MPC961P requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details. ©2016 Integrated Device Technology, Inc. 1 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet VCC Q6 Q7 Q8 GND Q9 Q10 Q11 Figure 1. MPC961P Logic Diagram 24 23 22 21 20 19 18 17 Q5 25 16 VCC Q4 26 15 Q12 Q3 27 14 Q13 GND 28 13 Q14 12 GND MPC961P 10 Q16 VCC 32 9 QFB 1 2 3 4 5 6 7 8 VCC 31 FB_IN Q0 OE Q15 VCCA 11 F_RANGE 30 PCLK Q1 PCLK 29 GND Q2 Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Configurations Number Name Type Description PCLK, PCLK Input LVCMOS PLL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to a QFB output F_RANGE Input LVCMOS PLL frequency range select OE Input LVCMOS Output enable/disable Q0 – Q16 Output LVCMOS Clock outputs QFB Output LVCMOS PLL feedback signal output, connect to a FB_IN GND Supply Ground Negative power supply VCCA Supply VCC PLL positive power supply (analog power supply). The MPC961P requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core Table 2. Function Table Control Default 0 F_RANGE 0 PLL high frequency range. MPC961P input reference and PLL low frequency range. MPC961P input reference and output clock frequency range is 100 – 200 MHz output clock frequency range is 50 – 100 MHz OE 0 Outputs enabled ©2016 Integrated Device Technology, Inc. 1 Outputs disabled (high-impedance state) 2 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Table 3. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.6 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V DC Input Current 20 mA DC Output Current 50 mA 125 °C VOUT IIN IOUT TS Storage Temperature –40 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. DC Characteristics (VCC = 3.3 V  5%, TA = –40° to 85°C) Symbol Characteristics Min Typ Max Unit VCC + 0.3 V Condition VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage –0.3 0.8 V LVCMOS VPP Peak-to-peak input voltage(1) PECL_CLK, PECL_CLK 500 1000 mV LVPECL Common Mode Range(2) 1.2 VCC – 0.8 V LVPECL V IOH = –20 mA(2) 0.55 V IOL = 20 mA(2) 20  120 A VCMR VOH Output HIGH Voltage VOL Output LOW Voltage ZOUT Output Impedance PECL_CLK, PECL_CLK 2.4 14 IIN Input Current CIN Input Capacitance 4.0 LVCMOS pF CPD Power Dissipation Capacitance 8.0 10 pF Per Output ICCA Maximum PLL Supply Current 2.0 5.0 mA VCCA Pin ICC Maximum Quiescent Supply Current mA All VCC Pins VTT Output Termination Voltage VCC 2 V 1. Exceeding the specified VCMR/VPP window results in a tPD changes of approximately 250 ps. 2. The MPC961P is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50  series terminated transmission lines. ©2016 Integrated Device Technology, Inc. 3 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Table 5. AC Characteristics (VCC = 3.3 V  5%, TA = –40° to 85°C)(1) Symbol Characteristics Typ Max Unit fREF Input Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz fMAX Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz fREFDC Reference Input Duty Cycle 25 75 % –80 120 ps 90 150 ps 50 50 60 55 % 1.0 ns 10 ns 10 ns 15 ps 10 ps t() (2) Propagation Delay (static phase offset) PECL_CLK to FB_IN tsk(O) Output-to-Output Skew(3) DCO Output Duty Cycle tr, tf Output Rise/Fall Time tPLZ,HZ Output Disable Time tPZL,LZ Output Enable Time F_RANGE = 0 F_RANGE = 1 tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT() tlock 1. 2. 3. 4. Min 40 45 0.1 RMS (1)(4) RMS (1) I/O Phase Jitter 7.0 0.0015 · T 0.0010 · T RMS (1) F_RANGE = 0 F_RANGE = 1 Maximum PLL Lock Time 10 Condition PLL locked 0.6 to 1.8 V T = Clock Signal Period ms AC characteristics apply for parallel output termination of 50  to VTT. tPD applies for VCMR = VCC –1.3 V and VPP = 800 mV. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1 Table 6. DC Characteristics (VCC = 2.5 V  5%, TA = –40° to 85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input HIGH Voltage 1.7 VCC + 0.3 V LVCMOS VIL Input LOW Voltage –0.3 0.7 V LVCMOS VPP VCMR Peak-to-peak input voltage(1) Common Mode Range(1) VOH Output HIGH Voltage VOL Output LOW Voltage ZOUT Output Impedance PECL_CLK, PECL_CLK 500 1000 mV LVPECL PECL_CLK, PECL_CLK 1.2 VCC – 0.7 V LVPECL V IOH = –15 mA(2) V IOL = 15 mA(2) 1.8 0.6 18 26  120 A IIN Input Current CIN Input Capacitance 4.0 CPD Power Dissipation Capacitance 8.0 10 pF Per Output ICCA Maximum PLL Supply Current 2.0 5.0 mA VCCA Pin ICC Maximum Quiescent Supply Current mA All VCC Pins VTT Output Termination Voltage VCC  2 pF V 1. Exceeding the specified VCMR/VPP window results in a tPD changes < 250 ps. 2. The MPC961P is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50  series terminated transmission lines. ©2016 Integrated Device Technology, Inc. 4 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Table 7. AC Characteristics (VCC = 2.5 V  5%, TA = –40° to 85°C)(1) Symbol Characteristics Typ Max Unit fREF Input Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz fMAX Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz fREFDC Reference Input Duty Cycle 25 75 % –50 175 ps 90 150 ps 50 50 60 55 % 1.0 ns 10 ns 10 ns 15 ps 10 ps t() (2) Propagation Delay (static phase offset) tsk(O) Output-to-Output Skew(3) DCO Output Duty Cycle tr, tf Output Rise/Fall Time tPLZ,HZ Output Disable Time tPZL,LZ Output Enable Time tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tJIT() tlock 1. 2. 3. 4. Min I/O Phase Jitter CCLK to FB_IN F_RANGE = 0 F_RANGE = 1 40 45 0.1 RMS (1)(4) RMS (1) 7.0 0.0015 · T 0.0010 · T RMS (1) F_RANGE = 0 F_RANGE = 1 Maximum PLL Lock Time 10 Condition PLL locked 0.6 to 1.8 V T = Clock Signal Period ms AC characteristics apply for parallel output termination of 50  to VTT. tPD applies for VCMR = VCC –1.3 V and VPP = 800 mV. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1 ©2016 Integrated Device Technology, Inc. 5 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet APPLICATIONS INFORMATION Power Supply Filtering The MPC961P is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC961P provides separate power supplies for the output buffers (VCC) and the phaselocked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC961P. Figure 3 illustrates a typical power supply filter scheme. The MPC961P is most susceptible to noise with spectral content in the 10 kHz to 5 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC961P. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2 mA (5 mA maximum), assuming that a minimum of 2.375 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3 must have a resistance of 270  (VCC = 3.3 V) or 5 to 15  (VCC = 2.5 V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Driving Transmission Lines The MPC961P clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15  the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-topoint scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50  resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC961P clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC961P clock driver is effectively doubled due to its capability to drive multiple lines. MPC961 Output Buffer IN MPC961 Output Buffer RF = 270  for VCC = 3.3 V RF = 5–15  for VCC = 2.5 V VCC RF 14  IN RS = 36  ZO = 50  RS = 36  ZO = 50  RS = 36  ZO = 50  OutA OutB0 14  OutB1 VCCA CF 10 nF MPC961P Figure 4. Single versus Dual Transmission Lines VCC The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC961P output buffer is more than sufficient to drive 50  transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC961P. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36  series resistor plus the output impedance does not match the parallel combination of 33...100 nF Figure 3. Power Supply Filter Although the MPC961P has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. ©2016 Integrated Device Technology, Inc. 6 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet the line impedances. The voltage wave launched down the two lines will equal: VL = VS (ZO / (RS + RO + ZO)) ZO = 50  || 50  RS = 36  || 36  RO = 14  VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). SPICE level and IBIS output buffer models are available for engineers who want to simulate their specific interconnect schemes. Using the MPC961P in Zero-Delay Applications Nested clock trees are typical applications for the MPC961P. Designs using the MPC961P as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC961P clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 Calculation of Part-to-Part Skew The MPC961P zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC961P are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() · CF 14 This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC961 Output Buffer RS = 22  TCLKCommon QFBDevice 1 tJIT() Any QDevice 1 +tSK(O) +t() ZO = 50  QFBDevice2 tJIT() 14  RS = 22  ZO = 50  Any QDevice 2 Max. skew 14 + 22  || 22  = 50  || 50  25  = 25  +tSK(O) tSK(PP) Figure 7. MPC961P Max. Device-to-Device Skew Figure 6. Optimized Dual Line Termination ©2016 Integrated Device Technology, Inc. tPD,LINE(FB) —t(ý) Due statistical nature of I/O jitter a rms value (1) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. 7 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC961P die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability refer to the Application Note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 8. Confidence Factor CF CF Probability of clock edge within the distribution  1 0.68268948  2 0.95449988  3 0.99730007  4 0.99993663  5 0.99999943  6 0.99999999 Table 9. Die Junction Temperature and MTBF The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of –236 ps to 361 ps relative to PCLK (f = 125 MHz, VCC = 2.5 V): tjit() [ps] RMS Due to the frequency dependence of the I/O jitter, Figure 8 “Max. I/O Jitter versus frequency” can be used for a more precise timing performance analysis. F_RANGE = 0 VCC = 3.3 V VCC = 2.5 V 110 130 MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC961P needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC961P is represented in equation 1. Where ICCQ is the static current consumption of the MPC961P, CPD is the power dissipation capacitance per output, CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC961P). The MPC961P supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH, and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. tSK(PP) = [-50 ps...175ps] + [-150 ps...150 ps] + [(12ps @ -3)...(12ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-236ps...361ps] + tPD, LINE(FB) F_RANGE = 1 18 16 14 VCC = 2.5 V 12 10 8 V = 3.3 V 6 CC 4 2 0 50 70 90 Junction temperature (C) 150 170 190 Clock frequency [MHz] Figure 8. Max. I/O Jitter versus Frequency Power Consumption of the MPC961P and Thermal Management The MPC961P AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The MPC961P power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical PTOT = [ ICCQ + VCC · fCLOCK · ( N · CPD +  CL ) ] · VCC Equation 1 M PTOT = VCC · [ ICCQ + VCC · fCLOCK · ( N · CPD +  CL ) ] +  [ DCQ · IOH · (VCC – VOH) + (1 – DCQ) · IOL · VOL ] Equation 2 M P Equation 3 TJ = TA + PTOT · Rthja fCLOCK,MAX = 1 CPD · N · V2 · CC [ Tj,MAX – TA ©2016 Integrated Device Technology, Inc. Rthja – (ICCQ · VCC) ] 8 Equation 4 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC961P in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200 MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the MPC961P. The charts were calculated for a maximum tolerable die junction temperature of 110C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5 V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120C. Table 10. Thermal Package Impedance of the 32ld LQFP Convection, LFPM Rthja (1P2S board), K/W Still air 80 100 lfpm 70 200 lfpm 61 300 lfpm 57 400 lfpm 56 500 lfpm 55 200 fMAX (AC) 180 TA = 85C 160 OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) 200 140 120 100 80 60 Safe operation 40 20 0 500 fMAX (AC) 180 TA = 75C 160 140 TA = 85C 120 100 80 60 Safe operation 40 20 400 300 200 IFPM, CONVECTION 100 0 500 0 Figure 9. Maximum MPC961P Frequency, VCC = 3.3 V, MTBF 9.1 Years, Driving Series Terminated Transmission Lines 400 300 200 IFPM, CONVECTION 100 0 Figure 10. Maximum MPC961P Frequency, VCC = 3.3 V, MTBF 9.1 Years, 4 pF Load per Line MPC961P DUT Pulse Generator Z = 50  ZO = 50  ZO = 50  RT = 50  RT = 50  VTT VTT Figure 11. TCLK MPC961P AC Test Reference for VCC = 3.3 V and VCC = 2.5 V ©2016 Integrated Device Technology, Inc. 9 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet PCLK VPP VCMR PCLK VCC = 3.3 V VCC VCC 2 Ext_FB GND tF t() Figure 12. Propagation Delay (t, static phase offset) Test Reference VCC = 2.5 V 2.4 1.8 V 0.55 0.6 V tR Figure 13. Output Transition Time Test Reference VCC VCC 2 VCC VCC 2 GND GND tP VCC VCC 2 T0 GND DC = tP/T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 14. Output Duty Cycle (DC) Figure 15. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN–TN+1| TJIT(PER) = |TN–1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter PCLK PCLK Ext_FB TJIT() = |T0–T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 18. I/O Jitter ©2016 Integrated Device Technology, Inc. 10 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet PACKAGE DIMENSIONS 4X 0.20 H 6 A-B D D1 3 e/2 D1/2 PIN 1 INDEX 32 A, B, D 25 1 E1/2 A F B 6 E1 E 4 F DETAIL G 8 17 9 7 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 4 D 4X A-B D H SEATING PLANE DETAIL G D D/2 0.20 C E/2 28X e 32X C 0.1 C DETAIL AD PLATING BASE METAL b1 c c1 b 8X (θ1˚) 0.20 R R2 A2 5 8 C A-B D SECTION F-F R R1 A M 0.25 GAUGE PLANE A1 (S) L (L1) θ˚ DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0˚ 7˚ 12 REF 0.08 0.20 0.08 --0.20 REF CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE ©2016 Integrated Device Technology, Inc. 11 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Revision History Sheet Rev Table Page Description of Change Date 5 1 NRND – Not Recommend for New Designs. 1/8/13 5 1 Product Discontinuation Notice - PDN CQ-15-02. 5/6/15 6 1 Obsolete per Product Discontinuation Notice - PDN CQ-15-02. 10/4/16 ©2016 Integrated Device Technology, Inc. 12 Revision 6, October 4, 2016 OBSOLETE MPC961P Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. 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