R1RP0408DGE-2PI#B0

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in 400-mil 36-pin plastic SOJ. Features • Single 5.0 V supply: 5.0 V ± 10 % • Access time: 12 ns (max) • Completely static memory  No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible  All inputs and outputs • Operating current: 130 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current: 5 mA (max) • Center VCC and VSS type pin out • Temperature range: −40 to +85°C Ordering Information Type No. Access time Package R1RP0408DGE-2PI 12 ns 400-mil 36-pin plastic SOJ (36P0K) Rev.1.00, Mar.12.2004, page 1 of 10 R1RP0408DI Series Pin Arrangement 36-pin SOJ A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 CS# 6 31 OE# I/O1 7 30 I/O8 I/O2 8 29 I/O7 VCC 9 28 VSS VSS 10 27 VCC I/O3 11 26 I/O6 I/O4 12 25 I/O5 WE# 13 24 A14 A5 14 23 A13 A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A9 18 19 NC (Top View) Pin Description Pin name Function A0 to A18 Address input I/O1 to I/O8 Data input/output CS# Chip select OE# Output enable WE# Write enable VCC Power supply VSS Ground NC No connection Rev.1.00, Mar.12.2004, page 2 of 10 R1RP0408DI Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 (MSB) Internal voltage generator Row decoder 1024-row × 32-column × 16-block × 8-bit (4,194,304 bits) VSS CS Column I/O I/O1 Input data control . . . Column decoder CS I/O8 A8 A9 A18 A16 A17 A0 A2 A4 A15 (LSB) WE# CS# OE# CS Rev.1.00, Mar.12.2004, page 3 of 10 VCC (MSB) R1RP0408DI Series Operation Table CS# OE# WE# Mode VCC current I/O Ref. cycle H × × Standby ISB, ISB1 High-Z  L H H Output disable ICC High-Z  L L H Read ICC DOUT Read cycle (1) to (3) L H L Write ICC DIN Write cycle (1) L L L Write ICC DIN Write cycle (2) Parameter Symbol Value Supply voltage relative to VSS VCC −0.5 to +7.0 Voltage on any pin relative to VSS VT −0.5* to VCC + 0.5* Power dissipation PT 1.0 W Operating temperature Topr −40 to +85 °C Storage temperature Tstg −55 to +125 °C Storage temperature under bias Tbias −40 to +85 °C Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Unit V 1 2 V Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. Recommended DC Operating Conditions (Ta = −40 to +85°C) Parameter Symbol Supply voltage Min Typ Max Unit 3 4.5 5.0 5.5 V 4 0 0 0 VIH 2.2  VCC + 0.5* VIL −0.5*  0.8 VCC* VSS* Input voltage Notes: 1. 2. 3. 4. 1 VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Rev.1.00, Mar.12.2004, page 4 of 10 V 2 V V R1RP0408DI Series DC Characteristics (Ta = −40 to +85°C, VCC = 5.0 V ± 10 %, VSS = 0 V) Parameter Symbol Min Max Unit Test conditions Input leakage current IILII  2 µA VIN = VSS to VCC Output leakage current IILOI  2 µA VIN = VSS to VCC Operation power supply current ICC  130 mA Min cycle CS# = VIL, lOUT = 0 mA Other inputs = VIH/VIL Standby power supply current ISB  40 mA Min cycle, CS# = VIH, Other inputs = VIH/VIL ISB1  5 mA f = 0 MHz VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V Output voltage VOL  0.4 V IOL = 8 mA VOH 2.4  V IOH = −4 mA Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* 1 Input/output capacitance* Note: 1 Symbol Min Max Unit Test conditions CIN  6 pF VIN = 0 V CI/O  8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. Rev.1.00, Mar.12.2004, page 5 of 10 R1RP0408DI Series AC Characteristics (Ta = −40 to +85°C, VCC = 5.0 V ± 10 %, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) 5V 1.5 V DOUT Zo = 50 Ω 480 Ω RL = 50 Ω DOUT 255 Ω 30 pF 5 pF Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Output load (A) Read Cycle R1RP0408DI -2 Parameter Symbol Min Max Unit Read cycle time tRC 12  ns Address access time tAA  12 ns Chip select access time tACS  12 ns Output enable to output valid tOE  6 ns Output hold from address change tOH 3  ns Chip select to output in low-Z tCLZ 3  ns 1 Output enable to output in low-Z tOLZ 0  ns 1 Chip deselect to output in high-Z tCHZ  6 ns 1 Output disable to output in high-Z tOHZ  6 ns 1 Rev.1.00, Mar.12.2004, page 6 of 10 Notes R1RP0408DI Series Write Cycle R1RP0408DI -2 Parameter Symbol Min Max Unit Notes Write cycle time tWC 12  ns Address valid to end of write tAW 8  ns Chip select to end of write tCW 8  ns 9 Write pulse width tWP 8  ns 8 Address setup time tAS 0  ns 6 Write recovery time tWR 0  ns 7 Data to write time overlap tDW 6  ns Data hold from write time tDH 0  ns Write disable to output in low-Z tOW 3  ns 1 Output disable to output in high-Z tOHZ  6 ns 1 Write enable to output in high-Z tWHZ  6 ns 1 Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS# transition low. 3. WE# and/or CS# must be high during address transition time. 4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, output remains a high impedance state. 6. tAS is measured from the latest address transition to the later of CS# or WE# going low. 7. tWR is measured from the earlier of CS# or WE# going high to the first address transition. 8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest transition among CS# going low and WE# going low. A write ends at the earliest transition among CS# going high and WE# going high. tWP is measured from the beginning of write to the end of write. 9. tCW is measured from the later of CS# going low to the end of write. Rev.1.00, Mar.12.2004, page 7 of 10 R1RP0408DI Series Timing Waveforms Read Timing Waveform (1) (WE# = VIH) tRC Address Valid address tOH tAA tACS tCHZ CS# tOE tOHZ OE# tOLZ tCLZ DOUT High impedance Valid data Read Timing Waveform (2) (WE# = VIH, CS# = VIL, OE# = VIL) tRC Address Valid address tAA tOH tOH DOUT Rev.1.00, Mar.12.2004, page 8 of 10 Valid data R1RP0408DI Series Read Timing Waveform (3) (WE# = VIH, CS# = VIL, OE# = VIL)* 2 tRC CS# tACS tCHZ tCLZ DOUT High impedance Valid data High impedance Write Timing Waveform (1) (WE# Controlled) tWC Valid address Address tWR tAW OE# tCW CS#*3 tAS tWP WE#*3 tOHZ High impedance*5 DOUT tDW DIN Rev.1.00, Mar.12.2004, page 9 of 10 *4 tDH Valid data *4 R1RP0408DI Series Write Timing Waveform (2) (CS# Controlled) tWC Valid address Address tWR tCW CS# *3 tAW tWP WE# *3 tAS tWHZ tOW High impedance*5 DOUT tDW DIN Rev.1.00, Mar.12.2004, page 10 of 10 *4 tDH Valid data *4 Revision History Rev. Date R1RP0408DI Series Data Sheet Contents of Modification Page Description 0.01 Oct. 01, 2003  Initial issue 1.00 Mar.12.2004  Deletion of Preliminary Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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