R2J20751NPG0

Preliminary Datasheet R2J20751NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters. In a simple peak-current mode topology, stable operation is obtained in a closed power loop, and a fast converter is easily realized with the addition of simple components. Furthermore, the same topology can be applied to realize converters for parallel synchronized operation with current sharing, and multi-phase operation. The package also incorporates a high-side bootstrap switch (Boot switch), eliminating the need for an external SBD for this purpose. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Features                 Three chip in one package for high efficiency and space saving Large average output current (25 A) Wide input voltage range: 3.3 V to 27 V 0.6 V reference voltage accurate to within 2% Wide programmable switching frequency: 200 kHz to 1 MHz Peak current mode topology with Active Current Sensing Slope compensation function Current sensing error: 1.5 A maximum @15 A load current Built-in Boot switch for boot strapping ON/OFF control Hiccup operation under over load condition Tracking function Thin and small package: QFN40 pins (6 mm  6 mm) Power Good function Over voltage protection Pre-OVP function Applications  Mother board  Servers Typical Characteristic Curve 96 94 VIN = 5V VOUT = 1.5V Frequency = 500kHz Efficiency (%) 92 90 88 86 84 82 80 0 5 10 15 20 25 Output Current Iout (A) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 1 of 25 R2J20751NP Preliminary Application Circuit Example VCIN (4.5V to 5.5V) VIN (3.3V to 27V) ON/OFF PGOOD TRK-SS BOOT CT VCIN IREF OUT IN VIN VCIN VOUT (1.5V) SW FB EO/CO Controller Chip Share SGND R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 PGND CSLP REFIN CS Page 2 of 25 4.5V to 5.5V R2J20751NP IN OUT VCIN BOOT CO Block Diagram ON/OFF Supervisor SYS. ENBL UVL Internal Logic Power Boot Switch VIN UVLO ON/OFF IN Pulse Generator VCIN 3.3V to 27V R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 oscillator 1.8V SYS.ENBL RES 1V CLK Max. Duty Max. Duty 50ns RES OUT OVP CT CT Active Current Sensing 50ns Blanking UVLO Idh 13700 SYS.ENBL Q Q PWM Idh CLK CLK Phase Ctrl Comp. Share CO S R SW Gate Drive Logic Circuit OCP VOUT EO/CO Slave REFIN/ POS VCIN 0.6V(2%) OCP Hiccup control Current Sense Comp. 1.5V PreOVP VCIN OCP Comp. OVP TRK-SS Error Amp. 10k 35k 40k Islope OVP RES Islope ON/OFF UVLO OCL SYS. ENBL R S 125% REF Q Q PGND VOUT FB PGOOD 300μA OVP Comp. Power Good Indicator 90% REF FB OVP 70% VCIN Slave M/S Selector SGND Share CSLP CS Iref Preliminary Page 3 of 25 R2J20751NP Preliminary Pin Arrangement PGOOD REFIN/POS 1 40 39 10 9 8 7 6 5 4 Share 3 IREF CS OUT IN SGND CLK BOOT SW VIN VIN VIN VIN EO/CO 2 SGND CSLP VCIN CT 11 12 FB TRK-SS SGND ON/OFF SW SW SW SW SW SW SGND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 38 37 36 35 VIN SW 34 33 32 31 PGND PGND PGND PGND Top view Package: QFN40 pin (6 mm × 6 mm, 0.5-mm pin pitch) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 PGND VIN VIN VIN VIN SW Page 4 of 25 R2J20751NP Preliminary Pin Description Pin Name VIN SW PGND SGND VCIN BOOT TRK-SS FB EO/CO Share IREF CSLP CS CT OUT IN CLK ON/OFF PGOOD REFIN/POS Pin No. 17 to 24 16, 25, 31 to 36 26 to 30 10, 13, 38 6 15 39 40 2 3 5 7 8 9 11 12 14 37 4 1 Description Input voltage for buck converter. Switching node. Connect a choke coil between the SW pin and dc output node of the converter. Ground of the power stage. Ground of the IC chip. Input voltage for control circuit. Bootstrap voltage pin. A bootstrap capacitance should be connected between BOOT pin and SW pin. Start-up timing control input. Feedback voltage input for the closed loop. Error amplifier output pin. (Master mode) Comparator output pin. (Slave mode) Current share bus. Reference current generator for the IC. Additional current slope input pin. Current output pin of Active Current Sensing circuit. Timing capacitor pin for the oscillator. Switching trigger output. Switching trigger input. I/O pin for synchronous operation. Signal disable pin. Power Good Indicator output. (Open drain) Reference voltage input. (Master mode) Comparator positive pin. (Slave mode) Tie to IN pin of previous device in multi phase operation. Tie to OUT pin of next device in multi phase operation. Should be connect to each CLK pin in multiphase operation. Disabled when ON/OFF pin is low state. Pulled low when No Good. Should be connected to each Share pin in multi phase operation. Need a 18 k resistance between IREF to GND plane. Should be connected capacitor between CSLP to GND. Need a resistance appropriately between CS to GND plane. Should be connected to SGND externally. Should be connected to PGND externally. Should be connected to 5 V power supply. To be supplied +5 V through the internal SBD. Remarks R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 5 of 25 R2J20751NP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage PGOOD voltage Other pins voltage TRK-SS dc current IREF current EO sink current CO sink current CO source current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol Pt(25) Pt(100) Iout VIN(DC) VIN(AC) VCIN(DC) Vsw(DC) Vsw(AC) Vboot(DC) Vboot(AC) Von/off Vpgood Vic Itrk Iref Iieo Iico Ioco Tj-opr Tstg Rating 25 8 25 –0.3 to +27 30 –0.3 to +6 27 30 32 36 –0.3 to VIN 0 to VIN –0.3 to (REG5 + 0.3) 0 to 1 –120 to 0 0 to 2 0 to 1 0 to 1 –40 to +150 –55 to +150 Unit W A V V V V V V V mA A mA mA mA °C °C Note 1 2 2, 5 2 2 2, 5 2 2, 5 2 3 2 3 3 3 3, 4 3, 4 Pt(25) represents a PCB temperature of 25°C, and Pt(100) represents 100°C. Rated voltages are relative to voltages on the SGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. Rated currents are only for slave mode. Ratings for which "ac" is indicated are limited to within 100 ns. Safe Operating Area 30 Average Output Current Iout (A) 25 20 15 10 5 VIN = 5 V VOUT = 1.5 V Frequency = 300 kHz 0 20 40 60 80 100 120 140 160 0 PCB Temperature Tpcb (°C) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 6 of 25 R2J20751NP Preliminary Electrical Characteristics (Ta = 25°C, VIN = VCIN = 5 V, unless otherwise specified) Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis Input bias current Slave standby current Input shutdown current Remote On/off Reference current generator Oscillator Disable threshold Enable threshold Input current IREF pin voltage Symbol VH VL dUVL Iin I-sin Isd Voff Von Ion/off VIref Min 4.1 3.6 — 15 2.1 3.1 1.0 2.0 0.5 1.75 Typ 4.3 3.8 0.5 * 30 3.5 4.5 1.3 2.5 2.0 1.80 1 Max 4.5 4.0 — 45 4.9 5.9 1.6 3.0 5.0 1.85 Unit V V V mA mA mA V V A V Test Conditions Freq = 500 kHz, Duty = 50% Von/off = 5 V, Vfb = 5 V ON/OFF = 0 V Von/off = 1 V Riref = 18 k CT oscillating frequency CT higher trip voltage CT lower trip voltage CT source current CT sink current Fct Vhct Vlct Ict-src Ict-snk Vfb Ifb Irefin Ieo-src Ieo-snk Av BW Rshare Ico-src Ico-snk Ipos Idh/Ics TLD Td-cs Vocp Tocp Vramp-dc Ics-dc Vgood dVgood Vpglow — — — –176 144 588 –0.1 0.5 150 3.5 — — 35 –3.0 2.0 0.5 — — — 1.4 1.85 70 — 0.855 — 0.6 500 1.8 *1 1 *1 –160 160 600 0 2 200 7.0 80 *1 15 *1 50 –2.0 3.0 2 13700 * 60 *1 65 *1 1.5 2.05 100 300 0.9 50 * 1.0 1 1 — — — –144 176 612 +0.1 5 250 14.0 — — 65 –1.0 4.0 5.0 — — — 1.6 2.26 130 — 0.945 — 1.4 kHz V V A A mV A A A mA dB MHz k mA mA A — ns ns V ms mV A V mV V CT = 180 pF CT = 180 pF CT = 180 pF CT = 0.5 V CT = 2.3 V TRK-SS = 1 V Error amplifier Feedback voltage FB input bias current REFIN input bias current Output source current Output sink current Voltage gain Band width Share pin resistance EO = 4 V, FB = 0 V EO = 1 V, FB = 0.7 V EO = 0 V. Ishare = 1 V Share = 0 V, POS = 1 V, CO = 4.5 V Share = 1 V, POS = 0 V, CO = 0.5 V POS = 1.0 V Phase control comparator Output source current Output sink current Input bias current Current sense CS current accuracy Leading edge blanking time CS comparator delay to output OCP comparator threshold on CS pin Hiccup interval RAMP offset voltage CS offset current CT = 180 pF CT = 180 pF CS = 0 V REFIN = 1.0 V Ipgood = 2 mA Power good indicator Rising threshold on FB Power good hysteresis Power good output low voltage Note: 1. Reference values for design. Not 100% tested in production. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 7 of 25 R2J20751NP Preliminary (Ta = 25°C, VIN = VCIN = 12 V, unless otherwise specified) Item Symbol Vtovp Vpovp ISLP Fclk Vh-out Vl-out Ibin Vth-in Vth-hys Min 1.19 — 7 450 4.0 0 0.5 — — Typ 1.25 1.67 10 500 5.0 — 2.0 2.2 0.25 Max 1.31 — 13 550 — 1.0 5.0 — — Unit V V A kHz V V A V V VSLP = 0 V CT = 180 pF Rout = 51 k to GND Rout = 51 k to VCIN V-in = 1 V Test Conditions REFIN = 1.0 V Overvoltage protection Slope generator Clock generator OVP trip voltage Pre-OVP trip voltage Slope current Clock frequency OUT high voltage OUT low voltage IN input bias current IN input threshold IN input hysteresis Note: 1. Reference values for design. Not 100% tested in production. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 8 of 25 R2J20751NP Preliminary Description of Operation Peak Current Control The control IC operates as current programmed control mode, in which output of the converter is controlled by the choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active current sensing circuit (ACS), the output current of which is 1/13700 (50 ppm) of the MOS FET current. The ACS current is then converted to certain voltage by external resistor on the CS pin. The CS voltage is fed to the internal current sense comparator via the slope compensation circuit, and then compared with current control signal which determined from the error amplifier output voltage (EO) via an NPN transistor and resister network. To start with, the RES pulse from pulse generator resets a latch, then the high-side MOS FET is turned on. The latch output (Q bar) is toggled when CS voltage reaches the level of the current control signal on EO, the high-side MOS FET is turned off, and the low-side MOS FET is turned off after a certain dead time interval. The IC remains in this state until the arrival of the next RES pulse. Applying current information for the control loop, the converter loop compensation design will be simple. Maximum Duty-Cycle Limitation If the current-sense comparator output is not toggled 60-ns prior to the arrival of the next RES pulse, an internal maximum duty pulse is generated and forces toggling of SR latch. So, the duty cycle of the high-side MOS FET is limited by the maximum duty period. The maximum duty period of the high-side MOS FET depends on its switching frequency. Max. duty = 1 – 60 ns  Fsw OCP Hiccup Operation Eight times the voltage of CS exceeds 1.5 V, OCP hiccup circuit disables switching operation of the IC and MOS FETs. Internal circuitry also pulls the TRK-SS pin down to SGND. The IC is turned off for a period of 1024 RES pulses; after this has elapsed, switching operation of the IC is restarted from the soft-start state. UVLO and ON/OFF Control When VCIN is under the start-up voltage, it is in the UVLO condition, functioning of the IC is disabled. The oscillator is turned off, both high and low-side MOS FETs are turned off, and the TRK-SS pin is pulled down. Furthermore, if the ON/OFF pin is the low state or left open, functioning of the IC is disabled and both MOS FETs are turned off. Oscillator and Pulse Generator The frequency of the oscillator (Fct) is set by the value of the external capacitor connected to the CT pin. The switching frequency (Fsw) is not the same as Fct, which also depends on the phase number N. The following equations determine these frequencies. Oscillator frequency: Fct = 160 A / (2  CT(F)  0.8 V)  N Switching frequency: Fsw = Fct / N (Hz) (Hz) In multi-phase operation, connect the CT pins for all devices. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 9 of 25 R2J20751NP Soft Start Preliminary TRK-SS pin is provided for start-up setup. Both simple soft start and sequential start up can be realized with this pin setup. The error amp has two reference inputs and one input for soft start. One of lower voltage inputs of the two positive inputs is dominant for the amplifier. Therefore simply having CR charging circuit on TRK-SS pin is easier for soft start design. The soft start period is determined with the equation as follows when TRK-SS pin has CR charging circuit. Tss = –C · R · Ln (1 – REF / VCIN) (s) REF is REFIN voltage or 0.6 V in internal reference voltage. Power Good Indicator The power good indicator is useful for controlling timing when multiple converter systems are started up or shut down. Voltage on the FB pin is internally monitored by a power good comparator. The power good comparator compares the voltage on the pin with 90% of the reference voltage. When the comparator detects the FB voltage reaching the reference voltage, the Power Good pin becomes high impedance. If the voltage on FB goes over 125% or falls below 80% of the reference voltage, the pin is pulled down to SGND. PGOOD has an n-channel MOS FET operating as an open drain output and capable of sinking up to 2 mA of current. Overvoltage Protection When the output voltage (FB voltage) reaches or exceeds 125% of the reference voltage, switching stops immediately, the gate of the low-side MOS FET is latched in the high level, which causes shorting of the SW pin to GND. Resetting to leave the OVP mode is by resupplying VCIN or switching the circuit OFF and ON. Pre-Overvoltage Protection When the IC is starting up, an internal circuit monitors the voltage at the switch node and detects the output of excessive voltages. When a voltage exceeding 1.67 V is detected on the SW pin after release from the UVL state, the gate of the low-side MOS FET is latched in the high level, which causes shorting of the SW pin to GND. The low-side MOS FET remains in this state until VCIN is resupplied. Multi Phase Operation The R2J20751NP is a scalable solution. Pulling the FB pin of a device up to VCIN causes the device to operate as a slave. Clock timing is synchronized by connecting the CLK and CT pins of all devices. Current sharing is available by connecting the Share pins. The timing of switching of the signal on the SW pin is generated from the switching trigger signal on the IN pin. A device that has received the switching trigger signal outputs the same signal on its OUT pin for the next device one clock cycle later. The phase number is controllable by the internal phase control comparators of slave devices. Slope Compensation If peak current control leads to the duty cycle being over 50%, sub-harmonic oscillation is generated and the output voltage becomes unstable regardless of the negative feedback for constant voltage control. The duty cycle, D, is obtained from the following equation. D = Vout / VIN  100 (%) To prevent such oscillation, add a constant slope to the slope of the voltage on the CS pin. This added slope is determined by 10 uA constant current output through the CSLP pin and the value of the connected external capacitor. Insufficient added slope leads to sub-harmonic oscillation. Too much added slope leads to voltage-mode operation and poorer response characteristics. An optimal slope (determined by the value of the external capacitor) needs to be set. The capacitance (Cslp) is determined by the following equation. Cslp = 70 A  13700  Toff / (2  Ipp  Rcs  M) In the above equation, Toff is the off portion of the duty cycle (as time), Ipp is the ripple current of the output inductor, Rcs is the value of the external resistor connected to the CS pin, and M is the rate of the added slope. A capacitor value that leads to a greater setting of M in the range from 0.5 to 1.0 will lead to a greater added slope. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 10 of 25 R2J20751NP Output Voltage Setting Preliminary The error amplifier of the device has an accurate 0.6 V reference voltage and REFIN pin which can input reference voltage from external voltage. When reference voltage is 0.6 V, feedback loop leads to the FB pin a voltage of 0.6 V in case of stable condition on the converter. Therefore the output voltage is; Vout = 0.6 V  (R1 + R2) / R2 REFIN pin should be pulled up to VCIN, when reference voltage refer to internal 0.6 V. R VCIN Vout REFIN CT FB R1 R2 Loop Compensation Peak-current control makes design in terms of phase margins easier than is the case with voltage control. This is because of differences between the characteristics of the PWM modulator and power stage in the two methods. Figure 1 and 2 shows the behavior of the PWM modulator and power stage in the case of voltage control and peak current control, respectively. Gain (dB) −40 dB/dec Gain (dB) −20 dB/dec freq. (Hz) 0 Phase (deg) −180 freq. (Hz) 0 Phase (deg) −90 −180 freq. (Hz) freq. (Hz) Figure 1 Bode Plot (Voltage Mode) Figure 2 Bode Plot (Peak Curent Mode) Feed-forward current to the modulator in the case of peak-current control means that the system is single pole, so we see a –20 dB/decade cutoff and phase margin of 90° in the Bode plot. In voltage control, the system configures a twopole system. That is why rather complicated loop compensation of the error amplifier is required. Such as type-III compensation. The design of effective compensation is thus much simpler in the case of peak-current control (refer to figure 3). R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 11 of 25 R2J20751NP Rf Cf EO R1 FB Preliminary Vout R2 REF 10k Amp-out to current-sense comparator 40k Figure 3 Error Amplifier Compensation Design example; Specification: L = 470 nH, Co = 600 F, Fsw = 500 kHz, Vin = 5 V, Vout = 1.5 V, R1 = 1 k, R2 = 1 kΩ, RCS = 820 Ω 1. Flat band gain of error amplifier The flat band gain is; Af = Rf / (R1 // R2)  4 / 5  {R2 / (R1 + R2)} Hence, Rf = 5 / 4  Af  (R1 // R2) / {R2 / (R1 + R2)} ......(1) In the Bode plot, the total gain should be lower than 1 (0 dB) at the switching frequency. The total gain at Fsw (= Asw) depends on the flat-band gain, so Af should be expressed as follows; Af = Asw  2   Fsw  Co  RCS / Nt ……(2) Here, Nt = Idh / Ics = 13700 In the typical way, the value chosen for Asw is in the range from 0.1 to 0.5, since this produces a stable control loop. The transient response will be faster if a large Asw is adopted, but the system might be unstable. We choose 0.2 for Asw in the example below. Af = 0.2  2   500 kHz  600 F  820  / 13700 = 22.564 Rf = 5 / 4  22.564  0.6 k / (2 / 3) = 25.385 k Therefore, we select a value of 24 k for Rf. 2. Selecting the Cf value to determine the frequency of the zero. The frequency of the zero established by Cf and Rf is about ten times the frequency of the pole for the power stage and modulator. We must start with the dc gain of the power stage and modulator. Nt/RCS × L × Vin × Fsw A0 = ……(3) 2 − 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) } SQRT {Vin Here VCS0 is the peak ac voltage on CS pin when the load current is zero, thus VCS0 = 0.5  RCS  (Vin – Vout)  Vout / (L  Vin  Fsw) / 13700 ……(4) = 0.5  820   (5 V – 1.5 V)  1.5 V / (470 nH  5 V  500 kHz) / 13700 = 0.134 V R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 12 of 25 R2J20751NP equation (3), A0 = Nt/RCS × L × Vin × Fsw SQRT {Vin2 − 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) } ……(3) Preliminary = 13700 / 820 Ω × 470 nH × 5 V × 500 kHz SQRT {5 V2 − 8 × 470 nH × 5 V × 500 kHz × (0.134 V × 13700 / 820 Ω) } = 19.63 SQRT {3.955} = 9.871 The frequency of the pole established by the power stage and modulator is F0 = Nt / (2   Co  RCS  A0) ......(5) Thus, F0 = 13700 / (2   600 F  820   9.871) = 448.967 Hz Thus, Fzero = 10  F0 = 4.489 kHz Cf = (2   Fzero  Rf)–1 = (2   4.489 kHz  24 k)–1 = 1477 pF Therefore, we select 1500 pF for Cf. Basically, the transient response is faster when Cf is smaller, but too small a value will make the system-loop unstable. Gain (dB) −20 dB/dec Converter open loop −40 dB/dec Compensated error amp. BW/Af A0 Af −20 dB/dec Error amp. unity gain frequency BW F0 Power and modulator Fzero Asw Fsw Freq. (Hz) Figure 4 R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 13 of 25 R2J20751NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB  (R1 + R2) / R2 ......(6) Here, the typical FB voltage is 0.6 V. Preliminary R VCIN Vout REFIN CT FB R1 R2 The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has variation of 1% and resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is extended to produce equation (7). Vout = R1 × K1 + R2 × K2 R2 × K2 R1 × K1 / K2 + R2 R2 × FB × FB ……(7) = Here, K1 and K2 are coefficients, Both are 1.00 in the ideal case. By equation (6), R1 is chosen as; R1 = Vout (typical) VFB (typical) − 1 × R2 ……(8) Substituting the expression for R1 into equation (7) yields the following Vout (typical) VFB (typical) K1 +1 K2 Vout = VFB × −1 × ……(9) Therefore, variation in Vout is expressed as Vout Vout (typical) VFB Vout (typical) Vout (typical) VFB (typical) K1 +1 K2 = × −1 × − 1 × 100 (%) ……(10) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 14 of 25 R2J20751NP The accuracy of Vout can be estimated by using equation (10). Preliminary For Example, if Vout (typical) = 1.5 V, resistance variation is 1% (i.e K1, K2 = 1.01 and 0.99), and VFB = 588 mV to 612 mV. Vout Vout (typical) VFB Vout (typical) Vout (typical) VFB (typical) K1 +1 K2 = × −1 × − 1 × 100 (%) ……(10) = 612 mV 1.5 V × 1.5 V 600 mV −1 × 1.01 +1 0.99 − 1 × 100 (%) = 3.23% or = 588 mV 1.5 V × 1.5 V 600 mV −1 × 0.99 +1 1.01 − 1 × 100 (%) = −3.16% Therefore, the output accuracy will be 3.2% under the above conditions. Figure 5 shows the relationship between the accuracy of the resistance and the accuracy of the output voltage. The resistor value must have an accuracy of 0.5% if the variation in output voltage from the system is to be kept within three percent across the voltage range from 0.6 V to 3.3 V. 4 3 Vout accuracy (%) 2 1 0 −1 −2 −3 −4 0.5 1.0 1.5 2.0 Vout (typical) 2.5 3.0 3.5 R = ±0.5% R = ±1% Figure 5 Vout Accuracy vs. Vout Set Voltage R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 15 of 25 R2J20751NP Preliminary Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) 60 ns (typ.) TLD 50 ns (typ.) EO (EO-Vbe) 4/5 (Internal signal) CS 0V VIN SW 0V The high-side MOS FET is turned off by the max. duty signal. Note: Propagation delay is ignored. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 16 of 25 R2J20751NP Oscillator and Pulse Generator 1. Standalone operation or working as Master Chip in parallel configuration with other chips. 1.8 V CT 1.0 V 5V CLK (IN) 0V Preliminary Max. Duty (Internal signal) 60 ns (typ.) RES (Internal signal) Note: Propagation delay is ignored. Switching frequency for CT Fsw = 160 μA 2 × (CT(F) + 20 pF) × 0.8 V × N (Hz) Frequency set range: 200 kHz to 1 MHz R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 17 of 25 R2J20751NP Hiccup Operation when the Over-Current Limit (OCL) is Reached Preliminary TRK-SS Detected OCL 1.5 V CS 0V Skipped 1024 pulses Skipped 1024 pulses Normal operation Note: Propagation delay is ignored. Detected OVP 125% FB 90% Top MOSFET signal Bottom MOSFET signal PGOOD *2 ON/OFF (UVL) Output current signal Note: 2. Connected 51 kΩ resistor between PGOOD and VCIN. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 18 of 25 R2J20751NP Preliminary Applications Multi Phase Operation Tie each CT, CLK and Share pin. Connect OUT pin to IN pin of next switching device. REFIN/POS EO/CO FB CLK Share CT IN VOUT Device 1 (Master) SW OUT VCIN REFIN/POS EO/CO FB CLK Share CT OUT IN Device 2 (Slave1) SW VOUT LOAD REFIN/POS EO/CO FB CLK Share CT IN Device 3 (Slave2) SW OUT R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 19 of 25 R2J20751NP Multi Phase Operation Waveforms (3 Phase) Fclk CLK Phase1 switching Device 1 (Master) OUT1 (IN2) The trigger signal is fed back with the same timing as CLK. Preliminary Device 2 (Slave1) OUT2 (IN3) Device 3 (Slave2) OUT3 (IN1) For the three-phase system, only the master device operates while the voltages on the POS pins of slave devices 1 and 2 are higher than the voltage on the Share pins. In single-phase operation, although the switching trigger signal is input on the IN pin of both slaves, both slaves 1 and 2 are disabled so they output the signal on the OUT pin with the same timing as the clock signal (CLK), feeding it back to the IN1 pin of the master. 2Fclk CLK Phase1 switching Device 1 (Master) OUT1 (IN2) Phase2 switching Device 2 (Slave1) OUT2 (IN3) Trigger signal is output after 1 cycle of CLK. Device 3 (Slave2) OUT3 (IN1) When only slave 1 is enabled, that is, the voltage on the POS pin is higher than the voltage on the Share pins only for slave 2, operation becomes two phase. The frequency is double that in single-phase mode because slave 1 supplies current at the frequency of CLK that is applied to the CT pin with the same timing as the master. Slave 1 outputs a switching trigger signal one clock cycle after it has received a switching trigger signal. Accordingly, the phase of the timing for turning slave 1 on lags 90? behind that for the master. CLK Phase1 switching Phase2 switching Phase3 switching Device 1 (Master) OUT1 (IN2) Device 2 (Slave1) OUT2 (IN3) Device 3 (Slave2) OUT3 (IN1) When slaves 1 and 2 are both enabled, the frequency is triple that in single-phase mode because slaves 1 and 2 supply current at the frequency of CLK that is applied to the CT pin with the same timing as the master. Switching operation is with the timing of the CLK signal, so the phase angle becomes 120? in three-phase operation and the phase shift is automatic. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 20 of 25 R2J20751NP Phase Control Preliminary The device incorporates a comparator for control of the phase number. Pulling the voltage on the FB pin up to that on VCIN exchanges the phase control comparator for the error amplifier, and the device operates as a slave. In this case, the output of the comparator (CO) is exchanged for the output of the error amplifier (EO), and the positive input (REFIN) of the error amplifier is exchanged for the positive input (POS) for the comparator. Furthermore, the inverse input for the comparator is internally connected to the Share pin. The level where the phase number is switched is set by an external resistor. Design example; Specification: L = 470 nH, Fsw = 500 kHz, Vin = 5 V, Vout = 1.5 V, RCS = 820 , Phase switching level is Iout = 10 A, hysteresis = 3.48 A 1. Deriving the voltage on the Share pins to return to single-phase operation with Iout = 6.52 A (3.48 A of hysteresis) from two-phase operation with Iout = 10 A. The peak of the output ripple current is: Ipp (10 A) = (VIN – Vout) / L  Vout / VIN / Fsw / 2 + Iout (10 A) = 12.23 A When Iout = 6.52 A in two-phase mode, current from each device is 3.26 A. Thus, Ipp (3.26 A) = (VIN – Vout) / L  Vout / VIN / Fsw / 2 + Iout (3.26 A) = 5.49 A The ratio between currents for the sense MOS FET and main MOS FET is 1:13700, so a bias current of 300 A flows through the CS pin. Thus, voltages on the CS pin are: Vcs (10 A) = (Ipp (10 A) / 13700 + 300 A)  Rcs = 978 mV and Vcs (3.26 A) = (Ipp (3.26 A) / 13700 + 300 A)  Rcs = 575 mV. The non-inverted input terminal of the internal current sense comparator has an offset voltage of 0.2 V, and 40-k and 10-k resistors are connected to the inverted input terminal. Therefore, the Share voltages are: Vshare (10 A) = (Vcs (10 A) + 0.2 V)  5 / 4 = 1.473 V and ......(11) Vshare (3.26 A) = (Vcs (3.26 A) + 0.2 V)  5 / 4 = 0.969 V. ......(12) VCIN R3 R5 EO/CO EO/CO Current Sense comparator 10k Sense current R4 REFIN/POS Phase control comparator Share Slave chip Share 0.2V 40k 35k Master chip RCS Figure 6 Phase Switching Control R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 21 of 25 R2J20751NP Vpos Preliminary VTHR VTHF Vshare 2. Selecting the external resistors When the output of phase control comparator becomes low, switching operation of the slave device starts and operation becomes two phase. According to the results of (11) and (12), VTHR and VTHF are 1.473 V and 0.969 V. These become the voltages on the POS pins (comparator non-inverted input pin). VTHR is the start-up level for the slave device and VTHF is the shut-down level for the slave device. We set the output current of CO at around 100 A when the voltage on Share is 1.379 V. In this case, R5 is: R5 = (VCIN – 1.379) / 100 A = 35.27 k The formulae that express R3 and R4 are: R3 = R4  R5 / (R4 + R5)  (VCIN – VTHF) / VTHF = 18.34 k and R4 = R5  (VTHR – VTHF) / (VCIN – VTHR) = 5.04 k. With E24-series resistors, R3 = 18 k, R4 = 5.1 k, and R5 = 36 k. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 22 of 25 R2J20751NP Preliminary Main Characteristics VH vs. Temperature 4.7 4.6 4.5 4.4 4.2 4.1 4.0 3.9 VL vs. Temperature VH (V) 4.3 4.2 4.1 4.0 3.9 –50 –25 0 25 50 75 100 125 150 VL (V) 3.8 3.7 3.6 3.5 3.4 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Viref vs. Temperature 1.90 1.88 1.86 610 1.84 605 600 595 590 1.74 1.72 1.70 –50 –25 0 25 50 75 100 125 150 585 580 –50 –25 620 615 Vfb vs. Temperature 1.80 1.78 1.76 Vfb (mV) Viref (V) 1.82 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 23 of 25 R2J20751NP Fsync vs. Temperature 440 430 420 410 2.70 2.65 2.60 Von vs. Temperature Preliminary Fct (kHz) 400 390 380 370 360 350 –50 –25 0 25 50 75 100 125 150 Von (V) 2.55 2.50 2.45 2.40 2.35 2.30 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 10000 Fsw vs. CT 1.25 1.20 1.15 1.10 1.05 –50 –25 0 25 50 75 100 125 150 Fsw (kHz) Voff (V) 1.30 1000 100 10 100 CT (pF) 1000 Temperature (°C) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Page 24 of 25 R2J20751NP Preliminary Package Dimensions JEITA Package Code — RENESAS Code PVQN0040KD-A Previous Code — MASS[Typ.] 0.07 HD D HD/2 39 E /2 HE E 1.95 HE/2 D /2 B Eject pin 1pin 40 2.250 4-C0.50 40 1pin 2.250 B 2.250 1.95 (C0.3) A 0.500 1.95 1 pin indication 2.100 2.250 2.250 0.950 Reference Dimension in Millimeters Symbol ZE 4(0 .1 ) 1.95 X4 t S AB Eject pin e y1 S ZD X4 f S AB b L1 A A2 0.69 c2 0.375 0.750 x S AB 20° 20° S Lp yS Min Nom Max D — 6.00 — — 6.00 — E — A2 — — f — — 0.20 A — — 0.95 A1 0.005 — — b 0.17 0.22 0.27 e — 0.50 — Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 — — 0.20 t HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — — 0.75 — ZE — 0.10 — L1 Ordering Information Part Name R2J20751NP#G0 Quantity 2500 pcs Shipping Container Taping Reel R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 A1 Page 25 of 25 Notice 1. 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