R5F213NATNBX

Datasheet R8C/3NT Group RENESAS MCU R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 1. 1.1 Overview Features The R8C/3NT Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. A sensor control unit is also integrated, enabling detection of the floating capacitance of the electrostatic capacitive touch electrode. The R8C/3NT Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function. 1.1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 1 of 55 R8C/3NT Group 1. Overview 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/3NT Group. Table 1.1 Item CPU Specifications for R8C/3NT Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.3 Product List for R8C/3NT Group • Power-on reset • Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 43, selectable pull-up resistor • High current drive ports: 43 • 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit (32 kHz), High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Real-time clock (timer RE) • Interrupt Vectors: 69 • External: 9 sources (INT × 5, key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable • 1 channel • Activation sources: 32 • Transfer modes: 2 (normal mode, repeat mode) 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 8 bits × 1 Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Interrupts Watchdog Timer DTC (Data Transfer Controller) Timer Timer RA Timer RB Timer RC Timer RE R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 2 of 55 R8C/3NT Group 1. Overview Table 1.2 Item Serial Interface Specifications for R8C/3NT Group (2) Specification Clock synchronous serial I/O/UART × 2 channel Clock synchronous serial I/O, UART 4 circuits (shared with I2C bus) 4 circuits (shared with SSU) System CH × 3, electrostatic capacitive touch detection × 5 10-bit resolution × 12 channels, includes sample and hold function, with sweep mode • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function • Background operation (BGO) function (data flash) f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V) Typ. 7.0 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 4.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) Typ. 2.0 µA (VCC = 3.0 V, stop mode) −20 to 85°C (N version) 48-pin WPP Package code: SWBG0048LA-A Function UART0, UART1 UART2 Synchronous Serial Communication Unit (SSU) I2C bus Sensor Control Unit A/D Converter Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 3 of 55 R8C/3NT Group 1. Overview 1.2 Product List Table 1.3 lists Product List for R8C/3NT Group. Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/3NT Group. Table 1.3 Product List for R8C/3NT Group ROM Capacity Program ROM Data flash 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 RAM Capacity 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Current of Jan 2011 Package Type SWBG0048LA-A SWBG0048LA-A SWBG0048LA-A SWBG0048LA-A Remarks N version Part No. R5F213N7TNBX R5F213N8TNBX R5F213NATNBX R5F213NCTNBX Part No. R 5 F 21 3N C T N BX Package type: BX: WPP (Resin-coated bottom) Classification N: Operating ambient temperature −20°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/3NT Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/3NT Group R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 4 of 55 R8C/3NT Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a Block Diagram. 8 8 8 6 5 1 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P6 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RE (8 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 4) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Sensor control unit Watchdog timer (14 bits) A/D converter (10 bits × 12 channels) Low-speed on-chip oscillator for watchdog timer Voltage detection circuit DTC R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (1) RAM (2) Multiplier Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.2 Block Diagram R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 5 of 55 R8C/3NT Group 1. Overview 1.4 Pin Assignment Figure 1.3 shows Pin Assignment. Table 1.4 outlines the Pin Name Information by Pin Number. TOP VIEW (Top View of Board) *Solder Balls on Bottom Side A2 A3 A4 A5 A6 A7 WPP Solder Ball Side A B C D E F G A7 A6 A5 A4 A3 A2 B1 B2 B3 B4 B5 B6 B7 B7 B6 B5 B4 B3 B2 B1 C1 C2 C3 C4 C5 C6 C7 C7 C6 C5 C4 C3 C2 C1 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 E1 E2 E3 E4 E5 E6 E7 E7 E6 E5 E4 E3 E2 E1 F1 F2 F3 F4 F5 F6 F7 F7 F6 F5 F4 F3 F2 F1 G1 G2 G3 G4 G5 G6 G7 G7 G6 G5 G4 G3 G2 G1 1 Figure 1.3 Pin Number 1 2 3 4 A 5 6 7 1 2 3 B 4 5 6 7 1 2 3 C 4 5 6 7 1 D 2 3 4 2 3 4 5 6 7 7 6 5 4 3 2 1 Pin Assignment Pin Name — VREF/P4_2 P4_4(/XCOUT) VSS/AVSS P4_6/XIN VCC/AVCC P3_5(/TRCIOD/CLK2)/SSCK_0/SCL_0 P6_3(/TXD1)/SSCK_3/SCL_3 P6_1/SCS_3 P3_0(/TRAO/INT3) P4_3(/XCIN) P4_7/XOUT P3_7(/RXD2/TXD2)/TRAO/SSO_0/SDA_0 P3_4(/TRCIOC/RXD2/TXD2)/SSI_0 P0_0/AN7(/TRCIOA/TRCTRG)/CHxC P6_4(/RXD1)/SSO_3/SDA_3 P6_2(/CLK1)/SSI_3 MODE RESET P3_3/INT3(/TRCCLK/CTS2/RTS2)/SCS_0 P2_7/SCS_2 P0_2/AN5/RXD1(/TRCIOA/TRCTRG)/CHxA P0_1/AN6(/TXD1/TRCIOA/TRCTRG)/CHxB P6_0(/TREO/INT2) P1_4(/TXD0/TRCCLK) G F Pin Number 5 D 6 7 1 2 3 E 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Pin Name P2_6 P2_5/SSO_1/SDA_1 P2_4/SSCK_1/SCL_1 P0_3/AN4(/CLK1/TRCIOB)/CH0 P0_4/AN3/TREO(/TRCIOB)/CH1 P1_0/KI0/AN8(/TRCIOD) P1_5(/RXD0/TRAIO/INT1) P2_1(/TRCIOC) P2_3/SSI_1 P2_2(/TRCIOD)/SCS_1 P0_5/AN2(/TRCIOB)/CH2 P0_6/AN1(/TRCIOD)/CH3 P1_2/KI2/AN10(/TRCIOB) P1_7/INT1(/TRAIO) P6_5/INT4(/CLK2/CLK1/TRCIOB)/SSI_2 P6_7(/INT3/TRCIOD)/SSO_2/SDA_2 P2_0(/INT1/TRCIOB) P0_7/AN0(/TRCIOC)/CH4 P1_1/KI1/AN9(/TRCIOA/TRCTRG) P1_3/KI3/AN11/TRBO(/TRCIOC) P1_6(/CLK0)/INT2 P4_5/INT0(/RXD2)/ADTRG P6_6/INT2(/TXD2/TRCIOC)/SSCK_2/SCL_2 P3_1(/TRBO) R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 6 of 55 R8C/3NT Group 1. Overview Table 1.4 Pin Number 48-pin WPP Pin Assignment 1 2 3 4 5 6 7 1 2 3 B 4 5 6 7 1 2 3 4 5 6 7 1 2 3 D 4 5 6 7 1 2 3 E 4 5 6 7 1 2 3 F 4 5 6 7 1 2 3 G 4 5 6 7 Pin Name Information by Pin Number Control Pin Port Interrupt I/O Pin Functions for Peripheral Modules Serial Timer SSU I2C bus Interface A/D SCU A (XCOUT) VSS/AVSS XIN VCC/AVCC P4_2 P4_4 P4_6 P3_5 P6_3 P6_1 P3_0 P4_3 P4_7 P3_7 P3_4 P0_0 P6_4 P6_2 (INT3) (TRCIOD) (CLK2) (TXD1) SSCK_0 SSCK_3 SCS_3 (TRAO) SCL_0 SCL_3 VREF (XCIN) XOUT TRAO (TRCIOC) (TRCIOA/TRCTRG) (RXD2/TXD2) (RXD2/TXD2) (RXD1) (CLK1) SSO_0 SSI_0 SSO_3 SSI_3 SDA_0 AN7 SDA_3 CHxC C MODE RESET P3_3 P2_7 P0_2 P0_1 P6_0 P1_4 P2_6 P2_5 P2_4 P0_3 P0_4 P1_0 P1_5 P2_1 P2_3 P2_2 P0_5 P0_6 P1_2 P1_7 P6_5 P6_7 P2_0 P0_7 P1_1 P1_3 P1_6 P4_5 P6_6 P3_1 KI2 INT1 INT4 (INT3) (INT1) KI1 KI3 (INT2) INT0 INT2 (TRCIOC) (TRBO) (INT2) INT3 (TRCCLK) (TRCIOA/TRCTRG) (TRCIOA/TRCTRG) (TREO) (TRCCLK) (CTS2/RTS2) RXD1 (TXD1) (TXD0) SSO_1 SSCK_1 (TRCIOB) TREO(/TRCIOB) KI0 (INT1) (TRCIOD) (TRAIO) (TRCIOC) (TRCIOD) (TRCIOB) (TRCIOD) (TRCIOB) (TRAIO) (TRCIOB) (TRCIOD) (TRCIOB) (TRCIOC) (TRCIOA/TRCTRG) TRBO(/TRCIOC) (CLK0) (RXD2) (TXD2) SSCK_2 SCL_2 ADTRG (CLK1/CLK2) SSI_2 SSO_2 SDA_2 AN0 AN9 AN11 CH4 (RXD0) SSI_1 SCS_1 AN2 AN1 AN10 CH2 CH3 (CLK1) SDA_1 SCL_1 AN4 AN3 AN8 CH0 CH1 SCS_0 SCS_2 AN5 AN6 CHxA CHxB Note: 1. Can be assigned to the pin in parentheses by a program. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 7 of 55 R8C/3NT Group 1. Overview 1.5 Pin Functions Tables 1.5 and 1.6 list Pin Functions. Table 1.5 Pin Functions (1) I/O Type Description — Apply 1.8 to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. — Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. I Input “L” on this pin resets the MCU. I I I/O Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. (1) To use an external clock, input it to the XOUT pin and leave the XIN pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins. (1) To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. Key input interrupt input pins. Timer RA I/O pin. Timer RA output pin. Timer RB output pin. External clock input pin. External trigger input pin. Timer RC I/O pins. Divided clock output pin. Transfer clock I/O pins. Serial data input pins. Serial data output pins. Transmission control input pin. Reception control output pin. Item Pin Name Power supply input VCC, VSS Analog power supply input Reset input MODE XIN clock input XIN clock output AVCC, AVSS RESET MODE XIN XOUT XCIN clock input XCIN clock output XCIN XCOUT I O INT interrupt input Key input interrupt Timer RA Timer RB Timer RC INT0 to INT4 KI0 to KI3 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD TREO CLK0, CLK1, CLK2 RXD0, RXD1, RXD2 TXD0, TXD1, TXD2 CTS2 RTS2 I I I/O O O I I I/O O I/O I O I O Timer RE Serial interface I: Input O: Output I/O: Input and output Note: 1. Refer to the oscillator manufacturer for oscillation characteristics. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 8 of 55 R8C/3NT Group 1. Overview Table 1.6 Item SSU Pin Functions (2) Pin Name SSI_i SCS_i SSCK_i SSO_i SCL_i SDA_i VREF AN0 to AN11 ADTRG CHxA, CHxB, CHxC CH0 to CH4 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6_0 to P6_7 P4_2 I/O Type Description I/O Data I/O pin. I/O Chip-select signal I/O pin. I/O I/O I/O I/O I I I I/O I I/O Clock I/O pin. Data I/O pin. Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter. Analog input pins to A/D converter. AD external trigger input pin. Control pins for electrostatic capacitive touch detection Electrostatic capacitive touch detection pins CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. I2C bus Reference voltage input A/D converter Sensor control unit I/O port Input port i = 0 to 3 I: Input I Input-only port. O: Output I/O: Input and output R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 9 of 55 R8C/3NT Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1) R2 R3 A0 A1 FB b19 b15 b0 Address registers (1) Frame base register (1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit Note: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 10 of 55 R8C/3NT Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the starting address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 11 of 55 R8C/3NT Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 12 of 55 R8C/3NT Group 3. Memory 3. 3.1 Memory R8C/3NT Group Figure 3.1 is a Memory Map of R8C/3NT Group. The R8C/3NT Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 64-Kbyte internal ROM area is allocated addresses 04000h to 13FFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h SFR (Refer to 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXXh 02C00h 0FFD8h Reserved area SFR (2) (Refer to 4. Special Function Registers (SFRs)) 0FFDCh 02FFFh 03000h Internal ROM (data flash) (1) 03FFFh 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor Address break (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh. 3. The blank areas are reserved and cannot be accessed by users. Part Number R5F213N7TNBX R5F213N8TNBX R5F213NATNBX R5F213NCTNBX Internal ROM Size 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 04000h 04000h 04000h 04000h Address ZZZZZh – 13FFFh 1BFFFh 23FFFh Size Internal RAM Address 0XXXXh 013FFh 01BFFh 023FFh 02BFFh 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Figure 3.1 Memory Map of R8C/3NT Group R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 13 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.14 list the special function registers. Table 4.15 lists the ID Code Areas and Option Function Select Area. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h SFR Information (1) (1) Register Symbol After Reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC 00h 00h 00101000b 00100000b 00h 00h 00h 0XXXXXXXb (2) 00000100b XXh XXh 00111111b High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping Count Source Protection Mode Register CSPR 00h 10000000b (3) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 5 High-Speed On-Chip Oscillator Control Register 6 FRA0 FRA1 FRA2 OCVREFCR CPSRF FRA4 FRA5 FRA6 00h When shipping 00h 00h 00h When shipping When shipping When shipping High-Speed On-Chip Oscillator Control Register 3 Voltage Monitor Circuit Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2 FRA3 CMPA VCAC VCA1 VCA2 When shipping 00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register Voltage Monitor 1 Circuit Control Register VD1LS VW0C VW1C X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 14 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.2 Address 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh SFR Information (2) (1) Register Voltage Monitor 2 Circuit Control Register Symbol VW2C After Reset 10000010b Flash Memory Ready Interrupt Control Register FMRDYIC XXXXX000b INT4 Interrupt Control Register Timer RC Interrupt Control Register INT4IC TRCIC XX00X000b XXXXX000b Timer RE Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU0 Interrupt Control Register/IIC0 bus Interrupt Control Register (2) UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register TREIC S2TIC S2RIC KUPIC ADIC SSU0IC/IIC0IC S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b INT0 Interrupt Control Register INT0IC XX00X000b Sensor Control Unit Interrupt Control Register SCUIC XXXXX000b Voltage Monitor 1 Interrupt Control Register Voltage Monitor 2 Interrupt Control Register VCMP1IC VCMP2IC XXXXX000b XXXXX000b SSU1 Interrupt Control Register/IIC1 bus Interrupt Control Register (2) SSU2 Interrupt Control Register/IIC2 bus Interrupt Control Register (2) SSU3 Interrupt Control Register/IIC3 bus Interrupt Control Register (2) SSU1IC/IIC1IC SSU2IC/IIC2IC SSU3IC/IIC3IC XXXXX000b XXXXX000b XXXXX000b X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by IIC0SEL, IIC1SEL, IIC2SEL, and IIC3SEL bits in the SSUIICSR register. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 15 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh SFR Information (3) (1) Register DTC Activation Control Register Symbol DTCTL After Reset 00h DTC Activation Enable Register 0 DTC Activation Enable Register 1 DTC Activation Enable Register 2 DTC Activation Enable Register 3 DTC Activation Enable Register 4 DTC Activation Enable Register 5 DTC Activation Enable Register 6 DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 DTCEN5 DTCEN6 00h 00h 00h 00h 00h 00h 00h UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register UART2 Digital Filter Function Select Register U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 16 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh SFR Information (4) (1) Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Symbol After Reset XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb A/D Mode Register A/D Input Select Register A/D Control Register 0 A/D Control Register 1 ADMOD ADINSEL ADCON0 ADCON1 00h 11000000b 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6 XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h XXh 00h X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 17 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh SFR Information (5) (1) Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA After Reset 00h 00h 00h FFh FFh Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register Timer RC Trigger Control Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR 00h 00h 00h 00h 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 18 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.6 Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh SFR Information (6) (1) Register Symbol After Reset UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1MR U1BRG U1TB U1C0 U1C1 U1RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 19 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.7 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh SFR Information (7) (1) Register Timer RA Pin Select Register Timer RB/RC Pin Select Register Timer RC Pin Select Register 0 Timer RC Pin Select Register 1 Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 After Reset 00h 00h 00h 00h Timer Pin Select Register UART0 Pin Select Register UART1 Pin Select Register UART2 Pin Select Register 0 UART2 Pin Select Register 1 SSU/IIC Pin Select Register Low-Voltage Signal Mode Control Register 1 INT Interrupt Input Pin Select Register I/O Function Pin Select Register Low-Voltage Signal Mode Control Register I/O Function Pin Select Register 1 I/O Function Pin Select Register 2 SS0 Bit Counter Register SS0 Transmit Data Register L / IIC_0 bus Transmit Data Register (2) SS0 Transmit Data Register H (2) SS0 Receive Data Register L / IIC_0 bus Receive Data Register (2) SS0 Receive Data Register H (2) SS0 Control Register H / IIC_0 bus Control Register 1 (2) SS0 Control Register L / IIC_0 bus Control Register 2 (2) SS0 Mode Register / IIC_0 bus Mode Register (2) SS0 Enable Register / IIC_0 bus Interrupt Enable Register (2) SS0 Status Register / IIC_0 bus Status Register (2) SS0 Mode Register 2 / Slave Address Register (2) TIMSR U0SR U1SR U2SR0 U2SR1 SSUIICSR LVMR1 INTSR PINSR LVMR PINSR1 PINSR2 SS0BR SS0TDR / IC0DRT SS0TDRH SS0RDR / IC0DRR SS0RDRH SS0CRH / IC0CR1 SS0CRL / IC0CR2 SS0MR / IC0MR SS0ER / IC0IER SS0SR / IC0SR SS0MR2 / SAR 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h F8h FFh FFh FFh FFh 00h 01111101b 00010000b / 00011000b 00h 00h / 0000X000b 00h Flash Memory Status Register Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 FST FMR0 FMR1 FMR2 10000X00b 00h 00h 00h X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by the IIC0SEL bit in the SSUIICSR register. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 20 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.8 Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh SFR Information (8) (1) Register Address Match Interrupt Register 0 Symbol RMAD0 After Reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb 00h Address Match Interrupt Enable Register 0 Address Match Interrupt Register 1 AIER0 RMAD1 Address Match Interrupt Enable Register 1 AIER1 Pull-Up Control Register 0 Pull-Up Control Register 1 PUR0 PUR1 00h 00h Port P1 Drive Capacity Control Register Port P2 Drive Capacity Control Register Drive Capacity Control Register 0 Drive Capacity Control Register 1 Input Threshold Control Register 0 Input Threshold Control Register 1 P1DRR P2DRR DRR0 DRR1 VLT0 VLT1 00h 00h 00h 00h 00h 00h External Input Enable Register 0 External Input Enable Register 1 INT Input Filter Select Register 0 INT Input Filter Select Register 1 Key Input Enable Register 0 INTEN INTEN1 INTF INTF1 KIEN 00h 00h 00h 00h 00h X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 21 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.9 Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh SFR Information (9) (1) Register Symbol After Reset SS1 Bit Counter Register SS1 Transmit Data Register L / IIC_1 bus Transmit Data Register (2) SS1 Transmit Data Register H (2) SS1 Receive Data Register L / IIC_1 bus Receive Data Register (2) SS1 Receive Data Register H (2) SS1 Control Register H / IIC_1 bus Control Register 1 (2) SS1 Control Register L / IIC_1 bus Control Register 2 (2) SS1 Mode Register / IIC1 bus Mode Register (2) SS1 Enable Register / IIC_1 bus Interrupt Enable Register (2) SS1 Status Register / IIC_1 bus Status Register (2) SS1 Mode Register 2 / Slave Address Register (2) SS1BR SS1TDR/IC1DRT SS1TDRH SS1RDR/IC1DRR SS1RDRH SS1CRH/IC1CR1 SS1CRL/IC1CR2 SS1MR/IC1MR SS1ER/IC1IER SS1SR/IC1SR SS1MR2/SAR1 F8h FFh FFh FFh FFh 00h 01111101b 00010000b/00011000b 00h 00h/0000X000b 00h SS2 Bit Counter Register SS2 Transmit Data Register L / IIC_2 bus Transmit Data Register (3) SS2 Transmit Data Register H (3) SS2 Receive Data Register L / IIC_2 bus Receive Data Register (3) SS2 Receive Data Register H (3) SS2 Control Register H / IIC_2 bus Control Register 1 (3) SS2 Control Register L / IIC_2 bus Control Register 2 (3) SS2 Mode Register / IIC_2 bus Mode Register (3) SS2 Enable Register / IIC_2 bus Interrupt Enable Register (3) SS2 Status Register / IIC_2 bus Status Register (3) SS2 Mode Register 2 / Slave Address Register (3) SS2BR SS2TDR/IC2DRT SS2TDRH SS2RDR/IC2DRR SS2RDRH SS2CRH/IC2CR1 SS2CRL/IC2CR2 SS2MR/IC2MR SS2ER/IC2IER SS2SR/IC2SR SS2MR2/SAR2 F8h FFh FFh FFh FFh 00h 01111101b 00010000b/00011000b 00h 00h/0000X000b 00h X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by the IIC1SEL bit in the SSUIICSR register. 3. Selectable by the IIC2SEL bit in the SSUIICSR register. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 22 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.10 Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh SFR Information (10) (1) Register Symbol After Reset SS3 Bit Counter Register SS3 Transmit Data Register L / IIC_3 bus Transmit Data Register (2) SS3 Transmit Data Register H (2) SS3 Receive Data Register L / IIC_3 bus Receive Data Register (2) SS3 Receive Data Register H (2) SS3 Control Register H / IIC_3 bus Control Register 1 (2) SS3 Control Register L / IIC_3 bus Control Register 2 (2) SS3 Mode Register / IIC_3 bus Mode Register (2) SS3 Enable Register / IIC_3 bus Interrupt Enable Register (2) SS3 Status Register / IIC_3 bus Status Register (2) SS3 Mode Register 2 / Slave Address Register (2) SS3BR SS3TDR/IC3DRT SS3TDRH SS3RDR/IC3DRR SS3RDRH SS3CRH/IC3CR1 SS3CRL/IC3CR2 SS3MR/IC3MR SS3ER/IC3IER SS3SR/IC3SR SS3MR2/SAR3 F8h FFh FFh FFh FFh 00h 01111101b 00010000b/00011000b 00h 00h/0000X000b 00h X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by the IIC3SEL bit in the SSUIICSR register. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 23 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.11 Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh : 2C00h 2C01h 2C02h 2C03h 2C04h 2C05h 2C06h 2C07h 2C08h 2C09h 2C0Ah : : 2C3Ah 2C3Bh 2C3Ch 2C3Dh 2C3Eh 2C3Fh 2C40h 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh SFR Information (9) (1) Register SCU Control Register 0 SCU Mode Register SCU Timing Control Register 0 SCU Timing Control Register 1 SCU Timing Control Register 2 SCU Timing Control Register 3 SCU Channel Control Register SCU Channel Control Counter SCU Flag Register SCU Status Counter SCU Secondary Counter Set Register SCU Secondary Counter Symbol SCUCR0 SCUMR SCTCR0 SCTCR1 SCTCR2 SCTCR3 SCHCR SCUCHC SCUFR SCUSTC SCSCSR SCUSCC After Reset 00h 00h 00000011b 00000001b 00010000b 00h 00h 00h 00h 00h 00000111b 00000111b SCU Destination Address Register SCU Data Buffer Register SCU Primary Counter SCUDAR SCUDBR SCUPRC 00h 00001100b 00h 00h 00h 00h Touch Sensor Input Enable Register 0 TSIER0 00h DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area XXh XXh XXh XXh XXh DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Control Data 0 DTCD0 DTC Control Data 1 DTCD1 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 24 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.12 Address 2C50h 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh 2C70h 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh SFR Information (10) (1) Register DTC Control Data 2 Symbol DTCD2 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh DTC Control Data 3 DTCD3 DTC Control Data 4 DTCD4 DTC Control Data 5 DTCD5 DTC Control Data 6 DTCD6 DTC Control Data 7 DTCD7 DTC Control Data 8 DTCD8 DTC Control Data 9 DTCD9 X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 25 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.13 Address 2C90h 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh 2CB0h 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh SFR Information (11) (1) Register DTC Control Data 10 Symbol DTCD10 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh DTC Control Data 11 DTCD11 DTC Control Data 12 DTCD12 DTC Control Data 13 DTCD13 DTC Control Data 14 DTCD14 DTC Control Data 15 DTCD15 DTC Control Data 16 DTCD16 DTC Control Data 17 DTCD17 X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 26 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.14 Address 2CD0h 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh SFR Information (12) (1) Register DTC Control Data 18 Symbol DTCD18 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh DTC Control Data 19 DTCD19 DTC Control Data 20 DTCD20 DTC Control Data 21 DTCD21 DTC Control Data 22 DTCD22 DTC Control Data 23 DTCD23 X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 27 of 55 R8C/3NT Group 4. Special Function Registers (SFRs) Table 4.15 Address : FFDBh : FFDFh : FFE3h : FFEBh : FFEFh : FFF3h : FFF7h : FFFBh : FFFFh ID Code Areas and Option Function Select Area Area Name Option Function Select Register 2 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Option Function Select Register OFS OFS2 Symbol After Reset (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) Notes: 1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select area is set to FFh. When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user. When factory-programming products are shipped, the value of the option function select area is the value programmed by the user. 2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh. When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user. When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 28 of 55 R8C/3NT Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Symbol VCC/AVCC VI VO Pd Topr Tstg Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Condition Rated Value −0.3 to 6.5 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 500 −20 to 85 (N version) −65 to 150 Unit V V V mW °C °C −20°C ≤ Topr ≤ 85°C R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 29 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.2 Symbol Recommended Operating Conditions (1) Parameter Conditions Min. 1.8 — 0.8 VCC 0.5 VCC 0.55 VCC 0.65 VCC 0.65 VCC 0.7 VCC 0.8 VCC 0.85 VCC 0.85 VCC 0.85 VCC 1.2 0 0 0 0 0 0 0 0 0 0 0 — — — — — — — — — — — — — — — 32 — — — — — — Standard Typ. — 0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 32.768 — — — — — — — Max. 5.5 — VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.55 VCC 0.45 VCC 0.35 VCC 0.4 −160 −80 −10 −40 −5 −20 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz kHz MHz MHz MHz MHz MHz MHz MHz 4.0 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 4.0 V 1.8 V ≤ VCC < 2.7 V 4.0 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 4.0 V 1.8 V ≤ VCC < 2.7 V Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.7 VCC 2.7 V ≤ VCC < 4.0 V 1.8 V ≤ VCC < 2.7 V External clock input (XOUT) Input “L” voltage Other than CMOS input VIL CMOS Input level Input level selection: 4.0 V ≤ VCC ≤ 5.5 V input switching 0.35 VCC 2.7 V ≤ VCC < 4.0 V function 1.8 V ≤ VCC < 2.7 V (I/O port) Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.5 VCC 2.7 V ≤ VCC < 4.0 V 1.8 V ≤ VCC < 2.7 V Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.7 VCC 2.7 V ≤ VCC < 4.0 V 1.8 V ≤ VCC < 2.7 V External clock input (XOUT) Peak sum output “H” Sum of all pins IOH(peak) IOH(sum) current Average sum output “H” Sum of all pins IOH(avg) IOH(sum) current Peak output “H” current Drive capacity Low IOH(peak) Drive capacity High Average output “H” Drive capacity Low IOH(avg) current Drive capacity High Peak sum output “L” Sum of all pins IOL(peak) IOL(sum) current Average sum output “L” Sum of all pins IOL(avg) IOL(sum) current Peak output “L” current Drive capacity Low IOL(peak) Drive capacity High Average output “L” Drive capacity Low IOL(avg) current Drive capacity High XIN clock input oscillation frequency 2.7 V ≤ VCC ≤ 5.5 V f(XIN) 1.8 V ≤ VCC < 2.7 V XCIN clock input oscillation frequency 1.8 V ≤ VCC ≤ 5.5 V f(XCIN) 2.7 V ≤ VCC ≤ 5.5 V fOCO40M When used as the count source for timer RC (3) fOCO-F — f(BCLK) fOCO-F frequency System clock frequency CPU clock frequency 2.7 V ≤ VCC ≤ 5.5 V 1.8 V ≤ VCC < 2.7 V 2.7 V ≤ VCC ≤ 5.5 V 1.8 V ≤ VCC < 2.7 V 2.7 V ≤ VCC ≤ 5.5 V 1.8 V ≤ VCC < 2.7 V VCC/AVCC Supply voltage VSS/AVSS Supply voltage Input “H” voltage Other than CMOS input VIH CMOS Input level Input level selection: input switching 0.35 VCC function (I/O port) Input level selection: 0.5 VCC 160 80 10 40 5 20 20 5 50 40 20 5 20 5 20 5 Notes: 1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. 3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 to 5.5 V. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 30 of 55 R8C/3NT Group 5. Electrical Characteristics P0 P1 P2 P3 P4 P6 10 pF Figure 5.1 Ports P0 to P4, P6 Timing Measurement Circuit R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 31 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.3 Symbol — — A/D Converter Characteristics Parameter Resolution Absolute accuracy Conditions Vref = AVCC Vref = AVCC = 5.0 V Vref = AVCC = 3.3 V Vref = AVCC = 3.0 V Vref = AVCC = 2.2 V 8-bit mode Vref = AVCC = 5.0 V Vref = AVCC = 3.3 V Vref = AVCC = 3.0 V Vref = AVCC = 2.2 V Min. — — — — — — — — — 2 2 2 2 2.2 2.2 0.8 — 2.2 0 1.19 Standard Typ. Max. — 10 — ±3 — — — — — — — — — — — 3 — — — 45 — — 1.34 ±5 ±5 ±5 ±2 ±2 ±2 ±2 Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB MHz MHz MHz MHz kΩ µs µs µs µA 10-bit mode AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input φAD A/D conversion clock 4.0 V ≤ Vref = AVCC ≤ 5.5 V (2) 3.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 2.7 V ≤ Vref = AVCC ≤ 5.5 V (2) 2.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 20 16 10 5 — — — — AVCC Vref 1.49 — tCONV tSAMP IVref Vref VIA OCVREF Tolerance level impedance Conversion time 10-bit mode 8-bit mode Sampling time Vref current Reference voltage Analog input voltage (3) On-chip reference voltage Vref = AVCC = 5.0 V, φAD = 20 MHz Vref = AVCC = 5.0 V, φAD = 20 MHz φAD = 20 MHz VCC = 5.0 V, XIN = f1 = φAD = 20 MHz V V V 2 MHz ≤ φAD ≤ 4 MHz Notes: 1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified. 2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion. 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 32 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.4 Symbol — — — td(SR-SUS) — — td(CMDRST -READY) — — — — Flash Memory (Program ROM) Electrical Characteristics Parameter Conditions Min. 1,000 (3) — — — 0 — − Program/erase endurance (2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart Time from when command is forcibly stopped until reading is enabled Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55 °C Standard Typ. — 80 0.3 — — — − Max. — Unit times µs TBD TBD 5 + CPU clock × 3 cycles — 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 60 — s ms µs µs µs 2.7 1.8 0 20 — — — — V V °C year Notes: 1. VCC = 2.7 to 5.5 V and Topr = 0 to 60 °C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.) 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 33 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.5 Symbol — — — — — td(SR-SUS) — — td(CMDRST -READY) — — — — Flash Memory (Data flash Block A to Block D) Electrical Characteristics Parameter Conditions Min. 10,000 (3) — — — — — 0 — − Program/erase endurance (2) Byte program time (program/erase endurance ≤ 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance ≤ 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart Time from when command is forcibly stopped until reading is enabled Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55 °C Standard Typ. — 160 300 0.2 0.3 — — — − Max. — TBD TBD 1 1 Unit times µs µs s s ms µs µs µs 5 + CPU clock × 3 cycles — 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 85 — 2.7 1.8 −20 20 — — — — V V °C year Notes: 1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.) 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Suspend request (FMR21 bit) FST7 bit FST6 bit Fixed time Clock-dependent time Access restart td(SR-SUS) FST6, FST7: Bit in FST register FMR21: Bit in FMR2 register Figure 5.2 Time delay until Suspend R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 34 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.6 Symbol Vdet0 Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Vdet0_0 (2) Voltage detection level Vdet0_1 (2) Voltage detection level Vdet0_2 (2) Voltage detection level Vdet0_3 (2) (4) Condition Min. TBD TBD TBD TBD Standard Typ. 1.90 2.35 2.85 3.80 6 1.5 — Max. TBD TBD TBD TBD TBD — TBD Unit V V V V µs µA µs — — td(E-A) Voltage detection 0 circuit response time Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3) At the falling of VCC from 5.0 V to (Vdet0_0 − 0.1) V VCA25 = 1, VCC = 5.0 V — — — Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. 4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0. Table 5.7 Symbol Vdet1 Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level Vdet1_0 (2) Voltage detection level Vdet1_1 (2) Voltage detection level Vdet1_2 (2) Voltage detection level Vdet1_3 Voltage detection level Vdet1_4 (2) (2) Condition At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC Vdet1_0 to Vdet1_5 selected Vdet1_6 to Vdet1_F selected At the falling of VCC from 5.0 V to (Vdet1_0 − 0.1) V VCA26 = 1, VCC = 5.0 V Min. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD — — — — — Standard Typ. 2.20 2.35 2.50 2.65 2.80 2.95 3.10 3.25 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 0.07 0.10 60 1.7 — Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD — — TBD — TBD Unit V V V V V V V V V V V V V V V V V V µs µA µs Voltage detection level Vdet1_5 (2) Voltage detection level Vdet1_6 (2) Voltage detection level Vdet1_7 Voltage detection level Vdet1_8 (2) (2) Voltage detection level Vdet1_9 (2) Voltage detection level Vdet1_A (2) Voltage detection level Vdet1_B Voltage detection level Vdet1_C (2) (2) Voltage detection level Vdet1_D (2) Voltage detection level Vdet1_E (2) — Voltage detection level Vdet1_F (2) Hysteresis width at the rising of VCC in voltage detection 1 circuit — — td(E-A) Voltage detection 1 circuit response time (3) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (4) Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version). 2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 35 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.8 Symbol Vdet2 — — — td(E-A) Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Vdet2_0 Hysteresis width at the rising of VCC in voltage detection 2 circuit Voltage detection 2 circuit response time (2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3) Condition At the falling of VCC Min. TBD — — — — Standard Typ. 4.00 0.10 20 1.7 — Max. TBD — 150 — 100 Unit V V µs µA µs At the falling of VCC from 5.0 V to (Vdet2_0 − 0.1) V VCA27 = 1, VCC = 5.0 V Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Table 5.9 Symbol trth Power-on Reset Circuit (2) Parameter External power VCC rise gradient (1) Condition Min. 0 Standard Typ. Max. — 50,000 Unit mV/msec Notes: 1. The measurement condition is Topr = −20 to 85 °C (N version), unless otherwise specified. 2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0. Vdet0 (1) trth External Power VCC 0.5 V tw(por) (2) Voltage detection 0 circuit response time trth Vdet0 (1) Internal reset signal 1 × 32 fOCO-S 1 × 32 fOCO-S Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por) for 1 ms or more. Figure 5.3 Power-on Reset Circuit Electrical Characteristics R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 36 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.10 Symbol — High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Condition VCC = 5.0 V, Topr = 25 °C VCC = 5.0 V, Topr = 25 °C Min. — — Standard Typ. 40 36.864 Max. — — Unit MHz MHz — — High-speed on-chip oscillator frequency after reset High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (2) High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25 °C — 32 — MHz VCC = 5.0 V, Topr = 25 °C VCC = 5.0 V, Topr = 25 °C — — TBD 400 — — ms µA Notes: 1. VCC = 5.0 V and Topr = 25 °C, unless otherwise specified. 2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Table 5.11 Symbol fOCO-S — — Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Condition Min. 60 — — Standard Typ. 125 30 2 Max. 250 TBD — Unit kHz µs µA Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25 °C VCC = 5.0 V, Topr = 25 °C Note: 1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified. Table 5.12 Symbol td(P-R) Power Supply Circuit Timing Characteristics Parameter Condition Min. — Standard Typ. Max. — 2,000 Unit µs Time for internal power supply stabilization during power-on (2) Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25 °C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 37 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.13 Symbol tSUCYC tHI tLO tRISE tFALL tSU Timing Requirements of Synchronous Serial Communication Unit (SSU) Parameter Conditions Min. 4 0.4 0.4 — — — During low-voltage signal mode VCC = 3.0 V, Minimum input voltage = 1.65 V, external pull-up resistor = 510 Ω (3) — 100 Standard Typ. — — — — — — — — Max. — 0.6 0.6 1 1 1 1 — Unit tCYC (2) tSUCYC tSUCYC tCYC (2) µs tCYC (2) µs ns SSCK_i clock cycle time SSCK_i clock “H” width SSCK_i clock “L” width SSCK_i clock rising Master time Slave SSCK_i clock falling time Master Slave SSO_i, SSI_i data input setup time tH tLEAD tLAG tOD tSA tOR i = 0 to 3 SSO_i, SSI_i data input hold time Slave SCS_i setup time SCS_i hold time SSO_i, SSI_i data output delay time SSI_i slave access time 2.7 V ≤ VCC ≤ 5.5 V 1.8 V ≤ VCC < 2.7 V SSI_i slave out open time 2.7 V ≤ VCC ≤ 5.5 V 1.8 V ≤ VCC < 2.7 V Slave 1 1tCYC + 50 1tCYC + 50 — — — — — — — — — — — — — — — — 1 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200 tCYC (2) ns ns tCYC (2) ns ns ns ns Notes: 1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified. 2. 1tCYC = 1/f1(s) f1 ≤ 10 MHz is required when the noise filter is used in low-voltage signal mode. 3. These indicate the measurement conditions in low-voltage signal mode. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 38 of 55 R8C/3NT Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS_i (output) VIL or VOL tHI tFALL tRISE SSCK_i (output) (CPOS = 1) tLO tHI SSCK_i (output) (CPOS = 0) tLO tSUCYC SSO_i (output) tOD SSI_i (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS_i (output) VIL or VOL tHI tFALL tRISE SSCK_i (output) (CPOS = 1) tLO tHI SSCK_i (output) (CPOS = 0) tLO tSUCYC SSO_i (output) tOD SSI_i (input) tSU tH CPHS, CPOS: Bits in SSiMR register i = 0 to 3 Figure 5.4 I/O Timing of Synchronous Serial Communication Unit (SSU) (Master) R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 39 of 55 R8C/3NT Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS_i (input) VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK_i (input) (CPOS = 1) tLO tHI SSCK_i (input) (CPOS = 0) tLO tSUCYC SSO_i (input) tSU tH SSI_i (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 VIH or VOH SCS_i (input) VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK_i (input) (CPOS = 1) tLO tHI SSCK_i (input) (CPOS = 0) tLO tSUCYC SSO_i (input) tSU tH SSI_i (output) tSA tOD tOR CPHS, CPOS: Bits in SSiMR register i = 0 to 3 Figure 5.5 I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave) R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 40 of 55 R8C/3NT Group 5. Electrical Characteristics tHI VIH or VOH SSCK_i VIL or VOL tLO tSUCYC SSO_i (output) tOD SSI_i (input) tSU tH i = 0 to 3 Figure 5.6 I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous Communication Mode) R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 41 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.14 Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH i = 0 to 3 Timing Requirements of I2C bus Interface Parameter Condition Standard Min. 12tCYC + 600 (2) 3tCYC + 300 (2) 5tCYC + 500 — — 5tCYC (2) 3tCYC (2) 3tCYC (2) 3tCYC (2) 1tCYC + 40 (2) 10 (2) Typ. — — — — — — — — — — — Max. — — — 300 1tCYC (2) — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns SCL_i input cycle time SCL_i input “H” width SCL_i input “L” width SCL_i, SDA_i input fall time SCL_i, SDA_i input spike pulse rejection time SDA_i input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Notes: 1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified. 2. 1tCYC = 1/f1(s) VIH SDA_i tBUF VIL tSTAH tSCLH tSTAS tSP tSTOP SCL_i P (2) S (1) tSf tSCLL tSCL tSr tSDAH Sr (3) tSDAS P (2) Notes: 1. Start condition 2. Stop condition 3. Retransmit start condition i = 0 to 3 Figure 5.7 I/O Timing of I2C bus Interface R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 42 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.15 Symbol VOH Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V] Parameter Condition Drive capacity High VCC = 5 V IOH = −20 mA Maximum number of I/Os = 4 VCC = 5 V IOH = −5 mA Maximum number of I/Os = 16 IOH = −200 µA VCC = 5 V IOL = 20 mA Maximum number of I/Os = 4 VCC = 5 V IOL = 5 mA Maximum number of I/Os = 16 IOL = 200 µA Standard Min. Typ. Max. VCC – 2.0 — VCC Unit V Output “H” Other than XOUT voltage Drive capacity Low VCC – 2.0 — VCC V VOL Output “L” voltage XOUT Other than XOUT VCC = 5 V Drive capacity High 1.0 — — — VCC 2.0 V V Drive capacity Low — — 2.0 V VT+-VT- XOUT Hysteresis INT0, INT1, INT2, INT3, INT4, KI0, KI1, KI2, KI3, TRAIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, CTS2, SSCK_i, SCS_i, SSI_i, SCL_i, SDA_i, SSO_i (i = 0 to 3) RESET Input “H” current Input “L” current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage VCC = 5 V VCC = 5.0 V — 0.1 — 1.2 0.5 — V V 0.1 VI = 5 V, VCC = 5.0 V VI = 0 V, VCC = 5.0 V VI = 0 V, VCC = 5.0 V — — 25 — — During stop mode 1.8 1.2 — — 50 0.3 8 — — 5.0 −5.0 100 — — — V µA µA kΩ MΩ IIH IIL RPULLUP RfXIN RfXCIN VRAM MΩ V Note: 1. 4.2 V ≤ VCC ≤ 5.5 V, Topr = −20 to 85 °C (N version), and f(XIN) = 20 MHz, unless otherwise specified. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 43 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.16 Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V] (Topr = −20 to 85 °C (N version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off, Topr = 25 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Symbol ICC Power supply current High-speed (VCC = 3.3 to 5.5 V) clock mode Single-chip mode, output pins are open, other pins are VSS Min. — Standard Typ. Max. 6.5 1.5 Unit mA — 5.3 12.5 mA — 3.6 — mA — 3.0 — mA — 2.2 — mA — 1.5 — mA High-speed on-chip oscillator mode — 7.0 15 mA — 3.0 — mA — 1 — mA Low-speed on-chip oscillator mode Low-speed clock mode — 90 400 µA — 85 400 µA — 47 — µA Wait mode — 15 100 µA — 4 90 µA — 3.5 — µA Stop mode — 2.0 5.0 µA — 15 — µA R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 44 of 55 R8C/3NT Group Timing Requirements Table 5.17 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width 5. Electrical Characteristics (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V, Topr = 25 °C) External Clock Input (XOUT, XCIN) Parameter Standard Min. Max. 50 — 24 — 24 — 41 — 7 — 7 — Unit ns ns ns µs µs µs tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 5 V External clock input tWL(XOUT), tWL(XCIN) Figure 5.8 External Clock Input Timing Diagram when VCC = 5 V Table 5.18 Symbol TRAIO Input Parameter Standard Min. Max. 100 — 40 — 40 — Unit ns ns ns TRAIO input cycle time tc(TRAIO) tWH(TRAIO) TRAIO input “H” width tWL(TRAIO) TRAIO input “L” width tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 5.9 TRAIO Input Timing Diagram when VCC = 5 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 45 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.19 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2 Serial Interface Parameter Condition When an external clock is selected Standard Min. 200 100 100 — 0 10 90 — 90 90 Max. — — — 90 — — — 10 — — Unit ns ns ns ns ns ns ns ns ns ns CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time TXDi output delay time RXDi input setup time RXDi input hold time When an internal clock is selected tC(CK) tW(CKH) VCC = 5 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 to 2 Figure 5.10 Serial Interface Timing Diagram when VCC = 5 V Table 5.20 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. Max. (1) — 250 250 (2) — Unit ns ns INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0 to 4) KIi input (i = 0 to 3) VCC = 5 V tW(INL) tW(INH) Figure 5.11 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when VCC = 5 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 46 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.21 Symbol VOH Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V] Parameter Condition Standard Min. VCC – 0.7 Typ. Max. — VCC Unit V Output “H” voltage Other than XOUT VOL Output “L” voltage VT+-VT- Hysteresis Drive capacity High VCC = 3 V IOH = −5 mA Maximum number of I/Os = 4 Drive capacity Low VCC = 3 V IOH = −1 mA Maximum number of I/Os = 16 XOUT IOH = −200 µA Other than XOUT Drive capacity High VCC = 3 V IOL = 5 mA Maximum number of I/Os = 4 Drive capacity Low VCC = 3 V IOL = 1 mA Maximum number of I/Os = 16 XOUT IOL = 200 µA INT0, INT1, INT2, INT3, VCC = 3.0 V INT4, KI0, KI1, KI2, KI3, TRAIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, CTS2, SSCK_i, SCS_i, SSI_i, SCL_i, SDA_i, SSO_i (i = 0 to 3) VCC = 3.0 V RESET VI = 3 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V XIN XCIN During stop mode VCC – 0.7 — VCC V 1.0 — — — VCC 0.7 V V — — 0.7 V — 0.1 — 0.4 0.5 — V V 0.1 — — 42 — — 1.8 0.5 — — 84 0.3 8 — — 4.0 −4.0 168 — — — V µA µA kΩ MΩ IIH IIL RPULLUP RfXIN RfXCIN VRAM Input “H” current Input “L” current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage MΩ V Note: 1. 2.7 V ≤ VCC < 4.2 V, Topr = −20 to 85 °C (N version), and f(XIN) = 10 MHz, unless otherwise specified. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 47 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.22 Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V] (Topr = −20 to 85 °C (N version), unless otherwise specified.) Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off, Topr = 25 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Symbol ICC Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS Min. — Standard Typ. Max. 3.5 10 Unit mA — 1.5 7.5 mA High-speed on-chip oscillator mode — 7.0 15 mA — 3.0 — mA — 4.0 — mA — 1.5 — mA — 1 — mA Low-speed on-chip oscillator mode Low-speed clock mode — 90 390 µA — 80 400 µA — 40 — µA Wait mode — 15 90 µA — 4 80 µA — 3.5 — µA Stop mode — 2.0 5.0 µA — 15 — µA R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 48 of 55 R8C/3NT Group Timing requirements Table 5.23 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width 5. Electrical Characteristics (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V, Topr = 25 °C) External Clock Input (XOUT, XCIN) Parameter Standard Min. 50 24 24 14 7 7 Max. — — — — — — Unit ns ns ns µs µs µs tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 3 V External clock input tWL(XOUT), tWL(XCIN) Figure 5.12 External Clock Input Timing Diagram when VCC = 3 V Table 5.24 Symbol TRAIO Input Parameter Standard Min. Max. 300 — 120 — 120 — Unit ns ns ns TRAIO input cycle time tc(TRAIO) tWH(TRAIO) TRAIO input “H” width tWL(TRAIO) TRAIO input “L” width tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 5.13 TRAIO Input Timing Diagram when VCC = 3 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 49 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.25 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2 Serial Interface Parameter Condition When an external clock is selected Standard Min. 300 150 150 — 0 30 90 — 120 90 Max. — — — 120 — — — 30 — — Unit ns ns ns ns ns ns ns ns ns ns CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time TXDi output delay time RXDi input setup time RXDi input hold time When an internal clock is selected tC(CK) tW(CKH) VCC = 3 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 to 2 Figure 5.14 Serial Interface Timing Diagram when VCC = 3 V Table 5.26 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. Max. (1) — 380 380 (2) — Unit ns ns INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0 to 4) KIi input (i = 0 to 3) VCC = 3 V tW(INL) tW(INH) Figure 5.15 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when VCC = 3 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 50 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.27 Symbol VOH Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V] Parameter Condition Drive capacity High VCC = 1.8 V IOH = −2 mA Maximum number of I/Os = 4 Drive capacity Low VCC = 1.8 V IOH = −1 mA Maximum number of I/Os = 16 IOH = −200 µA Drive capacity High VCC = 1.8 V IOL = 2 mA Maximum number of I/Os = 4 Drive capacity Low VCC = 1.8 V IOL = 1 mA Maximum number of I/Os = 16 IOL = 200 µA VCC = 2.2 V Standard Min. VCC – 0.5 Typ. Max. — VCC Unit V Output “H” voltage Other than XOUT VCC – 0.5 — VCC V VOL Output “L” voltage XOUT Other than XOUT 1.0 — — — VCC 0.5 V V — — 0.5 V XOUT VT+-VTHysteresis NT0, INT1, INT2, INT3, INT4, KI0, KI1, KI2, KI3, TRAIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, CTS2, SSCK_i, SCS_i, SSI_i, SCL_i, SDA_i, SSO_i (i = 0 to 3) RESET IIH IIL RPULLUP RfXIN RfXCIN VRAM Input “H” current Input “L” current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage — 0.05 — 0.20 0.5 — V V 0.05 VI = 2.2 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V — — 70 — — During stop mode 1.8 0.20 — — 140 0.3 8 — — 4.0 −4.0 300 — — — V µA µA kΩ MΩ XIN XCIN MΩ V Note: 1. 1.8 V ≤ VCC < 2.7 V, Topr = −20 to 85 °C (N version), and f(XIN) = 5 MHz, unless otherwise specified. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 51 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.28 Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V] (Topr = −20 to 85 °C (N version), unless otherwise specified.) Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Symbol ICC Standard Min. — Typ. 2.2 Max. — Unit mA Power supply current High-speed (VCC = 1.8 to 2.7 V) clock mode Single-chip mode, output pins are open, other pins are VSS — 0.8 — mA XIN clock off High-speed High-speed on-chip oscillator on fOCO-F = 5 MHz on-chip oscillator mode Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1 XIN clock off Low-speed High-speed on-chip oscillator off on-chip oscillator mode Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 — 2.5 10 mA — 1.7 — mA — 1 — mA — 90 300 µA Low-speed clock mode — 80 350 µA — 40 — µA Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 — 15 90 µA — 4 80 µA — 3.5 — µA Stop mode XIN clock off, Topr = 25 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 °C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 — 2.0 5 µA — 15 — µA R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 52 of 55 R8C/3NT Group Timing requirements Table 5.29 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width 5. Electrical Characteristics (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V, Topr = 25 °C) External Clock Input (XOUT, XCIN) Parameter Standard Min. 200 90 90 14 7 7 Max. — — — — — — Unit ns ns ns µs µs µs tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 2.2 V External clock input tWL(XOUT), tWL(XCIN) Figure 5.16 External Clock Input Timing Diagram when VCC = 2.2 V Table 5.30 Symbol TRAIO Input Parameter Standard Min. Max. 500 — 200 — 200 — Unit ns ns ns TRAIO input cycle time tc(TRAIO) tWH(TRAIO) TRAIO input “H” width tWL(TRAIO) TRAIO input “L” width tC(TRAIO) tWH(TRAIO) VCC = 2.2 V TRAIO input tWL(TRAIO) Figure 5.17 TRAIO Input Timing Diagram when VCC = 2.2 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 53 of 55 R8C/3NT Group 5. Electrical Characteristics Table 5.31 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2 Serial Interface Parameter Condition When an external clock is selected Standard Min. 800 400 400 — 0 150 90 When an internal clock is selected — 150 90 Max. — — — 200 — — — 200 — — Unit ns ns ns ns ns ns ns ns ns ns CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time TXDi output delay time RXDi input setup time RXDi input hold time tC(CK) tW(CKH) VCC = 2.2 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 to 2 Figure 5.18 Serial Interface Timing Diagram when VCC = 2.2 V Table 5.32 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. 1,000 (1) 1,000 (2) Max. — — Unit ns ns INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0 to 4) KIi input (i = 0 to 3) VCC = 2.2 V tW(INL) tW(INH) Figure 5.19 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when VCC = 2.2 V R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 54 of 55 R8C/3NT Group Package Dimensions Package Dimensions Underfill is applied to this package. Evaluate its strength under the environment that actual product modules are used. A A B C D E F G 7654321 B 4× 0.03 48-φ0.28±0.03 φ0.05 M S AB S SEATING PLANE C area 0.06 S C area Notes 1. Pin pitches are specified by the pin center positions. 2. Datum A and B indicate the center of the ball grid. R01DS0047EJ0100 Rev.1.00 Jan 25, 2011 Page 55 of 55 REVISION HISTORY R8C/3NT Group Datasheet Description Summary Rev. Date Page 0.01 1.00 May 17, 2010 Jan 25, 2011 — All 1 2 3 4 15 20 22 23 29 to 54 55 First Edition issued “PRELIMINARY” and “Under development” deleted 1.1 “A sensor control unit is ... capacitive touch electrode.” added Table 1.1 revised Table 1.2 revised Table 1.3 revised Table 4.2 revised Table 4.7 revised Table 4.9 revised Table 4.10 revised 5. Electrical Characteristics added Package Dimensions “Preliminary” deleted All trademarks and registered trademarks are the property of their respective owners. C-1 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. 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